5becbfa852
3P HDR+ test results: sponge/3c57475a-cbf2-4af5-ab22-ad6a4fc0c17f Bug: 131937949 Change-Id: I2fbac8d5183ae38415d4359ce2eef5192ad55297 Signed-off-by: Sean Howarth <showarth@google.com>
127 lines
3.9 KiB
C
127 lines
3.9 KiB
C
/*
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* Driver interface for the Paintbox Image Processing Unit
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*
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* Copyright (C) 2018 Google, Inc.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __UAPI_IPU_H__
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#define __UAPI_IPU_H__
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#include <linux/compiler.h>
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#include <linux/dma-direction.h>
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#include <linux/ioctl.h>
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#include <linux/types.h>
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#define PAINTBOX_SESSION_ID_MAX 32
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struct ipu_capabilities_rsp {
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__u32 version_major;
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__u32 version_minor;
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__u32 version_build;
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__u32 hardware_id;
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__u32 num_stps;
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__u32 num_interrupts;
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__u32 num_lbps;
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__u32 num_dma_channels;
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bool is_simulator;
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bool is_fpga;
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bool iommu_enabled;
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};
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struct ipu_resource_allocate_request {
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__u64 stp_mask;
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__u64 lbp_mask;
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__u64 dma_channel_mask;
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__u64 timeout_ns;
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};
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struct ipu_dma_buf_register_entry {
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int dma_buf_fd; /* Input Parameter */
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enum dma_data_direction dir; /* Input Parameter */
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__u32 buffer_id; /* Output Parameter */
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};
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struct ipu_power_core_enable_request {
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__u64 stp_mask;
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__u64 lbp_mask;
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};
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struct ipu_power_core_disable_request {
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__u64 stp_mask;
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__u64 lbp_mask;
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};
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struct ipu_dma_buf_bulk_register_req {
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unsigned int num_buffers;
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struct ipu_dma_buf_register_entry __user *bufs;
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};
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struct ipu_dma_buf_bulk_unregister_req {
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unsigned int num_buffers;
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__u32 __user *buf_ids;
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};
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/* On success will return 0, otherwise will return -1 with errno set. */
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#define IPU_GET_CAPABILITIES _IOR('i', 1, struct ipu_capabilities_rsp)
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/* On success will return a fd >= 0, otherwise will return -1 with errno set. */
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#define IPU_ALLOCATE_CMD_QUEUE _IO('i', 2)
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/* On success will return 0, otherwise will return -1 with errno set. */
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#define IPU_ALLOCATE_RESOURCES _IOW('i', 3, \
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struct ipu_resource_allocate_request)
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/* On success will return 0, otherwise will return -1 with errno set. */
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#define IPU_RELEASE_RESOURCES _IO('i', 4)
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/* On success will return 0, otherwise will return -1 with errno set. */
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#define IPU_POWER_ENABLE_CORES _IOW('i', 5, \
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struct ipu_power_core_enable_request)
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/* On success will return 0, otherwise will return -1 with errno set. */
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#define IPU_POWER_DISABLE_CORES _IOW('i', 6, \
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struct ipu_power_core_disable_request)
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/* Supports both AB Dram and ION buffers, buffers can be non-contiguous if IOMMU
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* is active. IPU DMA operations using ION buffers will be across the PCIe bus.
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* On success the return value will be zero and the buffer_id field will be set
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* to the buffer id for the buffer. On error the return value will be set to -1
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* and errno will be set.
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*/
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#define IPU_BULK_REGISTER_DMA_BUF _IOWR('i', 7, \
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struct ipu_dma_buf_bulk_register_req)
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/* The parameter to the ioctl is the buffer id to be unregistered. On success
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* the return value will be zero. On error the return value will be set to -1
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* and errno will be set.
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*/
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#define IPU_BULK_UNREGISTER_DMA_BUF _IOW('i', 8, \
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struct ipu_dma_buf_bulk_unregister_req)
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/* Only supports ab dram input buffer. buffer must be contiguous in memory.
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* On success the return value will be zero and the buffer_id field will be set
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* to the buffer id for the buffer. On error the return value will be set to -1
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* and errno will be set.
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*/
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#define IPU_BULK_REGISTER_32B_ADDRESS_DMA_BUF _IOWR('i', 9, \
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struct ipu_dma_buf_bulk_register_req)
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/* Associates an eventfd with a command queue allocated using
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* IPU_ALLOCATE_CMD_QUEUE.
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* The eventfd is incremented by one for every doorbell interrupt received for
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* the queue.
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*/
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#define IPU_CMD_QUEUE_SET_EVENTFD _IOW('q', 1, int)
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#define IPU_CMD_QUEUE_CLEAR_EVENTFD _IOW('q', 2, int)
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#endif /* __UAPI_IPU_H__ */
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