From 1f12ee970db119204eea64bbaff598f51b3cfba2 Mon Sep 17 00:00:00 2001
From: Madhukar Sharma <quic_madhukar@quicinc.com>
Date: Thu, 5 Jun 2025 11:32:16 +0530
Subject: [PATCH] ARM: dts: qcom: Add qce device for qcs610

Add qce device for qcs610 to enable cypto capability.

Change-Id: I4c65d67567e1b76584c07a5c1a00373304a133ea
Signed-off-by: Madhukar Sharma <quic_madhukar@quicinc.com>
---
 qcom/qcs610.dtsi | 21 ++++++++++++++++++++-
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/qcom/qcs610.dtsi b/qcom/qcs610.dtsi
index be5a3b90..d647599e 100644
--- a/qcom/qcs610.dtsi
+++ b/qcom/qcs610.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: BSD-3-Clause
 /*
- * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
  */
 
 #include "sm6150.dtsi"
@@ -91,6 +91,25 @@
 		};
 	};
 
+	qcom_cedev: qcedev@1de0000 {
+		compatible = "qcom,qcedev";
+		reg = <0x1de0000 0x20000>,
+			<0x1dc4000 0x24000>;
+		reg-names = "crypto-base","crypto-bam-base";
+		interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,bam-pipe-pair = <3>;
+		qcom,ce-hw-instance = <0>;
+		qcom,ce-device = <0>;
+		qcom,ce-hw-shared;
+		qcom,bam-ee = <0>;
+		qcom,smmu-s1-enable;
+		qcom,no-clock-support;
+		interconnect-names = "data_path";
+		interconnects = <&aggre1_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
+		iommus = <&apps_smmu 0x0106 0x0011>,
+			 <&apps_smmu 0x0116 0x0011>;
+		qcom,iommu-dma = "atomic";
+	};
 };
 
 &qupv3_se3_i2c {