From 6209d1663991fd0754a05777883b27efce46cbe8 Mon Sep 17 00:00:00 2001 From: Mohammed Aakib Patel Date: Tue, 15 Apr 2025 16:22:34 +0530 Subject: [PATCH 1/4] ARM: dts: msm: support of reboot_reason for qcs610 Devicetree changes to bringup adb reboot bootloader and adb reboot recovery for nvmem cell not supported. Change-Id: Ib7d942742cda25e539b33a301b598767dc7d0d76 Signed-off-by: Mohammed Aakib Patel --- qcom/sm6150.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 74ebca20..4a248d39 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -1221,6 +1221,11 @@ }; }; + reboot_reason { + compatible = "qcom,reboot-reason"; + qcom,no-nvmem-cell-support; + }; + qcom,mpm2-sleep-counter@c221000 { compatible = "qcom,mpm2-sleep-counter"; reg = <0xc221000 0x1000>; From 70a67c85107ba81d423de9b259f02d56047daf7f Mon Sep 17 00:00:00 2001 From: Mohammed Aakib Patel Date: Thu, 17 Apr 2025 11:57:26 +0530 Subject: [PATCH 2/4] ARM: dts: msm: Add Core Hang Detect node for QCS610 Add CHD node for QCS610 to enable Core Hang Detect feature. Change-Id: Iec698efd1f1e91f35368321ef75c55cfe5e002d3 Signed-off-by: Mohammed Aakib Patel --- qcom/sm6150.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 4a248d39..e2e40f16 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -1226,6 +1226,19 @@ qcom,no-nvmem-cell-support; }; + qcom,chd { + compatible = "qcom,core-hang-detect"; + label = "core"; + qcom,chd-percpu-info = <&CPU0 0x18000058 0x18000060>, + <&CPU1 0x18010058 0x18010060>, + <&CPU2 0x18020058 0x18020060>, + <&CPU3 0x18030058 0x18030060>, + <&CPU4 0x18040058 0x18040060>, + <&CPU5 0x18050058 0x18050060>, + <&CPU6 0x18060058 0x18060060>, + <&CPU7 0x18070058 0x18070060>; + }; + qcom,mpm2-sleep-counter@c221000 { compatible = "qcom,mpm2-sleep-counter"; reg = <0xc221000 0x1000>; From 0ba14955f691b5c9c5040ff770e1f02952028e5b Mon Sep 17 00:00:00 2001 From: Asit Shah Date: Wed, 5 Jul 2023 18:10:59 +0530 Subject: [PATCH 3/4] ARM: dts: msm: Add dcvs, l3 device tree node for SM6150 Add support for dcvs, compute_mon, pmu tables and L3 device tree node for SM6150. Change-Id: Iaf73e62a5937bcaea0b23f4e0a5c3b710895a7c7 Signed-off-by: Asit Shah --- qcom/sm6150.dtsi | 239 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 239 insertions(+) diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index e2e40f16..cfcbc955 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -867,6 +867,245 @@ cap-based-alloc-and-pwr-collapse; }; + llcc_pmu: llcc-pmu@90cc000 { + compatible = "qcom,llcc-pmu-ver2"; + reg = <0x090cc000 0x300>; + reg-names = "lagg-base"; + }; + + cpu_pmu: cpu-pmu { + compatible = "arm,armv8-pmuv3"; + qcom,irq-is-percpu; + interrupts = ; + }; + + qcom,pmu { + compatible = "qcom,pmu"; + qcom,long-counter; + qcom,pmu-events-tbl = + < 0x0008 0xFF 0xFF 0xFF >, + < 0x0011 0xFF 0xFF 0xFF >, + < 0x0017 0xFF 0xFF 0xFF >, + < 0x002A 0xFF 0xFF 0xFF >, + < 0x1000 0xFF 0xFF 0xFF >; + }; + + ddr_freq_table: ddr-freq-table { + qcom,freq-tbl = + < 200000 >, + < 300000 >, + < 451000 >, + < 547000 >, + < 681000 >, + < 768000 >, + < 1017000 >, + < 1353000 >, + < 1555000 >, + < 1804000 >; + }; + + llcc_freq_table: llcc-freq-table { + qcom,freq-tbl = + < 150000 >, + < 300000 >, + < 466000 >, + < 600000 >, + < 806000 >, + < 933000 >; + }; + + qcom_dcvs: qcom,dcvs { + compatible = "qcom,dcvs"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + qcom_ddr_dcvs_hw: ddr { + compatible = "qcom,dcvs-hw"; + qcom,dcvs-hw-type = <0>; + qcom,bus-width = <4>; + qcom,freq-tbl = <&ddr_freq_table>; + + ddr_dcvs_sp: sp { + compatible = "qcom,dcvs-path"; + qcom,dcvs-path-type = <0>; + interconnects = <&mc_virt MASTER_LLCC + &mc_virt SLAVE_EBI1>; + }; + }; + + qcom_llcc_dcvs_hw: llcc { + compatible = "qcom,dcvs-hw"; + qcom,dcvs-hw-type = <1>; + qcom,bus-width = <16>; + qcom,freq-tbl = <&llcc_freq_table>; + + llcc_dcvs_sp: sp { + compatible = "qcom,dcvs-path"; + qcom,dcvs-path-type = <0>; + interconnects = <&gem_noc MASTER_APPSS_PROC + &gem_noc SLAVE_LLCC>; + }; + }; + + qcom_l3_dcvs_hw: l3 { + compatible = "qcom,dcvs-hw"; + qcom,dcvs-hw-type = <2>; + qcom,bus-width = <32>; + qcom,ftbl-row-size = <0x20>; + reg = <0x18321000 0x4000>, <0x18321110 0x500>; + reg-names = "l3-base", "l3tbl-base"; + + l3_dcvs_sp: sp { + compatible = "qcom,dcvs-path"; + qcom,dcvs-path-type = <0>; + qcom,shared-offset = <0x0920>; + }; + }; + }; + + qcom_memlat: qcom,memlat { + compatible = "qcom,memlat"; + + ddr { + compatible = "qcom,memlat-grp"; + qcom,target-dev = <&qcom_ddr_dcvs_hw>; + qcom,sampling-path = <&ddr_dcvs_sp>; + qcom,miss-ev = <0x1000>; + + silver { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + qcom,cpufreq-memfreq-tbl = + < 748000 300000 >, + < 1017600 451000 >, + < 1209600 547000 >, + < 1516800 768000 >, + < 1804800 1017000 >; + qcom,sampling-enabled; + }; + + silver-compute { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + qcom,cpufreq-memfreq-tbl = + < 748800 300000 >, + < 1209600 451000 >, + < 1593600 547000 >, + < 1804800 768000 >; + qcom,sampling-enabled; + qcom,compute-mon; + }; + + gold { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU6 &CPU7>; + qcom,cpufreq-memfreq-tbl = + < 768000 451000 >, + < 1017600 547000 >, + < 1209600 1017000 >, + < 1708800 1555000 >, + < 2208000 1804000 >; + qcom,sampling-enabled; + }; + + gold-compute { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU6 &CPU7>; + qcom,cpufreq-memfreq-tbl = + < 1017600 300000 >, + < 1209600 547000 >, + < 1516800 768000 >, + < 1708800 1017000 >, + < 2208000 1804000 >; + qcom,sampling-enabled; + qcom,compute-mon; + }; + }; + + llcc { + compatible = "qcom,memlat-grp"; + qcom,target-dev = <&qcom_llcc_dcvs_hw>; + qcom,sampling-path = <&llcc_dcvs_sp>; + qcom,miss-ev = <0x2A>; + + silver { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + qcom,cpufreq-memfreq-tbl = + < 748000 150000 >, + < 1209600 300000 >, + < 1516800 466000 >, + < 1804800 600000 >; + qcom,sampling-enabled; + }; + + gold { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU6 &CPU7>; + qcom,cpufreq-memfreq-tbl = + < 768000 300000 >, + < 1017600 466000 >, + < 1209600 600000 >, + < 1708800 806000 >, + < 2208000 933000 >; + qcom,sampling-enabled; + }; + }; + + l3 { + compatible = "qcom,memlat-grp"; + qcom,target-dev = <&qcom_l3_dcvs_hw>; + qcom,sampling-path = <&l3_dcvs_sp>; + qcom,miss-ev = <0x17>; + + silver { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + qcom,cpufreq-memfreq-tbl = + < 576000 300000 >, + < 1017600 556800 >, + < 1209660 806400 >, + < 1516800 940800 >, + < 1804800 1363200 >; + qcom,sampling-enabled; + }; + + gold { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU6 &CPU7>; + qcom,cpufreq-memfreq-tbl = + < 1017600 556800 >, + < 1209600 806400 >, + < 1516800 940800 >, + < 1708800 1209600 >, + < 2208000 1363200 >; + qcom,sampling-enabled; + }; + }; + }; + + bwmon_llcc: qcom,bwmon-llcc@90b6400 { + compatible = "qcom,bwmon4"; + reg = <0x90b6300 0x300>, <0x90b6200 0x200>; + reg-names = "base", "global_base"; + interrupts = ; + qcom,mport = <0>; + qcom,hw-timer-hz = <19200000>; + qcom,count-unit = <0x10000>; + qcom,target-dev = <&qcom_llcc_dcvs_hw>; + }; + + bwmon_ddr: qcom,bwmon-ddr@90cd000 { + compatible = "qcom,bwmon5"; + reg = <0x90cd000 0x1000>; + reg-names = "base"; + interrupts = ; + qcom,hw-timer-hz = <19200000>; + qcom,count-unit = <0x10000>; + qcom,target-dev = <&qcom_ddr_dcvs_hw>; + }; + ufsphy_mem: ufsphy_mem@1d87000 { reg = <0x1d87000 0xe00>; /* PHY regs */ reg-names = "phy_mem"; From a15cf97f4d5da0b2f5f887bbc905d6af814619f2 Mon Sep 17 00:00:00 2001 From: Kunal Singh Ranawat Date: Tue, 22 Apr 2025 15:30:37 +0530 Subject: [PATCH 4/4] ARM: dts: msm: Add a node for cpufreq cycle counter driver Add cpufreq cycle counter register information to devicetree in a separate node for use by driver. This will initialize walt for QCS610. Change-Id: Ib3d581ba8a6d7c7b683e938a4ed3e28ec0593862 Signed-off-by: Kunal Singh Ranawat --- qcom/sm6150-walt.dtsi | 18 ++++++++++++++++++ qcom/sm6150.dtsi | 1 + 2 files changed, 19 insertions(+) create mode 100644 qcom/sm6150-walt.dtsi diff --git a/qcom/sm6150-walt.dtsi b/qcom/sm6150-walt.dtsi new file mode 100644 index 00000000..325e3679 --- /dev/null +++ b/qcom/sm6150-walt.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + walt { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + qcom,cycle-cntr { + compatible = "qcom,cycle-cntr-hw"; + reg = <0x18323000 0x1400>, <0x18325800 0x1400>; + reg-names = "freq-domain0", "freq-domain1"; + }; + }; +}; diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index cfcbc955..44eba822 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -1882,6 +1882,7 @@ #include "sm6150-qupv3.dtsi" #include "sm6150-usb.dtsi" #include "sm6150-dma-heaps.dtsi" +#include "sm6150-walt.dtsi" &tlmm { status = "okay";