From 9ec93bd62561083e2e61487afa5b46bb736b1d60 Mon Sep 17 00:00:00 2001
From: Ankur Matariya <quic_amatariy@quicinc.com>
Date: Mon, 14 Apr 2025 17:22:34 +0530
Subject: [PATCH] ARM: dts: msm: Add modem_pas node on SM6150

Add modem device tree node to load firmware image on SM6150.

Signed-off-by: Ankur Matariya <quic_amatariy@quicinc.com>
---
 bindings/remoteproc/qcom,adsp.yaml |  1 +
 qcom/qcs610-iot.dtsi               |  4 +++
 qcom/qcs610-opk.dtsi               |  4 +++
 qcom/qcs610.dtsi                   | 41 ++++++++++++++++++++++++++++++
 4 files changed, 50 insertions(+)

diff --git a/bindings/remoteproc/qcom,adsp.yaml b/bindings/remoteproc/qcom,adsp.yaml
index 0cf285ad..fc99ee1e 100644
--- a/bindings/remoteproc/qcom,adsp.yaml
+++ b/bindings/remoteproc/qcom,adsp.yaml
@@ -82,6 +82,7 @@ properties:
       - qcom,kera-wpss-pas
       - qcom,sm6150-adsp-pas
       - qcom,sm6150-cdsp-pas
+      - qcom,sm6150-modem-pas
 
   reg:
     maxItems: 1
diff --git a/qcom/qcs610-iot.dtsi b/qcom/qcs610-iot.dtsi
index 059f447d..9fe62e38 100644
--- a/qcom/qcs610-iot.dtsi
+++ b/qcom/qcs610-iot.dtsi
@@ -263,6 +263,10 @@
 	status = "ok";
 };
 
+&pil_modem_mem {
+	reg = <0x0 0x8fd00000 0x0 0x3100000>;
+};
+
 &ufsphy_mem {
 	compatible = "qcom,ufs-phy-qmp-v3-660";
 
diff --git a/qcom/qcs610-opk.dtsi b/qcom/qcs610-opk.dtsi
index da340d0c..76aecf80 100644
--- a/qcom/qcs610-opk.dtsi
+++ b/qcom/qcs610-opk.dtsi
@@ -292,6 +292,10 @@
 	status = "ok";
 };
 
+&pil_modem_mem {
+	reg = <0x0 0x8fd00000 0x0 0x3100000>;
+};
+
 &sdhc_1 {
 	vdd-supply = <&pm6150l_l11>;
 	qcom,vdd-voltage-level = <2950000 2950000>;
diff --git a/qcom/qcs610.dtsi b/qcom/qcs610.dtsi
index 502fb9be..09ceade3 100644
--- a/qcom/qcs610.dtsi
+++ b/qcom/qcs610.dtsi
@@ -26,6 +26,47 @@
 		clock-names = "eud_ahb2phy_clk";
 		status = "ok";
 	};
+
+	modem_pas: remoteproc-mss@04080000 {
+		compatible = "qcom,sm6150-modem-pas";
+		reg = <0x4080000 0x10000>;
+		status = "ok";
+
+		clocks = <&rpmhcc RPMH_CXO_CLK>;
+		clock-names = "xo";
+
+		cx-supply = <&VDD_CX_LEVEL>;
+		cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+		mss-supply = <&VDD_MSS_LEVEL>;
+		mss-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+		reg-names = "cx", "mss";
+
+		mboxes = <&qmp_aop 0>;
+		interconnects = <&aggre1_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
+		interconnect-names = "crypto_ddr";
+
+		memory-region = <&pil_modem_mem>;
+
+		/* Inputs from mss */
+		interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
+					<&modem_smp2p_in 0 0>,
+					<&modem_smp2p_in 2 0>,
+					<&modem_smp2p_in 1 0>,
+					<&modem_smp2p_in 3 0>,
+					<&modem_smp2p_in 7 0>;
+
+		interrupt-names = "wdog",
+				"fatal",
+				"handover",
+				"ready",
+				"stop-ack",
+				"shutdown-ack";
+
+		/* Outputs to mss */
+		qcom,smem-states = <&modem_smp2p_out 0>;
+		qcom,smem-state-names = "stop";
+	};
+
 };
 
 &qupv3_se3_i2c {