1d125bd012
Add compatible string "qcom,adreno-smmu" which enables per process pagetable feature for sm6150 GPU's MMU. Change-Id: If6a097fcb52fbee7216dc2cf2b6169c75aa3205a Signed-off-by: Piyush Mehta <quic_piyumeht@quicinc.com>
271 lines
7.8 KiB
Plaintext
271 lines
7.8 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
|
|
/*
|
|
* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
|
|
*/
|
|
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
|
|
&soc {
|
|
kgsl_smmu: kgsl-smmu@50a0000 {
|
|
compatible = "qcom,qsmmu-v500", "qcom,adreno-smmu";
|
|
status = "okay";
|
|
reg = <0x50a0000 0x10000>,
|
|
<0x50c2000 0x20>;
|
|
reg-names = "base", "tcu-base";
|
|
#iommu-cells = <2>;
|
|
qcom,dynamic;
|
|
qcom,skip-init;
|
|
qcom,use-3-lvl-tables;
|
|
#global-interrupts = <1>;
|
|
qcom,regulator-names = "vdd";
|
|
vdd-supply = <&gpu_cx_gdsc>;
|
|
clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
|
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
|
|
<&gpucc GPU_CC_AHB_CLK>,
|
|
<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
|
|
clock-names = "gcc_gpu_memnoc_gfx_clk",
|
|
"gcc_gpu_snoc_dvm_gfx_clk",
|
|
"gpu_cc_ahb_clk",
|
|
"gpu_cc_hlos1_vote_gpu_smmu_clk";
|
|
#size-cells = <1>;
|
|
#address-cells = <1>;
|
|
ranges;
|
|
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
gfx_0_tbu: gfx_0_tbu@50c5000 {
|
|
compatible = "qcom,qsmmuv500-tbu";
|
|
reg = <0x50c5000 0x1000>,
|
|
<0x50c2200 0x8>;
|
|
reg-names = "base", "status-reg";
|
|
qcom,stream-id-range = <0x0 0x400>;
|
|
qcom,iova-width = <49>;
|
|
};
|
|
|
|
gfx_1_tbu: gfx_1_tbu@50c9000 {
|
|
compatible = "qcom,qsmmuv500-tbu";
|
|
reg = <0x50c9000 0x1000>,
|
|
<0x50c2208 0x8>;
|
|
reg-names = "base", "status-reg";
|
|
qcom,stream-id-range = <0x400 0x400>;
|
|
qcom,iova-width = <49>;
|
|
};
|
|
};
|
|
|
|
apps_smmu: apps-smmu@15000000 {
|
|
compatible = "qcom,qsmmu-v500";
|
|
status = "okay";
|
|
reg = <0x15000000 0x80000>,
|
|
<0x150c2000 0x20>;
|
|
reg-names = "base", "tcu-base";
|
|
#iommu-cells = <2>;
|
|
qcom,skip-init;
|
|
qcom,use-3-lvl-tables;
|
|
qcom,handoff-smrs = <0x420 0x2>;
|
|
#global-interrupts = <1>;
|
|
#size-cells = <1>;
|
|
#address-cells = <1>;
|
|
ranges;
|
|
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
interconnects = <&system_noc MASTER_GEM_NOC_SNOC
|
|
&config_noc SLAVE_IMEM_CFG>;
|
|
qcom,active-only;
|
|
|
|
anoc_1_tbu: anoc_1_tbu@150c5000 {
|
|
compatible = "qcom,qsmmuv500-tbu";
|
|
reg = <0x150c5000 0x1000>,
|
|
<0x150c2200 0x8>;
|
|
reg-names = "base", "status-reg";
|
|
qcom,stream-id-range = <0x0 0x400>;
|
|
qcom,iova-width = <36>;
|
|
qcom,regulator-names = "vdd";
|
|
vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu1_gdsc>;
|
|
qcom,active-only;
|
|
interconnects = <&system_noc MASTER_GEM_NOC_SNOC
|
|
&config_noc SLAVE_IMEM_CFG>;
|
|
};
|
|
|
|
anoc_2_tbu: anoc_2_tbu@150c9000 {
|
|
compatible = "qcom,qsmmuv500-tbu";
|
|
reg = <0x150c9000 0x1000>,
|
|
<0x150c2208 0x8>;
|
|
reg-names = "base", "status-reg";
|
|
qcom,stream-id-range = <0x400 0x400>;
|
|
qcom,iova-width = <36>;
|
|
qcom,regulator-names = "vdd";
|
|
vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu2_gdsc>;
|
|
qcom,active-only;
|
|
interconnects = <&system_noc MASTER_GEM_NOC_SNOC
|
|
&config_noc SLAVE_IMEM_CFG>;
|
|
};
|
|
|
|
mnoc_hf_0_tbu: mnoc_hf_0_tbu@150cd000 {
|
|
compatible = "qcom,qsmmuv500-tbu";
|
|
reg = <0x150cd000 0x1000>,
|
|
<0x150c2210 0x8>;
|
|
reg-names = "base", "status-reg";
|
|
qcom,stream-id-range = <0x800 0x400>;
|
|
qcom,iova-width = <32>;
|
|
qcom,regulator-names = "vdd";
|
|
vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>;
|
|
qcom,active-only;
|
|
interconnects = <&mmss_noc MASTER_MDP0
|
|
&mmss_noc SLAVE_MNOC_HF_MEM_NOC>;
|
|
};
|
|
|
|
mnoc_sf_0_tbu: mnoc_sf_0_tbu@150d1000 {
|
|
compatible = "qcom,qsmmuv500-tbu";
|
|
reg = <0x150d1000 0x1000>,
|
|
<0x150c2218 0x8>;
|
|
reg-names = "base", "status-reg";
|
|
qcom,stream-id-range = <0xc00 0x400>;
|
|
qcom,iova-width = <32>;
|
|
qcom,regulator-names = "vdd";
|
|
vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc>;
|
|
qcom,active-only;
|
|
interconnects = <&mmss_noc MASTER_CAMNOC_SF
|
|
&mmss_noc SLAVE_MNOC_SF_MEM_NOC>;
|
|
};
|
|
|
|
compute_dsp_tbu: compute_dsp_tbu@150d5000 {
|
|
compatible = "qcom,qsmmuv500-tbu";
|
|
reg = <0x150d5000 0x1000>,
|
|
<0x150c2220 0x8>;
|
|
reg-names = "base", "status-reg";
|
|
qcom,stream-id-range = <0x1000 0x400>;
|
|
qcom,iova-width = <32>;
|
|
/* No GDSC */
|
|
qcom,active-only;
|
|
interconnects = <&system_noc MASTER_GEM_NOC_SNOC
|
|
&config_noc SLAVE_IMEM_CFG>;
|
|
};
|
|
|
|
adsp_tbu: adsp_tbu@150d9000 {
|
|
compatible = "qcom,qsmmuv500-tbu";
|
|
reg = <0x150d9000 0x1000>,
|
|
<0x150c2228 0x8>;
|
|
reg-names = "base", "status-reg";
|
|
qcom,stream-id-range = <0x1400 0x400>;
|
|
qcom,iova-width = <32>;
|
|
qcom,regulator-names = "vdd";
|
|
vdd-supply = <&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc>;
|
|
qcom,active-only;
|
|
interconnects = <&system_noc MASTER_GEM_NOC_SNOC
|
|
&config_noc SLAVE_IMEM_CFG>;
|
|
};
|
|
};
|
|
|
|
dma_dev {
|
|
compatible = "qcom,iommu-dma";
|
|
memory-region = <&system_cma>;
|
|
};
|
|
|
|
iommu_test_device {
|
|
compatible = "qcom,iommu-debug-test";
|
|
|
|
usecase0_apps {
|
|
compatible = "qcom,iommu-debug-usecase";
|
|
iommus = <&apps_smmu 0x21 0x0>;
|
|
};
|
|
|
|
usecase1_apps_dma {
|
|
compatible = "qcom,iommu-debug-usecase";
|
|
iommus = <&apps_smmu 0x23 0x0>;
|
|
};
|
|
|
|
usecase2_kgsl {
|
|
compatible = "qcom,iommu-debug-usecase";
|
|
iommus = <&kgsl_smmu 0x7 0x0>;
|
|
};
|
|
|
|
usecase3_kgsl_dma {
|
|
compatible = "qcom,iommu-debug-usecase";
|
|
iommus = <&kgsl_smmu 0x9 0x0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&kgsl_smmu {
|
|
qcom,actlr =
|
|
/* All CBs of GFX: +15 deep PF */
|
|
<0x0 0x7ff 0x303>;
|
|
};
|
|
|
|
&apps_smmu {
|
|
qcom,actlr =
|
|
/* HF and SF TBUs: +3 deep PF */
|
|
<0x800 0x7ff 0x103>;
|
|
};
|