251 lines
6.8 KiB
Plaintext
251 lines
6.8 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
|
|
/*
|
|
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
|
|
*/
|
|
|
|
#include "waipio-vm.dtsi"
|
|
#include <dt-bindings/clock/qcom,gcc-parrot.h>
|
|
|
|
/ {
|
|
qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
|
|
<633 0x10000>, <634 0x10000>, <638 0x10000>, <663 0x10000>,
|
|
<713 0x10000>, <714 0x10000>, <715 0x10000>;
|
|
interrupt-parent = <&vgic>;
|
|
|
|
qcom,vm-config {
|
|
iomemory-ranges = <0x0 0x0a28000 0x0 0x0a28000 0x0 0x4000 0x0
|
|
0x0 0xc400000 0x0 0xc400000 0x0 0x3000 0x1
|
|
0x0 0xc42d000 0x0 0xc42d000 0x0 0x4000 0x1
|
|
0x0 0xc440000 0x0 0xc440000 0x0 0x10000 0x1
|
|
0x0 0xc450000 0x0 0xc450000 0x0 0x70000 0x1
|
|
0x0 0xc4c0000 0x0 0xc4c0000 0x0 0x10000 0x1
|
|
0x0 0xae8f000 0x0 0xae8f000 0x0 0x1000 0x0>;
|
|
|
|
gic-irq-ranges = <325 325>; /* PVM->SVM IRQ transfer */
|
|
|
|
vcpus {
|
|
affinity = "proxy";
|
|
affinity-map = <0x0 0x0>;
|
|
};
|
|
|
|
vdevices {
|
|
gvsock-message-queue-pair {
|
|
status = "disabled";
|
|
};
|
|
|
|
ddump-shm {
|
|
vdevice-type = "shm-doorbell";
|
|
generate = "/hypervisor/ddump-shm";
|
|
push-compatible = "qcom,ddump-gunyah-gen";
|
|
peer-default;
|
|
memory {
|
|
qcom,label = <0x7>;
|
|
allocate-base;
|
|
};
|
|
};
|
|
|
|
gunyah-panic-notifier-shm {
|
|
vdevice-type = "shm-doorbell";
|
|
generate = "/hypervisor/gpn-shm";
|
|
push-compatible = "qcom,gunyah-panic-gen";
|
|
peer-default;
|
|
memory {
|
|
qcom,label = <0x9>;
|
|
allocate-base;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
dmesg-dump {
|
|
compatible = "qcom,dmesg-dump";
|
|
gunyah-label = <7>;
|
|
ddump-pubkey-size = <270>;
|
|
ddump-pubkey = /bits/ 8 <0x30 0x82 0x01 0x0a 0x02 0x82 0x01 0x01 0x00 0xe6 0x4b 0x31 0x82 0x61 0x14 0xf2
|
|
0xbe 0xd1 0xe4 0xde 0xe7 0xed 0xba 0x8f 0x3b 0x23 0x5f 0x7a 0xb8 0x16 0x40 0x96
|
|
0xae 0x77 0x5e 0x1b 0xf0 0x3f 0x39 0xab 0x69 0x90 0xb1 0xd4 0x70 0xcb 0x66 0xbc
|
|
0x41 0x08 0x1d 0x37 0xdb 0x49 0xc8 0x49 0x5b 0x99 0x5c 0x32 0xbe 0x62 0xd5 0xa7
|
|
0x3c 0x0f 0xa4 0x4b 0x43 0x49 0xdb 0x54 0x69 0x06 0x0c 0xe5 0x99 0xe5 0xf9 0x1e
|
|
0x25 0x84 0x17 0x47 0x62 0x2b 0x5d 0x0d 0xec 0x5e 0xc6 0xb5 0x86 0xb9 0x75 0x6d
|
|
0xfe 0x7d 0x35 0x4f 0x35 0xc1 0x48 0x10 0x75 0x4c 0x57 0x6b 0x46 0x4b 0xff 0x5b
|
|
0x52 0x22 0x40 0x2c 0xb0 0x47 0xe1 0x47 0xc4 0xe5 0x47 0x0c 0x56 0xe8 0x17 0xd0
|
|
0x7e 0xc3 0x4d 0x9f 0xea 0xd0 0xea 0x87 0xe5 0x51 0x39 0xe8 0x45 0x4c 0x54 0x27
|
|
0x9c 0x50 0x38 0xb7 0x72 0x93 0x12 0x0b 0xa1 0x2f 0x9e 0x04 0x92 0x20 0x6e 0x31
|
|
0x42 0x87 0xe1 0xfe 0x88 0x3f 0xe5 0x09 0xe1 0xf9 0xbe 0x44 0xc6 0xbf 0x10 0x79
|
|
0x36 0x47 0x7b 0xa0 0x8e 0x27 0x31 0xa3 0x70 0x69 0x01 0x54 0x92 0xf4 0x42 0xbd
|
|
0xcd 0x7e 0x79 0x2b 0x2c 0xe1 0xd4 0xba 0x6e 0x34 0xc6 0xe6 0xc6 0x5c 0x63 0xd0
|
|
0x7f 0x39 0x1f 0xe8 0x8d 0x67 0xe6 0x27 0x67 0x0d 0x16 0x57 0x94 0xd1 0xfb 0xdf
|
|
0xce 0xaf 0xfd 0x43 0xb3 0xbe 0x5d 0x83 0x4b 0x93 0x05 0xe8 0xdf 0x04 0xad 0xac
|
|
0xeb 0xa6 0x81 0xa7 0xd5 0x04 0x63 0xbf 0x83 0xb8 0x0c 0xbc 0x20 0x18 0xb5 0x50
|
|
0xd7 0x61 0x84 0x11 0xca 0x2d 0x22 0xb3 0x29 0x02 0x03 0x01 0x00 0x01>;
|
|
};
|
|
|
|
};
|
|
|
|
&soc {
|
|
|
|
/delete-node/ interrupt-controller@17100000;
|
|
|
|
qcom,spmi@c42d000 {
|
|
status = "disabled";
|
|
};
|
|
|
|
gcc: clock-controller@100000 {
|
|
compatible = "qcom,dummycc";
|
|
clock-output-names = "gcc_clocks";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
vgic: interrupt-controller@17200000 {
|
|
compatible = "arm,gic-v3";
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x3>;
|
|
#redistributor-regions = <1>;
|
|
redistributor-stride = <0x0 0x20000>;
|
|
reg = <0x17200000 0x10000>, /* GICD */
|
|
<0x17260000 0x100000>; /* GICR * 8 */
|
|
};
|
|
|
|
tlmm: pinctrl@f000000 {
|
|
compatible = "qcom,parrot-vm-tlmm";
|
|
gpios = /bits/ 16 <98 99 10 11 12 13 64 65>;
|
|
|
|
qupv3_se11_i2c_active: qupv3_se11_i2c_sda_active {
|
|
mux {
|
|
pins = "gpio10";
|
|
function = "qup1_se3_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio10";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep {
|
|
mux {
|
|
pins = "gpio10";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio10";
|
|
drive-strength = <2>;
|
|
};
|
|
};
|
|
};
|
|
|
|
tlmm-vm-test {
|
|
pinctrl-names = "active", "sleep";
|
|
pinctrl-0 = <&qupv3_se11_i2c_active>;
|
|
pinctrl-1 = <&qupv3_se11_i2c_sleep>;
|
|
tlmm-vm-gpio-list = <&tlmm 98 0 &tlmm 99 0 &tlmm 10 0 &tlmm 11 0
|
|
&tlmm 12 0 &tlmm 13 0 &tlmm 64 0 &tlmm 65 0>;
|
|
};
|
|
|
|
tlmm-vm-mem-access {
|
|
tlmm-vm-gpio-list = <&tlmm 98 0 &tlmm 99 0 &tlmm 10 0 &tlmm 11 0
|
|
&tlmm 12 0 &tlmm 13 0 &tlmm 64 0 &tlmm 65 0>;
|
|
};
|
|
|
|
apps-smmu@15000000 {
|
|
qcom,actlr =
|
|
/* Display and camera clients, +0 PF */
|
|
<0x800 0x7ff 0x1>,
|
|
<0x2000 0xE0 0x1>,
|
|
<0x2100 0x60 0x1>,
|
|
/* For video clients, +3 PF */
|
|
<0x2180 0x27 0x103>,
|
|
/* NSP clients, +15PF */
|
|
<0x1000 0x7ff 0x303>;
|
|
};
|
|
|
|
/delete-node/ qup_common_iommu_group;
|
|
/delete-node/ qcom,qupv3_0_geni_se@9c0000;
|
|
/delete-node/ qcom,gpi-dma@900000;
|
|
/delete-node/ i2c@990000;
|
|
/delete-node/ spi@990000;
|
|
|
|
qup_iommu_group: qup_common_iommu_group {
|
|
iommu-addresses = <&gpi_dma1 0x00000000 0x00020000>,
|
|
<&qupv3_1 0x00000000 0x00020000>;
|
|
};
|
|
|
|
gpi_dma1: qcom,gpi-dma@a00000 {
|
|
compatible = "qcom,gpi-dma";
|
|
#dma-cells = <5>;
|
|
reg = <0xa00000 0x60000>;
|
|
reg-names = "gpi-top";
|
|
iommus = <&apps_smmu 0x418 0x0>;
|
|
qcom,iommu-group = <&qup_iommu_group>;
|
|
memory-region = <&qup_iommu_group>;
|
|
dma-coherent;
|
|
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,max-num-gpii = <12>;
|
|
qcom,gpii-mask = <0x40>;
|
|
qcom,ev-factor = <2>;
|
|
qcom,gpi-ee-offset = <0x10000>;
|
|
qcom,le-vm;
|
|
status = "ok";
|
|
};
|
|
|
|
/* QUPv3_1 wrapper instance */
|
|
qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
|
|
compatible = "qcom,geni-se-qup";
|
|
reg = <0xac0000 0x2000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
clock-names = "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
iommus = <&apps_smmu 0x418 0x0>;
|
|
qcom,iommu-group = <&qup_iommu_group>;
|
|
memory-region = <&qup_iommu_group>;
|
|
dma-coherent;
|
|
ranges;
|
|
status = "ok";
|
|
|
|
/* TUI over I2C */
|
|
qupv3_se9_i2c: i2c@a8c000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xa8c000 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
dmas = <&gpi_dma1 0 3 3 64 0>,
|
|
<&gpi_dma1 1 3 3 64 0>;
|
|
dma-names = "tx", "rx";
|
|
qcom,le-vm;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se9_spi: spi@a8c000 {
|
|
compatible = "qcom,spi-geni";
|
|
reg = <0xa8c000 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg-names = "se_phys";
|
|
dmas = <&gpi_dma1 0 3 1 64 0>,
|
|
<&gpi_dma1 1 3 1 64 0>;
|
|
dma-names = "tx", "rx";
|
|
spi-max-frequency = <50000000>;
|
|
qcom,le-vm;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
|
|
};
|