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Madhukar Sharma 1f12ee970d ARM: dts: qcom: Add qce device for qcs610
Add qce device for qcs610 to enable cypto capability.

Change-Id: I4c65d67567e1b76584c07a5c1a00373304a133ea
Signed-off-by: Madhukar Sharma <quic_madhukar@quicinc.com>
2025-06-10 00:13:42 +05:30

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include "sm6150.dtsi"
#include "sm6150-pmic-overlay.dtsi"
/ {
model = "Qualcomm Technologies, Inc. QCS610";
qcom,msm-name = "QCS610";
qcom,msm-id = <401 0>;
};
&soc {
eud: qcom,msm-eud@88e0000 {
compatible = "qcom,msm-eud";
interrupt-names = "eud_irq";
interrupts = <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x88e0000 0x2000>,
<0x88e4000 0x1000>;
reg-names = "eud_base", "eud_mode_mgr2";
qcom,secure-eud-en;
qcom,eud-clock-vote-req;
clocks = <&gcc GCC_AHB2PHY_WEST_CLK>;
clock-names = "eud_ahb2phy_clk";
status = "ok";
};
modem_pas: remoteproc-mss@04080000 {
compatible = "qcom,sm6150-modem-pas";
reg = <0x4080000 0x10000>;
status = "ok";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
cx-supply = <&VDD_CX_LEVEL>;
cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
mss-supply = <&VDD_MSS_LEVEL>;
mss-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
reg-names = "cx", "mss";
mboxes = <&qmp_aop 0>;
interconnects = <&aggre1_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
interconnect-names = "crypto_ddr";
memory-region = <&pil_modem_mem>;
/* Inputs from mss */
interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 0 0>,
<&modem_smp2p_in 2 0>,
<&modem_smp2p_in 1 0>,
<&modem_smp2p_in 3 0>,
<&modem_smp2p_in 7 0>;
interrupt-names = "wdog",
"fatal",
"handover",
"ready",
"stop-ack",
"shutdown-ack";
/* Outputs to mss */
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "stop";
remoteproc_modem_glink: glink-edge {
qcom,remote-pid = <1>;
transport = "smem";
mboxes = <&apss_shared 12>;
mbox-names = "mpss_smem";
interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
label = "modem";
qcom,glink-label = "mpss";
qcom,modem_qrtr {
qcom,glink-channels = "IPCRTR";
qcom,low-latency;
qcom,intents = <0x800 5
0x2000 3
0x4400 2>;
};
qcom,modem_ds {
qcom,glink-channels = "DS";
qcom,intents = <0x4000 0x2>;
};
};
};
qcom_cedev: qcedev@1de0000 {
compatible = "qcom,qcedev";
reg = <0x1de0000 0x20000>,
<0x1dc4000 0x24000>;
reg-names = "crypto-base","crypto-bam-base";
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
qcom,bam-pipe-pair = <3>;
qcom,ce-hw-instance = <0>;
qcom,ce-device = <0>;
qcom,ce-hw-shared;
qcom,bam-ee = <0>;
qcom,smmu-s1-enable;
qcom,no-clock-support;
interconnect-names = "data_path";
interconnects = <&aggre1_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
iommus = <&apps_smmu 0x0106 0x0011>,
<&apps_smmu 0x0116 0x0011>;
qcom,iommu-dma = "atomic";
};
};
&qupv3_se3_i2c {
status = "ok";
#include "smb1390.dtsi"
};
&smb1390 {
/delete-property/ interrupts;
interrupts = <0x0 0xc2 0x0 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&smb_stat_default>;
status = "ok";
};
&smb1390_charger {
/delete-property/ compatible;
compatible = "qcom,smb1390-charger-psy";
io-channels = <&pm6150_vadc ADC5_AMUX_THM3>;
io-channel-names = "cp_die_temp";
status = "ok";
};