e4def914ef
Add TPDM/TPDA/TMC/FUNNEL device node on SM6150. Change-Id: I64fb12e9bfe8510d2377ae77da6e7d84d090daf6 Signed-off-by: Venkata Talluri <quic_vtalluri@quicinc.com>
2480 lines
53 KiB
Plaintext
2480 lines
53 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,camcc-sm6150.h>
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#include <dt-bindings/clock/qcom,dispcc-sm6150.h>
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#include <dt-bindings/clock/qcom,gcc-sm6150.h>
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#include <dt-bindings/clock/qcom,gpucc-sm6150.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/interconnect/qcom,icc.h>
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#include <dt-bindings/interconnect/qcom,sm6150.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
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#include <dt-bindings/clock/qcom,videocc-sm6150.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Qualcomm Technologies, Inc. SM6150";
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compatible = "qcom,sm6150";
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qcom,msm-name = "SM6150";
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qcom,msm-id = <355 0x0>;
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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chosen {
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bootargs = "log_buf_len=2M earlycon=msm_geni_serial,0x880000 rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off";
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};
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memory { device_type = "memory"; reg = <0 0 0 0>; };
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reserved_memory: reserved-memory { };
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aliases: aliases {
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ufshc1 = &ufshc_mem; /* Embedded UFS slot */
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serial0 = &qupv3_se0_2uart;
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mmc0 = &sdhc_1; /* SDC1 eMMC slot */
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hsuart0 = &qupv3_se7_4uart;
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hsuart1 = &qupv3_se4_2uart;
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mmc1 = &sdhc_2; /* SDC2 SD card slot */
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};
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firmware: firmware {
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qcom_scm: qcom_scm { };
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x0>;
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enable-method = "psci";
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cpu-idle-states = <&SILVER_OFF &SILVER_PLL_OFF>;
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power-domains = <&CPU_PD0>;
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power-domain-names = "psci";
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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cache-size = <0x8000>;
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next-level-cache = <&L2_0>;
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#cooling-cells = <2>;
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qcom,freq-domain = <&cpufreq_hw 0 6>;
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L2_0: l2-cache {
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compatible = "cache";
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cache-size = <0x10000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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L3_0: l3-cache {
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compatible = "cache";
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cache-size = <0x100000>;
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cache-level = <3>;
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};
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};
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};
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CPU1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x100>;
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enable-method = "psci";
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cpu-idle-states = <&SILVER_OFF &SILVER_PLL_OFF>;
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power-domains = <&CPU_PD1>;
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power-domain-names = "psci";
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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cache-size = <0x8000>;
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next-level-cache = <&L2_100>;
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#cooling-cells = <2>;
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qcom,freq-domain = <&cpufreq_hw 0 6>;
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L2_100: l2-cache {
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compatible = "cache";
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cache-size = <0x10000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU2: cpu@200 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x200>;
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enable-method = "psci";
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cpu-idle-states = <&SILVER_OFF &SILVER_PLL_OFF>;
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power-domains = <&CPU_PD2>;
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power-domain-names = "psci";
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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cache-size = <0x8000>;
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next-level-cache = <&L2_200>;
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#cooling-cells = <2>;
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qcom,freq-domain = <&cpufreq_hw 0 6>;
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L2_200: l2-cache {
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compatible = "cache";
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cache-size = <0x10000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU3: cpu@300 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x300>;
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enable-method = "psci";
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cpu-idle-states = <&SILVER_OFF &SILVER_PLL_OFF>;
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power-domains = <&CPU_PD3>;
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power-domain-names = "psci";
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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cache-size = <0x8000>;
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next-level-cache = <&L2_300>;
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#cooling-cells = <2>;
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qcom,freq-domain = <&cpufreq_hw 0 6>;
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L2_300: l2-cache {
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compatible = "cache";
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cache-size = <0x10000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU4: cpu@400 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x400>;
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enable-method = "psci";
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cpu-idle-states = <&SILVER_OFF &SILVER_PLL_OFF>;
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power-domains = <&CPU_PD4>;
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power-domain-names = "psci";
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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cache-size = <0x8000>;
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next-level-cache = <&L2_400>;
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#cooling-cells = <2>;
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qcom,freq-domain = <&cpufreq_hw 0 6>;
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L2_400: l2-cache {
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compatible = "cache";
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cache-size = <0x10000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU5: cpu@500 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x500>;
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enable-method = "psci";
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cpu-idle-states = <&SILVER_OFF &SILVER_PLL_OFF>;
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power-domains = <&CPU_PD5>;
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power-domain-names = "psci";
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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cache-size = <0x8000>;
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next-level-cache = <&L2_500>;
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#cooling-cells = <2>;
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qcom,freq-domain = <&cpufreq_hw 0 6>;
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L2_500: l2-cache {
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compatible = "cache";
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cache-size = <0x10000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU6: cpu@600 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x600>;
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enable-method = "psci";
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cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
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power-domains = <&CPU_PD6>;
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power-domain-names = "psci";
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capacity-dmips-mhz = <1740>;
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dynamic-power-coefficient = <404>;
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cache-size = <0x10000>;
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next-level-cache = <&L2_600>;
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qcom,freq-domain = <&cpufreq_hw 1 2>;
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#cooling-cells = <2>;
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L2_600: l2-cache {
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compatible = "cache";
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cache-size = <0x40000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU7: cpu@700 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x700>;
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enable-method = "psci";
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cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
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power-domains = <&CPU_PD7>;
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power-domain-names = "psci";
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capacity-dmips-mhz = <1740>;
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dynamic-power-coefficient = <404>;
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cache-size = <0x10000>;
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next-level-cache = <&L2_700>;
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#cooling-cells = <2>;
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qcom,freq-domain = <&cpufreq_hw 1 2>;
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L2_700: l2-cache {
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compatible = "cache";
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cache-size = <0x40000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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core4 {
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cpu = <&CPU4>;
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};
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core5 {
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cpu = <&CPU5>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU6>;
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};
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core1 {
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cpu = <&CPU7>;
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};
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};
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};
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};
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idle-states {
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entry-method = "psci";
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SILVER_OFF: silver-c3 { /* C3 */
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compatible = "arm,idle-state";
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idle-state-name = "pc";
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entry-latency-us = <549>;
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exit-latency-us = <901>;
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min-residency-us = <1774>;
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arm,psci-suspend-param = <0x40000003>;
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local-timer-stop;
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};
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SILVER_PLL_OFF: silver-c4 { /* C4 */
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compatible = "arm,idle-state";
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idle-state-name = "rail-pc";
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entry-latency-us = <702>;
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exit-latency-us = <915>;
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min-residency-us = <4001>;
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arm,psci-suspend-param = <0x40000004>;
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local-timer-stop;
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};
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GOLD_OFF: gold-c3 { /* C3 */
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compatible = "arm,idle-state";
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idle-state-name = "pc";
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entry-latency-us = <523>;
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exit-latency-us = <1244>;
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min-residency-us = <2207>;
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arm,psci-suspend-param = <0x40000003>;
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local-timer-stop;
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};
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GOLD_RAIL_OFF: gold-c4 { /* C4 */
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compatible = "arm,idle-state";
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idle-state-name = "rail-pc";
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entry-latency-us = <526>;
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exit-latency-us = <1854>;
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min-residency-us = <5555>;
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arm,psci-suspend-param = <0x40000004>;
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local-timer-stop;
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};
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CLUSTER_OFF: cluster-d4 { /* D4 */
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compatible = "domain-idle-state";
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idle-state-name = "llcc-off";
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entry-latency-us = <2752>;
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exit-latency-us = <3048>;
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min-residency-us = <6118>;
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arm,psci-suspend-param = <0x41000044>;
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};
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CX_RET: cx-ret { /* Cx Ret */
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compatible = "domain-idle-state";
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idle-state-name = "llcc-off";
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entry-latency-us = <3263>;
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exit-latency-us = <4562>;
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min-residency-us = <8467>;
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arm,psci-suspend-param = <0x41001344>;
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};
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APSS_OFF: cluster-e3 { /* AOSS sleep */
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compatible = "domain-idle-state";
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idle-state-name = "llcc-off";
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entry-latency-us = <3638>;
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exit-latency-us = <6562>;
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min-residency-us = <9826>;
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arm,psci-suspend-param = <0x4100b344>;
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};
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};
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soc: soc { };
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};
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&reserved_memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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hyp_region: hyp_region@85700000 {
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no-map;
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reg = <0x0 0x85700000 0x0 0x600000>;
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};
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xbl_aop_mem: xbl_aop_mem@85e00000 {
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no-map;
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reg = <0x0 0x85e00000 0x0 0x120000>;
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};
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aop_cmd_db: memory@85f20000 {
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compatible = "qcom,cmd-db";
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reg = <0x0 0x85f20000 0x0 0x20000>;
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no-map;
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};
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sec_apps_mem: sec_apps_region@85fff000 {
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no-map;
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reg = <0x0 0x85fff000 0x0 0x1000>;
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};
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smem_region: smem@86000000 {
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no-map;
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reg = <0x0 0x86000000 0x0 0x200000>;
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};
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removed_region: removed_region@86200000 {
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no-map;
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reg = <0x0 0x86200000 0x0 0x2d00000>;
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};
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pil_camera_mem: camera_region@8ab00000 {
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no-map;
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reg = <0x0 0x8ab00000 0x0 0x500000>;
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};
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pil_modem_mem: modem_region@8b000000 {
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no-map;
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reg = <0x0 0x8b000000 0x0 0x8400000>;
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};
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pil_video_mem: pil_video_region@93400000 {
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no-map;
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reg = <0x0 0x93400000 0x0 0x500000>;
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};
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wlan_msa_mem: wlan_msa_region@93900000 {
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no-map;
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reg = <0x0 0x93900000 0x0 0x200000>;
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};
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pil_cdsp_mem: cdsp_regions@93b00000 {
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no-map;
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reg = <0x0 0x93b00000 0x0 0x1e00000>;
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};
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pil_adsp_mem: pil_adsp_region@95900000 {
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no-map;
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reg = <0x0 0x95900000 0x0 0x1e00000>;
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};
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pil_ipa_fw_mem: ips_fw_region@97700000 {
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no-map;
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reg = <0x0 0x97700000 0x0 0x10000>;
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};
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pil_ipa_gsi_mem: ipa_gsi_region@97710000 {
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no-map;
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reg = <0x0 0x97710000 0x0 0x5000>;
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};
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pil_gpu_mem: gpu_region@97715000 {
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no-map;
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reg = <0x0 0x97715000 0x0 0x2000>;
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};
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qseecom_mem: qseecom_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x1400000>;
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};
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kinfo_mem: debug_kinfo_region {
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alloc-ranges = <0x0 0x00000000 0xffffffff 0xffffffff>;
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size = <0x0 0x1000>;
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no-map;
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};
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cdsp_sec_mem: cdsp_sec_regions@9f800000 {
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no-map;
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reg = <0x0 0x9f800000 0x0 0x1e00000>;
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};
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adsp_mem: adsp_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x800000>;
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};
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va_md_mem: va_md_mem_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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size = <0 0x1000000>;
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};
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sdsp_mem: sdsp_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0 0x00000000 0 0xffffffff>;
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reusable;
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alignment = <0 0x400000>;
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size = <0 0x400000>;
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};
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user_contig_mem: user_contig_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x1000000>;
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};
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qseecom_ta_mem: qseecom_ta_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0 0x00000000 0 0xffffffff>;
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reusable;
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alignment = <0 0x400000>;
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size = <0 0x1000000>;
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};
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sp_mem: sp_region { /* SPSS-HLOS ION shared mem */
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compatible = "shared-dma-pool";
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alloc-ranges = <0 0x00000000 0 0xffffffff>; /* 32-bit */
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reusable;
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alignment = <0 0x400000>;
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size = <0 0x800000>;
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};
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secure_display_memory: secure_display_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0 0x00000000 0 0xffffffff>;
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reusable;
|
|
alignment = <0 0x400000>;
|
|
size = <0 0x8c00000>;
|
|
};
|
|
|
|
cont_splash_memory: splash_region {
|
|
reg = <0x0 0x9c000000 0x0 0x0f00000>;
|
|
label = "cont_splash_region";
|
|
};
|
|
|
|
dfps_data_memory: dfps_data_region@9cf00000 {
|
|
reg = <0x0 0x9cf00000 0x0 0x0100000>;
|
|
label = "dfps_data_region";
|
|
};
|
|
|
|
disp_rdump_memory: disp_rdump_region@9c000000 {
|
|
reg = <0x0 0x9c000000 0x0 0x01000000>;
|
|
label = "disp_rdump_region";
|
|
};
|
|
|
|
dump_mem: mem_dump_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0 0x00000000 0 0xffffffff>;
|
|
reusable;
|
|
size = <0 0x2800000>;
|
|
};
|
|
|
|
/* global autoconfigured region for contiguous allocations */
|
|
system_cma: linux,cma {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x0 0x400000>;
|
|
size = <0x0 0x2000000>;
|
|
linux,cma-default;
|
|
};
|
|
};
|
|
|
|
&soc {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0 0 0xffffffff>;
|
|
compatible = "simple-bus";
|
|
|
|
psci {
|
|
compatible = "arm,psci-1.0";
|
|
method = "smc";
|
|
|
|
CPU_PD0: cpu-pd0 {
|
|
#power-domain-cells = <0>;
|
|
power-domains = <&CLUSTER_PD>;
|
|
};
|
|
|
|
CPU_PD1: cpu-pd1 {
|
|
#power-domain-cells = <0>;
|
|
power-domains = <&CLUSTER_PD>;
|
|
};
|
|
|
|
CPU_PD2: cpu-pd2 {
|
|
#power-domain-cells = <0>;
|
|
power-domains = <&CLUSTER_PD>;
|
|
};
|
|
|
|
CPU_PD3: cpu-pd3 {
|
|
#power-domain-cells = <0>;
|
|
power-domains = <&CLUSTER_PD>;
|
|
};
|
|
|
|
CPU_PD4: cpu-pd4 {
|
|
#power-domain-cells = <0>;
|
|
power-domains = <&CLUSTER_PD>;
|
|
};
|
|
|
|
CPU_PD5: cpu-pd5 {
|
|
#power-domain-cells = <0>;
|
|
power-domains = <&CLUSTER_PD>;
|
|
};
|
|
|
|
CPU_PD6: cpu-pd6 {
|
|
#power-domain-cells = <0>;
|
|
power-domains = <&CLUSTER_PD>;
|
|
};
|
|
|
|
CPU_PD7: cpu-pd7 {
|
|
#power-domain-cells = <0>;
|
|
power-domains = <&CLUSTER_PD>;
|
|
};
|
|
|
|
CLUSTER_PD: cluster-pd {
|
|
#power-domain-cells = <0>;
|
|
domain-idle-states = <&CLUSTER_OFF &CX_RET &APSS_OFF>;
|
|
};
|
|
};
|
|
|
|
slimbam_aud: bamdma@62d84000 {
|
|
compatible = "qcom,bam-v1.7.0";
|
|
qcom,controlled-remotely;
|
|
reg = <0x62d84000 0x2a000>;
|
|
reg-names = "bam";
|
|
num-channels = <31>;
|
|
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
|
|
#dma-cells = <1>;
|
|
qcom,ee = <1>;
|
|
qcom,num-ees = <2>;
|
|
};
|
|
|
|
slim_aud: slim@62dc0000 {
|
|
compatible = "qcom,slim-ngd-v1.5.0";
|
|
reg = <0x62dc0000 0x2c000>;
|
|
reg-names = "ctrl";
|
|
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&slimbam_aud 3>, <&slimbam_aud 4>;
|
|
dma-names = "rx", "tx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
slimbam_qca: bamdma@62e04000 {
|
|
compatible = "qcom,bam-v1.7.0";
|
|
qcom,controlled-remotely;
|
|
reg = <0x62e04000 0x20000>;
|
|
reg-names = "bam";
|
|
num-channels = <31>;
|
|
interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
|
|
#dma-cells = <1>;
|
|
qcom,ee = <1>;
|
|
qcom,num-ees = <2>;
|
|
};
|
|
|
|
slim_qca: slim@62e40000 {
|
|
compatible = "qcom,slim-ngd-v1.5.0";
|
|
reg = <0x62e40000 0x2c000>;
|
|
reg-names = "ctrl";
|
|
interrupts = <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&slimbam_qca 3>, <&slimbam_qca 4>;
|
|
dma-names = "rx", "tx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
apps_rsc: rsc@18200000 {
|
|
label = "apps_rsc";
|
|
compatible = "qcom,rpmh-rsc";
|
|
reg = <0x18200000 0x10000>,
|
|
<0x18210000 0x10000>,
|
|
<0x18220000 0x10000>;
|
|
reg-names = "drv-0", "drv-1", "drv-2";
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,drv-count = <3>;
|
|
power-domains = <&CLUSTER_PD>;
|
|
|
|
apps_rsc_drv2: drv@2 {
|
|
qcom,drv-id = <2>;
|
|
qcom,tcs-offset = <0xd00>;
|
|
channel@0 {
|
|
qcom,tcs-config = <ACTIVE_TCS 2>,
|
|
<SLEEP_TCS 3>,
|
|
<WAKE_TCS 3>,
|
|
<CONTROL_TCS 1>,
|
|
<FAST_PATH_TCS 0>;
|
|
};
|
|
|
|
apps_bcm_voter: bcm_voter {
|
|
compatible = "qcom,bcm-voter";
|
|
};
|
|
|
|
rpmhcc: qcom,rpmhclk {
|
|
compatible = "qcom,sm6150-rpmh-clk";
|
|
#clock-cells = <1>;
|
|
status = "okay";
|
|
};
|
|
};
|
|
};
|
|
|
|
disp_rsc: rsc@af20000 {
|
|
label = "disp_rsc";
|
|
compatible = "qcom,rpmh-rsc";
|
|
reg = <0xaf20000 0x10000>;
|
|
reg-names = "drv-0";
|
|
qcom,drv-count = <1>;
|
|
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
disp_rsc_drv0: drv@0 {
|
|
qcom,drv-id = <0>;
|
|
qcom,tcs-offset = <0x1c00>;
|
|
channel@0 {
|
|
qcom,tcs-config = <SLEEP_TCS 1>,
|
|
<WAKE_TCS 1>,
|
|
<ACTIVE_TCS 2>,
|
|
<CONTROL_TCS 0>,
|
|
<FAST_PATH_TCS 0>;
|
|
};
|
|
|
|
disp_bcm_voter: bcm_voter {
|
|
compatible = "qcom,bcm-voter";
|
|
qcom,tcs-wait = <QCOM_ICC_TAG_AMC>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cluster-device {
|
|
compatible = "qcom,lpm-cluster-dev";
|
|
power-domains = <&CLUSTER_PD>;
|
|
};
|
|
|
|
intc: interrupt-controller@17a00000 {
|
|
compatible = "arm,gic-v3";
|
|
#interrupt-cells = <3>;
|
|
interrupt-controller;
|
|
#redistributor-regions = <1>;
|
|
redistributor-stride = <0x0 0x20000>;
|
|
reg = <0x17a00000 0x10000>, /* GICD */
|
|
<0x17a60000 0x100000>; /* GICR * 8 */
|
|
interrupts = <1 9 4>;
|
|
interrupt-parent = <&intc>;
|
|
};
|
|
|
|
pdc: interrupt-controller@b220000 {
|
|
compatible = "qcom,sm6150-pdc", "qcom,pdc";
|
|
reg = <0xb220000 0x30000>, <0x17c000f0 0x60>;
|
|
qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
|
|
#interrupt-cells = <2>;
|
|
interrupt-parent = <&intc>;
|
|
interrupt-controller;
|
|
};
|
|
|
|
msm_gpu: qcom,kgsl-3d0@5000000 { };
|
|
|
|
spmi_bus: qcom,spmi@c440000 {
|
|
compatible = "qcom,spmi-pmic-arb";
|
|
reg = <0xc440000 0x1100>,
|
|
<0xc600000 0x2000000>,
|
|
<0xe600000 0x100000>,
|
|
<0xe700000 0xa0000>,
|
|
<0xc40a000 0x26000>;
|
|
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
|
|
interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "periph_irq";
|
|
interrupt-controller;
|
|
#interrupt-cells = <4>;
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
cell-index = <0>;
|
|
qcom,channel = <0>;
|
|
qcom,ee = <0>;
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <1 1 0xf08>,
|
|
<1 2 0xf08>,
|
|
<1 3 0xf08>,
|
|
<1 0 0xf08>;
|
|
clock-frequency = <19200000>;
|
|
};
|
|
|
|
timer@17c20000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
compatible = "arm,armv7-timer-mem";
|
|
reg = <0x17c20000 0x1000>;
|
|
clock-frequency = <19200000>;
|
|
|
|
frame@17c21000 {
|
|
frame-number = <0>;
|
|
interrupts = <0 8 0x4>,
|
|
<0 6 0x4>;
|
|
reg = <0x17c21000 0x1000>,
|
|
<0x17c22000 0x1000>;
|
|
};
|
|
|
|
frame@17c23000 {
|
|
frame-number = <1>;
|
|
interrupts = <0 9 0x4>;
|
|
reg = <0x17c23000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c25000 {
|
|
frame-number = <2>;
|
|
interrupts = <0 10 0x4>;
|
|
reg = <0x17c25000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c27000 {
|
|
frame-number = <3>;
|
|
interrupts = <0 11 0x4>;
|
|
reg = <0x17c27000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c29000 {
|
|
frame-number = <4>;
|
|
interrupts = <0 12 0x4>;
|
|
reg = <0x17c29000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c2b000 {
|
|
frame-number = <5>;
|
|
interrupts = <0 13 0x4>;
|
|
reg = <0x17c2b000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c2d000 {
|
|
frame-number = <6>;
|
|
interrupts = <0 14 0x4>;
|
|
reg = <0x17c2d000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
clocks {
|
|
xo_board: xo_board {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <38400000>;
|
|
clock-output-names = "xo_board";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
sleep_clk: sleep_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <32000>;
|
|
clock-output-names = "sleep_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
};
|
|
|
|
camnoc_virt: interconnect@0 {
|
|
compatible = "qcom,sm6150-camnoc_virt";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
ipa_virt: interconnect@1 {
|
|
compatible = "qcom,sm6150-ipa_virt";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
mc_virt: interconnect@2 {
|
|
compatible = "qcom,sm6150-mc_virt";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos", "disp";
|
|
qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
|
|
};
|
|
|
|
dc_noc: interconnect@9160000 {
|
|
reg = <0x9160000 0x3200>;
|
|
compatible = "qcom,sm6150-dc_noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
gem_noc: interconnect@9680000 {
|
|
reg = <0x9680000 0x3e200>;
|
|
compatible = "qcom,sm6150-gem_noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos", "disp";
|
|
qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
|
|
};
|
|
|
|
config_noc: interconnect@1500000 {
|
|
reg = <0x1500000 0x5080>;
|
|
compatible = "qcom,sm6150-config_noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
system_noc: interconnect@1620000 {
|
|
reg = <0x1620000 0x1f300>;
|
|
compatible = "qcom,sm6150-system_noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
aggre1_noc: interconnect@1700000 {
|
|
reg = <0x1700000 0x3f200>;
|
|
compatible = "qcom,sm6150-aggre1_noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
|
|
<&gcc GCC_AGGRE_USB2_SEC_AXI_CLK>,
|
|
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
|
|
};
|
|
|
|
mmss_noc: interconnect@1740000 {
|
|
reg = <0x1740000 0x1c100>;
|
|
compatible = "qcom,sm6150-mmss_noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos", "disp";
|
|
qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
|
|
};
|
|
|
|
thermal_zones: thermal-zones {
|
|
};
|
|
|
|
gcc: clock-controller@100000 {
|
|
compatible = "qcom,sm6150-gcc", "syscon";
|
|
reg = <0x100000 0x1f0000>;
|
|
reg-name = "cc_base";
|
|
vdd_cx-supply = <&VDD_CX_LEVEL>;
|
|
vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>;
|
|
vdd_mx-supply = <&VDD_MX_LEVEL>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK_A>,
|
|
<&sleep_clk>;
|
|
clock-names = "bi_tcxo",
|
|
"bi_tcxo_ao",
|
|
"sleep_clk";
|
|
protected-clocks = <GCC_SDR_CORE_CLK>,
|
|
<GCC_SDR_WR0_MEM_CLK>,
|
|
<GCC_SDR_WR1_MEM_CLK>,
|
|
<GCC_SDR_WR2_MEM_CLK>,
|
|
<GCC_SDR_CSR_HCLK>,
|
|
<GCC_SDR_PRI_MI2S_CLK>,
|
|
<GCC_SDR_SEC_MI2S_CLK>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
camcc: clock-controller@ad00000 {
|
|
compatible = "qcom,sm6150-camcc", "syscon";
|
|
reg = <0xad00000 0x10000>;
|
|
reg-name = "cc_base";
|
|
vdd_cx-supply = <&VDD_CX_LEVEL>;
|
|
vdd_mx-supply = <&VDD_MX_LEVEL>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "bi_tcxo";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
dispcc: clock-controller@af00000 {
|
|
compatible = "qcom,sm6150-dispcc", "syscon";
|
|
reg = <0xaf00000 0x20000>;
|
|
reg-name = "cc_base";
|
|
vdd_cx-supply = <&VDD_CX_LEVEL>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
|
|
clock-names = "bi_tcxo", "gpll0";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
gpucc: clock-controller@5090000 {
|
|
compatible = "qcom,sm6150-gpucc", "syscon";
|
|
reg = <0x5090000 0x9000>;
|
|
reg-name = "cc_base";
|
|
vdd_cx-supply = <&VDD_CX_LEVEL>;
|
|
vdd_mx-supply = <&VDD_MX_LEVEL>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
|
|
clock-names = "bi_tcxo", "gpll0";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
videocc: clock-controller@ab00000 {
|
|
compatible = "qcom,sm6150-videocc", "syscon";
|
|
reg = <0xab00000 0x10000>;
|
|
reg-name = "cc_base";
|
|
vdd_cx-supply = <&VDD_CX_LEVEL>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
|
|
clock-names = "bi_tcxo", "sleep_clk";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
apsscc: syscon@182a0000 {
|
|
compatible = "syscon";
|
|
reg = <0x182a0000 0x1c>;
|
|
};
|
|
|
|
mccc: syscon@90b0000 {
|
|
compatible = "syscon";
|
|
reg = <0x90b0000 0x54>;
|
|
};
|
|
|
|
debugcc: debug-clock-controller@0 {
|
|
compatible = "qcom,sm6150-debugcc";
|
|
qcom,apsscc = <&apsscc>;
|
|
qcom,camcc = <&camcc>;
|
|
qcom,dispcc = <&dispcc>;
|
|
qcom,gcc = <&gcc>;
|
|
qcom,gpucc = <&gpucc>;
|
|
qcom,mccc = <&mccc>;
|
|
qcom,videocc = <&videocc>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "xo_clk_src";
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
cpufreq_hw: cpufreq@18323000 {
|
|
compatible = "qcom,cpufreq-hw";
|
|
reg = <0x18323000 0x1400>, <0x18325800 0x1400>;
|
|
reg-names = "freq-domain0", "freq-domain1";
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
|
|
clock-names = "xo", "alternate";
|
|
#freq-domain-cells = <2>;
|
|
};
|
|
|
|
llcc: cache-controller@9200000 {
|
|
compatible = "qcom,sm6150-llcc";
|
|
reg = <0x9200000 0x50000>, <0x9600000 0x50000>;
|
|
reg-names = "llcc_base", "llcc_broadcast_or_base";
|
|
cap-based-alloc-and-pwr-collapse;
|
|
};
|
|
|
|
llcc_pmu: llcc-pmu@90cc000 {
|
|
compatible = "qcom,llcc-pmu-ver2";
|
|
reg = <0x090cc000 0x300>;
|
|
reg-names = "lagg-base";
|
|
};
|
|
|
|
wdog: qcom,wdt@17c10000 {
|
|
compatible = "qcom,msm-watchdog";
|
|
reg = <0x17c10000 0x1000>;
|
|
reg-names = "wdt-base";
|
|
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,bark-time = <11000>;
|
|
qcom,pet-time = <9360>;
|
|
qcom,ipi-ping;
|
|
qcom,wakeup-enable;
|
|
};
|
|
|
|
cpu_pmu: cpu-pmu {
|
|
compatible = "arm,armv8-pmuv3";
|
|
qcom,irq-is-percpu;
|
|
interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
qcom,pmu {
|
|
compatible = "qcom,pmu";
|
|
qcom,long-counter;
|
|
qcom,pmu-events-tbl =
|
|
< 0x0008 0xFF 0xFF 0xFF >,
|
|
< 0x0011 0xFF 0xFF 0xFF >,
|
|
< 0x0017 0xFF 0xFF 0xFF >,
|
|
< 0x002A 0xFF 0xFF 0xFF >,
|
|
< 0x1000 0xFF 0xFF 0xFF >;
|
|
};
|
|
|
|
ddr_freq_table: ddr-freq-table {
|
|
qcom,freq-tbl =
|
|
< 200000 >,
|
|
< 300000 >,
|
|
< 451000 >,
|
|
< 547000 >,
|
|
< 681000 >,
|
|
< 768000 >,
|
|
< 1017000 >,
|
|
< 1353000 >,
|
|
< 1555000 >,
|
|
< 1804000 >;
|
|
};
|
|
|
|
llcc_freq_table: llcc-freq-table {
|
|
qcom,freq-tbl =
|
|
< 150000 >,
|
|
< 300000 >,
|
|
< 466000 >,
|
|
< 600000 >,
|
|
< 806000 >,
|
|
< 933000 >;
|
|
};
|
|
|
|
qcom_dcvs: qcom,dcvs {
|
|
compatible = "qcom,dcvs";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
qcom_ddr_dcvs_hw: ddr {
|
|
compatible = "qcom,dcvs-hw";
|
|
qcom,dcvs-hw-type = <0>;
|
|
qcom,bus-width = <4>;
|
|
qcom,freq-tbl = <&ddr_freq_table>;
|
|
|
|
ddr_dcvs_sp: sp {
|
|
compatible = "qcom,dcvs-path";
|
|
qcom,dcvs-path-type = <0>;
|
|
interconnects = <&mc_virt MASTER_LLCC
|
|
&mc_virt SLAVE_EBI1>;
|
|
};
|
|
};
|
|
|
|
qcom_llcc_dcvs_hw: llcc {
|
|
compatible = "qcom,dcvs-hw";
|
|
qcom,dcvs-hw-type = <1>;
|
|
qcom,bus-width = <16>;
|
|
qcom,freq-tbl = <&llcc_freq_table>;
|
|
|
|
llcc_dcvs_sp: sp {
|
|
compatible = "qcom,dcvs-path";
|
|
qcom,dcvs-path-type = <0>;
|
|
interconnects = <&gem_noc MASTER_APPSS_PROC
|
|
&gem_noc SLAVE_LLCC>;
|
|
};
|
|
};
|
|
|
|
qcom_l3_dcvs_hw: l3 {
|
|
compatible = "qcom,dcvs-hw";
|
|
qcom,dcvs-hw-type = <2>;
|
|
qcom,bus-width = <32>;
|
|
qcom,ftbl-row-size = <0x20>;
|
|
reg = <0x18321000 0x4000>, <0x18321110 0x500>;
|
|
reg-names = "l3-base", "l3tbl-base";
|
|
|
|
l3_dcvs_sp: sp {
|
|
compatible = "qcom,dcvs-path";
|
|
qcom,dcvs-path-type = <0>;
|
|
qcom,shared-offset = <0x0920>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom_memlat: qcom,memlat {
|
|
compatible = "qcom,memlat";
|
|
|
|
ddr {
|
|
compatible = "qcom,memlat-grp";
|
|
qcom,target-dev = <&qcom_ddr_dcvs_hw>;
|
|
qcom,sampling-path = <&ddr_dcvs_sp>;
|
|
qcom,miss-ev = <0x1000>;
|
|
|
|
silver {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
|
|
qcom,cpufreq-memfreq-tbl =
|
|
< 748000 300000 >,
|
|
< 1017600 451000 >,
|
|
< 1209600 547000 >,
|
|
< 1516800 768000 >,
|
|
< 1804800 1017000 >;
|
|
qcom,sampling-enabled;
|
|
};
|
|
|
|
silver-compute {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
|
|
qcom,cpufreq-memfreq-tbl =
|
|
< 748800 300000 >,
|
|
< 1209600 451000 >,
|
|
< 1593600 547000 >,
|
|
< 1804800 768000 >;
|
|
qcom,sampling-enabled;
|
|
qcom,compute-mon;
|
|
};
|
|
|
|
gold {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <&CPU6 &CPU7>;
|
|
qcom,cpufreq-memfreq-tbl =
|
|
< 768000 451000 >,
|
|
< 1017600 547000 >,
|
|
< 1209600 1017000 >,
|
|
< 1708800 1555000 >,
|
|
< 2208000 1804000 >;
|
|
qcom,sampling-enabled;
|
|
};
|
|
|
|
gold-compute {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <&CPU6 &CPU7>;
|
|
qcom,cpufreq-memfreq-tbl =
|
|
< 1017600 300000 >,
|
|
< 1209600 547000 >,
|
|
< 1516800 768000 >,
|
|
< 1708800 1017000 >,
|
|
< 2208000 1804000 >;
|
|
qcom,sampling-enabled;
|
|
qcom,compute-mon;
|
|
};
|
|
};
|
|
|
|
llcc {
|
|
compatible = "qcom,memlat-grp";
|
|
qcom,target-dev = <&qcom_llcc_dcvs_hw>;
|
|
qcom,sampling-path = <&llcc_dcvs_sp>;
|
|
qcom,miss-ev = <0x2A>;
|
|
|
|
silver {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
|
|
qcom,cpufreq-memfreq-tbl =
|
|
< 748000 150000 >,
|
|
< 1209600 300000 >,
|
|
< 1516800 466000 >,
|
|
< 1804800 600000 >;
|
|
qcom,sampling-enabled;
|
|
};
|
|
|
|
gold {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <&CPU6 &CPU7>;
|
|
qcom,cpufreq-memfreq-tbl =
|
|
< 768000 300000 >,
|
|
< 1017600 466000 >,
|
|
< 1209600 600000 >,
|
|
< 1708800 806000 >,
|
|
< 2208000 933000 >;
|
|
qcom,sampling-enabled;
|
|
};
|
|
};
|
|
|
|
l3 {
|
|
compatible = "qcom,memlat-grp";
|
|
qcom,target-dev = <&qcom_l3_dcvs_hw>;
|
|
qcom,sampling-path = <&l3_dcvs_sp>;
|
|
qcom,miss-ev = <0x17>;
|
|
|
|
silver {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
|
|
qcom,cpufreq-memfreq-tbl =
|
|
< 576000 300000 >,
|
|
< 1017600 556800 >,
|
|
< 1209660 806400 >,
|
|
< 1516800 940800 >,
|
|
< 1804800 1363200 >;
|
|
qcom,sampling-enabled;
|
|
};
|
|
|
|
gold {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <&CPU6 &CPU7>;
|
|
qcom,cpufreq-memfreq-tbl =
|
|
< 1017600 556800 >,
|
|
< 1209600 806400 >,
|
|
< 1516800 940800 >,
|
|
< 1708800 1209600 >,
|
|
< 2208000 1363200 >;
|
|
qcom,sampling-enabled;
|
|
};
|
|
};
|
|
};
|
|
|
|
bwmon_llcc: qcom,bwmon-llcc@90b6400 {
|
|
compatible = "qcom,bwmon4";
|
|
reg = <0x90b6300 0x300>, <0x90b6200 0x200>;
|
|
reg-names = "base", "global_base";
|
|
interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,mport = <0>;
|
|
qcom,hw-timer-hz = <19200000>;
|
|
qcom,count-unit = <0x10000>;
|
|
qcom,target-dev = <&qcom_llcc_dcvs_hw>;
|
|
};
|
|
|
|
bwmon_ddr: qcom,bwmon-ddr@90cd000 {
|
|
compatible = "qcom,bwmon5";
|
|
reg = <0x90cd000 0x1000>;
|
|
reg-names = "base";
|
|
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,hw-timer-hz = <19200000>;
|
|
qcom,count-unit = <0x10000>;
|
|
qcom,target-dev = <&qcom_ddr_dcvs_hw>;
|
|
};
|
|
|
|
ufsphy_mem: ufsphy_mem@1d87000 {
|
|
reg = <0x1d87000 0xe00>; /* PHY regs */
|
|
reg-names = "phy_mem";
|
|
#phy-cells = <0>;
|
|
|
|
lanes-per-direction = <1>;
|
|
|
|
clock-names = "ref_clk_src",
|
|
"ref_clk",
|
|
"ref_aux_clk";
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&gcc GCC_UFS_MEM_CLKREF_CLK>,
|
|
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
|
|
|
|
resets = <&ufshc_mem 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ufshc_mem: ufshc@1d84000 {
|
|
compatible = "qcom,ufshc";
|
|
reg = <0x1d84000 0x3000>,
|
|
<0x1d90000 0x8000>;
|
|
reg-names = "ufs_mem", "ice";
|
|
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
|
|
phys = <&ufsphy_mem>;
|
|
phy-names = "ufsphy";
|
|
#reset-cells = <1>;
|
|
|
|
lanes-per-direction = <1>;
|
|
limit-phy-submode = <0>;
|
|
dev-ref-clk-freq = <0>; /* 19.2 MHz */
|
|
spm-level = <5>;
|
|
|
|
clock-names =
|
|
"core_clk",
|
|
"bus_aggr_clk",
|
|
"iface_clk",
|
|
"core_clk_unipro",
|
|
"core_clk_ice",
|
|
"ref_clk",
|
|
"tx_lane0_sync_clk",
|
|
"rx_lane0_sync_clk";
|
|
clocks =
|
|
<&gcc GCC_UFS_PHY_AXI_CLK>,
|
|
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
|
|
<&gcc GCC_UFS_PHY_AHB_CLK>,
|
|
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
|
|
<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK>,
|
|
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
|
|
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>;
|
|
freq-table-hz =
|
|
<50000000 200000000>,
|
|
<0 0>,
|
|
<0 0>,
|
|
<37500000 150000000>,
|
|
<75000000 300000000>,
|
|
<0 0>,
|
|
<0 0>,
|
|
<0 0>;
|
|
|
|
interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
|
|
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
|
|
interconnect-names = "ufs-ddr", "cpu-ufs";
|
|
|
|
qcom,ufs-bus-bw,name = "ufshc_mem";
|
|
qcom,ufs-bus-bw,num-cases = <12>;
|
|
qcom,ufs-bus-bw,num-paths = <2>;
|
|
qcom,ufs-bus-bw,vectors-KBps =
|
|
/*
|
|
* During HS G3 UFS runs at nominal voltage corner, vote
|
|
* higher bandwidth to push other buses in the data path
|
|
* to run at nominal to achieve max throughput.
|
|
* 4GBps pushes BIMC to run at nominal.
|
|
* 200MBps pushes CNOC to run at nominal.
|
|
* Vote for half of this bandwidth for HS G3 1-lane.
|
|
* For max bandwidth, vote high enough to push the buses
|
|
* to run in turbo voltage corner.
|
|
*/
|
|
<0 0>, <0 0>, /* No vote */
|
|
<922 0>, <1000 0>, /* PWM G1 */
|
|
<1844 0>, <1000 0>, /* PWM G2 */
|
|
<3688 0>, <1000 0>, /* PWM G3 */
|
|
<7376 0>, <1000 0>, /* PWM G4 */
|
|
<127796 0>, <1000 0>, /* HS G1 RA */
|
|
<255591 0>, <1000 0>, /* HS G2 RA */
|
|
<2097152 0>, <102400 0>, /* HS G3 RA */
|
|
<149422 0>, <1000 0>, /* HS G1 RB */
|
|
<298189 0>, <1000 0>, /* HS G2 RB */
|
|
<2097152 0>, <102400 0>, /* HS G3 RB */
|
|
<7643136 0>, <307200 0>; /* Max. bandwidth */
|
|
|
|
qcom,bus-vector-names = "MIN",
|
|
"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
|
|
"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1",
|
|
"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",
|
|
"MAX";
|
|
|
|
reset-gpios = <&tlmm 123 GPIO_ACTIVE_LOW>;
|
|
|
|
resets = <&gcc GCC_UFS_PHY_BCR>;
|
|
reset-names = "rst";
|
|
non-removable;
|
|
|
|
iommus = <&apps_smmu 0x300 0x0>;
|
|
qcom,iommu-dma = "fastmap";
|
|
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
|
|
qcom,iommu-geometry = <0x40000000 0x10000000>;
|
|
|
|
dma-coherent;
|
|
|
|
nvmem-cells = <&boot_config>;
|
|
nvmem-cell-names = "boot_conf";
|
|
boot_device_type = <0x4>;
|
|
|
|
status = "disabled";
|
|
|
|
qos0 {
|
|
mask = <0xc0>;
|
|
vote = <67>;
|
|
};
|
|
|
|
qos1 {
|
|
mask = <0x3f>;
|
|
vote = <67>;
|
|
};
|
|
};
|
|
|
|
sdhc1_opp_table: sdhc1-opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-100000000 {
|
|
opp-hz = /bits/ 64 <100000000>;
|
|
opp-peak-kBps = <200000 150000>;
|
|
opp-avg-kBps = <104000 0>;
|
|
};
|
|
|
|
opp-384000000 {
|
|
opp-hz = /bits/ 64 <384000000>;
|
|
opp-peak-kBps = <2718822 1359411>;
|
|
opp-avg-kBps = <400000 0>;
|
|
};
|
|
};
|
|
|
|
sdhc_1: sdhci@7c4000 {
|
|
compatible = "qcom,sdhci-msm-v5";
|
|
reg = <0x7c4000 0x1000>, <0x7c5000 0x1000>, <0x7C8000 0x8000>;
|
|
reg-names = "hc", "cqhci", "ice";
|
|
|
|
interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "hc_irq", "pwr_irq";
|
|
|
|
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
|
|
<&gcc GCC_SDCC1_APPS_CLK>,
|
|
<&gcc GCC_SDCC1_ICE_CORE_CLK>;
|
|
clock-names = "iface", "core", "ice_core";
|
|
|
|
qcom,ice-clk-rates = <300000000 75000000>;
|
|
|
|
qcom,devfreq,freq-table = <50000000 200000000>;
|
|
|
|
bus-width = <8>;
|
|
qcom,restore-after-cx-collapse;
|
|
supports-cqe;
|
|
|
|
mmc-ddr-1_8v;
|
|
mmc-hs200-1_8v;
|
|
mmc-hs400-1_8v;
|
|
mmc-hs400-enhanced-strobe;
|
|
non-removable;
|
|
|
|
interconnects = <&aggre1_noc MASTER_SDCC_1 &mc_virt SLAVE_EBI1>,
|
|
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_1>;
|
|
interconnect-names = "sdhc-ddr","cpu-sdhc";
|
|
|
|
operating-points-v2 = <&sdhc1_opp_table>;
|
|
/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
|
|
qcom,dll-hsr-list = <0x000F642C 0x0 0x0 0x00010800 0x80040868>;
|
|
no-sd;
|
|
no-sdio;
|
|
|
|
iommus = <&apps_smmu 0x02C0 0x0>;
|
|
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
|
|
qcom,iommu-geometry = <0x40000000 0x10000000>;
|
|
|
|
qcom,iommu-dma = "fastmap";
|
|
dma-coherent;
|
|
|
|
nvmem-cells = <&boot_config>;
|
|
nvmem-cell-names = "boot_conf";
|
|
boot_device_type = <0x0>;
|
|
|
|
cap-mmc-hw-reset;
|
|
|
|
status = "disabled";
|
|
|
|
qos0 {
|
|
mask = <0x3f>;
|
|
vote = <67>;
|
|
};
|
|
|
|
qos1 {
|
|
mask = <0xc0>;
|
|
vote = <67>;
|
|
};
|
|
};
|
|
|
|
sdhc2_opp_table: sdhc2-opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-100000000 {
|
|
opp-hz = /bits/ 64 <100000000>;
|
|
opp-peak-kBps = <200000 150000>;
|
|
opp-avg-kBps = <50000 0>;
|
|
};
|
|
|
|
opp-202000000 {
|
|
opp-hz = /bits/ 64 <202000000>;
|
|
opp-peak-kBps = <400000 300000>;
|
|
opp-avg-kBps = <104000 0>;
|
|
};
|
|
};
|
|
|
|
sdhc_2: sdhci@8804000 {
|
|
compatible = "qcom,sdhci-msm-v5";
|
|
reg = <0x8804000 0x1000>;
|
|
reg-names = "hc_mem";
|
|
|
|
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "hc_irq", "pwr_irq";
|
|
|
|
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
|
|
<&gcc GCC_SDCC2_APPS_CLK>;
|
|
clock-names = "iface", "core";
|
|
|
|
bus-width = <4>;
|
|
qcom,restore-after-cx-collapse;
|
|
|
|
no-sdio;
|
|
no-mmc;
|
|
|
|
/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
|
|
qcom,dll-hsr-list = <0x0007642C 0x0 0x0 0x00010800 0x80040868>;
|
|
|
|
qcom,devfreq,freq-table = <50000000 202000000>;
|
|
|
|
interconnects = <&aggre1_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>,
|
|
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_2>;
|
|
interconnect-names = "sdhc-ddr","cpu-sdhc";
|
|
|
|
operating-points-v2 = <&sdhc2_opp_table>;
|
|
iommus = <&apps_smmu 0x02A0 0x0>;
|
|
qcom,iommu-dma = "fastmap";
|
|
dma-coherent;
|
|
|
|
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
|
|
qcom,iommu-geometry = <0x40000000 0x10000000>;
|
|
|
|
resets = <&gcc GCC_SDCC2_BCR>;
|
|
reset-names = "core_reset";
|
|
|
|
status = "disabled";
|
|
|
|
qos0 {
|
|
mask = <0x3f>;
|
|
vote = <67>;
|
|
};
|
|
|
|
qos1 {
|
|
mask = <0xc0>;
|
|
vote = <67>;
|
|
};
|
|
};
|
|
|
|
cpu_pmu: cpu-pmu {
|
|
compatible = "arm,armv8-pmuv3";
|
|
qcom,irq-is-percpu;
|
|
interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
qfprom: qfprom@780000 {
|
|
compatible = "qcom,qfprom";
|
|
reg = <0x780000 0x7000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
read-only;
|
|
ranges;
|
|
|
|
feat_id: feat_id@130 {
|
|
reg = <0x130 0x4>;
|
|
};
|
|
|
|
boot_config: boot_config@6070 {
|
|
reg = <0x6070 0x4>;
|
|
};
|
|
|
|
gpu_speed_bin: gpu_speed_bin@6004 {
|
|
reg = <0x6004 0x1>;
|
|
bits = <21 28>;
|
|
};
|
|
};
|
|
|
|
qfprom_sys: qfprom {
|
|
compatible = "qcom,qfprom-sys";
|
|
nvmem-cells = <&feat_id>;
|
|
nvmem-cell-names = "feat_id";
|
|
};
|
|
|
|
qcom,msm-imem@146aa000 {
|
|
compatible = "qcom,msm-imem";
|
|
reg = <0x146aa000 0x1000>;
|
|
ranges = <0x0 0x146aa000 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
mem_dump_table@10 {
|
|
compatible = "qcom,msm-imem-mem_dump_table";
|
|
reg = <0x10 0x8>;
|
|
};
|
|
|
|
dload_type@1c {
|
|
compatible = "qcom,msm-imem-dload-type";
|
|
reg = <0x1c 0x4>;
|
|
};
|
|
|
|
boot_stats@6b0 {
|
|
compatible = "qcom,msm-imem-boot_stats";
|
|
reg = <0x6b0 0x20>;
|
|
};
|
|
|
|
kaslr_offset@6d0 {
|
|
compatible = "qcom,msm-imem-kaslr_offset";
|
|
reg = <0x6d0 0xc>;
|
|
};
|
|
|
|
pil@94c {
|
|
compatible = "qcom,pil-reloc-info";
|
|
reg = <0x94c 0xc8>;
|
|
};
|
|
|
|
pil@6dc {
|
|
compatible = "qcom,msm-imem-pil-disable-timeout";
|
|
reg = <0x6dc 0x4>;
|
|
};
|
|
|
|
diag_dload@c8 {
|
|
compatible = "qcom,msm-imem-diag-dload";
|
|
reg = <0xc8 0xc8>;
|
|
};
|
|
};
|
|
|
|
reboot_reason {
|
|
compatible = "qcom,reboot-reason";
|
|
qcom,no-nvmem-cell-support;
|
|
};
|
|
|
|
restart@c264000 {
|
|
compatible = "qcom,pshold";
|
|
reg = <0xc264000 0x1000>;
|
|
};
|
|
|
|
tcsr: syscon@1fc0000 {
|
|
compatible = "syscon";
|
|
reg = <0x1fc0000 0x30000>;
|
|
};
|
|
|
|
qcom,chd {
|
|
compatible = "qcom,core-hang-detect";
|
|
label = "core";
|
|
qcom,chd-percpu-info = <&CPU0 0x18000058 0x18000060>,
|
|
<&CPU1 0x18010058 0x18010060>,
|
|
<&CPU2 0x18020058 0x18020060>,
|
|
<&CPU3 0x18030058 0x18030060>,
|
|
<&CPU4 0x18040058 0x18040060>,
|
|
<&CPU5 0x18050058 0x18050060>,
|
|
<&CPU6 0x18060058 0x18060060>,
|
|
<&CPU7 0x18070058 0x18070060>;
|
|
};
|
|
|
|
qcom,mpm2-sleep-counter@c221000 {
|
|
compatible = "qcom,mpm2-sleep-counter";
|
|
reg = <0xc221000 0x1000>;
|
|
clock-frequency = <32768>;
|
|
};
|
|
|
|
qcom-secure-buffer {
|
|
compatible = "qcom,secure-buffer";
|
|
qcom,vmid-cp-camera-preview-ro;
|
|
};
|
|
|
|
qcom,mem-buf-msgq {
|
|
compatible = "qcom,mem-buf-msgq";
|
|
};
|
|
|
|
qcom,mem-buf {
|
|
compatible = "qcom,mem-buf";
|
|
qcom,mem-buf-capabilities = "supplier";
|
|
qcom,vmid = <3>;
|
|
};
|
|
|
|
google,debug-kinfo {
|
|
compatible = "google,debug-kinfo";
|
|
memory-region = <&kinfo_mem>;
|
|
};
|
|
|
|
mini_dump_mode {
|
|
compatible = "qcom,minidump";
|
|
status = "ok";
|
|
};
|
|
|
|
vendor_hooks: qcom,cpu-vendor-hooks {
|
|
compatible = "qcom,cpu-vendor-hooks";
|
|
};
|
|
|
|
logbuf: qcom,logbuf-vendor-hooks {
|
|
compatible = "qcom,logbuf-vendor-hooks";
|
|
};
|
|
|
|
va_mini_dump {
|
|
compatible = "qcom,va-minidump";
|
|
memory-region = <&va_md_mem>;
|
|
status = "ok";
|
|
};
|
|
|
|
qcom_qseecom: qseecom@86d00000 {
|
|
compatible = "qcom,qseecom";
|
|
reg = <0x86d00000 0xe00000>;
|
|
reg-names = "secapp-region";
|
|
memory-region = <&qseecom_mem>;
|
|
qseecom_mem = <&qseecom_mem>;
|
|
qseecom_ta_mem = <&qseecom_ta_mem>;
|
|
user_contig_mem = <&user_contig_mem>;
|
|
qcom,hlos-num-ce-hw-instances = <1>;
|
|
qcom,hlos-ce-hw-instance = <0>;
|
|
qcom,qsee-ce-hw-instance = <0>;
|
|
qcom,disk-encrypt-pipe-pair = <2>;
|
|
qcom,support-fde;
|
|
qcom,no-clock-support;
|
|
qcom,fde-key-size;
|
|
qcom,appsbl-qseecom-support;
|
|
qcom,commonlib64-loaded-by-uefi;
|
|
qcom,qsee-reentrancy-support = <2>;
|
|
};
|
|
|
|
qcom_smcinvoke: smcinvoke@86d00000 {
|
|
compatible = "qcom,smcinvoke";
|
|
reg = <0x86d00000 0xe00000>;
|
|
reg-names = "secapp-region";
|
|
};
|
|
|
|
qcom_rng: qrng@793000 {
|
|
compatible = "qcom,msm-rng";
|
|
reg = <0x793000 0x1000>;
|
|
qcom,msm-rng-iface-clk;
|
|
qcom,no-qrng-config;
|
|
interconnect-names = "data_path";
|
|
interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_PRNG>;
|
|
clock-names = "km_clk_src";
|
|
clocks = <&gcc GCC_PRNG_AHB_CLK>;
|
|
};
|
|
|
|
qtee_shmbridge {
|
|
compatible = "qcom,tee-shared-memory-bridge";
|
|
};
|
|
|
|
qcom_tzlog: tz-log@146aa720 {
|
|
compatible = "qcom,tz-log";
|
|
reg = <0x146aa720 0x3000>;
|
|
qcom,hyplog-enabled;
|
|
hyplog-address-offset = <0x410>;
|
|
hyplog-size-offset = <0x414>;
|
|
};
|
|
|
|
kryo-erp {
|
|
compatible = "arm,arm64-kryo-cpu-erp";
|
|
interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
interrupt-names = "l1-l2-faultirq",
|
|
"l1-l2-errirq",
|
|
"l3-scu-errirq",
|
|
"l3-scu-faultirq";
|
|
};
|
|
|
|
tlmm: pinctrl@03000000 {
|
|
compatible = "qcom,sm6150-pinctrl";
|
|
reg = <0x03000000 0xdc2000>, <0x17c000f0 0x50>;
|
|
reg-names = "pinctrl", "spi_cfg";
|
|
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
qcom,gpios-reserved = <0 1 2 3 6 7 8 9>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
wakeup-parent = <&pdc>;
|
|
};
|
|
|
|
mem_dump {
|
|
compatible = "qcom,mem-dump";
|
|
memory-region = <&dump_mem>;
|
|
|
|
c0_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x0>;
|
|
};
|
|
|
|
c100_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x1>;
|
|
};
|
|
|
|
c200_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x2>;
|
|
};
|
|
|
|
c300_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x3>;
|
|
};
|
|
|
|
c400_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x4>;
|
|
};
|
|
|
|
c500_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x5>;
|
|
};
|
|
|
|
c600_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x6>;
|
|
};
|
|
|
|
c700_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x7>;
|
|
};
|
|
|
|
rpmh {
|
|
qcom,dump-size = <0x2000000>;
|
|
qcom,dump-id = <0xec>;
|
|
};
|
|
|
|
rpm_sw {
|
|
qcom,dump-size = <0x28000>;
|
|
qcom,dump-id = <0xea>;
|
|
};
|
|
|
|
pmic {
|
|
qcom,dump-size = <0x10000>;
|
|
qcom,dump-id = <0xe4>;
|
|
};
|
|
|
|
fcm {
|
|
qcom,dump-size = <0x8400>;
|
|
qcom,dump-id = <0xee>;
|
|
};
|
|
|
|
tmc_etf {
|
|
qcom,dump-size = <0x8000>;
|
|
qcom,dump-id = <0xf0>;
|
|
};
|
|
|
|
etf_swao {
|
|
qcom,dump-size = <0x8000>;
|
|
qcom,dump-id = <0xf1>;
|
|
};
|
|
|
|
etr_reg {
|
|
qcom,dump-size = <0x1000>;
|
|
qcom,dump-id = <0x100>;
|
|
};
|
|
|
|
etf_reg {
|
|
qcom,dump-size = <0x1000>;
|
|
qcom,dump-id = <0x101>;
|
|
};
|
|
|
|
etfswao_reg {
|
|
qcom,dump-size = <0x1000>;
|
|
qcom,dump-id = <0x102>;
|
|
};
|
|
|
|
misc_data {
|
|
qcom,dump-size = <0x1000>;
|
|
qcom,dump-id = <0xe8>;
|
|
};
|
|
|
|
l1_icache0 {
|
|
qcom,dump-size = <0x8800>;
|
|
qcom,dump-id = <0x60>;
|
|
};
|
|
|
|
l1_icache100 {
|
|
qcom,dump-size = <0x8800>;
|
|
qcom,dump-id = <0x61>;
|
|
};
|
|
|
|
l1_icache200 {
|
|
qcom,dump-size = <0x8800>;
|
|
qcom,dump-id = <0x62>;
|
|
};
|
|
|
|
l1_icache300 {
|
|
qcom,dump-size = <0x8800>;
|
|
qcom,dump-id = <0x63>;
|
|
};
|
|
|
|
l1_icache400 {
|
|
qcom,dump-size = <0x8800>;
|
|
qcom,dump-id = <0x64>;
|
|
};
|
|
|
|
l1_icache500 {
|
|
qcom,dump-size = <0x8800>;
|
|
qcom,dump-id = <0x65>;
|
|
};
|
|
|
|
l1_icache600 {
|
|
qcom,dump-size = <0x11000>;
|
|
qcom,dump-id = <0x66>;
|
|
};
|
|
|
|
l1_icache700 {
|
|
qcom,dump-size = <0x11000>;
|
|
qcom,dump-id = <0x67>;
|
|
};
|
|
|
|
l1_dcache0 {
|
|
qcom,dump-size = <0x9000>;
|
|
qcom,dump-id = <0x80>;
|
|
};
|
|
|
|
l1_dcache100 {
|
|
qcom,dump-size = <0x9000>;
|
|
qcom,dump-id = <0x81>;
|
|
};
|
|
|
|
l1_dcache200 {
|
|
qcom,dump-size = <0x9000>;
|
|
qcom,dump-id = <0x82>;
|
|
};
|
|
|
|
l1_dcache300 {
|
|
qcom,dump-size = <0x9000>;
|
|
qcom,dump-id = <0x83>;
|
|
};
|
|
|
|
l1_dcache400 {
|
|
qcom,dump-size = <0x9000>;
|
|
qcom,dump-id = <0x84>;
|
|
};
|
|
|
|
l1_dcache500 {
|
|
qcom,dump-size = <0x9000>;
|
|
qcom,dump-id = <0x85>;
|
|
};
|
|
|
|
l1_dcache600 {
|
|
qcom,dump-size = <0x12000>;
|
|
qcom,dump-id = <0x86>;
|
|
};
|
|
|
|
l1_dcache700 {
|
|
qcom,dump-size = <0x12000>;
|
|
qcom,dump-id = <0x87>;
|
|
};
|
|
|
|
l1_itlb600 {
|
|
qcom,dump-size = <0x300>;
|
|
qcom,dump-id = <0x26>;
|
|
};
|
|
|
|
l1_itlb700 {
|
|
qcom,dump-size = <0x300>;
|
|
qcom,dump-id = <0x27>;
|
|
};
|
|
|
|
l1_dtlb600 {
|
|
qcom,dump-size = <0x480>;
|
|
qcom,dump-id = <0x46>;
|
|
};
|
|
|
|
l1_dtlb700 {
|
|
qcom,dump-size = <0x480>;
|
|
qcom,dump-id = <0x47>;
|
|
};
|
|
|
|
l2_cache600 {
|
|
qcom,dump-size = <0x48000>;
|
|
qcom,dump-id = <0xc6>;
|
|
};
|
|
|
|
l2_cache700 {
|
|
qcom,dump-size = <0x48000>;
|
|
qcom,dump-id = <0xc7>;
|
|
};
|
|
|
|
l2_tlb0 {
|
|
qcom,dump-size = <0x5000>;
|
|
qcom,dump-id = <0x120>;
|
|
};
|
|
|
|
l2_tlb100 {
|
|
qcom,dump-size = <0x5000>;
|
|
qcom,dump-id = <0x121>;
|
|
};
|
|
|
|
l2_tlb200 {
|
|
qcom,dump-size = <0x5000>;
|
|
qcom,dump-id = <0x122>;
|
|
};
|
|
|
|
l2_tlb300 {
|
|
qcom,dump-size = <0x5000>;
|
|
qcom,dump-id = <0x123>;
|
|
};
|
|
|
|
l2_tlb400 {
|
|
qcom,dump-size = <0x5000>;
|
|
qcom,dump-id = <0x124>;
|
|
};
|
|
|
|
l2_tlb500 {
|
|
qcom,dump-size = <0x5000>;
|
|
qcom,dump-id = <0x125>;
|
|
};
|
|
|
|
l2_tlb600 {
|
|
qcom,dump-size = <0x7800>;
|
|
qcom,dump-id = <0x126>;
|
|
};
|
|
|
|
l2_tlb700 {
|
|
qcom,dump-size = <0x7800>;
|
|
qcom,dump-id = <0x127>;
|
|
};
|
|
|
|
llcc1_d_cache {
|
|
qcom,dump-size = <0x6c000>;
|
|
qcom,dump-id = <0x140>;
|
|
};
|
|
};
|
|
|
|
apss_shared: mailbox@17c00000 {
|
|
compatible = "qcom,sm8150-apss-shared";
|
|
reg = <0x17c00000 0x1000>;
|
|
#mbox-cells = <1>;
|
|
};
|
|
|
|
aoss_qmp: power-controller@c300000 {
|
|
compatible = "qcom,aoss-qmp";
|
|
reg = <0xc300000 0x400>;
|
|
interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&apss_shared 0>;
|
|
|
|
#clock-cells = <0>;
|
|
#power-domain-cells = <1>;
|
|
};
|
|
|
|
qmp_aop: qmp-aop {
|
|
compatible = "qcom,qmp-mbox";
|
|
qcom,qmp = <&aoss_qmp>;
|
|
label = "aop";
|
|
#mbox-cells = <1>;
|
|
};
|
|
|
|
apcs: syscon@17c0000c {
|
|
compatible = "syscon";
|
|
reg = <0x17c0000c 0x4>;
|
|
};
|
|
|
|
tcsr_mutex_block: syscon@1f40000 {
|
|
compatible = "syscon";
|
|
reg = <0x1f40000 0x20000>;
|
|
};
|
|
|
|
tcsr_mutex: hwlock@1f40000 {
|
|
compatible = "qcom,tcsr-mutex";
|
|
syscon = <&tcsr_mutex_block 0 0x1000>;
|
|
#hwlock-cells = <1>;
|
|
};
|
|
|
|
smem: qcom,smem@8600000 {
|
|
compatible = "qcom,smem";
|
|
memory-region = <&smem_region>;
|
|
hwlocks = <&tcsr_mutex 3>;
|
|
};
|
|
|
|
adsp_pas: remoteproc-adsp@62400000 {
|
|
compatible = "qcom,sm6150-adsp-pas";
|
|
reg = <0x62400000 0x00100>;
|
|
status = "ok";
|
|
|
|
cx-supply = <&L8A_LEVEL>;
|
|
cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
|
|
reg-names = "cx";
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "xo";
|
|
|
|
mboxes = <&qmp_aop 0>;
|
|
|
|
interconnects = <&aggre1_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
|
|
interconnect-names = "crypto_ddr";
|
|
|
|
memory-region = <&pil_adsp_mem>;
|
|
|
|
/* Inputs from ssc */
|
|
interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
|
|
<&adsp_smp2p_in 0 0>,
|
|
<&adsp_smp2p_in 2 0>,
|
|
<&adsp_smp2p_in 1 0>,
|
|
<&adsp_smp2p_in 3 0>,
|
|
<&adsp_smp2p_in 7 0>;
|
|
|
|
interrupt-names = "wdog",
|
|
"fatal",
|
|
"handover",
|
|
"ready",
|
|
"stop-ack",
|
|
"shutdown-ack";
|
|
|
|
/* Outputs to turing */
|
|
qcom,smem-states = <&adsp_smp2p_out 0>;
|
|
qcom,smem-state-names = "stop";
|
|
|
|
remoteproc_adsp_glink: glink-edge {
|
|
qcom,remote-pid = <2>;
|
|
transport = "smem";
|
|
mboxes = <&apss_shared 24>;
|
|
mbox-names = "adsp_smem";
|
|
interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
|
|
|
|
label = "adsp";
|
|
qcom,glink-label = "lpass";
|
|
cpu-affinity = <1 2>;
|
|
|
|
qcom,adsp_qrtr {
|
|
qcom,glink-channels = "IPCRTR";
|
|
qcom,intents = <0x800 5
|
|
0x2000 3
|
|
0x4400 2>;
|
|
};
|
|
|
|
};
|
|
};
|
|
|
|
cdsp_pas: remoteproc-cdsp@0x8300000 {
|
|
compatible = "qcom,sm6150-cdsp-pas";
|
|
reg = <0x8300000 0x100000>;
|
|
status = "ok";
|
|
|
|
cx-supply = <&VDD_CX_LEVEL>;
|
|
cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
|
|
reg-names = "cx";
|
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "xo";
|
|
|
|
qcom,qmp = <&aoss_qmp>;
|
|
|
|
interconnects = <&aggre1_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
|
|
interconnect-names = "crypto_ddr";
|
|
|
|
memory-region = <&pil_cdsp_mem>;
|
|
|
|
/* Inputs from ssc */
|
|
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
|
|
<&cdsp_smp2p_in 0 0>,
|
|
<&cdsp_smp2p_in 2 0>,
|
|
<&cdsp_smp2p_in 1 0>,
|
|
<&cdsp_smp2p_in 3 0>,
|
|
<&cdsp_smp2p_in 7 0>;
|
|
|
|
interrupt-names = "wdog",
|
|
"fatal",
|
|
"handover",
|
|
"ready",
|
|
"stop-ack",
|
|
"shutdown-ack";
|
|
|
|
/* Outputs to turing */
|
|
qcom,smem-states = <&cdsp_smp2p_out 0>;
|
|
qcom,smem-state-names = "stop";
|
|
|
|
remoteproc_cdsp_glink: glink-edge {
|
|
qcom,remote-pid = <5>;
|
|
transport = "smem";
|
|
mboxes = <&apss_shared 4>;
|
|
mbox-names = "cdsp_smem";
|
|
interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
|
|
|
|
label = "cdsp";
|
|
qcom,glink-label = "cdsp";
|
|
|
|
qcom,cdsp_qrtr {
|
|
qcom,glink-channels = "IPCRTR";
|
|
qcom,intents = <0x800 5
|
|
0x2000 3
|
|
0x4400 2>;
|
|
};
|
|
|
|
qcom,msm_cdsprm_rpmsg {
|
|
compatible = "qcom,msm-cdsprm-rpmsg";
|
|
qcom,glink-channels = "cdsprmglink-apps-dsp";
|
|
qcom,intents = <0x20 12>;
|
|
msm_cdsp_rm: qcom,msm_cdsp_rm {
|
|
compatible = "qcom,msm-cdsp-rm";
|
|
qcom,qos-latency-us = <44>;
|
|
qcom,qos-maxhold-ms = <20>;
|
|
qcom,compute-cx-limit-en;
|
|
qcom,compute-priority-mode = <2>;
|
|
#cooling-cells = <2>;
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
};
|
|
|
|
qcom,sps {
|
|
compatible = "qcom,msm-sps-4k";
|
|
qcom,pipe-attr-ee;
|
|
};
|
|
|
|
glinkpkt {
|
|
compatible = "qcom,glinkpkt";
|
|
|
|
qcom,glinkpkt-apr-apps2 {
|
|
qcom,glinkpkt-edge = "adsp";
|
|
qcom,glinkpkt-ch-name = "apr_apps2";
|
|
qcom,glinkpkt-dev-name = "apr_apps2";
|
|
};
|
|
};
|
|
|
|
qcom,smp2p_sleepstate {
|
|
compatible = "qcom,smp2p-sleepstate";
|
|
qcom,smem-states = <&sleepstate_smp2p_out 0>;
|
|
interrupt-parent = <&sleepstate_smp2p_in>;
|
|
interrupts = <0 0>;
|
|
interrupt-names = "smp2p-sleepstate-in";
|
|
};
|
|
|
|
smp2p-modem {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <435>, <428>;
|
|
interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
|
|
qcom,ipc = <&apcs 0 14>;
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <1>;
|
|
|
|
modem_smp2p_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
modem_smp2p_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {
|
|
qcom,entry-name = "ipa";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
/* ipa - inbound entry from mss */
|
|
smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {
|
|
qcom,entry-name = "ipa";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
smp2p_wlan_1_in: qcom,smp2p-wlan-1-in {
|
|
qcom,entry-name = "wlan";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
qcom_smp2p_adsp: smp2p-adsp {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <443>, <429>;
|
|
interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
|
|
qcom,ipc = <&apcs 0 26>;
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <2>;
|
|
|
|
adsp_smp2p_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
adsp_smp2p_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
sleepstate_smp2p_out: sleepstate-out {
|
|
qcom,entry-name = "sleepstate";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
sleepstate_smp2p_in: qcom,sleepstate-in {
|
|
qcom,entry-name = "sleepstate_see";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
smp2p_rdbg2_out: qcom,smp2p-rdbg2-out {
|
|
qcom,entry-name = "rdbg";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
smp2p_rdbg2_in: qcom,smp2p-rdbg2-in {
|
|
qcom,entry-name = "rdbg";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
smp2p-cdsp {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <94>, <432>;
|
|
interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
|
|
qcom,ipc = <&apcs 0 6>;
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <5>;
|
|
|
|
cdsp_smp2p_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
cdsp_smp2p_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
smp2p_rdbg5_out: qcom,smp2p-rdbg5-out {
|
|
qcom,entry-name = "rdbg";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
smp2p_rdbg5_in: qcom,smp2p-rdbg5-in {
|
|
qcom,entry-name = "rdbg";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
qcom,rmtfs_sharedmem@0 {
|
|
compatible = "qcom,sharedmem-uio";
|
|
reg = <0x0 0x200000>;
|
|
reg-names = "rmtfs";
|
|
qcom,client-id = <0x00000001>;
|
|
qcom,guard-memory;
|
|
};
|
|
|
|
sram@c3f0000 {
|
|
compatible = "qcom,rpmh-stats";
|
|
reg = <0x0c3f0000 0x400>;
|
|
ss-name = "modem", "adsp", "adsp_island", "cdsp", "apss";
|
|
};
|
|
|
|
qcom,power-state {
|
|
compatible = "qcom,power-state";
|
|
};
|
|
};
|
|
|
|
#include "sm6150-regulator.dtsi"
|
|
#include "sm6150-gdsc.dtsi"
|
|
#include "sm6150-thermal.dtsi"
|
|
#include "sm6150-pinctrl.dtsi"
|
|
#include "msm-rdbg.dtsi"
|
|
#include "msm-arm-smmu-sm6150.dtsi"
|
|
#include "sm6150-qupv3.dtsi"
|
|
#include "sm6150-usb.dtsi"
|
|
#include "sm6150-dma-heaps.dtsi"
|
|
#include "sm6150-walt.dtsi"
|
|
#include "sm6150-coresight.dtsi"
|
|
#include "sm6150-debug.dtsi"
|
|
|
|
&tlmm {
|
|
status = "okay";
|
|
};
|
|
|
|
&emac_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&pcie_0_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&ufs_phy_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&usb30_prim_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&usb20_sec_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_aggre_noc_mmu_tbu1_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_aggre_noc_mmu_tbu2_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&titan_top_gdsc {
|
|
parent-supply = <&VDD_MX_LEVEL>;
|
|
status = "ok";
|
|
};
|
|
|
|
&bps_gdsc {
|
|
qcom,support-hw-trigger;
|
|
status = "ok";
|
|
};
|
|
|
|
&ife_0_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&ife_1_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&ipe_0_gdsc {
|
|
qcom,support-hw-trigger;
|
|
status = "ok";
|
|
};
|
|
|
|
&mdss_core_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&gpu_cx_gdsc {
|
|
parent-supply = <&VDD_CX_LEVEL>;
|
|
status = "ok";
|
|
};
|
|
|
|
&gpu_gx_gdsc {
|
|
parent-supply = <&VDD_CX_LEVEL>;
|
|
status = "ok";
|
|
};
|
|
|
|
&vcodec0_gdsc {
|
|
qcom,support-hw-trigger;
|
|
status = "ok";
|
|
};
|
|
|
|
&venus_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&firmware {
|
|
qcom_scm {
|
|
compatible = "qcom,scm";
|
|
qcom,dload-mode = <&tcsr 0x13000>;
|
|
};
|
|
};
|