From 2eabb846d6061395b56645277a958dacfefac7c8 Mon Sep 17 00:00:00 2001 From: Mahadevan Date: Thu, 2 Nov 2023 23:09:22 +0530 Subject: [PATCH] disp: msm: sde: avoid double clearing of INTR registers When there is CPU processing delay between first INTR clear and second INTR clear there is a chance that the second register write might clear the next frames interrupts which will avoid triggering the irq callbacks causing software hung. This patch avoids such a scenario by removing such double clearing of INTR registers. Change-Id: I8407991769c69d2d2c691763240671d5f3c0416d Signed-off-by: Mahadevan --- .../opensource/display-drivers/msm/sde/sde_core_irq.c | 11 +---------- .../display-drivers/msm/sde/sde_hw_interrupts.c | 10 ++-------- .../display-drivers/msm/sde/sde_hw_interrupts.h | 9 --------- 3 files changed, 3 insertions(+), 27 deletions(-) diff --git a/qcom/opensource/display-drivers/msm/sde/sde_core_irq.c b/qcom/opensource/display-drivers/msm/sde/sde_core_irq.c index cb17596256..4c6dd2b21d 100644 --- a/qcom/opensource/display-drivers/msm/sde/sde_core_irq.c +++ b/qcom/opensource/display-drivers/msm/sde/sde_core_irq.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. */ @@ -66,15 +66,6 @@ static void sde_core_irq_callback_handler(void *arg, int irq_idx) SDE_EVT32_IRQ(irq_idx, enable_counts, SDE_EVTLOG_ERROR); } } - - /* - * Clear pending interrupt status in HW. - * NOTE: sde_core_irq_callback_handler is protected by top-level - * spinlock, so it is safe to clear any interrupt status here. - */ - sde_kms->hw_intr->ops.clear_intr_status_nolock( - sde_kms->hw_intr, - irq_idx); } int sde_core_irq_idx_lookup(struct sde_kms *sde_kms, diff --git a/qcom/opensource/display-drivers/msm/sde/sde_hw_interrupts.c b/qcom/opensource/display-drivers/msm/sde/sde_hw_interrupts.c index 3e1bb2bab2..06f9c6f0cc 100644 --- a/qcom/opensource/display-drivers/msm/sde/sde_hw_interrupts.c +++ b/qcom/opensource/display-drivers/msm/sde/sde_hw_interrupts.c @@ -505,16 +505,11 @@ static void sde_hw_intr_dispatch_irq(struct sde_hw_intr *intr, reg_idx)) { /* * Once a match on irq mask, perform a callback - * to the given cbfunc. cbfunc will take care - * the interrupt status clearing. If cbfunc is - * not provided, then the interrupt clearing - * is here. + * to the given cbfunc. This callback is done + * after clearing the interrupt registers. */ if (cbfunc) cbfunc(arg, irq_idx); - else - intr->ops.clear_intr_status_nolock( - intr, irq_idx); /* * When callback finish, clear the irq_status @@ -878,7 +873,6 @@ static void __setup_intr_ops(struct sde_hw_intr_ops *ops) ops->disable_all_irqs = sde_hw_intr_disable_irqs; ops->get_interrupt_sources = sde_hw_intr_get_interrupt_sources; ops->clear_interrupt_status = sde_hw_intr_clear_interrupt_status; - ops->clear_intr_status_nolock = sde_hw_intr_clear_intr_status_nolock; ops->get_interrupt_status = sde_hw_intr_get_interrupt_status; ops->get_intr_status_nolock = sde_hw_intr_get_intr_status_nolock; } diff --git a/qcom/opensource/display-drivers/msm/sde/sde_hw_interrupts.h b/qcom/opensource/display-drivers/msm/sde/sde_hw_interrupts.h index 0310f340f0..9ed730a322 100644 --- a/qcom/opensource/display-drivers/msm/sde/sde_hw_interrupts.h +++ b/qcom/opensource/display-drivers/msm/sde/sde_hw_interrupts.h @@ -188,15 +188,6 @@ struct sde_hw_intr_ops { struct sde_hw_intr *intr, int irq_idx); - /** - * clear_intr_status_nolock() - clears the HW interrupts without lock - * @intr: HW interrupt handle - * @irq_idx: Lookup irq index return from irq_idx_lookup - */ - void (*clear_intr_status_nolock)( - struct sde_hw_intr *intr, - int irq_idx); - /** * get_interrupt_status - Gets HW interrupt status, and clear if set, * based on given lookup IRQ index.