From 8c9964feab359cce44e68c4f95dc97761e1ed3da Mon Sep 17 00:00:00 2001 From: SIVA MULLATI Date: Tue, 24 Dec 2024 11:41:04 +0530 Subject: [PATCH 01/12] kgsl: gen8: Enable L1 preemption for gen8_6_0 Enable the L1 preemption GPU functionality for QoS improvement. Change-Id: I2ab854ac31bf7a78645d01977bdebf48156cd3f3 Signed-off-by: SIVA MULLATI --- adreno-gpulist.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/adreno-gpulist.h b/adreno-gpulist.h index 50dc5617fb..14433d45d0 100644 --- a/adreno-gpulist.h +++ b/adreno-gpulist.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2002,2007-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2025, Qualcomm Innovation Center, Inc. All rights reserved. */ #define ANY_ID (~0) @@ -3293,7 +3293,8 @@ static const struct adreno_gen8_core adreno_gpu_core_gen8_6_0 = { .compatible = "qcom,adreno-gpu-gen8-6-0", .features = ADRENO_APRIV | ADRENO_IOCOHERENT | ADRENO_CONTENT_PROTECTION | ADRENO_LPAC | ADRENO_AQE | - ADRENO_GMU_WARMBOOT | ADRENO_L3_VOTE | ADRENO_IFPC, + ADRENO_GMU_WARMBOOT | ADRENO_L3_VOTE | ADRENO_IFPC | + ADRENO_PREEMPTION, .gpudev = &adreno_gen8_hwsched_gpudev.base, .perfcounters = &adreno_gen8_perfcounters, .uche_gmem_alignment = SZ_64M, @@ -3318,6 +3319,7 @@ static const struct adreno_gen8_core adreno_gpu_core_gen8_6_0 = { .gen8_snapshot_block_list = &gen8_6_0_snapshot_block_list, .noc_timeout_us = 3410, /* 3.41 msec */ .ctxt_record_size = (3372 * SZ_1K), + .preempt_level = 1, }; static const struct adreno_gpu_core *adreno_gpulist[] = { From 2f61ec1cf5db60a7fcbaf892a9f8c220e4bc99eb Mon Sep 17 00:00:00 2001 From: SIVA MULLATI Date: Fri, 10 Jan 2025 10:23:54 +0530 Subject: [PATCH 02/12] kgsl: gen8: Enable ACV perfmode vote for gen8_6_0 Enable ACV perfmode vote for gen8_6_0 for improved performance. Change-Id: I1dc8e50237d36882e150804a03a872ab610c8844 Signed-off-by: SIVA MULLATI Signed-off-by: Gayathri Veeragandam --- adreno-gpulist.h | 1 + 1 file changed, 1 insertion(+) diff --git a/adreno-gpulist.h b/adreno-gpulist.h index 14433d45d0..4c96330493 100644 --- a/adreno-gpulist.h +++ b/adreno-gpulist.h @@ -3320,6 +3320,7 @@ static const struct adreno_gen8_core adreno_gpu_core_gen8_6_0 = { .noc_timeout_us = 3410, /* 3.41 msec */ .ctxt_record_size = (3372 * SZ_1K), .preempt_level = 1, + .acv_perfmode_ddr_freq = MHZ_TO_KBPS(2736, 4), }; static const struct adreno_gpu_core *adreno_gpulist[] = { From 97ba40095c23863a8869aa81fc7cbebc37c0de78 Mon Sep 17 00:00:00 2001 From: Gayathri Veeragandam Date: Tue, 31 Dec 2024 11:34:30 +0530 Subject: [PATCH 03/12] kgsl: gen8: Enable BCL support for gen8_6_0 GPU Enable Battery Current Limiting feature for gen8_6_0 GPU. BCL prevents UVLO (Under Voltage Lock out) due to sudden voltage droop and OCP (Over Current Protection). Change-Id: I0d92f47873ec597b15210dfe5ce2932a947145f1 Signed-off-by: Gayathri Veeragandam --- adreno-gpulist.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/adreno-gpulist.h b/adreno-gpulist.h index 4c96330493..4eee31e2e9 100644 --- a/adreno-gpulist.h +++ b/adreno-gpulist.h @@ -3294,7 +3294,7 @@ static const struct adreno_gen8_core adreno_gpu_core_gen8_6_0 = { .features = ADRENO_APRIV | ADRENO_IOCOHERENT | ADRENO_CONTENT_PROTECTION | ADRENO_LPAC | ADRENO_AQE | ADRENO_GMU_WARMBOOT | ADRENO_L3_VOTE | ADRENO_IFPC | - ADRENO_PREEMPTION, + ADRENO_PREEMPTION | ADRENO_BCL, .gpudev = &adreno_gen8_hwsched_gpudev.base, .perfcounters = &adreno_gen8_perfcounters, .uche_gmem_alignment = SZ_64M, @@ -3321,6 +3321,7 @@ static const struct adreno_gen8_core adreno_gpu_core_gen8_6_0 = { .ctxt_record_size = (3372 * SZ_1K), .preempt_level = 1, .acv_perfmode_ddr_freq = MHZ_TO_KBPS(2736, 4), + .bcl_data = 1, }; static const struct adreno_gpu_core *adreno_gpulist[] = { From 6cd61218bacb58c5fa4bd336a4b02a674ef1084c Mon Sep 17 00:00:00 2001 From: SIVA MULLATI Date: Tue, 24 Dec 2024 11:29:58 +0530 Subject: [PATCH 04/12] kgsl: gen8: Enable ACD on gen8_6_0 GPU Adaptive Clock Distribution feature helps mitigate peak current and voltage droops. Change-Id: I870628c76a9f809b505fc97cddb9d568c82e8243 Signed-off-by: SIVA MULLATI --- adreno-gpulist.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/adreno-gpulist.h b/adreno-gpulist.h index 4eee31e2e9..da5236c153 100644 --- a/adreno-gpulist.h +++ b/adreno-gpulist.h @@ -3294,7 +3294,7 @@ static const struct adreno_gen8_core adreno_gpu_core_gen8_6_0 = { .features = ADRENO_APRIV | ADRENO_IOCOHERENT | ADRENO_CONTENT_PROTECTION | ADRENO_LPAC | ADRENO_AQE | ADRENO_GMU_WARMBOOT | ADRENO_L3_VOTE | ADRENO_IFPC | - ADRENO_PREEMPTION | ADRENO_BCL, + ADRENO_PREEMPTION | ADRENO_BCL | ADRENO_ACD, .gpudev = &adreno_gen8_hwsched_gpudev.base, .perfcounters = &adreno_gen8_perfcounters, .uche_gmem_alignment = SZ_64M, From 0ca54ccf3902eb51972ade010e61feae046e21f3 Mon Sep 17 00:00:00 2001 From: SIVA MULLATI Date: Fri, 10 Jan 2025 10:36:28 +0530 Subject: [PATCH 05/12] kgsl: gen8: Update AHB timeout for gen8_6_0 Update noc_timeout_us for gen8_6_0 GPU as per the latest recommendation. Change-Id: I04bd75c00383dfc9c5f26ec2eb9dd11a7b97cac7 Signed-off-by: SIVA MULLATI Signed-off-by: Gayathri Veeragandam --- adreno-gpulist.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/adreno-gpulist.h b/adreno-gpulist.h index 50dc5617fb..8d3beed652 100644 --- a/adreno-gpulist.h +++ b/adreno-gpulist.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2002,2007-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2025, Qualcomm Innovation Center, Inc. All rights reserved. */ #define ANY_ID (~0) @@ -3316,7 +3316,7 @@ static const struct adreno_gen8_core adreno_gpu_core_gen8_6_0 = { .highest_bank_bit = 16, .gmu_hub_clk_freq = 200000000, .gen8_snapshot_block_list = &gen8_6_0_snapshot_block_list, - .noc_timeout_us = 3410, /* 3.41 msec */ + .noc_timeout_us = 6800, /* 6.8 msec */ .ctxt_record_size = (3372 * SZ_1K), }; From fe5db95e467098cc540d3ebec615ff415e6187cd Mon Sep 17 00:00:00 2001 From: SIVA MULLATI Date: Tue, 28 Jan 2025 11:21:43 +0530 Subject: [PATCH 06/12] kgsl: gen8: Update GMU firmware binary name for gen8_6_0 GPU Update the GPU list for gen8_6_0 GPU to pick right GPU firmware binary. Change-Id: Iae7d928f3445bcce220918fe13aefd0005aede4d Signed-off-by: SIVA MULLATI Signed-off-by: Gayathri Veeragandam --- adreno-gpulist.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/adreno-gpulist.h b/adreno-gpulist.h index 70d0d9be1d..78a456eaad 100644 --- a/adreno-gpulist.h +++ b/adreno-gpulist.h @@ -3308,7 +3308,7 @@ static const struct adreno_gen8_core adreno_gpu_core_gen8_6_0 = { }, .aqefw_name = "gen80000_aqe.fw", .sqefw_name = "gen80000_sqe.fw", - .gmufw_name = "gen80000_gmu.bin", + .gmufw_name = "gen80600_gmu.bin", .zap_name = "gen80000_zap.mbn", .ao_hwcg = gen8_ao_hwcg_regs, .ao_hwcg_count = ARRAY_SIZE(gen8_ao_hwcg_regs), From bbba7d96cd7c539e086d77bc628fe10232291edb Mon Sep 17 00:00:00 2001 From: Kaushal Sanadhya Date: Thu, 23 Jan 2025 12:19:14 +0530 Subject: [PATCH 07/12] kgsl: gen7: Reduce snapshot size to 2M for gen7_17_0 GPU Gen7_17_0 GPU necessitates only 2M snapshot memory. Therefore, cut down the size. Change-Id: I5ab9757d874bc8df38219d0d5a164ff9d97981ff Signed-off-by: Kaushal Sanadhya --- adreno-gpulist.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/adreno-gpulist.h b/adreno-gpulist.h index 1d8b235e6f..448080434f 100644 --- a/adreno-gpulist.h +++ b/adreno-gpulist.h @@ -2633,7 +2633,7 @@ static const struct adreno_gen7_core adreno_gpu_core_gen7_17_0 = { .uche_gmem_alignment = SZ_16M, .gmem_size = SZ_1M, .bus_width = 32, - .snapshot_size = SZ_4M, + .snapshot_size = SZ_2M, }, .sqefw_name = "gen70e00_sqe.fw", .gmufw_name = "gen71700_gmu.bin", From fc2e1ca1e407d7d615044e5ccea790c6bcd3bc4f Mon Sep 17 00:00:00 2001 From: Kamal Agrawal Date: Thu, 19 Dec 2024 17:12:14 +0530 Subject: [PATCH 08/12] kgsl: Mark KGSL device as dma coherent Currently, cache operations are performed for DMA buffers imported to KGSL even when IO-coherency is enabled. This commit marks the KGSL device as dma coherent when IO-coherency is enabled, thereby skipping cache operations for imported dma buffers. Change-Id: I39a8c5ddbe7e9baad8086d8c07ae2055b99d24eb Signed-off-by: Kamal Agrawal Signed-off-by: Pankaj Gupta --- kgsl.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/kgsl.c b/kgsl.c index 7679e719d9..25c3041f33 100644 --- a/kgsl.c +++ b/kgsl.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2008-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2025, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -5127,6 +5127,15 @@ static int _register_device(struct kgsl_device *device) device->dev->dma_mask = &dma_mask; device->dev->dma_parms = &dma_parms; + /* + * Mark KGSL device as dma coherent when io-coherency + * is enabled to skip cache operations for imported dma + * buffers. + */ + if (kgsl_mmu_has_feature(device, KGSL_MMU_IO_COHERENT) && + IS_ENABLED(CONFIG_QCOM_KGSL_IOCOHERENCY_DEFAULT)) + device->dev->dma_coherent = true; + dma_set_max_seg_size(device->dev, (u32)DMA_BIT_MASK(32)); set_dma_ops(device->dev, NULL); From ce599df5fc90db5f9ff1193675d4f0dd402e8cc6 Mon Sep 17 00:00:00 2001 From: Carter Cooper Date: Wed, 21 Aug 2024 16:03:15 -0700 Subject: [PATCH 09/12] kgsl: adreno: DCVS Tuning nodes Add sysfs nodes to allow for dynamic DCVS tuning. Change-Id: Ic1c9eec76001962fc8a4c51b96197bdc2b7b979e Signed-off-by: Carter Cooper Signed-off-by: Pankaj Gupta --- adreno.c | 3 +- adreno.h | 10 +++- adreno_sysfs.c | 124 ++++++++++++++++++++++++++++++++++++++- adreno_trace.h | 21 ++++++- governor_msm_adreno_tz.c | 4 +- 5 files changed, 157 insertions(+), 5 deletions(-) diff --git a/adreno.c b/adreno.c index 109e9c5a29..153c026fed 100644 --- a/adreno.c +++ b/adreno.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2002,2007-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include @@ -1198,6 +1198,7 @@ static void adreno_setup_device(struct adreno_device *adreno_dev) mutex_init(&adreno_dev->dev.mutex); mutex_init(&adreno_dev->dev.file_mutex); mutex_init(&adreno_dev->fault_recovery_mutex); + mutex_init(&adreno_dev->dcvs_tuning_mutex); INIT_LIST_HEAD(&adreno_dev->dev.globals); /* Set the fault tolerance policy to replay, skip, throttle */ diff --git a/adreno.h b/adreno.h index 169b16b8d7..d935df5d56 100644 --- a/adreno.h +++ b/adreno.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2008-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef __ADRENO_H #define __ADRENO_H @@ -766,6 +766,14 @@ struct adreno_device { struct kthread_work scheduler_work; /** @scheduler_fault: Atomic to trigger scheduler based fault recovery */ atomic_t scheduler_fault; + /** @dcvs_tuning_mutex: Mutex taken during dcvs tuning */ + struct mutex dcvs_tuning_mutex; + /** @dcvs_tuning_mingap_lvl: Current DCVS tuning level for mingap */ + u32 dcvs_tuning_mingap_lvl; + /** @dcvs_tuning_penalty_lvl: Current DCVS tuning level for penalty */ + u32 dcvs_tuning_penalty_lvl; + /** @dcvs_tuning_numbusy_lvl: Current DCVS tuning level for numbusy */ + u32 dcvs_tuning_numbusy_lvl; }; /* Time to wait for suspend recovery gate to complete */ diff --git a/adreno_sysfs.c b/adreno_sysfs.c index 9fab257c9a..342c4c701b 100644 --- a/adreno_sysfs.c +++ b/adreno_sysfs.c @@ -1,13 +1,20 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include +#include +#if (KERNEL_VERSION(6, 3, 0) <= LINUX_VERSION_CODE) +#include +#else +#include +#endif #include "adreno.h" #include "adreno_sysfs.h" +#include "adreno_trace.h" #include "kgsl_sysfs.h" static ssize_t _gpu_model_show(struct kgsl_device *device, char *buf) @@ -99,6 +106,114 @@ static u32 _rt_bus_hint_show(struct adreno_device *adreno_dev) return device->pwrctrl.rt_bus_hint; } +/* Tuning values can be set to 0/1/2/3 */ +#define DCVS_TUNING_MAX 3 +#define DCVS_TUNING_EN_BIT BIT(5) + +/* + * GPU DCVS Tuning allows for small adjustments to the DCVS + * algorithm. The default value for each tunable is 0. Setting + * a higher tunable value will increase the aggressivenes + * of the DCVS algorithm. Currently 0-3 are supported values + * for each tunable, 3 being most aggressive. + */ + +/* Mingap is the count of consecutive low requests before moving to lower DCVS levels. */ +#define DCVS_TUNING_MINGAP 0 +/* Penalty is the busy threshold for moving between levels. */ +#define DCVS_TUNING_PENALTY 1 +/* Numbusy is the backoff from mingap to transition power level more quickly. */ +#define DCVS_TUNING_NUMBUSY 2 + +#if (KERNEL_VERSION(6, 3, 0) <= LINUX_VERSION_CODE) +static int __dcvs_tuning_scm_entry(struct adreno_device *adreno_dev, + u32 param, u32 val) +{ + int ret; + u32 mingap = 0, penalty = 0, numbusy = 0; + u32 *save; + + switch (param) { + case DCVS_TUNING_MINGAP: + mingap = DCVS_TUNING_EN_BIT | FIELD_PREP(GENMASK(4, 0), val); + save = &adreno_dev->dcvs_tuning_mingap_lvl; + break; + case DCVS_TUNING_PENALTY: + penalty = DCVS_TUNING_EN_BIT | FIELD_PREP(GENMASK(4, 0), val); + save = &adreno_dev->dcvs_tuning_penalty_lvl; + break; + case DCVS_TUNING_NUMBUSY: + numbusy = DCVS_TUNING_EN_BIT | FIELD_PREP(GENMASK(4, 0), val); + save = &adreno_dev->dcvs_tuning_numbusy_lvl; + break; + default: + return -EINVAL; + } + + if (!mutex_trylock(&adreno_dev->dcvs_tuning_mutex)) + return -EDEADLK; + + ret = qcom_scm_kgsl_dcvs_tuning(mingap, penalty, numbusy); + if (ret == 0) { + *save = val; + trace_adreno_dcvs_tuning(param, + adreno_dev->dcvs_tuning_mingap_lvl, + adreno_dev->dcvs_tuning_penalty_lvl, + adreno_dev->dcvs_tuning_numbusy_lvl); + } + mutex_unlock(&adreno_dev->dcvs_tuning_mutex); + + return ret; +} +#else +static int __dcvs_tuning_scm_entry(struct adreno_device *adreno_dev, u32 param, u32 val) +{ + return -EOPNOTSUPP; +} +#endif + +static int _dcvs_tuning_mingap_store(struct adreno_device *adreno_dev, + unsigned int val) +{ + if (val > DCVS_TUNING_MAX) + return -EINVAL; + + return __dcvs_tuning_scm_entry(adreno_dev, DCVS_TUNING_MINGAP, val); +} + +static u32 _dcvs_tuning_mingap_show(struct adreno_device *adreno_dev) +{ + return adreno_dev->dcvs_tuning_mingap_lvl; +} + +static int _dcvs_tuning_penalty_store(struct adreno_device *adreno_dev, + unsigned int val) +{ + if (val > DCVS_TUNING_MAX) + return -EINVAL; + + return __dcvs_tuning_scm_entry(adreno_dev, DCVS_TUNING_PENALTY, val); +} + +static u32 _dcvs_tuning_penalty_show(struct adreno_device *adreno_dev) +{ + return adreno_dev->dcvs_tuning_penalty_lvl; +} + +static int _dcvs_tuning_numbusy_store(struct adreno_device *adreno_dev, + unsigned int val) +{ + if (val > DCVS_TUNING_MAX) + return -EINVAL; + + return __dcvs_tuning_scm_entry(adreno_dev, DCVS_TUNING_NUMBUSY, val); +} + +static u32 _dcvs_tuning_numbusy_show(struct adreno_device *adreno_dev) +{ + return adreno_dev->dcvs_tuning_numbusy_lvl; +} + static int _gpu_llc_slice_enable_store(struct adreno_device *adreno_dev, bool val) { @@ -450,6 +565,10 @@ static DEVICE_ATTR_RO(gpu_model); static DEVICE_ATTR_RO(gpufaults); static DEVICE_ATTR_RO(gpufault_procs); +static ADRENO_SYSFS_U32(dcvs_tuning_mingap); +static ADRENO_SYSFS_U32(dcvs_tuning_penalty); +static ADRENO_SYSFS_U32(dcvs_tuning_numbusy); + static const struct attribute *_attr_list[] = { &adreno_attr_ft_policy.attr.attr, &adreno_attr_ft_pagefault_policy.attr.attr, @@ -477,6 +596,9 @@ static const struct attribute *_attr_list[] = { &adreno_attr_clx.attr.attr, &dev_attr_gpufaults.attr, &dev_attr_gpufault_procs.attr, + &adreno_attr_dcvs_tuning_mingap.attr.attr, + &adreno_attr_dcvs_tuning_penalty.attr.attr, + &adreno_attr_dcvs_tuning_numbusy.attr.attr, NULL, }; diff --git a/adreno_trace.h b/adreno_trace.h index 16974a83f7..890a8990a5 100644 --- a/adreno_trace.h +++ b/adreno_trace.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2013-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #if !defined(_ADRENO_TRACE_H) || defined(TRACE_HEADER_MULTI_READ) @@ -985,6 +985,25 @@ TRACE_EVENT(adreno_ifpc_count, TP_printk("total times GMU entered IFPC = %d", __entry->ifpc_count) ); +TRACE_EVENT(adreno_dcvs_tuning, + TP_PROTO(u32 param, u32 mingap, u32 penalty, u32 numbusy), + TP_ARGS(param, mingap, penalty, numbusy), + TP_STRUCT__entry( + __field(u32, param) + __field(u32, mingap) + __field(u32, penalty) + __field(u32, numbusy) + ), + TP_fast_assign( + __entry->param = param; + __entry->mingap = mingap; + __entry->penalty = penalty; + __entry->numbusy = numbusy; + ), + TP_printk("param=%u mingap=%u penalty=%u numbusy=%u", + __entry->param, __entry->mingap, __entry->penalty, __entry->numbusy) +); + #endif /* _ADRENO_TRACE_H */ /* This part must be outside protection */ diff --git a/governor_msm_adreno_tz.c b/governor_msm_adreno_tz.c index 4f52ae0ecd..5cbb5e6be4 100644 --- a/governor_msm_adreno_tz.c +++ b/governor_msm_adreno_tz.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2010-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2025, Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include @@ -57,6 +57,8 @@ static DEFINE_SPINLOCK(suspend_lock); #define TZ_V2_INIT_CA_ID_64 0xC #define TZ_V2_UPDATE_WITH_CA_ID_64 0xD +#define TZ_DCVS_TUNING_ID 0xE + #define TAG "msm_adreno_tz: " static u64 suspend_time; From bafdd911287ddee03750e38b112533d171b846fd Mon Sep 17 00:00:00 2001 From: Urvashi Agrawal Date: Tue, 12 Nov 2024 13:57:50 -0800 Subject: [PATCH 10/12] kgsl: gen8: Fix snapshot header for GPU registers Some unsliced registers need to have UINT_MAX in the snapshot header to correctly identify them as unsliced registers. Ensure the header is correct. Change-Id: Ib1f3a06b3d7e0ca622c0fb2c6af18d92f12c85de Signed-off-by: Urvashi Agrawal --- adreno_gen8_snapshot.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/adreno_gen8_snapshot.c b/adreno_gen8_snapshot.c index 521a6f542d..1c7ac63400 100644 --- a/adreno_gen8_snapshot.c +++ b/adreno_gen8_snapshot.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2025, Qualcomm Innovation Center, Inc. All rights reserved. */ #include "adreno.h" @@ -247,7 +247,7 @@ size_t gen8_legacy_snapshot_registers(struct kgsl_device *device, header->location_id = UINT_MAX; header->sp_id = UINT_MAX; header->usptp_id = UINT_MAX; - header->slice_id = info->slice_id; + header->slice_id = info->regs->slice_region ? info->slice_id : UINT_MAX; if (info->regs->sel) kgsl_regwrite(device, info->regs->sel->host_reg, info->regs->sel->val); @@ -298,7 +298,7 @@ static size_t gen8_snapshot_registers(struct kgsl_device *device, u8 *buf, header->location_id = UINT_MAX; header->sp_id = UINT_MAX; header->usptp_id = UINT_MAX; - header->slice_id = info->slice_id; + header->slice_id = info->regs->slice_region ? info->slice_id : UINT_MAX; src = gen8_crashdump_registers->hostptr + info->offset; @@ -336,7 +336,7 @@ static size_t gen8_legacy_snapshot_shader(struct kgsl_device *device, } header->type = block->statetype; - header->slice_id = info->slice_id; + header->slice_id = block->slice_region ? info->slice_id : UINT_MAX; header->sp_index = info->sp_id; header->usptp = info->usptp; header->pipe_id = block->pipeid; @@ -376,7 +376,7 @@ static size_t gen8_snapshot_shader_memory(struct kgsl_device *device, } header->type = block->statetype; - header->slice_id = info->slice_id; + header->slice_id = block->slice_region ? info->slice_id : UINT_MAX; header->sp_index = info->sp_id; header->usptp = info->usptp; header->pipe_id = block->pipeid; @@ -820,7 +820,7 @@ static size_t gen8_legacy_snapshot_cluster_dbgahb(struct kgsl_device *device, header->location_id = info->location_id; header->sp_id = info->sp_id; header->usptp_id = info->usptp_id; - header->slice_id = info->slice_id; + header->slice_id = info->cluster->slice_region ? info->slice_id : UINT_MAX; read_sel = GEN8_SP_READ_SEL_VAL(info->slice_id, info->location_id, info->pipe_id, info->statetype_id, info->usptp_id, info->sp_id); @@ -872,7 +872,7 @@ static size_t gen8_snapshot_cluster_dbgahb(struct kgsl_device *device, u8 *buf, header->location_id = info->location_id; header->sp_id = info->sp_id; header->usptp_id = info->usptp_id; - header->slice_id = info->slice_id; + header->slice_id = info->cluster->slice_region ? info->slice_id : UINT_MAX; src = gen8_crashdump_registers->hostptr + info->offset; @@ -1009,7 +1009,7 @@ static size_t gen8_legacy_snapshot_mvc(struct kgsl_device *device, u8 *buf, header->location_id = UINT_MAX; header->sp_id = UINT_MAX; header->usptp_id = UINT_MAX; - header->slice_id = info->slice_id; + header->slice_id = info->cluster->slice_region ? info->slice_id : UINT_MAX; /* * Set the AHB control for the Host to read from the @@ -1064,7 +1064,7 @@ static size_t gen8_snapshot_mvc(struct kgsl_device *device, u8 *buf, header->location_id = UINT_MAX; header->sp_id = UINT_MAX; header->usptp_id = UINT_MAX; - header->slice_id = info->slice_id; + header->slice_id = info->cluster->slice_region ? info->slice_id : UINT_MAX; src = gen8_crashdump_registers->hostptr + info->offset; From e2ff146c3266f8995e9a5e9e2828a3c3db5d7724 Mon Sep 17 00:00:00 2001 From: Sanjay Yadav Date: Thu, 26 Dec 2024 15:58:09 +0530 Subject: [PATCH 11/12] kgsl: Fix imported memory calculation for shared buffers Currently, when the same buffer is mapped as a surface in one process, it is ignored in the imported memory calculation of another process that imports it as an image, causing discrepancies. To fix this, the memory object size is now divided by the sum of EGL surface and EGL image counts. This ensures that the imported memory is accurately accounted for across different processes, regardless of flags. Change-Id: Ieade58964c51758f7fe54b2a473aa03fe374482e Signed-off-by: Sanjay Yadav --- kgsl_sharedmem.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/kgsl_sharedmem.c b/kgsl_sharedmem.c index e7f55670c4..24bb1f120f 100644 --- a/kgsl_sharedmem.c +++ b/kgsl_sharedmem.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2002,2007-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -256,19 +256,19 @@ imported_mem_show(struct kgsl_process_private *priv, m = &entry->memdesc; if (kgsl_memdesc_usermem_type(m) == KGSL_MEM_ENTRY_ION) { + u64 size = m->size; + int total_egl_count; + kgsl_get_egl_counts(entry, &egl_surface_count, &egl_image_count); + total_egl_count = egl_surface_count + egl_image_count; - if ((kgsl_memdesc_get_memtype(m) == KGSL_MEMTYPE_EGL_SURFACE) || - (kgsl_memdesc_get_memtype(m) == KGSL_MEMTYPE_SURFACE)) - imported_mem += m->size; - else if (egl_surface_count == 0) { - uint64_t size = m->size; - - do_div(size, (egl_image_count ? - egl_image_count : 1)); - imported_mem += size; - } + /* + * Divide the total buffer size uniformly across all the + * processes that imported the buffer. + */ + do_div(size, (total_egl_count ? total_egl_count : 1)); + imported_mem += size; } kgsl_mem_entry_put(entry); From 6d74af52fbe2fa82d8fab0c05ac4681d567a48b4 Mon Sep 17 00:00:00 2001 From: Gayathri Veeragandam Date: Wed, 19 Feb 2025 12:15:39 +0530 Subject: [PATCH 12/12] Revert "Merge "kgsl: Mark KGSL device as dma coherent"" Boot up Failures. This reverts commit 2033a54d99bc14fb4e868a662e22a64b9b1f3a7b, reversing changes made to df8a84e63ec52da9fd936141604d3e5c0141d984. Change-Id: I668279aa6a7dac090bcf5d272eae5880611b9177 Signed-off-by: Gayathri Veeragandam --- kgsl.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/kgsl.c b/kgsl.c index 25c3041f33..13d4c6887c 100644 --- a/kgsl.c +++ b/kgsl.c @@ -5127,15 +5127,6 @@ static int _register_device(struct kgsl_device *device) device->dev->dma_mask = &dma_mask; device->dev->dma_parms = &dma_parms; - /* - * Mark KGSL device as dma coherent when io-coherency - * is enabled to skip cache operations for imported dma - * buffers. - */ - if (kgsl_mmu_has_feature(device, KGSL_MMU_IO_COHERENT) && - IS_ENABLED(CONFIG_QCOM_KGSL_IOCOHERENCY_DEFAULT)) - device->dev->dma_coherent = true; - dma_set_max_seg_size(device->dev, (u32)DMA_BIT_MASK(32)); set_dma_ops(device->dev, NULL);