clk: Always vote INT_MAX as maximum voltage for a rail

Update regulator set voltage requests to always send INT_MAX as the max
voltage, this will ensure clocks never set any upper bound request for any
voltage regulator.

This avoids regulator_set_voltage() failures arising from different
regulator consumers specifying different max voltages.

Change-Id: Ie803d45623dbc4b9b2c31502e240c311db261f66
Signed-off-by: Taniya Das <tdas@codeaurora.org>
This commit is contained in:
Taniya Das
2019-05-17 13:27:17 +05:30
parent a7d847f5c2
commit 83d12e55ba

View File

@@ -646,8 +646,7 @@ static int clk_update_vdd(struct clk_vdd_class *vdd_class)
for (i = 0; i < vdd_class->num_regulators; i++) {
pr_debug("Set Voltage level Min %d, Max %d\n", uv[new_base + i],
uv[max_lvl + i]);
rc = regulator_set_voltage(r[i], uv[new_base + i],
vdd_class->use_max_uV ? INT_MAX : uv[max_lvl + i]);
rc = regulator_set_voltage(r[i], uv[new_base + i], INT_MAX);
if (rc)
goto set_voltage_fail;
@@ -668,13 +667,11 @@ static int clk_update_vdd(struct clk_vdd_class *vdd_class)
return rc;
enable_disable_fail:
regulator_set_voltage(r[i], uv[cur_base + i],
vdd_class->use_max_uV ? INT_MAX : uv[max_lvl + i]);
regulator_set_voltage(r[i], uv[cur_base + i], INT_MAX);
set_voltage_fail:
for (i--; i >= 0; i--) {
regulator_set_voltage(r[i], uv[cur_base + i],
vdd_class->use_max_uV ? INT_MAX : uv[max_lvl + i]);
regulator_set_voltage(r[i], uv[cur_base + i], INT_MAX);
if (cur_lvl == 0 || cur_lvl == vdd_class->num_levels)
regulator_disable(r[i]);
else if (level == 0)