clk: Always vote INT_MAX as maximum voltage for a rail
Update regulator set voltage requests to always send INT_MAX as the max voltage, this will ensure clocks never set any upper bound request for any voltage regulator. This avoids regulator_set_voltage() failures arising from different regulator consumers specifying different max voltages. Change-Id: Ie803d45623dbc4b9b2c31502e240c311db261f66 Signed-off-by: Taniya Das <tdas@codeaurora.org>
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@@ -646,8 +646,7 @@ static int clk_update_vdd(struct clk_vdd_class *vdd_class)
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for (i = 0; i < vdd_class->num_regulators; i++) {
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pr_debug("Set Voltage level Min %d, Max %d\n", uv[new_base + i],
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uv[max_lvl + i]);
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rc = regulator_set_voltage(r[i], uv[new_base + i],
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vdd_class->use_max_uV ? INT_MAX : uv[max_lvl + i]);
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rc = regulator_set_voltage(r[i], uv[new_base + i], INT_MAX);
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if (rc)
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goto set_voltage_fail;
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@@ -668,13 +667,11 @@ static int clk_update_vdd(struct clk_vdd_class *vdd_class)
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return rc;
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enable_disable_fail:
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regulator_set_voltage(r[i], uv[cur_base + i],
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vdd_class->use_max_uV ? INT_MAX : uv[max_lvl + i]);
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regulator_set_voltage(r[i], uv[cur_base + i], INT_MAX);
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set_voltage_fail:
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for (i--; i >= 0; i--) {
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regulator_set_voltage(r[i], uv[cur_base + i],
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vdd_class->use_max_uV ? INT_MAX : uv[max_lvl + i]);
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regulator_set_voltage(r[i], uv[cur_base + i], INT_MAX);
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if (cur_lvl == 0 || cur_lvl == vdd_class->num_levels)
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regulator_disable(r[i]);
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else if (level == 0)
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