diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt index df5db732138d..9ff13d5af0ce 100644 --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt @@ -36,24 +36,33 @@ each local arbiter. like display, video decode, and camera. And there are different ports in each larb. Take a example, There are many ports like MC, PP, VLD in the video decode local arbiter, all these ports are according to the video HW. + In some Socs, there may be a GALS(Global Async Local Sync) module between +smi-common and m4u, and additional GALS module between smi-larb and +smi-common. GALS can been seen as a "asynchronous fifo" which could help +synchronize for the modules in different clock frequence. Required properties: - compatible : must be one of the following string: "mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW. "mediatek,mt2712-m4u" for mt2712 which uses generation two m4u HW. "mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW. + "mediatek,mt8183-m4u" for mt8183 which uses generation two m4u HW. - reg : m4u register base and size. - interrupts : the interrupt of m4u. - clocks : must contain one entry for each clock-names. -- clock-names : must be "bclk", It is the block clock of m4u. +- clock-names : Only 1 optional clock: + - "bclk": the block clock of m4u. + Note that m4u use EMI clock which always has been enabled before kernel if + there is no this "bclk", like mt8183. - mediatek,larbs : List of phandle to the local arbiters in the current Socs. Refer to bindings/memory-controllers/mediatek,smi-larb.txt. It must sort according to the local arbiter index, like larb0, larb1, larb2... - iommu-cells : must be 1. This is the mtk_m4u_id according to the HW. Specifies the mtk_m4u_id as defined in dt-binding/memory/mt2701-larb-port.h for mt2701, - dt-binding/memory/mt2712-larb-port.h for mt2712, and - dt-binding/memory/mt8173-larb-port.h for mt8173. + dt-binding/memory/mt2712-larb-port.h for mt2712, + dt-binding/memory/mt8173-larb-port.h for mt8173, and + dt-binding/memory/mt8183-larb-port.h for mt8183. Example: iommu: iommu@10205000 { diff --git a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt new file mode 100644 index 000000000000..26f65a402a90 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt @@ -0,0 +1,65 @@ +MediaTek GCE +=============== + +The Global Command Engine (GCE) is used to help read/write registers with +critical time limitation, such as updating display configuration during the +vblank. The GCE can be used to implement the Command Queue (CMDQ) driver. + +CMDQ driver uses mailbox framework for communication. Please refer to +mailbox.txt for generic information about mailbox device-tree bindings. + +Required properties: +- compatible: Must be "mediatek,mt8173-gce" +- reg: Address range of the GCE unit +- interrupts: The interrupt signal from the GCE block +- clock: Clocks according to the common clock binding +- clock-names: Must be "gce" to stand for GCE clock +- thread-num: Maximum threads count of GCE. +- #mbox-cells: Should be 4. + <&phandle channel timeout priority atomic_exec> + phandle: Label name of a gce node. + channel: Channel of mailbox. Be equal to the thread id of GCE. + timeout: Maximum time of software waiting GCE processing done, in unit + of millisecond. + priority: Priority of GCE thread. + atomic_exec: GCE processing continuous packets of commands in atomic + way. + +Required properties for a client device: +- mboxes: Client use mailbox to communicate with GCE, it should have this + property and list of phandle, mailbox specifiers. +- gce-subsys: Specify the sub-system id which is corresponding to the register + address. + +Optional properties for a client device: +- gce-event: Specify the event if the client has any. Because the event is + parsed by client, so client can replace 'gce-event' with other meaningful + name. + +Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h'. Such as +thread number, sub-system ids, thread priority, event ids. + +Example: + + gce: gce@10212000 { + compatible = "mediatek,mt8173-gce"; + reg = <0 0x10212000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_GCE>; + clock-names = "gce"; + thread-num = CMDQ_THR_MAX_COUNT; + #mbox-cells = <4>; + }; + +Example for a client device: + + mmsys: clock-controller@14000000 { + compatible = "mediatek,mt8173-mmsys"; + mboxes = <&gce 0 2000 CMDQ_THR_PRIO_LOWEST 1>, + <&gce 1 2000 CMDQ_THR_PRIO_LOWEST 1>; + gce-subsys = ; + mutex-event-eof = ; + + ... + }; diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt index 615abdd0eb0d..147d00d04fd0 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt @@ -2,9 +2,10 @@ SMI (Smart Multimedia Interface) Common The hardware block diagram please check bindings/iommu/mediatek,iommu.txt -Mediatek SMI have two generations of HW architecture, mt2712 and mt8173 use -the second generation of SMI HW while mt2701 uses the first generation HW of -SMI. +Mediatek SMI have two generations of HW architecture, here is the list +which generation the Socs use: +generation 1: mt2701. +generation 2: mt2712, mt8173 and mt8183. There's slight differences between the two SMI, for generation 2, the register which control the iommu port is at each larb's register base. But @@ -18,6 +19,7 @@ Required properties: "mediatek,mt2701-smi-common" "mediatek,mt2712-smi-common" "mediatek,mt8173-smi-common" + "mediatek,mt8183-smi-common" - reg : the register and size of the SMI block. - power-domains : a phandle to the power domain of this local arbiter. - clocks : Must contain an entry for each entry in clock-names. @@ -29,6 +31,11 @@ Required properties: They may be the same if both source clocks are the same. - "async" : asynchronous clock, it help transform the smi clock into the emi clock domain, this clock is only needed by generation 1 smi HW. + and these 2 option clocks for generation 2 smi HW: + - "gals0": the path0 clock of GALS(Global Async Local Sync). + - "gals1": the path1 clock of GALS(Global Async Local Sync). + Note that "gals0" and "gals1" clock only exist while the SMI HW has "GALS" + modules. Example: smi_common: smi@14022000 { diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt index 083155cdc2a0..e46bf5eb8b55 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt @@ -7,6 +7,7 @@ Required properties: "mediatek,mt2701-smi-larb" "mediatek,mt2712-smi-larb" "mediatek,mt8173-smi-larb" + "mediatek,mt8183-smi-larb" - reg : the register and size of this local arbiter. - mediatek,smi : a phandle to the smi_common node. - power-domains : a phandle to the power domain of this local arbiter. @@ -15,6 +16,8 @@ Required properties: - "apb" : Advanced Peripheral Bus clock, It's the clock for setting the register. - "smi" : It's the clock for transfer data and command. + and this optional clock name: + - "gals": the clock for gals(Global Async Local Sync). Required property for mt2701 and mt2712: - mediatek,larb-id :the hardware id of this larb. diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.txt b/Documentation/devicetree/bindings/mmc/mtk-sd.txt index f33467a54a05..d844f2d7e18d 100644 --- a/Documentation/devicetree/bindings/mmc/mtk-sd.txt +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.txt @@ -14,6 +14,7 @@ Required properties: "mediatek,mt2712-mmc": for mmc host ip compatible with mt2712 "mediatek,mt7622-mmc": for MT7622 SoC "mediatek,mt7623-mmc", "mediatek,mt2701-mmc": for MT7623 SoC + "mediatek,mt8183-mmc": for mmc host ip compatible with mt8183 - reg: physical base address of the controller and length - interrupts: Should contain MSDC interrupt number diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 567df6e5759f..c985802d453d 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -1,13 +1,11 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_MEDIATEK) += aiv8183m1v2.dtb -dtb-$(CONFIG_ARCH_MEDIATEK) += aiv8183m1v2-clkitg.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb -dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-clkitg.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb ifeq ($(strip $(CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE)), y) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index da64e1cab233..b07a2d69944c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -18,6 +18,7 @@ #include #include #include +#include #include "mt8173-pinfunc.h" / { @@ -429,6 +430,16 @@ status = "disabled"; }; + gce: gce@10212000 { + compatible = "mediatek,mt8173-gce"; + reg = <0 0x10212000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_GCE>; + clock-names = "gce"; + thread-num = ; + #mbox-cells = <4>; + }; + mipi_tx0: mipi-dphy@10215000 { compatible = "mediatek,mt8173-mipi-tx"; reg = <0 0x10215000 0 0x1000>; diff --git a/drivers/clk/mediatek/clkdbg.c b/drivers/clk/mediatek/clkdbg.c index 4fe9385529eb..f4a65edf834d 100644 --- a/drivers/clk/mediatek/clkdbg.c +++ b/drivers/clk/mediatek/clkdbg.c @@ -1688,6 +1688,11 @@ static struct pdev_drv pderv[] = { PDEV_DRV("clkdbg-pd8"), PDEV_DRV("clkdbg-pd9"), PDEV_DRV("clkdbg-pd10"), + PDEV_DRV("clkdbg-pd11"), + PDEV_DRV("clkdbg-pd12"), + PDEV_DRV("clkdbg-pd13"), + PDEV_DRV("clkdbg-pd14"), + PDEV_DRV("clkdbg-pd15"), }; static void reg_pdev_drv(const char *pdname, struct seq_file *s) diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile index ce83c396a742..ee29d1267d7b 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -13,6 +13,8 @@ mediatek-drm-y := mtk_disp_color.o \ mtk_mipi_tx.o \ mtk_dpi.o +mediatek-drm-$(CONFIG_DRM_FBDEV_EMULATION) += mtk_drm_fbdev.o + obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o mediatek-drm-hdmi-objs := mtk_cec.o \ diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index a2ca90fc403c..f5f9888d54b2 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -30,6 +30,7 @@ #include "mtk_drm_ddp_comp.h" #include "mtk_drm_drv.h" #include "mtk_drm_fb.h" +#include "mtk_drm_fbdev.h" #include "mtk_drm_gem.h" #define DRIVER_NAME "mediatek" @@ -127,10 +128,20 @@ static int mtk_atomic_commit(struct drm_device *drm, return 0; } +static void mtk_drm_mode_output_poll_changed(struct drm_device *dev) +{ + struct mtk_drm_private *priv = dev->dev_private; + struct drm_fb_helper *fb_helper = &priv->fb_helper; + + if (fb_helper) + drm_fb_helper_hotplug_event(fb_helper); +} + static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = { .fb_create = mtk_drm_mode_fb_create, .atomic_check = drm_atomic_helper_check, .atomic_commit = mtk_atomic_commit, + .output_poll_changed = mtk_drm_mode_output_poll_changed, }; static const enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = { @@ -257,8 +268,14 @@ static int mtk_drm_kms_init(struct drm_device *drm) drm_kms_helper_poll_init(drm); drm_mode_config_reset(drm); + ret = mtk_fbdev_init(drm); + if (ret) + goto err_kms_helper_poll_fini; + return 0; +err_kms_helper_poll_fini: + drm_kms_helper_poll_fini(drm); err_component_unbind: component_unbind_all(drm->dev, drm); err_config_cleanup: @@ -269,6 +286,7 @@ err_config_cleanup: static void mtk_drm_kms_deinit(struct drm_device *drm) { + mtk_fbdev_fini(drm); drm_kms_helper_poll_fini(drm); component_unbind_all(drm->dev, drm); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h index c3378c452c0a..4edc0023684c 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -14,6 +14,7 @@ #ifndef MTK_DRM_DRV_H #define MTK_DRM_DRV_H +#include #include #include "mtk_drm_ddp_comp.h" @@ -24,7 +25,6 @@ struct device; struct device_node; struct drm_crtc; struct drm_device; -struct drm_fb_helper; struct drm_property; struct regmap; @@ -56,6 +56,8 @@ struct mtk_drm_private { } commit; struct drm_atomic_state *suspend_state; + struct drm_fb_helper fb_helper; + struct drm_gem_object *fbdev_bo; }; extern struct platform_driver mtk_ddp_driver; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_fb.c b/drivers/gpu/drm/mediatek/mtk_drm_fb.c index 0d8d506695f9..ac8561de79b8 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_fb.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_fb.c @@ -96,6 +96,19 @@ static struct mtk_drm_fb *mtk_drm_framebuffer_init(struct drm_device *dev, return mtk_fb; } +struct drm_framebuffer *mtk_drm_framebuffer_create(struct drm_device *dev, + const struct drm_mode_fb_cmd2 *mode, + struct drm_gem_object *obj) +{ + struct mtk_drm_fb *mtk_fb; + + mtk_fb = mtk_drm_framebuffer_init(dev, mode, obj); + if (IS_ERR(mtk_fb)) + return ERR_CAST(mtk_fb); + + return &mtk_fb->base; +} + /* * Wait for any exclusive fence in fb's gem object's reservation object. * diff --git a/drivers/gpu/drm/mediatek/mtk_drm_fb.h b/drivers/gpu/drm/mediatek/mtk_drm_fb.h index 9b2ae345a4e9..9ee1ac266a79 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_fb.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_fb.h @@ -19,5 +19,8 @@ int mtk_fb_wait(struct drm_framebuffer *fb); struct drm_framebuffer *mtk_drm_mode_fb_create(struct drm_device *dev, struct drm_file *file, const struct drm_mode_fb_cmd2 *cmd); +struct drm_framebuffer *mtk_drm_framebuffer_create(struct drm_device *dev, + const struct drm_mode_fb_cmd2 *mode, + struct drm_gem_object *obj); #endif /* MTK_DRM_FB_H */ diff --git a/drivers/gpu/drm/mediatek/mtk_drm_fbdev.c b/drivers/gpu/drm/mediatek/mtk_drm_fbdev.c new file mode 100644 index 000000000000..f70ae1111635 --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_drm_fbdev.c @@ -0,0 +1,183 @@ +/* + * Copyright (c) 2016 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#include "mtk_drm_drv.h" +#include "mtk_drm_fb.h" +#include "mtk_drm_gem.h" + +#define to_drm_private(x) \ + container_of(x, struct mtk_drm_private, fb_helper) + +static int mtk_drm_fbdev_mmap(struct fb_info *info, struct vm_area_struct *vma) +{ + struct drm_fb_helper *helper = info->par; + struct mtk_drm_private *private = to_drm_private(helper); + + return mtk_drm_gem_mmap_buf(private->fbdev_bo, vma); +} + +static struct fb_ops mtk_fbdev_ops = { + .owner = THIS_MODULE, + .fb_fillrect = drm_fb_helper_cfb_fillrect, + .fb_copyarea = drm_fb_helper_cfb_copyarea, + .fb_imageblit = drm_fb_helper_cfb_imageblit, + .fb_check_var = drm_fb_helper_check_var, + .fb_set_par = drm_fb_helper_set_par, + .fb_blank = drm_fb_helper_blank, + .fb_pan_display = drm_fb_helper_pan_display, + .fb_setcmap = drm_fb_helper_setcmap, + .fb_mmap = mtk_drm_fbdev_mmap, +}; + +static int mtk_fbdev_probe(struct drm_fb_helper *helper, + struct drm_fb_helper_surface_size *sizes) +{ + struct drm_device *dev = helper->dev; + struct mtk_drm_private *private = to_drm_private(helper); + struct drm_mode_fb_cmd2 mode = { 0 }; + struct mtk_drm_gem_obj *mtk_gem; + struct fb_info *info; + struct drm_framebuffer *fb; + unsigned int bytes_per_pixel; + unsigned long offset; + size_t size; + int err; + + bytes_per_pixel = DIV_ROUND_UP(sizes->surface_bpp, 8); + + mode.width = sizes->surface_width; + mode.height = sizes->surface_height; + mode.pitches[0] = sizes->surface_width * bytes_per_pixel; + mode.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp, + sizes->surface_depth); + + size = mode.pitches[0] * mode.height; + + mtk_gem = mtk_drm_gem_create(dev, size, true); + if (IS_ERR(mtk_gem)) + return PTR_ERR(mtk_gem); + + private->fbdev_bo = &mtk_gem->base; + + info = drm_fb_helper_alloc_fbi(helper); + if (IS_ERR(info)) { + err = PTR_ERR(info); + dev_err(dev->dev, "failed to allocate framebuffer info, %d\n", + err); + goto err_gem_free_object; + } + + fb = mtk_drm_framebuffer_create(dev, &mode, private->fbdev_bo); + if (IS_ERR(fb)) { + err = PTR_ERR(fb); + dev_err(dev->dev, "failed to allocate DRM framebuffer, %d\n", + err); + goto err_release_fbi; + } + helper->fb = fb; + + info->par = helper; + info->flags = FBINFO_FLAG_DEFAULT; + info->fbops = &mtk_fbdev_ops; + + drm_fb_helper_fill_fix(info, fb->pitches[0], fb->format->depth); + drm_fb_helper_fill_var(info, helper, sizes->fb_width, sizes->fb_height); + + offset = info->var.xoffset * bytes_per_pixel; + offset += info->var.yoffset * fb->pitches[0]; + + dev->mode_config.fb_base = 0; + info->screen_base = mtk_gem->kvaddr + offset; + info->screen_size = size; + info->fix.smem_len = size; + + DRM_DEBUG_KMS("FB [%ux%u]-%u offset=%lu size=%zd\n", + fb->width, fb->height, fb->format->depth, offset, size); + + info->skip_vt_switch = true; + + return 0; + +err_release_fbi: +err_gem_free_object: + mtk_drm_gem_free_object(&mtk_gem->base); + return err; +} + +static const struct drm_fb_helper_funcs mtk_drm_fb_helper_funcs = { + .fb_probe = mtk_fbdev_probe, +}; + +int mtk_fbdev_init(struct drm_device *dev) +{ + struct mtk_drm_private *priv = dev->dev_private; + struct drm_fb_helper *helper = &priv->fb_helper; + int ret; + + if (!dev->mode_config.num_crtc || !dev->mode_config.num_connector) + return -EINVAL; + + drm_fb_helper_prepare(dev, helper, &mtk_drm_fb_helper_funcs); + + ret = drm_fb_helper_init(dev, helper, + dev->mode_config.num_connector); + if (ret) { + dev_err(dev->dev, "failed to initialize DRM FB helper, %d\n", + ret); + goto fini; + } + + ret = drm_fb_helper_single_add_all_connectors(helper); + if (ret) { + dev_err(dev->dev, "failed to add connectors, %d\n", ret); + goto fini; + } + + /* disable all the possible outputs/crtcs before entering KMS mode */ + if (!drm_drv_uses_atomic_modeset(dev)) + drm_helper_disable_unused_functions(dev); + + ret = drm_fb_helper_initial_config(helper, 32); + if (ret) { + dev_err(dev->dev, "failed to set initial configuration, %d\n", + ret); + goto fini; + } + + return 0; + +fini: + drm_fb_helper_fini(helper); + + return ret; +} + +void mtk_fbdev_fini(struct drm_device *dev) +{ + struct mtk_drm_private *priv = dev->dev_private; + struct drm_fb_helper *helper = &priv->fb_helper; + + drm_fb_helper_unregister_fbi(helper); + + if (helper->fb) { + drm_framebuffer_unregister_private(helper->fb); + drm_framebuffer_remove(helper->fb); + } + + drm_fb_helper_fini(helper); +} diff --git a/drivers/gpu/drm/mediatek/mtk_drm_fbdev.h b/drivers/gpu/drm/mediatek/mtk_drm_fbdev.h new file mode 100644 index 000000000000..f3e09492aa47 --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_drm_fbdev.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2016 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MTK_DRM_FBDEV_H +#define MTK_DRM_FBDEV_H + +#ifdef CONFIG_DRM_FBDEV_EMULATION +int mtk_fbdev_init(struct drm_device *dev); +void mtk_fbdev_fini(struct drm_device *dev); +#else +int mtk_fbdev_init(struct drm_device *dev) +{ + return 0; +} + +void mtk_fbdev_fini(struct drm_device *dev) +{ + +} +#endif /* CONFIG_DRM_FBDEV_EMULATION */ + +#endif /* MTK_DRM_FBDEV_H */ diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c index 2ca08dc9331c..9eff0434f87a 100644 --- a/drivers/iommu/io-pgtable-arm-v7s.c +++ b/drivers/iommu/io-pgtable-arm-v7s.c @@ -124,7 +124,9 @@ #define ARM_V7S_TEX_MASK 0x7 #define ARM_V7S_ATTR_TEX(val) (((val) & ARM_V7S_TEX_MASK) << ARM_V7S_TEX_SHIFT) -#define ARM_V7S_ATTR_MTK_4GB BIT(9) /* MTK extend it for 4GB mode */ +/* MTK extend the two bits below for over 4GB mode */ +#define ARM_V7S_ATTR_MTK_PA_BIT32 BIT(9) +#define ARM_V7S_ATTR_MTK_PA_BIT33 BIT(4) /* *well, except for TEX on level 2 large pages, of course :( */ #define ARM_V7S_CONT_PAGE_TEX_SHIFT 6 @@ -263,7 +265,8 @@ static void __arm_v7s_set_pte(arm_v7s_iopte *ptep, arm_v7s_iopte pte, } static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl, - struct io_pgtable_cfg *cfg) + struct io_pgtable_cfg *cfg, + phys_addr_t paddr) /* Only for MTK */ { bool ap = !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS); arm_v7s_iopte pte = ARM_V7S_ATTR_NG | ARM_V7S_ATTR_S; @@ -290,8 +293,12 @@ static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl, if (lvl == 1 && (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS)) pte |= ARM_V7S_ATTR_NS_SECTION; - if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB) - pte |= ARM_V7S_ATTR_MTK_4GB; + if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB) { + if (paddr & BIT_ULL(32)) + pte |= ARM_V7S_ATTR_MTK_PA_BIT32; + if (paddr & BIT_ULL(33)) + pte |= ARM_V7S_ATTR_MTK_PA_BIT33; + } return pte; } @@ -387,7 +394,7 @@ static int arm_v7s_init_pte(struct arm_v7s_io_pgtable *data, return -EEXIST; } - pte = arm_v7s_prot_to_pte(prot, lvl, cfg); + pte = arm_v7s_prot_to_pte(prot, lvl, cfg, paddr); if (num_entries > 1) pte = arm_v7s_pte_to_cont(pte, lvl); @@ -479,7 +486,11 @@ static int arm_v7s_map(struct io_pgtable_ops *ops, unsigned long iova, if (!(prot & (IOMMU_READ | IOMMU_WRITE))) return 0; - if (WARN_ON(upper_32_bits(iova) || upper_32_bits(paddr))) + if (WARN_ON(upper_32_bits(iova))) + return -ERANGE; + + if (WARN_ON(upper_32_bits(paddr) && + !(iop->cfg.quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB))) return -ERANGE; ret = __arm_v7s_map(data, iova, paddr, size, prot, 1, data->pgd); @@ -557,7 +568,7 @@ static int arm_v7s_split_blk_unmap(struct arm_v7s_io_pgtable *data, num_entries = size >> ARM_V7S_LVL_SHIFT(2); unmap_idx = ARM_V7S_LVL_IDX(iova, 2); - pte = arm_v7s_prot_to_pte(arm_v7s_pte_to_prot(blk_pte, 1), 2, cfg); + pte = arm_v7s_prot_to_pte(arm_v7s_pte_to_prot(blk_pte, 1), 2, cfg, 0); if (num_entries > 1) pte = arm_v7s_pte_to_cont(pte, 2); @@ -671,7 +682,9 @@ static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops, unsigned long iova) { struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops); + struct io_pgtable_cfg *cfg = &data->iop.cfg; arm_v7s_iopte *ptep = data->pgd, pte; + phys_addr_t paddr; int lvl = 0; u32 mask; @@ -687,7 +700,16 @@ static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops, mask = ARM_V7S_LVL_MASK(lvl); if (arm_v7s_pte_is_cont(pte, lvl)) mask *= ARM_V7S_CONT_PAGES; - return (pte & mask) | (iova & ~mask); + paddr = (pte & mask) | (iova & ~mask); + + if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) && + cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB) { + if (pte & ARM_V7S_ATTR_MTK_PA_BIT32) + paddr |= BIT_ULL(32); + if (pte & ARM_V7S_ATTR_MTK_PA_BIT33) + paddr |= BIT_ULL(33); + } + return paddr; } static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, diff --git a/drivers/iommu/io-pgtable.h b/drivers/iommu/io-pgtable.h index cd2e1eafffe6..6e92a82ad57e 100644 --- a/drivers/iommu/io-pgtable.h +++ b/drivers/iommu/io-pgtable.h @@ -62,10 +62,10 @@ struct io_pgtable_cfg { * (unmapped) entries but the hardware might do so anyway, perform * TLB maintenance when mapping as well as when unmapping. * - * IO_PGTABLE_QUIRK_ARM_MTK_4GB: (ARM v7s format) Set bit 9 in all - * PTEs, for Mediatek IOMMUs which treat it as a 33rd address bit - * when the SoC is in "4GB mode" and they can only access the high - * remap of DRAM (0x1_00000000 to 0x1_ffffffff). + * IO_PGTABLE_QUIRK_ARM_MTK_4GB: (ARM v7s format) Set bit 4 and 9 in all + * PTEs, for Mediatek IOMMUs which treat it as the 33rd and 32rd + * address bit when the SoC dram is over 4GB and they can access + * the physical address from 0x4000_0000 to 0x3_ffff_ffff. * * IO_PGTABLE_QUIRK_NO_DMA: Guarantees that the tables will only ever * be accessed by a fully cache-coherent IOMMU or CPU (e.g. for a diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index f2832a10fcea..193d568d9c52 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -36,6 +36,7 @@ #include "mtk_iommu.h" #define REG_MMU_PT_BASE_ADDR 0x000 +#define MMU_PT_ADDR_MASK GENMASK(31, 7) #define REG_MMU_INVALIDATE 0x020 #define F_ALL_INVLD 0x2 @@ -54,7 +55,7 @@ #define REG_MMU_CTRL_REG 0x110 #define F_MMU_PREFETCH_RT_REPLACE_MOD BIT(4) #define F_MMU_TF_PROTECT_SEL_SHIFT(data) \ - ((data)->m4u_plat == M4U_MT2712 ? 4 : 5) + ((data)->plat_data->m4u_plat == M4U_MT8173 ? 5 : 4) /* It's named by F_MMU_TF_PROT_SEL in mt2712. */ #define F_MMU_TF_PROTECT_SEL(prot, data) \ (((prot) & 0x3) << F_MMU_TF_PROTECT_SEL_SHIFT(data)) @@ -73,27 +74,32 @@ #define F_MISS_FIFO_ERR_INT_EN BIT(6) #define F_INT_CLR_BIT BIT(12) -#define REG_MMU_INT_MAIN_CONTROL 0x124 -#define F_INT_TRANSLATION_FAULT BIT(0) -#define F_INT_MAIN_MULTI_HIT_FAULT BIT(1) -#define F_INT_INVALID_PA_FAULT BIT(2) -#define F_INT_ENTRY_REPLACEMENT_FAULT BIT(3) -#define F_INT_TLB_MISS_FAULT BIT(4) -#define F_INT_MISS_TRANSACTION_FIFO_FAULT BIT(5) -#define F_INT_PRETETCH_TRANSATION_FIFO_FAULT BIT(6) +#define REG_MMU_INT_MAIN_CONTROL 0x124 /* mmu0 | mmu1 */ +#define F_INT_TRANSLATION_FAULT (BIT(0) | BIT(7)) +#define F_INT_MAIN_MULTI_HIT_FAULT (BIT(1) | BIT(8)) +#define F_INT_INVALID_PA_FAULT (BIT(2) | BIT(9)) +#define F_INT_ENTRY_REPLACEMENT_FAULT (BIT(3) | BIT(10)) +#define F_INT_TLB_MISS_FAULT (BIT(4) | BIT(11)) +#define F_INT_MISS_TRANSACTION_FIFO_FAULT (BIT(5) | BIT(12)) +#define F_INT_PRETETCH_TRANSATION_FIFO_FAULT (BIT(6) | BIT(13)) #define REG_MMU_CPE_DONE 0x12C #define REG_MMU_FAULT_ST1 0x134 +#define F_REG_MMU0_FAULT_MASK GENMASK(6, 0) +#define F_REG_MMU1_FAULT_MASK GENMASK(13, 7) -#define REG_MMU_FAULT_VA 0x13c +#define REG_MMU0_FAULT_VA 0x13c #define F_MMU_FAULT_VA_WRITE_BIT BIT(1) #define F_MMU_FAULT_VA_LAYER_BIT BIT(0) -#define REG_MMU_INVLD_PA 0x140 -#define REG_MMU_INT_ID 0x150 -#define F_MMU0_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7) -#define F_MMU0_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f) +#define REG_MMU0_INVLD_PA 0x140 +#define REG_MMU1_FAULT_VA 0x144 +#define REG_MMU1_INVLD_PA 0x148 +#define REG_MMU0_INT_ID 0x150 +#define REG_MMU1_INT_ID 0x154 +#define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7) +#define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f) #define MTK_PROTECT_PA_ALIGN 128 @@ -202,6 +208,17 @@ static const struct iommu_gather_ops mtk_iommu_gather_ops = { .tlb_sync = mtk_iommu_tlb_sync, }; +static unsigned int mtk_iommu_get_larbid(const unsigned int *larbid_in_common, + const unsigned int fault_larb) +{ + int i; + + for (i = 0; i < MTK_LARB_NR_MAX; i++) + if (larbid_in_common[i] == fault_larb) + return i; + return MTK_LARB_NR_MAX; /* Invalid larb id. */ +} + static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) { struct mtk_iommu_data *data = dev_id; @@ -212,14 +229,24 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) /* Read error info from registers */ int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST1); - fault_iova = readl_relaxed(data->base + REG_MMU_FAULT_VA); + if (int_state & F_REG_MMU0_FAULT_MASK) { + regval = readl_relaxed(data->base + REG_MMU0_INT_ID); + fault_iova = readl_relaxed(data->base + REG_MMU0_FAULT_VA); + fault_pa = readl_relaxed(data->base + REG_MMU0_INVLD_PA); + } else { + regval = readl_relaxed(data->base + REG_MMU1_INT_ID); + fault_iova = readl_relaxed(data->base + REG_MMU1_FAULT_VA); + fault_pa = readl_relaxed(data->base + REG_MMU1_INVLD_PA); + } layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT; write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT; - fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA); - regval = readl_relaxed(data->base + REG_MMU_INT_ID); - fault_larb = F_MMU0_INT_ID_LARB_ID(regval); - fault_port = F_MMU0_INT_ID_PORT_ID(regval); + fault_larb = F_MMU_INT_ID_LARB_ID(regval); + fault_port = F_MMU_INT_ID_PORT_ID(regval); + if (data->plat_data->larbid_remap_enable) + fault_larb = mtk_iommu_get_larbid( + data->plat_data->larbid_in_common, + fault_larb); if (report_iommu_fault(&dom->domain, data->dev, fault_iova, write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) { dev_err_ratelimited( @@ -344,7 +371,7 @@ static int mtk_iommu_attach_device(struct iommu_domain *domain, /* Update the pgtable base address register of the M4U HW */ if (!data->m4u_dom) { data->m4u_dom = dom; - writel(dom->cfg.arm_v7s_cfg.ttbr[0], + writel(dom->cfg.arm_v7s_cfg.ttbr[0] & MMU_PT_ADDR_MASK, data->base + REG_MMU_PT_BASE_ADDR); } @@ -367,12 +394,17 @@ static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova, phys_addr_t paddr, size_t size, int prot) { struct mtk_iommu_domain *dom = to_mtk_domain(domain); + struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); unsigned long flags; int ret; + if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) && + data->plat_data->has_4gb_mode && + data->enable_4GB) + paddr |= BIT_ULL(32); + spin_lock_irqsave(&dom->pgtlock, flags); - ret = dom->iop->map(dom->iop, iova, paddr & DMA_BIT_MASK(32), - size, prot); + ret = dom->iop->map(dom->iop, iova, paddr, size, prot); spin_unlock_irqrestore(&dom->pgtlock, flags); return ret; @@ -401,7 +433,6 @@ static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova) { struct mtk_iommu_domain *dom = to_mtk_domain(domain); - struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); unsigned long flags; phys_addr_t pa; @@ -409,9 +440,6 @@ static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain, pa = dom->iop->iova_to_phys(dom->iop, iova); spin_unlock_irqrestore(&dom->pgtlock, flags); - if (data->enable_4GB) - pa |= BIT_ULL(32); - return pa; } @@ -508,6 +536,7 @@ static struct iommu_ops mtk_iommu_ops = { static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) { + enum mtk_iommu_plat m4u_plat = data->plat_data->m4u_plat; u32 regval; int ret; @@ -518,7 +547,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) } regval = F_MMU_TF_PROTECT_SEL(2, data); - if (data->m4u_plat == M4U_MT8173) + if (m4u_plat == M4U_MT8173) regval |= F_MMU_PREFETCH_RT_REPLACE_MOD; writel_relaxed(regval, data->base + REG_MMU_CTRL_REG); @@ -539,14 +568,14 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) F_INT_PRETETCH_TRANSATION_FIFO_FAULT; writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL); - if (data->m4u_plat == M4U_MT8173) + if (m4u_plat == M4U_MT8173) regval = (data->protect_base >> 1) | (data->enable_4GB << 31); else regval = lower_32_bits(data->protect_base) | upper_32_bits(data->protect_base); writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR); - if (data->enable_4GB && data->m4u_plat != M4U_MT8173) { + if (data->enable_4GB && m4u_plat == M4U_MT2712) { /* * If 4GB mode is enabled, the validate PA range is from * 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30]. @@ -556,8 +585,11 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) } writel_relaxed(0, data->base + REG_MMU_DCM_DIS); - /* It's MISC control register whose default value is ok except mt8173.*/ - if (data->m4u_plat == M4U_MT8173) + /* + * It's MISC control register whose default value is ok + * except mt8173 and mt8183. + */ + if (m4u_plat == M4U_MT8173 || m4u_plat == M4U_MT8183) writel_relaxed(0, data->base + REG_MMU_STANDARD_AXI_MODE); if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, @@ -590,7 +622,7 @@ static int mtk_iommu_probe(struct platform_device *pdev) if (!data) return -ENOMEM; data->dev = dev; - data->m4u_plat = (enum mtk_iommu_plat)of_device_get_match_data(dev); + data->plat_data = of_device_get_match_data(dev); /* Protect memory. HW will access here while translation fault.*/ protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, GFP_KERNEL); @@ -612,7 +644,9 @@ static int mtk_iommu_probe(struct platform_device *pdev) return data->irq; data->bclk = devm_clk_get(dev, "bclk"); - if (IS_ERR(data->bclk)) + if (PTR_ERR(data->bclk) == -ENOENT) + data->bclk = NULL; + else if (IS_ERR(data->bclk)) return PTR_ERR(data->bclk); larb_nr = of_count_phandle_with_args(dev->of_node, @@ -688,6 +722,11 @@ static int mtk_iommu_remove(struct platform_device *pdev) return 0; } +static void mtk_iommu_shutdown(struct platform_device *pdev) +{ + mtk_iommu_remove(pdev); +} + static int __maybe_unused mtk_iommu_suspend(struct device *dev) { struct mtk_iommu_data *data = dev_get_drvdata(dev); @@ -701,6 +740,7 @@ static int __maybe_unused mtk_iommu_suspend(struct device *dev) reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL0); reg->int_main_control = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL); reg->ivrp_paddr = readl_relaxed(base + REG_MMU_IVRP_PADDR); + reg->vld_pa_range = readl_relaxed(base + REG_MMU_VLD_PA_RNG); clk_disable_unprepare(data->bclk); return 0; } @@ -709,6 +749,7 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev) { struct mtk_iommu_data *data = dev_get_drvdata(dev); struct mtk_iommu_suspend_reg *reg = &data->reg; + struct mtk_iommu_domain *dom = data->m4u_dom; void __iomem *base = data->base; int ret; @@ -724,8 +765,9 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev) writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0); writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL); writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR); - if (data->m4u_dom) - writel(data->m4u_dom->cfg.arm_v7s_cfg.ttbr[0], + writel_relaxed(reg->vld_pa_range, base + REG_MMU_VLD_PA_RNG); + if (dom) + writel(dom->cfg.arm_v7s_cfg.ttbr[0] & MMU_PT_ADDR_MASK, base + REG_MMU_PT_BASE_ADDR); return 0; } @@ -734,15 +776,33 @@ static const struct dev_pm_ops mtk_iommu_pm_ops = { SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_iommu_suspend, mtk_iommu_resume) }; +static const struct mtk_iommu_plat_data mt2712_data = { + .m4u_plat = M4U_MT2712, + .has_4gb_mode = true, +}; + +static const struct mtk_iommu_plat_data mt8173_data = { + .m4u_plat = M4U_MT8173, + .has_4gb_mode = true, +}; + +static const struct mtk_iommu_plat_data mt8183_data = { + .m4u_plat = M4U_MT8183, + .larbid_remap_enable = true, + .larbid_in_common = {0, 7, 5, 6, 1, 2, 3, 4}, +}; + static const struct of_device_id mtk_iommu_of_ids[] = { - { .compatible = "mediatek,mt2712-m4u", .data = (void *)M4U_MT2712}, - { .compatible = "mediatek,mt8173-m4u", .data = (void *)M4U_MT8173}, + { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data}, + { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data}, + { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data}, {} }; static struct platform_driver mtk_iommu_driver = { .probe = mtk_iommu_probe, .remove = mtk_iommu_remove, + .shutdown = mtk_iommu_shutdown, .driver = { .name = "mtk-iommu", .of_match_table = of_match_ptr(mtk_iommu_of_ids), diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h index 778498b8633f..f6588a8858f2 100644 --- a/drivers/iommu/mtk_iommu.h +++ b/drivers/iommu/mtk_iommu.h @@ -33,12 +33,23 @@ struct mtk_iommu_suspend_reg { u32 int_control0; u32 int_main_control; u32 ivrp_paddr; + u32 vld_pa_range; }; enum mtk_iommu_plat { M4U_MT2701, M4U_MT2712, M4U_MT8173, + M4U_MT8183, +}; + +struct mtk_iommu_plat_data { + enum mtk_iommu_plat m4u_plat; + bool has_4gb_mode; + + /* The larb-id may be remapped in the smi-common. */ + bool larbid_remap_enable; + unsigned int larbid_in_common[MTK_LARB_NR_MAX]; }; struct mtk_iommu_domain; @@ -53,11 +64,11 @@ struct mtk_iommu_data { struct mtk_iommu_domain *m4u_dom; struct iommu_group *m4u_group; struct mtk_smi_iommu smi_imu; /* SMI larb iommu info */ - bool enable_4GB; + bool enable_4GB; /* Dram is over 4gb */ bool tlb_flush_active; struct iommu_device iommu; - enum mtk_iommu_plat m4u_plat; + const struct mtk_iommu_plat_data *plat_data; struct list_head list; }; diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index 5db83b90337a..a3663346b01a 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -172,7 +172,7 @@ config BCM_FLEXRM_MBOX SoCs. Say Y here if you want to use the Broadcom FlexRM. config MTK_CMDQ_MBOX - bool "MediaTek CMDQ Mailbox Support" + tristate "MediaTek CMDQ Mailbox Support" help Say yes here to add support for the MediaTek Command Queue (CMDQ) mailbox driver. The CMDQ is used to help read/write registers with diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index e579f2886f3b..23fa6775e075 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -37,4 +37,4 @@ obj-$(CONFIG_QCOM_APCS_IPC) += qcom-apcs-ipc-mailbox.o obj-$(CONFIG_TEGRA_HSP_MBOX) += tegra-hsp.o -obj-$(CONFIG_MTK_CMDQ_MBOX) += mtk-cmdq-mailbox.o \ No newline at end of file +obj-$(CONFIG_MTK_CMDQ_MBOX) += mtk-cmdq-mailbox.o diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c index 8f2d152a78b8..7ee81fbaddd1 100644 --- a/drivers/memory/mtk-smi.c +++ b/drivers/memory/mtk-smi.c @@ -49,6 +49,24 @@ #define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4)) #define F_MMU_EN BIT(0) +/* SMI COMMON */ +#define SMI_BUS_SEL 0x220 +#define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1) +/* All are MMU0 defaultly. Only specialize mmu1 here. */ +#define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid)) + +enum mtk_smi_gen { + MTK_SMI_GEN1, + MTK_SMI_GEN2 +}; + +struct mtk_smi_common_plat { + enum mtk_smi_gen gen; + + /* Adjust some larbs to mmu1 to balance the bandwidth */ + unsigned int bus_sel; +}; + struct mtk_smi_larb_gen { bool need_larbid; int port_in_larb[MTK_LARB_NR_MAX + 1]; @@ -58,8 +76,11 @@ struct mtk_smi_larb_gen { struct mtk_smi { struct device *dev; struct clk *clk_apb, *clk_smi; + struct clk *clk_gals0, *clk_gals1; struct clk *clk_async; /*only needed by mt2701*/ - void __iomem *smi_ao_base; + void __iomem *smi_ao_base; /* only for gen1 */ + void __iomem *base; /* only for gen2 */ + const struct mtk_smi_common_plat *plat; }; struct mtk_smi_larb { /* larb: local arbiter */ @@ -71,82 +92,56 @@ struct mtk_smi_larb { /* larb: local arbiter */ u32 *mmu; }; -enum mtk_smi_gen { - MTK_SMI_GEN1, - MTK_SMI_GEN2 -}; - -static int mtk_smi_enable(const struct mtk_smi *smi) +static int mtk_smi_clk_enable(const struct mtk_smi *smi) { int ret; - ret = pm_runtime_get_sync(smi->dev); - if (ret < 0) - return ret; - ret = clk_prepare_enable(smi->clk_apb); if (ret) - goto err_put_pm; + return ret; ret = clk_prepare_enable(smi->clk_smi); if (ret) goto err_disable_apb; + ret = clk_prepare_enable(smi->clk_gals0); + if (ret) + goto err_disable_smi; + + ret = clk_prepare_enable(smi->clk_gals1); + if (ret) + goto err_disable_gals0; + return 0; +err_disable_gals0: + clk_disable_unprepare(smi->clk_gals0); +err_disable_smi: + clk_disable_unprepare(smi->clk_smi); err_disable_apb: clk_disable_unprepare(smi->clk_apb); -err_put_pm: - pm_runtime_put_sync(smi->dev); return ret; } -static void mtk_smi_disable(const struct mtk_smi *smi) +static void mtk_smi_clk_disable(const struct mtk_smi *smi) { + clk_disable_unprepare(smi->clk_gals1); + clk_disable_unprepare(smi->clk_gals0); clk_disable_unprepare(smi->clk_smi); clk_disable_unprepare(smi->clk_apb); - pm_runtime_put_sync(smi->dev); } int mtk_smi_larb_get(struct device *larbdev) { - struct mtk_smi_larb *larb = dev_get_drvdata(larbdev); - const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen; - struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev); - int ret; + int ret = pm_runtime_get_sync(larbdev); - /* Enable the smi-common's power and clocks */ - ret = mtk_smi_enable(common); - if (ret) - return ret; - - /* Enable the larb's power and clocks */ - ret = mtk_smi_enable(&larb->smi); - if (ret) { - mtk_smi_disable(common); - return ret; - } - - /* Configure the iommu info for this larb */ - larb_gen->config_port(larbdev); - - return 0; + return (ret < 0) ? ret : 0; } EXPORT_SYMBOL_GPL(mtk_smi_larb_get); void mtk_smi_larb_put(struct device *larbdev) { - struct mtk_smi_larb *larb = dev_get_drvdata(larbdev); - struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev); - - /* - * Don't de-configure the iommu info for this larb since there may be - * several modules in this larb. - * The iommu info will be reset after power off. - */ - - mtk_smi_disable(&larb->smi); - mtk_smi_disable(common); + pm_runtime_put_sync(larbdev); } EXPORT_SYMBOL_GPL(mtk_smi_larb_put); @@ -176,12 +171,23 @@ mtk_smi_larb_bind(struct device *dev, struct device *master, void *data) return -ENODEV; } -static void mtk_smi_larb_config_port_mt2712(struct device *dev) +static void mtk_smi_larb_config_port_gen2_general(struct device *dev) { struct mtk_smi_larb *larb = dev_get_drvdata(dev); u32 reg; int i; + for_each_set_bit(i, (unsigned long *)larb->mmu, 32) { + reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i)); + reg |= F_MMU_EN; + writel(reg, larb->base + SMI_LARB_NONSEC_CON(i)); + } +} + +static void mtk_smi_larb_config_port_mt2712(struct device *dev) +{ + struct mtk_smi_larb *larb = dev_get_drvdata(dev); + /* * larb 8/9 is the bdpsys larb, the iommu_en is enabled defaultly. * Don't need to set it again. @@ -189,11 +195,7 @@ static void mtk_smi_larb_config_port_mt2712(struct device *dev) if (larb->larbid == 8 || larb->larbid == 9) return; - for_each_set_bit(i, (unsigned long *)larb->mmu, 32) { - reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i)); - reg |= F_MMU_EN; - writel(reg, larb->base + SMI_LARB_NONSEC_CON(i)); - } + mtk_smi_larb_config_port_gen2_general(dev); } static void mtk_smi_larb_config_port_mt8173(struct device *dev) @@ -264,6 +266,10 @@ static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = { .config_port = mtk_smi_larb_config_port_mt2712, }; +static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = { + .config_port = mtk_smi_larb_config_port_gen2_general, +}; + static const struct of_device_id mtk_smi_larb_of_ids[] = { { .compatible = "mediatek,mt8173-smi-larb", @@ -277,6 +283,10 @@ static const struct of_device_id mtk_smi_larb_of_ids[] = { .compatible = "mediatek,mt2712-smi-larb", .data = &mtk_smi_larb_mt2712 }, + { + .compatible = "mediatek,mt8183-smi-larb", + .data = &mtk_smi_larb_mt8183 + }, {} }; @@ -306,6 +316,12 @@ static int mtk_smi_larb_probe(struct platform_device *pdev) larb->smi.clk_smi = devm_clk_get(dev, "smi"); if (IS_ERR(larb->smi.clk_smi)) return PTR_ERR(larb->smi.clk_smi); + + larb->smi.clk_gals0 = devm_clk_get(dev, "gals"); + if (PTR_ERR(larb->smi.clk_gals0) == -ENOENT) + larb->smi.clk_gals0 = NULL; + else if (IS_ERR(larb->smi.clk_gals0)) + return PTR_ERR(larb->smi.clk_gals0); larb->smi.dev = dev; if (larb->larb_gen->need_larbid) { @@ -344,27 +360,85 @@ static int mtk_smi_larb_remove(struct platform_device *pdev) return 0; } +static int __maybe_unused mtk_smi_larb_resume(struct device *dev) +{ + struct mtk_smi_larb *larb = dev_get_drvdata(dev); + const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen; + int ret; + + /* Power on smi-common. */ + ret = pm_runtime_get_sync(larb->smi_common_dev); + if (ret < 0) { + dev_err(dev, "smi-common pm get failed(%d).\n", ret); + return ret; + } + + ret = mtk_smi_clk_enable(&larb->smi); + if (ret < 0) { + dev_err(dev, "larb clk enable failed(%d).\n", ret); + pm_runtime_put_sync(larb->smi_common_dev); + return ret; + } + + /* Configure the basic setting for this larb */ + larb_gen->config_port(dev); + + return 0; +} + +static int __maybe_unused mtk_smi_larb_suspend(struct device *dev) +{ + struct mtk_smi_larb *larb = dev_get_drvdata(dev); + + mtk_smi_clk_disable(&larb->smi); + pm_runtime_put_sync(larb->smi_common_dev); + return 0; +} + +static const struct dev_pm_ops smi_larb_pm_ops = { + SET_RUNTIME_PM_OPS(mtk_smi_larb_suspend, mtk_smi_larb_resume, NULL) +}; + static struct platform_driver mtk_smi_larb_driver = { .probe = mtk_smi_larb_probe, .remove = mtk_smi_larb_remove, .driver = { .name = "mtk-smi-larb", .of_match_table = mtk_smi_larb_of_ids, + .pm = &smi_larb_pm_ops, } }; +static const struct mtk_smi_common_plat mtk_smi_common_gen1 = { + .gen = MTK_SMI_GEN1, +}; + +static const struct mtk_smi_common_plat mtk_smi_common_gen2 = { + .gen = MTK_SMI_GEN2, +}; + +static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = { + .gen = MTK_SMI_GEN2, + .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(3) | F_MMU1_LARB(4) | + F_MMU1_LARB(7), +}; + static const struct of_device_id mtk_smi_common_of_ids[] = { { .compatible = "mediatek,mt8173-smi-common", - .data = (void *)MTK_SMI_GEN2 + .data = &mtk_smi_common_gen2, }, { .compatible = "mediatek,mt2701-smi-common", - .data = (void *)MTK_SMI_GEN1 + .data = &mtk_smi_common_gen1, }, { .compatible = "mediatek,mt2712-smi-common", - .data = (void *)MTK_SMI_GEN2 + .data = &mtk_smi_common_gen2, + }, + { + .compatible = "mediatek,mt8183-smi-common", + .data = &mtk_smi_common_mt8183, }, {} }; @@ -374,13 +448,13 @@ static int mtk_smi_common_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct mtk_smi *common; struct resource *res; - enum mtk_smi_gen smi_gen; int ret; common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL); if (!common) return -ENOMEM; common->dev = dev; + common->plat = of_device_get_match_data(dev); common->clk_apb = devm_clk_get(dev, "apb"); if (IS_ERR(common->clk_apb)) @@ -390,14 +464,25 @@ static int mtk_smi_common_probe(struct platform_device *pdev) if (IS_ERR(common->clk_smi)) return PTR_ERR(common->clk_smi); + common->clk_gals0 = devm_clk_get(dev, "gals0"); + if (PTR_ERR(common->clk_gals0) == -ENOENT) + common->clk_gals0 = NULL; + else if (IS_ERR(common->clk_gals0)) + return PTR_ERR(common->clk_gals0); + + common->clk_gals1 = devm_clk_get(dev, "gals1"); + if (PTR_ERR(common->clk_gals1) == -ENOENT) + common->clk_gals1 = NULL; + else if (IS_ERR(common->clk_gals1)) + return PTR_ERR(common->clk_gals1); + /* * for mtk smi gen 1, we need to get the ao(always on) base to config * m4u port, and we need to enable the aync clock for transform the smi * clock into emi clock domain, but for mtk smi gen2, there's no smi ao * base. */ - smi_gen = (enum mtk_smi_gen)of_device_get_match_data(dev); - if (smi_gen == MTK_SMI_GEN1) { + if (common->plat->gen == MTK_SMI_GEN1) { res = platform_get_resource(pdev, IORESOURCE_MEM, 0); common->smi_ao_base = devm_ioremap_resource(dev, res); if (IS_ERR(common->smi_ao_base)) @@ -410,6 +495,11 @@ static int mtk_smi_common_probe(struct platform_device *pdev) ret = clk_prepare_enable(common->clk_async); if (ret) return ret; + } else { + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + common->base = devm_ioremap_resource(dev, res); + if (IS_ERR(common->base)) + return PTR_ERR(common->base); } pm_runtime_enable(dev); platform_set_drvdata(pdev, common); @@ -422,12 +512,40 @@ static int mtk_smi_common_remove(struct platform_device *pdev) return 0; } +static int __maybe_unused mtk_smi_common_resume(struct device *dev) +{ + struct mtk_smi *common = dev_get_drvdata(dev); + unsigned int bus_sel = common->plat->bus_sel; + int ret; + + ret = mtk_smi_clk_enable(common); + if (ret) + return ret; + + if (common->plat->gen == MTK_SMI_GEN2 && bus_sel) + writel(bus_sel, common->base + SMI_BUS_SEL); + return 0; +} + +static int __maybe_unused mtk_smi_common_suspend(struct device *dev) +{ + struct mtk_smi *common = dev_get_drvdata(dev); + + mtk_smi_clk_disable(common); + return 0; +} + +static const struct dev_pm_ops smi_common_pm_ops = { + SET_RUNTIME_PM_OPS(mtk_smi_common_suspend, mtk_smi_common_resume, NULL) +}; + static struct platform_driver mtk_smi_common_driver = { .probe = mtk_smi_common_probe, .remove = mtk_smi_common_remove, .driver = { .name = "mtk-smi-common", .of_match_table = mtk_smi_common_of_ids, + .pm = &smi_common_pm_ops, } }; @@ -454,3 +572,6 @@ err_unreg_smi: } module_init(mtk_smi_init); + +MODULE_DESCRIPTION("MediaTek SMI driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c index 04a601f6aebe..bf7cf667fb7f 100644 --- a/drivers/mfd/mt6397-core.c +++ b/drivers/mfd/mt6397-core.c @@ -21,15 +21,21 @@ #include #include #include +#include #include #define MT6397_RTC_BASE 0xe000 #define MT6397_RTC_SIZE 0x3e #define MT6323_CID_CODE 0x23 +#define MT6358_CID_CODE 0x20 #define MT6391_CID_CODE 0x91 #define MT6397_CID_CODE 0x97 +struct chip_data { + u32 cid_addr; +}; + static const struct resource mt6397_rtc_resources[] = { { .start = MT6397_RTC_BASE, @@ -43,6 +49,16 @@ static const struct resource mt6397_rtc_resources[] = { }, }; +static const struct resource mt6323_keys_resources[] = { + DEFINE_RES_IRQ(MT6323_IRQ_STATUS_PWRKEY), + DEFINE_RES_IRQ(MT6323_IRQ_STATUS_FCHRKEY), +}; + +static const struct resource mt6397_keys_resources[] = { + DEFINE_RES_IRQ(MT6397_IRQ_PWRKEY), + DEFINE_RES_IRQ(MT6397_IRQ_HOMEKEY), +}; + static const struct mfd_cell mt6323_devs[] = { { .name = "mt6323-regulator", @@ -50,6 +66,18 @@ static const struct mfd_cell mt6323_devs[] = { }, { .name = "mt6323-led", .of_compatible = "mediatek,mt6323-led" + }, { + .name = "mtk-pmic-keys", + .num_resources = ARRAY_SIZE(mt6323_keys_resources), + .resources = mt6323_keys_resources, + .of_compatible = "mediatek,mt6323-keys" + }, +}; + +static const struct mfd_cell mt6358_devs[] = { + { + .name = "mt6358-regulator", + .of_compatible = "mediatek,mt6358-regulator" }, }; @@ -71,7 +99,24 @@ static const struct mfd_cell mt6397_devs[] = { }, { .name = "mt6397-pinctrl", .of_compatible = "mediatek,mt6397-pinctrl", - }, + }, { + .name = "mtk-pmic-keys", + .num_resources = ARRAY_SIZE(mt6397_keys_resources), + .resources = mt6397_keys_resources, + .of_compatible = "mediatek,mt6397-keys" + } +}; + +static const struct chip_data mt6323_core = { + .cid_addr = MT6397_CID, +}; + +static const struct chip_data mt6358_core = { + .cid_addr = MT6358_SWCID, +}; + +static const struct chip_data mt6397_core = { + .cid_addr = MT6397_CID, }; static void mt6397_irq_lock(struct irq_data *data) @@ -250,6 +295,7 @@ static int mt6397_probe(struct platform_device *pdev) int ret; unsigned int id; struct mt6397_chip *pmic; + const struct chip_data *pmic_core; pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL); if (!pmic) @@ -267,7 +313,11 @@ static int mt6397_probe(struct platform_device *pdev) platform_set_drvdata(pdev, pmic); - ret = regmap_read(pmic->regmap, MT6397_CID, &id); + pmic_core = of_device_get_match_data(&pdev->dev); + if (!pmic_core) + return -ENODEV; + + ret = regmap_read(pmic->regmap, pmic_core->cid_addr, &id); if (ret) { dev_err(pmic->dev, "Failed to read chip id: %d\n", ret); return ret; @@ -289,7 +339,21 @@ static int mt6397_probe(struct platform_device *pdev) ret = devm_mfd_add_devices(&pdev->dev, -1, mt6323_devs, ARRAY_SIZE(mt6323_devs), NULL, - 0, NULL); + 0, pmic->irq_domain); + break; + + case MT6358_CID_CODE: + pmic->int_con[0] = MT6358_PSC_TOP_INT_CON0; + pmic->int_con[1] = MT6358_HK_TOP_INT_CON0; + pmic->int_status[0] = MT6358_PSC_TOP_INT_STATUS0; + pmic->int_status[1] = MT6358_HK_TOP_INT_STATUS0; + ret = mt6397_irq_init(pmic); + if (ret) + return ret; + + ret = devm_mfd_add_devices(&pdev->dev, -1, mt6358_devs, + ARRAY_SIZE(mt6358_devs), NULL, + 0, pmic->irq_domain); break; case MT6397_CID_CODE: @@ -304,7 +368,7 @@ static int mt6397_probe(struct platform_device *pdev) ret = devm_mfd_add_devices(&pdev->dev, -1, mt6397_devs, ARRAY_SIZE(mt6397_devs), NULL, - 0, NULL); + 0, pmic->irq_domain); break; default: @@ -322,9 +386,18 @@ static int mt6397_probe(struct platform_device *pdev) } static const struct of_device_id mt6397_of_match[] = { - { .compatible = "mediatek,mt6397" }, - { .compatible = "mediatek,mt6323" }, - { } + { + .compatible = "mediatek,mt6323", + .data = &mt6323_core, + }, { + .compatible = "mediatek,mt6358", + .data = &mt6358_core, + }, { + .compatible = "mediatek,mt6397", + .data = &mt6397_core, + }, { + /* sentinel */ + } }; MODULE_DEVICE_TABLE(of, mt6397_of_match); diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c index a2baa8702257..1bc82a600388 100644 --- a/drivers/mmc/host/mtk-sd.c +++ b/drivers/mmc/host/mtk-sd.c @@ -85,6 +85,13 @@ #define EMMC50_CFG3 0x220 #define SDC_FIFO_CFG 0x228 +/*--------------------------------------------------------------------------*/ +/* Top Register Offset */ +/*--------------------------------------------------------------------------*/ +#define EMMC_TOP_CONTROL (0x00) +#define EMMC_TOP_CMD (0x04) +#define EMMC50_PAD_DS_TUNE (0x0c) + /*--------------------------------------------------------------------------*/ /* Register Mask */ /*--------------------------------------------------------------------------*/ @@ -260,6 +267,23 @@ #define SDC_FIFO_CFG_WRVALIDSEL (0x1 << 24) /* RW */ #define SDC_FIFO_CFG_RDVALIDSEL (0x1 << 25) /* RW */ +/* EMMC_TOP_CONTROL mask */ +#define PAD_RXDLY_SEL (0x1 << 0) /* RW */ +#define DELAY_EN (0x1 << 1) /* RW */ +#define PAD_DAT_RD_RXDLY2 (0x1F << 2) /* RW */ +#define PAD_DAT_RD_RXDLY (0x1F << 7) /* RW */ +#define PAD_DAT_RD_RXDLY2_SEL (0x1 << 12) /* RW */ +#define PAD_DAT_RD_RXDLY_SEL (0x1 << 13) /* RW */ +#define DATA_K_VALUE_SEL (0x1 << 14) /* RW */ +#define SDC_RX_ENH_EN (0x1 << 15) /* TW */ + +/* EMMC_TOP_CMD mask */ +#define PAD_CMD_RXDLY2 (0x1F << 0) /* RW */ +#define PAD_CMD_RXDLY (0x1F << 5) /* RW */ +#define PAD_CMD_RD_RXDLY2_SEL (0x1 << 10) /* RW */ +#define PAD_CMD_RD_RXDLY_SEL (0x1 << 11) /* RW */ +#define PAD_CMD_TX_DLY (0x1F << 12) /* RW */ + #define REQ_CMD_EIO (0x1 << 0) #define REQ_CMD_TMO (0x1 << 1) #define REQ_DAT_ERR (0x1 << 2) @@ -332,6 +356,9 @@ struct msdc_save_para { u32 emmc50_cfg0; u32 emmc50_cfg3; u32 sdc_fifo_cfg; + u32 emmc_top_control; + u32 emmc_top_cmd; + u32 emmc50_pad_ds_tune; }; struct mtk_mmc_compatible { @@ -344,12 +371,15 @@ struct mtk_mmc_compatible { bool stop_clk_fix; bool enhance_rx; bool support_64g; + bool tune_resp_data_together; }; struct msdc_tune_para { u32 iocon; u32 pad_tune; u32 pad_cmd_tune; + u32 emmc_top_control; + u32 emmc_top_cmd; }; struct msdc_delay_phase { @@ -371,6 +401,7 @@ struct msdc_host { int error; void __iomem *base; /* host base address */ + void __iomem *top_base; /* host top register base address */ struct msdc_dma dma; /* dma channel */ u64 dma_mask; @@ -414,6 +445,7 @@ static const struct mtk_mmc_compatible mt8135_compat = { .stop_clk_fix = false, .enhance_rx = false, .support_64g = false, + .tune_resp_data_together = false, }; static const struct mtk_mmc_compatible mt8173_compat = { @@ -426,6 +458,7 @@ static const struct mtk_mmc_compatible mt8173_compat = { .stop_clk_fix = false, .enhance_rx = false, .support_64g = false, + .tune_resp_data_together = false, }; static const struct mtk_mmc_compatible mt2701_compat = { @@ -438,6 +471,7 @@ static const struct mtk_mmc_compatible mt2701_compat = { .stop_clk_fix = false, .enhance_rx = false, .support_64g = false, + .tune_resp_data_together = false, }; static const struct mtk_mmc_compatible mt2712_compat = { @@ -450,6 +484,7 @@ static const struct mtk_mmc_compatible mt2712_compat = { .stop_clk_fix = true, .enhance_rx = true, .support_64g = true, + .tune_resp_data_together = true, }; static const struct mtk_mmc_compatible mt7622_compat = { @@ -462,6 +497,20 @@ static const struct mtk_mmc_compatible mt7622_compat = { .stop_clk_fix = true, .enhance_rx = true, .support_64g = false, + .tune_resp_data_together = false, +}; + +static const struct mtk_mmc_compatible mt8183_compat = { + .clk_div_bits = 12, + .hs400_tune = false, + .pad_tune_reg = MSDC_PAD_TUNE0, + .async_fifo = true, + .data_tune = true, + .busy_check = true, + .stop_clk_fix = true, + .enhance_rx = true, + .support_64g = true, + .tune_resp_data_together = true, }; static const struct of_device_id msdc_of_ids[] = { @@ -470,6 +519,7 @@ static const struct of_device_id msdc_of_ids[] = { { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat}, { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat}, { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, + { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat}, {} }; MODULE_DEVICE_TABLE(of, msdc_of_ids); @@ -774,11 +824,23 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) if (host->sclk <= 52000000) { writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); writel(host->def_tune_para.pad_tune, host->base + tune_reg); + if (host->top_base != NULL) { + writel(host->def_tune_para.emmc_top_control, + host->top_base + EMMC_TOP_CONTROL); + writel(host->def_tune_para.emmc_top_cmd, + host->top_base + EMMC_TOP_CMD); + } } else { writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); writel(host->saved_tune_para.pad_tune, host->base + tune_reg); writel(host->saved_tune_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); + if (host->top_base != NULL) { + writel(host->saved_tune_para.emmc_top_control, + host->top_base + EMMC_TOP_CONTROL); + writel(host->saved_tune_para.emmc_top_cmd, + host->top_base + EMMC_TOP_CMD); + } } if (timing == MMC_TIMING_MMC_HS400 && @@ -1000,8 +1062,10 @@ static bool msdc_cmd_done(struct msdc_host *host, int events, host->error |= REQ_CMD_TMO; } } - if (cmd->error) - dev_dbg(host->dev, + if (cmd->error && + cmd->opcode != MMC_SEND_TUNING_BLOCK && + cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200) + dev_info(host->dev, "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n", __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); @@ -1190,11 +1254,14 @@ static bool msdc_data_xfer_done(struct msdc_host *host, u32 events, data->error = -ETIMEDOUT; else if (events & MSDC_INT_DATCRCERR) data->error = -EILSEQ; - - dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", - __func__, mrq->cmd->opcode, data->blocks); - dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", - (int)data->error, data->bytes_xfered); + if (mrq->cmd->opcode != MMC_SEND_TUNING_BLOCK && + mrq->cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200) { + dev_info(host->dev, "%s: cmd=%d; blocks=%d", + __func__, mrq->cmd->opcode, + data->blocks); + dev_info(host->dev, "data_error=%d xfer_size=%d\n", + (int)data->error, data->bytes_xfered); + } } msdc_data_xfer_next(host, mrq, data); @@ -1351,6 +1418,10 @@ static void msdc_init_hw(struct msdc_host *host) writel(val, host->base + MSDC_INT); writel(0, host->base + tune_reg); + if (host->top_base != NULL) { + writel(0, host->top_base + EMMC_TOP_CONTROL); + writel(0, host->top_base + EMMC_TOP_CMD); + } writel(0, host->base + MSDC_IOCON); sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); writel(0x403c0046, host->base + MSDC_PATCH_BIT); @@ -1374,8 +1445,12 @@ static void msdc_init_hw(struct msdc_host *host) sdr_set_field(host->base + MSDC_PATCH_BIT2, MSDC_PB2_RESPWAIT, 3); if (host->dev_comp->enhance_rx) { - sdr_set_bits(host->base + SDC_ADV_CFG0, - SDC_RX_ENHANCE_EN); + if (host->top_base != NULL) + sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, + SDC_RX_ENH_EN); + else + sdr_set_bits(host->base + SDC_ADV_CFG0, + SDC_RX_ENHANCE_EN); } else { sdr_set_field(host->base + MSDC_PATCH_BIT2, MSDC_PB2_RESPSTSENSEL, 2); @@ -1393,11 +1468,26 @@ static void msdc_init_hw(struct msdc_host *host) sdr_set_bits(host->base + MSDC_PATCH_BIT2, MSDC_PB2_SUPPORT_64G); if (host->dev_comp->data_tune) { - sdr_set_bits(host->base + tune_reg, - MSDC_PAD_TUNE_RD_SEL | MSDC_PAD_TUNE_CMD_SEL); + if (host->top_base != NULL) { + sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, + PAD_DAT_RD_RXDLY_SEL); + sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL, + DATA_K_VALUE_SEL); + sdr_set_bits(host->top_base + EMMC_TOP_CMD, + PAD_CMD_RD_RXDLY_SEL); + } else { + sdr_set_bits(host->base + tune_reg, + MSDC_PAD_TUNE_RD_SEL | + MSDC_PAD_TUNE_CMD_SEL); + } } else { /* choose clock tune */ - sdr_set_bits(host->base + tune_reg, MSDC_PAD_TUNE_RXDLYSEL); + if (host->top_base != NULL) + sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, + PAD_RXDLY_SEL); + else + sdr_set_bits(host->base + tune_reg, + MSDC_PAD_TUNE_RXDLYSEL); } /* Configure to enable SDIO mode. @@ -1415,6 +1505,16 @@ static void msdc_init_hw(struct msdc_host *host) host->def_tune_para.pad_tune = readl(host->base + tune_reg); host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); host->saved_tune_para.pad_tune = readl(host->base + tune_reg); + if (host->top_base != NULL) { + host->def_tune_para.emmc_top_control = + readl(host->top_base + EMMC_TOP_CONTROL); + host->def_tune_para.emmc_top_cmd = + readl(host->top_base + EMMC_TOP_CMD); + host->saved_tune_para.emmc_top_control = + readl(host->top_base + EMMC_TOP_CONTROL); + host->saved_tune_para.emmc_top_cmd = + readl(host->top_base + EMMC_TOP_CMD); + } dev_dbg(host->dev, "init hardware done!"); } @@ -1562,6 +1662,132 @@ static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay) return delay_phase; } +static int msdc_tune_resp_data(struct mmc_host *mmc, u32 opcode) +{ + struct msdc_host *host = mmc_priv(mmc); + u32 rise_delay = 0, fall_delay = 0; + struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; + u8 final_delay, final_maxlen; + u32 tune_reg = host->dev_comp->pad_tune_reg; + int err; + int i, j; + + sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, + host->latch_ck); + sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); + sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); + sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); + for (i = 0 ; i < PAD_DELAY_MAX; i++) { + if (host->top_base != NULL) { + sdr_set_field(host->top_base + EMMC_TOP_CMD, + PAD_CMD_RXDLY, i); + sdr_set_field(host->top_base + EMMC_TOP_CONTROL, + PAD_DAT_RD_RXDLY, i); + } else { + sdr_set_field(host->base + tune_reg, + MSDC_PAD_TUNE_CMDRDLY, i); + sdr_set_field(host->base + tune_reg, + MSDC_PAD_TUNE_DATRRDLY, i); + } + /* + * Using the same parameters, it may sometimes pass the test, + * but sometimes it may fail. To make sure the parameters are + * more stable, we test each set of parameters 3 times. + */ + for (j = 0; j < 3; j++) { + err = mmc_send_tuning(mmc, opcode, NULL); + if (!err) { + rise_delay |= (1 << i); + } else { + rise_delay &= ~(1 << i); + break; + } + } + } + final_rise_delay = get_best_delay(host, rise_delay); + /* if rising edge has enough margin, then do not scan falling edge */ + if (final_rise_delay.maxlen >= 12 || + (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) + goto skip_fall; + + sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); + sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); + sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); + for (i = 0; i < PAD_DELAY_MAX; i++) { + if (host->top_base != NULL) { + sdr_set_field(host->top_base + EMMC_TOP_CMD, + PAD_CMD_RXDLY, i); + sdr_set_field(host->top_base + EMMC_TOP_CONTROL, + PAD_DAT_RD_RXDLY, i); + } else { + sdr_set_field(host->base + tune_reg, + MSDC_PAD_TUNE_CMDRDLY, i); + sdr_set_field(host->base + tune_reg, + MSDC_PAD_TUNE_DATRRDLY, i); + } + + for (j = 0; j < 3; j++) { + err = mmc_send_tuning(mmc, opcode, NULL); + if (!err) { + fall_delay |= (1 << i); + } else { + fall_delay &= ~(1 << i); + break; + } + } + } + final_fall_delay = get_best_delay(host, fall_delay); + +skip_fall: + final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); + if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4) + final_maxlen = final_fall_delay.maxlen; + if (final_maxlen == final_rise_delay.maxlen) { + sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); + sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); + sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); + if (host->top_base != NULL) { + sdr_set_field(host->top_base + EMMC_TOP_CMD, + PAD_CMD_RXDLY, + final_rise_delay.final_phase); + sdr_set_field(host->top_base + EMMC_TOP_CONTROL, + PAD_DAT_RD_RXDLY, + final_rise_delay.final_phase); + } else { + sdr_set_field(host->base + tune_reg, + MSDC_PAD_TUNE_CMDRDLY, + final_rise_delay.final_phase); + sdr_set_field(host->base + tune_reg, + MSDC_PAD_TUNE_DATRRDLY, + final_rise_delay.final_phase); + } + final_delay = final_rise_delay.final_phase; + } else { + sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); + sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); + sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); + if (host->top_base != NULL) { + sdr_set_field(host->top_base + EMMC_TOP_CMD, + PAD_CMD_RXDLY, + final_fall_delay.final_phase); + sdr_set_field(host->top_base + EMMC_TOP_CONTROL, + PAD_DAT_RD_RXDLY, + final_fall_delay.final_phase); + } else { + sdr_set_field(host->base + tune_reg, + MSDC_PAD_TUNE_CMDRDLY, + final_fall_delay.final_phase); + sdr_set_field(host->base + tune_reg, + MSDC_PAD_TUNE_DATRRDLY, + final_fall_delay.final_phase); + } + final_delay = final_fall_delay.final_phase; + } + + dev_info(host->dev, "Final cmd/data pad delay: %x\n", final_delay); + return final_delay == 0xff ? -EIO : 0; +} + static int msdc_tune_response(struct mmc_host *mmc, u32 opcode) { struct msdc_host *host = mmc_priv(mmc); @@ -1582,8 +1808,12 @@ static int msdc_tune_response(struct mmc_host *mmc, u32 opcode) sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); for (i = 0 ; i < PAD_DELAY_MAX; i++) { - sdr_set_field(host->base + tune_reg, - MSDC_PAD_TUNE_CMDRDLY, i); + if (host->top_base != NULL) + sdr_set_field(host->top_base + EMMC_TOP_CMD, + PAD_CMD_RXDLY, i); + else + sdr_set_field(host->base + tune_reg, + MSDC_PAD_TUNE_CMDRDLY, i); /* * Using the same parameters, it may sometimes pass the test, * but sometimes it may fail. To make sure the parameters are @@ -1607,8 +1837,12 @@ static int msdc_tune_response(struct mmc_host *mmc, u32 opcode) sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); for (i = 0; i < PAD_DELAY_MAX; i++) { - sdr_set_field(host->base + tune_reg, - MSDC_PAD_TUNE_CMDRDLY, i); + if (host->top_base != NULL) + sdr_set_field(host->top_base + EMMC_TOP_CMD, + PAD_CMD_RXDLY, i); + else + sdr_set_field(host->base + tune_reg, + MSDC_PAD_TUNE_CMDRDLY, i); /* * Using the same parameters, it may sometimes pass the test, * but sometimes it may fail. To make sure the parameters are @@ -1632,13 +1866,25 @@ skip_fall: final_maxlen = final_fall_delay.maxlen; if (final_maxlen == final_rise_delay.maxlen) { sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); - sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, - final_rise_delay.final_phase); + if (host->top_base != NULL) + sdr_set_field(host->top_base + EMMC_TOP_CMD, + PAD_CMD_RXDLY, + final_rise_delay.final_phase); + else + sdr_set_field(host->base + tune_reg, + MSDC_PAD_TUNE_CMDRDLY, + final_rise_delay.final_phase); final_delay = final_rise_delay.final_phase; } else { sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); - sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, - final_fall_delay.final_phase); + if (host->top_base != NULL) + sdr_set_field(host->top_base + EMMC_TOP_CMD, + PAD_CMD_RXDLY, + final_fall_delay.final_phase); + else + sdr_set_field(host->base + tune_reg, + MSDC_PAD_TUNE_CMDRDLY, + final_fall_delay.final_phase); final_delay = final_fall_delay.final_phase; } if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay) @@ -1651,12 +1897,12 @@ skip_fall: if (!cmd_err) internal_delay |= (1 << i); } - dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay); + dev_info(host->dev, "Final internal delay: 0x%x\n", internal_delay); internal_delay_phase = get_best_delay(host, internal_delay); sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY, internal_delay_phase.final_phase); skip_internal: - dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); + dev_info(host->dev, "Final cmd pad delay: %x\n", final_delay); return final_delay == 0xff ? -EIO : 0; } @@ -1705,7 +1951,7 @@ static int hs400_tune_response(struct mmc_host *mmc, u32 opcode) final_cmd_delay.final_phase); final_delay = final_cmd_delay.final_phase; - dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); + dev_info(host->dev, "Final cmd pad delay: %x\n", final_delay); return final_delay == 0xff ? -EIO : 0; } @@ -1723,8 +1969,12 @@ static int msdc_tune_data(struct mmc_host *mmc, u32 opcode) sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); for (i = 0 ; i < PAD_DELAY_MAX; i++) { - sdr_set_field(host->base + tune_reg, - MSDC_PAD_TUNE_DATRRDLY, i); + if (host->top_base != NULL) + sdr_set_field(host->top_base + EMMC_TOP_CONTROL, + PAD_DAT_RD_RXDLY, i); + else + sdr_set_field(host->base + tune_reg, + MSDC_PAD_TUNE_DATRRDLY, i); ret = mmc_send_tuning(mmc, opcode, NULL); if (!ret) rise_delay |= (1 << i); @@ -1738,8 +1988,12 @@ static int msdc_tune_data(struct mmc_host *mmc, u32 opcode) sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); for (i = 0; i < PAD_DELAY_MAX; i++) { - sdr_set_field(host->base + tune_reg, - MSDC_PAD_TUNE_DATRRDLY, i); + if (host->top_base != NULL) + sdr_set_field(host->top_base + EMMC_TOP_CONTROL, + PAD_DAT_RD_RXDLY, i); + else + sdr_set_field(host->base + tune_reg, + MSDC_PAD_TUNE_DATRRDLY, i); ret = mmc_send_tuning(mmc, opcode, NULL); if (!ret) fall_delay |= (1 << i); @@ -1751,20 +2005,30 @@ skip_fall: if (final_maxlen == final_rise_delay.maxlen) { sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); - sdr_set_field(host->base + tune_reg, - MSDC_PAD_TUNE_DATRRDLY, - final_rise_delay.final_phase); + if (host->top_base != NULL) + sdr_set_field(host->top_base + EMMC_TOP_CONTROL, + PAD_DAT_RD_RXDLY, + final_rise_delay.final_phase); + else + sdr_set_field(host->base + tune_reg, + MSDC_PAD_TUNE_DATRRDLY, + final_rise_delay.final_phase); final_delay = final_rise_delay.final_phase; } else { sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); - sdr_set_field(host->base + tune_reg, - MSDC_PAD_TUNE_DATRRDLY, - final_fall_delay.final_phase); + if (host->top_base != NULL) + sdr_set_field(host->top_base + EMMC_TOP_CONTROL, + PAD_DAT_RD_RXDLY, + final_fall_delay.final_phase); + else + sdr_set_field(host->base + tune_reg, + MSDC_PAD_TUNE_DATRRDLY, + final_fall_delay.final_phase); final_delay = final_fall_delay.final_phase; } - dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay); + dev_info(host->dev, "Final data pad delay: %x\n", final_delay); return final_delay == 0xff ? -EIO : 0; } @@ -1774,24 +2038,48 @@ static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode) int ret; u32 tune_reg = host->dev_comp->pad_tune_reg; - if (host->hs400_mode && - host->dev_comp->hs400_tune) - ret = hs400_tune_response(mmc, opcode); - else - ret = msdc_tune_response(mmc, opcode); - if (ret == -EIO) { - dev_err(host->dev, "Tune response fail!\n"); - return ret; - } - if (host->hs400_mode == false) { - ret = msdc_tune_data(mmc, opcode); + if (host->dev_comp->tune_resp_data_together) { + ret = msdc_tune_resp_data(mmc, opcode); if (ret == -EIO) - dev_err(host->dev, "Tune data fail!\n"); + dev_err(host->dev, "Tune cmd/data fail!\n"); + if (host->hs400_mode) { + sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); + sdr_clr_bits(host->base + MSDC_IOCON, + MSDC_IOCON_W_DSPL); + if (host->top_base != NULL) + sdr_set_field(host->top_base + EMMC_TOP_CONTROL, + PAD_DAT_RD_RXDLY, 0); + else + sdr_set_field(host->base + tune_reg, + MSDC_PAD_TUNE_DATRRDLY, 0); + } + } else { + if (host->hs400_mode && + host->dev_comp->hs400_tune) + ret = hs400_tune_response(mmc, opcode); + else + ret = msdc_tune_response(mmc, opcode); + if (ret == -EIO) { + dev_err(host->dev, "Tune response fail!\n"); + return ret; + } + if (host->hs400_mode == false) { + ret = msdc_tune_data(mmc, opcode); + if (ret == -EIO) + dev_err(host->dev, "Tune data fail!\n"); + } + } host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); host->saved_tune_para.pad_tune = readl(host->base + tune_reg); host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); + if (host->top_base != NULL) { + host->saved_tune_para.emmc_top_control = readl(host->top_base + + EMMC_TOP_CONTROL); + host->saved_tune_para.emmc_top_cmd = readl(host->top_base + + EMMC_TOP_CMD); + } return ret; } @@ -1800,7 +2088,11 @@ static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) struct msdc_host *host = mmc_priv(mmc); host->hs400_mode = true; - writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); + if (host->top_base != NULL) + writel(host->hs400_ds_delay, + host->top_base + EMMC50_PAD_DS_TUNE); + else + writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); /* hs400 mode must set it to 0 */ sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS); /* to improve read performance, set outstanding to 2 */ @@ -1887,6 +2179,11 @@ static int msdc_drv_probe(struct platform_device *pdev) goto host_free; } + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + host->top_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(host->top_base)) + host->top_base = NULL; + ret = mmc_regulator_get_supply(mmc); if (ret) goto host_free; @@ -2061,6 +2358,15 @@ static void msdc_save_reg(struct msdc_host *host) host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3); host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG); + if (host->top_base != NULL) { + host->save_para.emmc_top_control = + readl(host->top_base + EMMC_TOP_CONTROL); + host->save_para.emmc_top_cmd = + readl(host->top_base + EMMC_TOP_CMD); + host->save_para.emmc50_pad_ds_tune = + readl(host->top_base + EMMC50_PAD_DS_TUNE); + + } } static void msdc_restore_reg(struct msdc_host *host) @@ -2079,6 +2385,14 @@ static void msdc_restore_reg(struct msdc_host *host) writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3); writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG); + if (host->top_base != NULL) { + writel(host->save_para.emmc_top_control, + host->top_base + EMMC_TOP_CONTROL); + writel(host->save_para.emmc_top_cmd, + host->top_base + EMMC_TOP_CMD); + writel(host->save_para.emmc50_pad_ds_tune, + host->top_base + EMMC50_PAD_DS_TUNE); + } } static int msdc_runtime_suspend(struct device *dev) diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index ba19b65ce4b9..ad0bcb6e57a0 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -53,6 +53,17 @@ config PINCTRL_MT6397 default MFD_MT6397 select PINCTRL_MTK +# For pintcrl command debug +config PINCTRL_MTK_DEBUG + bool "Mediatek pin control common debug" + depends on OF + default ARM64 && ARCH_MEDIATEK + select PINCTRL_MTK + help + Say yes here to enable support for MediaTek pinctrl debug command. + It can provide gpio status debug shell command. + We also can use these shell command to change gpio status. + endif if !ARCH_MEDIATEK diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index 3b4c3af7f39a..71867c1970be 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -855,9 +855,11 @@ static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev, return mtk_pinctrl_set_gpio_mode(pctl, pin, mode); #endif - if (pctl->devdata->spec_pinmux_set) + if (pctl->devdata->spec_pinmux_set) { pctl->devdata->spec_pinmux_set(mtk_get_regmap(pctl, pin), pin, mode); + return 0; + } reg_addr = ((pin / MAX_GPIO_MODE_PER_REG) << pctl->devdata->port_shf) + pctl->devdata->pinmux_offset; diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index 0fd6195601ba..3bf3f7c770dd 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -559,6 +559,15 @@ config REGULATOR_MT6323 This driver supports the control of different power rails of device through regulator interface. +config REGULATOR_MT6358 + tristate "MediaTek MT6358 PMIC" + depends on MFD_MT6397 + help + Say y here to select this option to enable the power regulator of + MediaTek MT6358 PMIC. + This driver supports the control of different power rails of device + through regulator interface. + config REGULATOR_MT6380 tristate "MediaTek MT6380 PMIC" depends on MTK_PMIC_WRAP diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile index 80ffc57a9ca3..b3c28d432a00 100644 --- a/drivers/regulator/Makefile +++ b/drivers/regulator/Makefile @@ -73,6 +73,7 @@ obj-$(CONFIG_REGULATOR_MC13892) += mc13892-regulator.o obj-$(CONFIG_REGULATOR_MC13XXX_CORE) += mc13xxx-regulator-core.o obj-$(CONFIG_REGULATOR_MT6311) += mt6311-regulator.o obj-$(CONFIG_REGULATOR_MT6323) += mt6323-regulator.o +obj-$(CONFIG_REGULATOR_MT6358) += mt6358-regulator.o obj-$(CONFIG_REGULATOR_MT6380) += mt6380-regulator.o obj-$(CONFIG_REGULATOR_MT6397) += mt6397-regulator.o obj-$(CONFIG_REGULATOR_QCOM_RPM) += qcom_rpm-regulator.o diff --git a/drivers/regulator/mt6358-regulator.c b/drivers/regulator/mt6358-regulator.c new file mode 100644 index 000000000000..37349e61d2ee --- /dev/null +++ b/drivers/regulator/mt6358-regulator.c @@ -0,0 +1,495 @@ +/* + * Copyright (c) 2018 MediaTek Inc. + * Author: Hsin-Hsiung Wang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * MT6358 regulators' information + * + * @desc: standard fields of regulator description. + * @qi: Mask for query enable signal status of regulators + */ +struct mt6358_regulator_info { + struct regulator_desc desc; + u32 status_reg; + u32 qi; + const u32 *index_table; + unsigned int n_table; + u32 vsel_shift; +}; + +#define MT6358_BUCK(match, vreg, min, max, step, \ + volt_ranges, vosel_mask) \ +[MT6358_ID_##vreg] = { \ + .desc = { \ + .name = #vreg, \ + .of_match = of_match_ptr(match), \ + .ops = &mt6358_volt_range_ops, \ + .type = REGULATOR_VOLTAGE, \ + .id = MT6358_ID_##vreg, \ + .owner = THIS_MODULE, \ + .n_voltages = (max - min)/step + 1, \ + .linear_ranges = volt_ranges, \ + .n_linear_ranges = ARRAY_SIZE(volt_ranges), \ + .vsel_reg = MT6358_BUCK_##vreg##_ELR0, \ + .vsel_mask = vosel_mask, \ + .enable_reg = MT6358_BUCK_##vreg##_CON0, \ + .enable_mask = BIT(0), \ + }, \ + .status_reg = MT6358_BUCK_##vreg##_DBG1, \ + .qi = BIT(0), \ +} + +#define MT6358_LDO(match, vreg, ldo_volt_table, ldo_index_table, enreg, \ + enbit, vosel, vosel_mask, vosel_shift) \ +[MT6358_ID_##vreg] = { \ + .desc = { \ + .name = #vreg, \ + .of_match = of_match_ptr(match), \ + .ops = &mt6358_volt_table_ops, \ + .type = REGULATOR_VOLTAGE, \ + .id = MT6358_ID_##vreg, \ + .owner = THIS_MODULE, \ + .n_voltages = ARRAY_SIZE(ldo_volt_table), \ + .volt_table = ldo_volt_table, \ + .vsel_reg = vosel, \ + .vsel_mask = vosel_mask, \ + .enable_reg = enreg, \ + .enable_mask = BIT(enbit), \ + }, \ + .status_reg = MT6358_LDO_##vreg##_CON1, \ + .qi = BIT(15), \ + .index_table = ldo_index_table, \ + .n_table = ARRAY_SIZE(ldo_index_table), \ + .vsel_shift = vosel_shift, \ +} + +#define MT6358_LDO1(match, vreg, min, max, step, \ + volt_ranges, vosel, vosel_mask) \ +[MT6358_ID_##vreg] = { \ + .desc = { \ + .name = #vreg, \ + .of_match = of_match_ptr(match), \ + .ops = &mt6358_volt_range_ops, \ + .type = REGULATOR_VOLTAGE, \ + .id = MT6358_ID_##vreg, \ + .owner = THIS_MODULE, \ + .n_voltages = (max - min)/step + 1, \ + .linear_ranges = volt_ranges, \ + .n_linear_ranges = ARRAY_SIZE(volt_ranges), \ + .vsel_reg = vosel, \ + .vsel_mask = vosel_mask, \ + .enable_reg = MT6358_LDO_##vreg##_CON0, \ + .enable_mask = BIT(0), \ + }, \ + .status_reg = MT6358_LDO_##vreg##_DBG1, \ + .qi = BIT(0), \ +} + +#define MT6358_REG_FIXED(match, vreg, enreg, enbit, volt) \ +[MT6358_ID_##vreg] = { \ + .desc = { \ + .name = #vreg, \ + .of_match = of_match_ptr(match), \ + .ops = &mt6358_volt_fixed_ops, \ + .type = REGULATOR_VOLTAGE, \ + .id = MT6358_ID_##vreg, \ + .owner = THIS_MODULE, \ + .n_voltages = 1, \ + .enable_reg = enreg, \ + .enable_mask = BIT(enbit), \ + .min_uV = volt, \ + }, \ + .status_reg = MT6358_LDO_##vreg##_CON1, \ + .qi = BIT(15), \ +} + +static const struct regulator_linear_range buck_volt_range1[] = { + REGULATOR_LINEAR_RANGE(500000, 0, 0x7f, 6250), +}; + +static const struct regulator_linear_range buck_volt_range2[] = { + REGULATOR_LINEAR_RANGE(500000, 0, 0x7f, 12500), +}; + +static const struct regulator_linear_range buck_volt_range3[] = { + REGULATOR_LINEAR_RANGE(500000, 0, 0x3f, 50000), +}; + +static const struct regulator_linear_range buck_volt_range4[] = { + REGULATOR_LINEAR_RANGE(1000000, 0, 0x7f, 12500), +}; + +static const u32 vdram2_voltages[] = { + 600000, 1800000, +}; + +static const u32 vsim1_voltages[] = { + 1700000, 1800000, 2700000, 3000000, 3100000, +}; + +static const u32 vibr_voltages[] = { + 1200000, 1300000, 1500000, 1800000, + 2000000, 2800000, 3000000, 3300000, +}; + +static const u32 vusb_voltages[] = { + 3000000, 3100000, +}; + +static const u32 vcamd_voltages[] = { + 900000, 1000000, 1100000, 1200000, + 1300000, 1500000, 1800000, +}; + +static const u32 vefuse_voltages[] = { + 1700000, 1800000, 1900000, +}; + +static const u32 vmch_voltages[] = { + 2900000, 3000000, 3300000, +}; + +static const u32 vcama1_voltages[] = { + 1800000, 2500000, 2700000, + 2800000, 2900000, 3000000, +}; + +static const u32 vemc_voltages[] = { + 2900000, 3000000, 3300000, +}; + +static const u32 vcn33_bt_voltages[] = { + 3300000, 3400000, 3500000, +}; + +static const u32 vcn33_wifi_voltages[] = { + 3300000, 3400000, 3500000, +}; + +static const u32 vcama2_voltages[] = { + 1800000, 2500000, 2700000, + 2800000, 2900000, 3000000, +}; + +static const u32 vmc_voltages[] = { + 1800000, 2900000, 3000000, 3300000, +}; + +static const u32 vldo28_voltages[] = { + 2800000, 3000000, +}; + +static const u32 vsim2_voltages[] = { + 1700000, 1800000, 2700000, + 3000000, 3100000, +}; + +static const u32 vdram2_idx[] = { + 0, 12, +}; + +static const u32 vsim1_idx[] = { + 3, 4, 8, 11, 12, +}; + +static const u32 vibr_idx[] = { + 0, 1, 2, 4, 5, 9, 11, 13, +}; + +static const u32 vusb_idx[] = { + 3, 4, +}; + +static const u32 vcamd_idx[] = { + 3, 4, 5, 6, 7, 9, 12, +}; + +static const u32 vefuse_idx[] = { + 11, 12, 13, +}; + +static const u32 vmch_idx[] = { + 2, 3, 5, +}; + +static const u32 vcama1_idx[] = { + 0, 7, 9, 10, 11, 12, +}; + +static const u32 vemc_idx[] = { + 2, 3, 5, +}; + +static const u32 vcn33_bt_idx[] = { + 1, 2, 3, +}; + +static const u32 vcn33_wifi_idx[] = { + 1, 2, 3, +}; + +static const u32 vcama2_idx[] = { + 0, 7, 9, 10, 11, 12, +}; + +static const u32 vmc_idx[] = { + 4, 10, 11, 13, +}; + +static const u32 vldo28_idx[] = { + 1, 3, +}; + +static const u32 vsim2_idx[] = { + 3, 4, 8, 11, 12, +}; + +static int mt6358_set_voltage_sel( + struct regulator_dev *rdev, unsigned int selector) +{ + int idx, ret; + const u32 *pVoltidx; + struct mt6358_regulator_info *info = rdev_get_drvdata(rdev); + + pVoltidx = (const u32 *)info->index_table; + + idx = pVoltidx[selector]; + ret = regmap_update_bits(rdev->regmap, info->desc.vsel_reg, + info->desc.vsel_mask, idx << info->vsel_shift); + + return ret; +} + +static int mt6358_get_voltage_sel(struct regulator_dev *rdev) +{ + int idx, ret; + u32 selector; + struct mt6358_regulator_info *info = rdev_get_drvdata(rdev); + const u32 *pVoltidx; + + ret = regmap_read(rdev->regmap, info->desc.vsel_reg, &selector); + if (ret != 0) { + dev_info(&rdev->dev, + "Failed to get mt6358 %s vsel reg: %d\n", + info->desc.name, ret); + return ret; + } + + selector = (selector & info->desc.vsel_mask) >> info->vsel_shift; + pVoltidx = (const u32 *)info->index_table; + ret = -1; + for (idx = 0; idx < info->desc.n_voltages; idx++) { + if (pVoltidx[idx] == selector) { + ret = idx; + break; + } + } + + return ret; +} + +static int mt6358_get_status(struct regulator_dev *rdev) +{ + int ret; + u32 regval; + struct mt6358_regulator_info *info = rdev_get_drvdata(rdev); + + ret = regmap_read(rdev->regmap, info->status_reg, ®val); + if (ret != 0) { + dev_info(&rdev->dev, "Failed to get enable reg: %d\n", ret); + return ret; + } + + return (regval & info->qi) ? REGULATOR_STATUS_ON : REGULATOR_STATUS_OFF; +} + +static const struct regulator_ops mt6358_volt_range_ops = { + .list_voltage = regulator_list_voltage_linear_range, + .map_voltage = regulator_map_voltage_linear_range, + .set_voltage_sel = regulator_set_voltage_sel_regmap, + .get_voltage_sel = regulator_get_voltage_sel_regmap, + .set_voltage_time_sel = regulator_set_voltage_time_sel, + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, + .get_status = mt6358_get_status, +}; + +static const struct regulator_ops mt6358_volt_table_ops = { + .list_voltage = regulator_list_voltage_table, + .map_voltage = regulator_map_voltage_iterate, + .set_voltage_sel = mt6358_set_voltage_sel, + .get_voltage_sel = mt6358_get_voltage_sel, + .set_voltage_time_sel = regulator_set_voltage_time_sel, + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, + .get_status = mt6358_get_status, +}; + +static const struct regulator_ops mt6358_volt_fixed_ops = { + .list_voltage = regulator_list_voltage_linear, + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, + .get_status = mt6358_get_status, +}; + +/* The array is indexed by id(MT6358_ID_XXX) */ +static struct mt6358_regulator_info mt6358_regulators[] = { + MT6358_BUCK("buck_vdram1", VDRAM1, 500000, 2087500, 12500, + buck_volt_range2, 0x7f), + MT6358_BUCK("buck_vcore", VCORE, 500000, 1293750, 6250, + buck_volt_range1, 0x7f), + MT6358_BUCK("buck_vpa", VPA, 500000, 3650000, 50000, + buck_volt_range3, 0x3f), + MT6358_BUCK("buck_vproc11", VPROC11, 500000, 1293750, 6250, + buck_volt_range1, 0x7f), + MT6358_BUCK("buck_vproc12", VPROC12, 500000, 1293750, 6250, + buck_volt_range1, 0x7f), + MT6358_BUCK("buck_vgpu", VGPU, 500000, 1293750, 6250, + buck_volt_range1, 0x7f), + MT6358_BUCK("buck_vs2", VS2, 500000, 2087500, 12500, + buck_volt_range2, 0x7f), + MT6358_BUCK("buck_vmodem", VMODEM, 500000, 1293750, 6250, + buck_volt_range1, 0x7f), + MT6358_BUCK("buck_vs1", VS1, 1000000, 2587500, 12500, + buck_volt_range4, 0x7f), + MT6358_REG_FIXED("ldo_vrf12", VRF12, + MT6358_LDO_VRF12_CON0, 0, 1200000), + MT6358_REG_FIXED("ldo_vio18", VIO18, + MT6358_LDO_VIO18_CON0, 0, 1800000), + MT6358_REG_FIXED("ldo_vcamio", VCAMIO, + MT6358_LDO_VCAMIO_CON0, 0, 1800000), + MT6358_REG_FIXED("ldo_vcn18", VCN18, MT6358_LDO_VCN18_CON0, 0, 1800000), + MT6358_REG_FIXED("ldo_vfe28", VFE28, MT6358_LDO_VFE28_CON0, 0, 2800000), + MT6358_REG_FIXED("ldo_vcn28", VCN28, MT6358_LDO_VCN28_CON0, 0, 2800000), + MT6358_REG_FIXED("ldo_vxo22", VXO22, MT6358_LDO_VXO22_CON0, 0, 2200000), + MT6358_REG_FIXED("ldo_vaux18", VAUX18, + MT6358_LDO_VAUX18_CON0, 0, 1800000), + MT6358_REG_FIXED("ldo_vbif28", VBIF28, + MT6358_LDO_VBIF28_CON0, 0, 2800000), + MT6358_REG_FIXED("ldo_vio28", VIO28, MT6358_LDO_VIO28_CON0, 0, 2800000), + MT6358_REG_FIXED("ldo_va12", VA12, MT6358_LDO_VA12_CON0, 0, 1200000), + MT6358_REG_FIXED("ldo_vrf18", VRF18, MT6358_LDO_VRF18_CON0, 0, 1800000), + MT6358_REG_FIXED("ldo_vaud28", VAUD28, + MT6358_LDO_VAUD28_CON0, 0, 2800000), + MT6358_LDO("ldo_vdram2", VDRAM2, vdram2_voltages, vdram2_idx, + MT6358_LDO_VDRAM2_CON0, 0, MT6358_LDO_VDRAM2_ELR0, 0x10, 0), + MT6358_LDO("ldo_vsim1", VSIM1, vsim1_voltages, vsim1_idx, + MT6358_LDO_VSIM1_CON0, 0, MT6358_VSIM1_ANA_CON0, 0xf00, 8), + MT6358_LDO("ldo_vibr", VIBR, vibr_voltages, vibr_idx, + MT6358_LDO_VIBR_CON0, 0, MT6358_VIBR_ANA_CON0, 0xf00, 8), + MT6358_LDO("ldo_vusb", VUSB, vusb_voltages, vusb_idx, + MT6358_LDO_VUSB_CON0_0, 0, MT6358_VUSB_ANA_CON0, 0x700, 8), + MT6358_LDO("ldo_vcamd", VCAMD, vcamd_voltages, vcamd_idx, + MT6358_LDO_VCAMD_CON0, 0, MT6358_VCAMD_ANA_CON0, 0xf00, 8), + MT6358_LDO("ldo_vefuse", VEFUSE, vefuse_voltages, vefuse_idx, + MT6358_LDO_VEFUSE_CON0, 0, MT6358_VEFUSE_ANA_CON0, 0xf00, 8), + MT6358_LDO("ldo_vmch", VMCH, vmch_voltages, vmch_idx, + MT6358_LDO_VMCH_CON0, 0, MT6358_VMCH_ANA_CON0, 0x700, 8), + MT6358_LDO("ldo_vcama1", VCAMA1, vcama1_voltages, vcama1_idx, + MT6358_LDO_VCAMA1_CON0, 0, MT6358_VCAMA1_ANA_CON0, 0xf00, 8), + MT6358_LDO("ldo_vemc", VEMC, vemc_voltages, vemc_idx, + MT6358_LDO_VEMC_CON0, 0, MT6358_VEMC_ANA_CON0, 0x700, 8), + MT6358_LDO("ldo_vcn33_bt", VCN33_BT, vcn33_bt_voltages, vcn33_bt_idx, + MT6358_LDO_VCN33_CON0_0, 0, MT6358_VCN33_ANA_CON0, 0x300, 8), + MT6358_LDO("ldo_vcn33_wifi", VCN33_WIFI, vcn33_wifi_voltages, + vcn33_wifi_idx, MT6358_LDO_VCN33_CON0_1, + 0, MT6358_VCN33_ANA_CON0, 0x300, 8), + MT6358_LDO("ldo_vcama2", VCAMA2, vcama2_voltages, vcama2_idx, + MT6358_LDO_VCAMA2_CON0, 0, MT6358_VCAMA2_ANA_CON0, 0xf00, 8), + MT6358_LDO("ldo_vmc", VMC, vmc_voltages, vmc_idx, + MT6358_LDO_VMC_CON0, 0, MT6358_VMC_ANA_CON0, 0xf00, 8), + MT6358_LDO("ldo_vldo28", VLDO28, vldo28_voltages, vldo28_idx, + MT6358_LDO_VLDO28_CON0_0, 0, MT6358_VLDO28_ANA_CON0, 0x300, 8), + MT6358_LDO("ldo_vsim2", VSIM2, vsim2_voltages, vsim2_idx, + MT6358_LDO_VSIM2_CON0, 0, MT6358_VSIM2_ANA_CON0, 0xf00, 8), + MT6358_LDO1("ldo_vsram_proc11", VSRAM_PROC11, 500000, 1293750, 6250, + buck_volt_range1, MT6358_LDO_VSRAM_CON0, 0x7f), + MT6358_LDO1("ldo_vsram_others", VSRAM_OTHERS, 500000, 1293750, 6250, + buck_volt_range1, MT6358_LDO_VSRAM_CON2, 0x7f), + MT6358_LDO1("ldo_vsram_gpu", VSRAM_GPU, 500000, 1293750, 6250, + buck_volt_range1, MT6358_LDO_VSRAM_CON3, 0x7f), + MT6358_LDO1("ldo_vsram_proc12", VSRAM_PROC12, 500000, 1293750, 6250, + buck_volt_range1, MT6358_LDO_VSRAM_CON1, 0x7f), +}; + +static int mt6358_regulator_probe(struct platform_device *pdev) +{ + struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent); + struct regulator_config config = {}; + struct regulator_dev *rdev; + int i; + u32 reg_value; + + /* Read PMIC chip revision to update constraints and voltage table */ + if (regmap_read(mt6397->regmap, MT6358_SWCID, ®_value) < 0) { + dev_err(&pdev->dev, "Failed to read Chip ID\n"); + return -EIO; + } + + for (i = 0; i < MT6358_MAX_REGULATOR; i++) { + config.dev = &pdev->dev; + config.driver_data = &mt6358_regulators[i]; + config.regmap = mt6397->regmap; + + rdev = devm_regulator_register(&pdev->dev, + &mt6358_regulators[i].desc, &config); + if (IS_ERR(rdev)) { + dev_err(&pdev->dev, "failed to register %s\n", + mt6358_regulators[i].desc.name); + return PTR_ERR(rdev); + } + } + + return 0; +} + +static const struct platform_device_id mt6358_platform_ids[] = { + {"mt6358-regulator", 0}, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(platform, mt6358_platform_ids); + +static const struct of_device_id mt6358_of_match[] = { + { .compatible = "mediatek,mt6358-regulator", }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, mt6358_of_match); + +static struct platform_driver mt6358_regulator_driver = { + .driver = { + .name = "mt6358-regulator", + .of_match_table = of_match_ptr(mt6358_of_match), + }, + .probe = mt6358_regulator_probe, + .id_table = mt6358_platform_ids, +}; + +module_platform_driver(mt6358_regulator_driver); + +MODULE_AUTHOR("Hsin-Hsiung Wang "); +MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6358 PMIC"); +MODULE_LICENSE("GPL"); diff --git a/drivers/rtc/rtc-mt6397.c b/drivers/rtc/rtc-mt6397.c index 1a61fa56f3ad..385f8303bb41 100644 --- a/drivers/rtc/rtc-mt6397.c +++ b/drivers/rtc/rtc-mt6397.c @@ -322,10 +322,9 @@ static int mtk_rtc_probe(struct platform_device *pdev) res = platform_get_resource(pdev, IORESOURCE_MEM, 0); rtc->addr_base = res->start; - res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - rtc->irq = irq_create_mapping(mt6397_chip->irq_domain, res->start); - if (rtc->irq <= 0) - return -EINVAL; + rtc->irq = platform_get_irq(pdev, 0); + if (rtc->irq < 0) + return rtc->irq; rtc->regmap = mt6397_chip->regmap; rtc->dev = &pdev->dev; diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig index e530cda0288c..a462b748c1ee 100644 --- a/drivers/soc/mediatek/Kconfig +++ b/drivers/soc/mediatek/Kconfig @@ -10,6 +10,18 @@ config MTK_INFRACFG INFRACFG controller contains various infrastructure registers not directly associated to any device. +config MTK_CMDQ + tristate "MediaTek CMDQ Support" + depends on ARCH_MEDIATEK || COMPILE_TEST + select MAILBOX + select MTK_CMDQ_MBOX + select MTK_INFRACFG + help + Say yes here to add support for the MediaTek Command Queue (CMDQ) + driver. The CMDQ is used to help read/write registers with critical + time limitation, such as updating display configuration during the + vblank. + config MTK_PMIC_WRAP tristate "MediaTek PMIC Wrapper Support" select REGMAP diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile index d405ea562d8d..1840bd7c7e35 100644 --- a/drivers/soc/mediatek/Makefile +++ b/drivers/soc/mediatek/Makefile @@ -1,3 +1,4 @@ +obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c index fb2a8b1e7979..36a9b8911cfa 100644 --- a/drivers/soc/mediatek/mtk-scpsys.c +++ b/drivers/soc/mediatek/mtk-scpsys.c @@ -24,6 +24,7 @@ #include #include #include +#include #define SPM_VDE_PWR_CON 0x0210 #define SPM_MFG_PWR_CON 0x0214 @@ -84,6 +85,13 @@ enum clk_id { CLK_ETHIF, CLK_VDEC, CLK_HIFSEL, + CLK_ISP, + CLK_AUDIO, + CLK_CAM, + CLK_VPU, + CLK_VPU1, + CLK_VPU2, + CLK_VPU3, CLK_MAX, }; @@ -96,6 +104,13 @@ static const char * const clk_names[] = { "ethif", "vdec", "hif_sel", + "isp", + "audio", + "cam", + "vpu", + "vpu1", + "vpu2", + "vpu3", NULL, }; @@ -810,6 +825,147 @@ static const struct scp_subdomain scp_subdomain_mt8173[] = { {MT8173_POWER_DOMAIN_MFG_2D, MT8173_POWER_DOMAIN_MFG}, }; +/* + * MT8183 power domain support + */ + +static const struct scp_domain_data scp_domain_data_mt8183[] = { + [MT8183_POWER_DOMAIN_AUDIO] = { + .name = "audio", + .sta_mask = PWR_STATUS_AUDIO, + .ctl_offs = 0x0314, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + .clk_id = {CLK_AUDIO}, + }, + [MT8183_POWER_DOMAIN_CONN] = { + .name = "conn", + .sta_mask = PWR_STATUS_CONN, + .ctl_offs = 0x032c, + .sram_pdn_bits = 0, + .sram_pdn_ack_bits = 0, + .clk_id = {CLK_NONE}, + }, + [MT8183_POWER_DOMAIN_MFG_ASYNC] = { + .name = "mfg_async", + .sta_mask = PWR_STATUS_MFG_ASYNC, + .ctl_offs = 0x0334, + .sram_pdn_bits = 0, + .sram_pdn_ack_bits = 0, + .clk_id = {CLK_MFG}, + }, + [MT8183_POWER_DOMAIN_MFG] = { + .name = "mfg", + .sta_mask = PWR_STATUS_MFG, + .ctl_offs = 0x0338, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .clk_id = {CLK_NONE}, + }, + [MT8183_POWER_DOMAIN_MFG_CORE0] = { + .name = "mfg_core0", + .sta_mask = BIT(7), + .ctl_offs = 0x034c, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .clk_id = {CLK_NONE}, + }, + [MT8183_POWER_DOMAIN_MFG_CORE1] = { + .name = "mfg_core1", + .sta_mask = BIT(20), + .ctl_offs = 0x0310, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .clk_id = {CLK_NONE}, + }, + [MT8183_POWER_DOMAIN_MFG_2D] = { + .name = "mfg_2d", + .sta_mask = PWR_STATUS_MFG_2D, + .ctl_offs = 0x0348, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .clk_id = {CLK_NONE}, + }, + [MT8183_POWER_DOMAIN_DISP] = { + .name = "disp", + .sta_mask = PWR_STATUS_DISP, + .ctl_offs = 0x030c, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .clk_id = {CLK_MM}, + }, + [MT8183_POWER_DOMAIN_CAM] = { + .name = "cam", + .sta_mask = BIT(25), + .ctl_offs = 0x0344, + .sram_pdn_bits = GENMASK(9, 8), + .sram_pdn_ack_bits = GENMASK(13, 12), + .clk_id = {CLK_CAM}, + }, + [MT8183_POWER_DOMAIN_ISP] = { + .name = "isp", + .sta_mask = PWR_STATUS_ISP, + .ctl_offs = 0x0308, + .sram_pdn_bits = GENMASK(9, 8), + .sram_pdn_ack_bits = GENMASK(13, 12), + .clk_id = {CLK_ISP}, + }, + [MT8183_POWER_DOMAIN_VDEC] = { + .name = "vdec", + .sta_mask = BIT(31), + .ctl_offs = 0x0300, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .clk_id = {CLK_NONE}, + }, + [MT8183_POWER_DOMAIN_VENC] = { + .name = "venc", + .sta_mask = PWR_STATUS_VENC, + .ctl_offs = 0x0304, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + .clk_id = {CLK_NONE}, + }, + [MT8183_POWER_DOMAIN_VPU_TOP] = { + .name = "vpu_top", + .sta_mask = BIT(26), + .ctl_offs = 0x0324, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .clk_id = {CLK_VPU, CLK_VPU1}, + }, + [MT8183_POWER_DOMAIN_VPU_CORE0] = { + .name = "vpu_core0", + .sta_mask = BIT(27), + .ctl_offs = 0x33c, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(13, 12), + .clk_id = {CLK_VPU2}, + }, + [MT8183_POWER_DOMAIN_VPU_CORE1] = { + .name = "vpu_core1", + .sta_mask = BIT(28), + .ctl_offs = 0x0340, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(13, 12), + .clk_id = {CLK_VPU3}, + }, +}; + +static const struct scp_subdomain scp_subdomain_mt8183[] = { + {MT8183_POWER_DOMAIN_MFG_ASYNC, MT8183_POWER_DOMAIN_MFG}, + {MT8183_POWER_DOMAIN_MFG, MT8183_POWER_DOMAIN_MFG_2D}, + {MT8183_POWER_DOMAIN_MFG, MT8183_POWER_DOMAIN_MFG_CORE0}, + {MT8183_POWER_DOMAIN_MFG, MT8183_POWER_DOMAIN_MFG_CORE1}, + {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_CAM}, + {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_ISP}, + {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_VDEC}, + {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_VENC}, + {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_VPU_TOP}, + {MT8183_POWER_DOMAIN_VPU_TOP, MT8183_POWER_DOMAIN_VPU_CORE0}, + {MT8183_POWER_DOMAIN_VPU_TOP, MT8183_POWER_DOMAIN_VPU_CORE1}, +}; + static const struct scp_soc_data mt2701_data = { .domains = scp_domain_data_mt2701, .num_domains = ARRAY_SIZE(scp_domain_data_mt2701), @@ -850,6 +1006,17 @@ static const struct scp_soc_data mt8173_data = { } }; +static const struct scp_soc_data mt8183_data = { + .domains = scp_domain_data_mt8183, + .num_domains = ARRAY_SIZE(scp_domain_data_mt8183), + .subdomains = scp_subdomain_mt8183, + .num_subdomains = ARRAY_SIZE(scp_subdomain_mt8183), + .regs = { + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184 + } +}; + /* * scpsys driver init */ @@ -867,6 +1034,9 @@ static const struct of_device_id of_scpsys_match_tbl[] = { }, { .compatible = "mediatek,mt8173-scpsys", .data = &mt8173_data, + }, { + .compatible = "mediatek,mt8183-scpsys", + .data = &mt8183_data, }, { /* sentinel */ } @@ -874,15 +1044,13 @@ static const struct of_device_id of_scpsys_match_tbl[] = { static int scpsys_probe(struct platform_device *pdev) { - const struct of_device_id *match; const struct scp_subdomain *sd; const struct scp_soc_data *soc; struct scp *scp; struct genpd_onecell_data *pd_data; int i, ret; - match = of_match_device(of_scpsys_match_tbl, &pdev->dev); - soc = (const struct scp_soc_data *)match->data; + soc = of_device_get_match_data(&pdev->dev); scp = init_scp(pdev, soc->domains, soc->num_domains, &soc->regs); if (IS_ERR(scp)) diff --git a/include/dt-bindings/gce/mt8173-gce.h b/include/dt-bindings/gce/mt8173-gce.h new file mode 100644 index 000000000000..89eb3b815d9c --- /dev/null +++ b/include/dt-bindings/gce/mt8173-gce.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018 MediaTek Inc. + * Author: Houlong Wei + * + */ + +#ifndef _DT_BINDINGS_GCE_MT8173_H +#define _DT_BINDINGS_GCE_MT8173_H + +#define CMDQ_NO_TIMEOUT 0xffffffff + +#define CMDQ_THR_MAX_COUNT 16 + +/* GCE HW thread priority */ +#define CMDQ_THR_PRIO_LOWEST 0 +#define CMDQ_THR_PRIO_HIGHEST 1 + +/* GCE SUBSYS */ +#define SUBSYS_1400XXXX 1 +#define SUBSYS_1401XXXX 2 +#define SUBSYS_1402XXXX 3 + +/* GCE HW EVENT */ +#define CMDQ_EVENT_DISP_OVL0_SOF 11 +#define CMDQ_EVENT_DISP_OVL1_SOF 12 +#define CMDQ_EVENT_DISP_RDMA0_SOF 13 +#define CMDQ_EVENT_DISP_RDMA1_SOF 14 +#define CMDQ_EVENT_DISP_RDMA2_SOF 15 +#define CMDQ_EVENT_DISP_WDMA0_SOF 16 +#define CMDQ_EVENT_DISP_WDMA1_SOF 17 +#define CMDQ_EVENT_DISP_OVL0_EOF 39 +#define CMDQ_EVENT_DISP_OVL1_EOF 40 +#define CMDQ_EVENT_DISP_RDMA0_EOF 41 +#define CMDQ_EVENT_DISP_RDMA1_EOF 42 +#define CMDQ_EVENT_DISP_RDMA2_EOF 43 +#define CMDQ_EVENT_DISP_WDMA0_EOF 44 +#define CMDQ_EVENT_DISP_WDMA1_EOF 45 +#define CMDQ_EVENT_MUTEX0_STREAM_EOF 53 +#define CMDQ_EVENT_MUTEX1_STREAM_EOF 54 +#define CMDQ_EVENT_MUTEX2_STREAM_EOF 55 +#define CMDQ_EVENT_MUTEX3_STREAM_EOF 56 +#define CMDQ_EVENT_MUTEX4_STREAM_EOF 57 +#define CMDQ_EVENT_DISP_RDMA0_UNDERRUN 63 +#define CMDQ_EVENT_DISP_RDMA1_UNDERRUN 64 +#define CMDQ_EVENT_DISP_RDMA2_UNDERRUN 65 + +#endif diff --git a/include/dt-bindings/power/mt8173-power.h b/include/dt-bindings/power/mt8173-power.h index 15d531aa6e78..ef4a7f944848 100644 --- a/include/dt-bindings/power/mt8173-power.h +++ b/include/dt-bindings/power/mt8173-power.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _DT_BINDINGS_POWER_MT8183_POWER_H -#define _DT_BINDINGS_POWER_MT8183_POWER_H +#ifndef _DT_BINDINGS_POWER_MT8173_POWER_H +#define _DT_BINDINGS_POWER_MT8173_POWER_H #define MT8173_POWER_DOMAIN_VDEC 0 #define MT8173_POWER_DOMAIN_VENC 1 @@ -13,4 +13,4 @@ #define MT8173_POWER_DOMAIN_MFG_2D 8 #define MT8173_POWER_DOMAIN_MFG 9 -#endif /* _DT_BINDINGS_POWER_MT8183_POWER_H */ +#endif /* _DT_BINDINGS_POWER_MT8173_POWER_H */ diff --git a/include/dt-bindings/power/mt8183-power.h b/include/dt-bindings/power/mt8183-power.h new file mode 100644 index 000000000000..5618726dd77d --- /dev/null +++ b/include/dt-bindings/power/mt8183-power.h @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See http://www.gnu.org/licenses/gpl-2.0.html for more details. + */ + +#ifndef _DT_BINDINGS_POWER_MT8183_POWER_H +#define _DT_BINDINGS_POWER_MT8183_POWER_H + +#define MT8183_POWER_DOMAIN_AUDIO 0 +#define MT8183_POWER_DOMAIN_CONN 1 +#define MT8183_POWER_DOMAIN_MFG_ASYNC 2 +#define MT8183_POWER_DOMAIN_MFG 3 +#define MT8183_POWER_DOMAIN_MFG_CORE0 4 +#define MT8183_POWER_DOMAIN_MFG_CORE1 5 +#define MT8183_POWER_DOMAIN_MFG_2D 6 +#define MT8183_POWER_DOMAIN_DISP 7 +#define MT8183_POWER_DOMAIN_CAM 8 +#define MT8183_POWER_DOMAIN_ISP 9 +#define MT8183_POWER_DOMAIN_VDEC 10 +#define MT8183_POWER_DOMAIN_VENC 11 +#define MT8183_POWER_DOMAIN_VPU_TOP 12 +#define MT8183_POWER_DOMAIN_VPU_CORE0 13 +#define MT8183_POWER_DOMAIN_VPU_CORE1 14 + +#endif /* _DT_BINDINGS_POWER_MT8183_POWER_H */ diff --git a/include/linux/mfd/mt6358/registers.h b/include/linux/mfd/mt6358/registers.h new file mode 100644 index 000000000000..df1bf660dd2c --- /dev/null +++ b/include/linux/mfd/mt6358/registers.h @@ -0,0 +1,1935 @@ +/* + * Copyright (c) 2018 MediaTek Inc. + * Author: Hsin-Hsiung Wang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MFD_MT6358_REGISTERS_H__ +#define __MFD_MT6358_REGISTERS_H__ + +/* PMIC Registers */ +#define MT6358_TOP0_ID 0x0 +#define MT6358_TOP0_REV0 0x2 +#define MT6358_TOP0_DSN_DBI 0x4 +#define MT6358_TOP0_DSN_DXI 0x6 +#define MT6358_HWCID 0x8 +#define MT6358_SWCID 0xa +#define MT6358_PONSTS 0xc +#define MT6358_POFFSTS 0xe +#define MT6358_PSTSCTL 0x10 +#define MT6358_PG_DEB_STS0 0x12 +#define MT6358_PG_DEB_STS1 0x14 +#define MT6358_PG_SDN_STS0 0x16 +#define MT6358_PG_SDN_STS1 0x18 +#define MT6358_OC_SDN_STS0 0x1a +#define MT6358_THERMALSTATUS 0x1c +#define MT6358_TOP_CON 0x1e +#define MT6358_TEST_OUT 0x20 +#define MT6358_TEST_CON0 0x22 +#define MT6358_TEST_CON1 0x24 +#define MT6358_TESTMODE_SW 0x26 +#define MT6358_TOPSTATUS 0x28 +#define MT6358_TDSEL_CON 0x2a +#define MT6358_RDSEL_CON 0x2c +#define MT6358_SMT_CON0 0x2e +#define MT6358_SMT_CON1 0x30 +#define MT6358_TOP_RSV0 0x32 +#define MT6358_TOP_RSV1 0x34 +#define MT6358_DRV_CON0 0x36 +#define MT6358_DRV_CON1 0x38 +#define MT6358_DRV_CON2 0x3a +#define MT6358_DRV_CON3 0x3c +#define MT6358_DRV_CON4 0x3e +#define MT6358_FILTER_CON0 0x40 +#define MT6358_FILTER_CON1 0x42 +#define MT6358_FILTER_CON2 0x44 +#define MT6358_FILTER_CON3 0x46 +#define MT6358_TOP_STATUS 0x48 +#define MT6358_TOP_STATUS_SET 0x4a +#define MT6358_TOP_STATUS_CLR 0x4c +#define MT6358_TOP_TRAP 0x4e +#define MT6358_TOP1_ID 0x80 +#define MT6358_TOP1_REV0 0x82 +#define MT6358_TOP1_DSN_DBI 0x84 +#define MT6358_TOP1_DSN_DXI 0x86 +#define MT6358_GPIO_DIR0 0x88 +#define MT6358_GPIO_DIR0_SET 0x8a +#define MT6358_GPIO_DIR0_CLR 0x8c +#define MT6358_GPIO_DIR1 0x8e +#define MT6358_GPIO_DIR1_SET 0x90 +#define MT6358_GPIO_DIR1_CLR 0x92 +#define MT6358_GPIO_PULLEN0 0x94 +#define MT6358_GPIO_PULLEN0_SET 0x96 +#define MT6358_GPIO_PULLEN0_CLR 0x98 +#define MT6358_GPIO_PULLEN1 0x9a +#define MT6358_GPIO_PULLEN1_SET 0x9c +#define MT6358_GPIO_PULLEN1_CLR 0x9e +#define MT6358_GPIO_PULLSEL0 0xa0 +#define MT6358_GPIO_PULLSEL0_SET 0xa2 +#define MT6358_GPIO_PULLSEL0_CLR 0xa4 +#define MT6358_GPIO_PULLSEL1 0xa6 +#define MT6358_GPIO_PULLSEL1_SET 0xa8 +#define MT6358_GPIO_PULLSEL1_CLR 0xaa +#define MT6358_GPIO_DINV0 0xac +#define MT6358_GPIO_DINV0_SET 0xae +#define MT6358_GPIO_DINV0_CLR 0xb0 +#define MT6358_GPIO_DINV1 0xb2 +#define MT6358_GPIO_DINV1_SET 0xb4 +#define MT6358_GPIO_DINV1_CLR 0xb6 +#define MT6358_GPIO_DOUT0 0xb8 +#define MT6358_GPIO_DOUT0_SET 0xba +#define MT6358_GPIO_DOUT0_CLR 0xbc +#define MT6358_GPIO_DOUT1 0xbe +#define MT6358_GPIO_DOUT1_SET 0xc0 +#define MT6358_GPIO_DOUT1_CLR 0xc2 +#define MT6358_GPIO_PI0 0xc4 +#define MT6358_GPIO_PI1 0xc6 +#define MT6358_GPIO_POE0 0xc8 +#define MT6358_GPIO_POE1 0xca +#define MT6358_GPIO_MODE0 0xcc +#define MT6358_GPIO_MODE0_SET 0xce +#define MT6358_GPIO_MODE0_CLR 0xd0 +#define MT6358_GPIO_MODE1 0xd2 +#define MT6358_GPIO_MODE1_SET 0xd4 +#define MT6358_GPIO_MODE1_CLR 0xd6 +#define MT6358_GPIO_MODE2 0xd8 +#define MT6358_GPIO_MODE2_SET 0xda +#define MT6358_GPIO_MODE2_CLR 0xdc +#define MT6358_GPIO_MODE3 0xde +#define MT6358_GPIO_MODE3_SET 0xe0 +#define MT6358_GPIO_MODE3_CLR 0xe2 +#define MT6358_GPIO_MODE4 0xe4 +#define MT6358_GPIO_MODE4_SET 0xe6 +#define MT6358_GPIO_MODE4_CLR 0xe8 +#define MT6358_GPIO_RSV 0xea +#define MT6358_TOP2_ID 0x100 +#define MT6358_TOP2_REV0 0x102 +#define MT6358_TOP2_DSN_DBI 0x104 +#define MT6358_TOP2_DSN_DXI 0x106 +#define MT6358_TOP_PAM0 0x108 +#define MT6358_TOP_PAM1 0x10a +#define MT6358_TOP_CKPDN_CON0 0x10c +#define MT6358_TOP_CKPDN_CON0_SET 0x10e +#define MT6358_TOP_CKPDN_CON0_CLR 0x110 +#define MT6358_TOP_CKPDN_CON1 0x112 +#define MT6358_TOP_CKPDN_CON1_SET 0x114 +#define MT6358_TOP_CKPDN_CON1_CLR 0x116 +#define MT6358_TOP_CKSEL_CON0 0x118 +#define MT6358_TOP_CKSEL_CON0_SET 0x11a +#define MT6358_TOP_CKSEL_CON0_CLR 0x11c +#define MT6358_TOP_CKSEL_CON1 0x11e +#define MT6358_TOP_CKSEL_CON1_SET 0x120 +#define MT6358_TOP_CKSEL_CON1_CLR 0x122 +#define MT6358_TOP_CKDIVSEL_CON0 0x124 +#define MT6358_TOP_CKDIVSEL_CON0_SET 0x126 +#define MT6358_TOP_CKDIVSEL_CON0_CLR 0x128 +#define MT6358_TOP_CKHWEN_CON0 0x12a +#define MT6358_TOP_CKHWEN_CON0_SET 0x12c +#define MT6358_TOP_CKHWEN_CON0_CLR 0x12e +#define MT6358_TOP_CKTST_CON0 0x130 +#define MT6358_TOP_CKTST_CON1 0x132 +#define MT6358_TOP_CLK_CON0 0x134 +#define MT6358_TOP_CLK_CON0_SET 0x136 +#define MT6358_TOP_CLK_CON0_CLR 0x138 +#define MT6358_TOP_DCM_CON0 0x13a +#define MT6358_TOP_HANDOVER_DEBUG0 0x13c +#define MT6358_TOP_RST_CON0 0x13e +#define MT6358_TOP_RST_CON0_SET 0x140 +#define MT6358_TOP_RST_CON0_CLR 0x142 +#define MT6358_TOP_RST_CON1 0x144 +#define MT6358_TOP_RST_CON1_SET 0x146 +#define MT6358_TOP_RST_CON1_CLR 0x148 +#define MT6358_TOP_RST_CON2 0x14a +#define MT6358_TOP_RST_MISC 0x14c +#define MT6358_TOP_RST_MISC_SET 0x14e +#define MT6358_TOP_RST_MISC_CLR 0x150 +#define MT6358_TOP_RST_STATUS 0x152 +#define MT6358_TOP_RST_STATUS_SET 0x154 +#define MT6358_TOP_RST_STATUS_CLR 0x156 +#define MT6358_TOP2_ELR_NUM 0x158 +#define MT6358_TOP2_ELR0 0x15a +#define MT6358_TOP2_ELR1 0x15c +#define MT6358_TOP3_ID 0x180 +#define MT6358_TOP3_REV0 0x182 +#define MT6358_TOP3_DSN_DBI 0x184 +#define MT6358_TOP3_DSN_DXI 0x186 +#define MT6358_MISC_TOP_INT_CON0 0x188 +#define MT6358_MISC_TOP_INT_CON0_SET 0x18a +#define MT6358_MISC_TOP_INT_CON0_CLR 0x18c +#define MT6358_MISC_TOP_INT_MASK_CON0 0x18e +#define MT6358_MISC_TOP_INT_MASK_CON0_SET 0x190 +#define MT6358_MISC_TOP_INT_MASK_CON0_CLR 0x192 +#define MT6358_MISC_TOP_INT_STATUS0 0x194 +#define MT6358_MISC_TOP_INT_RAW_STATUS0 0x196 +#define MT6358_TOP_INT_MASK_CON0 0x198 +#define MT6358_TOP_INT_MASK_CON0_SET 0x19a +#define MT6358_TOP_INT_MASK_CON0_CLR 0x19c +#define MT6358_TOP_INT_STATUS0 0x19e +#define MT6358_TOP_INT_RAW_STATUS0 0x1a0 +#define MT6358_TOP_INT_CON0 0x1a2 +#define MT6358_PLT0_ID 0x380 +#define MT6358_PLT0_REV0 0x382 +#define MT6358_PLT0_REV1 0x384 +#define MT6358_PLT0_DSN_DXI 0x386 +#define MT6358_TOP_CLK_TRIM 0x388 +#define MT6358_OTP_CON0 0x38a +#define MT6358_OTP_CON1 0x38c +#define MT6358_OTP_CON2 0x38e +#define MT6358_OTP_CON3 0x390 +#define MT6358_OTP_CON4 0x392 +#define MT6358_OTP_CON5 0x394 +#define MT6358_OTP_CON6 0x396 +#define MT6358_OTP_CON7 0x398 +#define MT6358_OTP_CON8 0x39a +#define MT6358_OTP_CON9 0x39c +#define MT6358_OTP_CON10 0x39e +#define MT6358_OTP_CON11 0x3a0 +#define MT6358_OTP_CON12 0x3a2 +#define MT6358_OTP_CON13 0x3a4 +#define MT6358_OTP_CON14 0x3a6 +#define MT6358_TOP_TMA_KEY 0x3a8 +#define MT6358_TOP_MDB_CONF0 0x3aa +#define MT6358_TOP_MDB_CONF1 0x3ac +#define MT6358_TOP_MDB_CONF2 0x3ae +#define MT6358_PLT0_ELR_NUM 0x3b0 +#define MT6358_PLT0_ELR0 0x3b2 +#define MT6358_PLT0_ELR1 0x3b4 +#define MT6358_SPISLV_ID 0x400 +#define MT6358_SPISLV_REV0 0x402 +#define MT6358_SPISLV_REV1 0x404 +#define MT6358_SPISLV_DSN_DXI 0x406 +#define MT6358_RG_SPI_CON0 0x408 +#define MT6358_RG_SPI_RECORD0 0x40a +#define MT6358_DEW_DIO_EN 0x40c +#define MT6358_DEW_READ_TEST 0x40e +#define MT6358_DEW_WRITE_TEST 0x410 +#define MT6358_DEW_CRC_SWRST 0x412 +#define MT6358_DEW_CRC_EN 0x414 +#define MT6358_DEW_CRC_VAL 0x416 +#define MT6358_DEW_DBG_MON_SEL 0x418 +#define MT6358_DEW_CIPHER_KEY_SEL 0x41a +#define MT6358_DEW_CIPHER_IV_SEL 0x41c +#define MT6358_DEW_CIPHER_EN 0x41e +#define MT6358_DEW_CIPHER_RDY 0x420 +#define MT6358_DEW_CIPHER_MODE 0x422 +#define MT6358_DEW_CIPHER_SWRST 0x424 +#define MT6358_DEW_RDDMY_NO 0x426 +#define MT6358_INT_TYPE_CON0 0x428 +#define MT6358_INT_TYPE_CON0_SET 0x42a +#define MT6358_INT_TYPE_CON0_CLR 0x42c +#define MT6358_INT_STA 0x42e +#define MT6358_RG_SPI_CON1 0x430 +#define MT6358_RG_SPI_CON2 0x432 +#define MT6358_RG_SPI_CON3 0x434 +#define MT6358_RG_SPI_CON4 0x436 +#define MT6358_RG_SPI_CON5 0x438 +#define MT6358_RG_SPI_CON6 0x43a +#define MT6358_RG_SPI_CON7 0x43c +#define MT6358_RG_SPI_CON8 0x43e +#define MT6358_RG_SPI_CON9 0x440 +#define MT6358_RG_SPI_CON10 0x442 +#define MT6358_RG_SPI_CON11 0x444 +#define MT6358_RG_SPI_CON12 0x446 +#define MT6358_RG_SPI_CON13 0x448 +#define MT6358_SPISLV_KEY 0x44a +#define MT6358_TOP_SPI_CON0 0x44c +#define MT6358_TOP_SPI_CON1 0x44e +#define MT6358_SCK_TOP_DSN_ID 0x500 +#define MT6358_SCK_TOP_DSN_REV0 0x502 +#define MT6358_SCK_TOP_DBI 0x504 +#define MT6358_SCK_TOP_DXI 0x506 +#define MT6358_SCK_TOP_TPM0 0x508 +#define MT6358_SCK_TOP_TPM1 0x50a +#define MT6358_SCK_TOP_CON0 0x50c +#define MT6358_SCK_TOP_CON1 0x50e +#define MT6358_SCK_TOP_TEST_OUT 0x510 +#define MT6358_SCK_TOP_TEST_CON0 0x512 +#define MT6358_FQMTR_CON0 0x514 +#define MT6358_FQMTR_CON1 0x516 +#define MT6358_FQMTR_CON2 0x518 +#define MT6358_SCK_TOP_CKPDN_CON0 0x51a +#define MT6358_SCK_TOP_CKPDN_CON0_SET 0x51c +#define MT6358_SCK_TOP_CKPDN_CON0_CLR 0x51e +#define MT6358_SCK_TOP_CKHWEN_CON0 0x520 +#define MT6358_SCK_TOP_CKHWEN_CON0_SET 0x522 +#define MT6358_SCK_TOP_CKHWEN_CON0_CLR 0x524 +#define MT6358_SCK_TOP_CKTST_CON 0x526 +#define MT6358_SCK_TOP_RST_CON0 0x528 +#define MT6358_SCK_TOP_RST_CON0_SET 0x52a +#define MT6358_SCK_TOP_RST_CON0_CLR 0x52c +#define MT6358_SCK_TOP_INT_CON0 0x52e +#define MT6358_SCK_TOP_INT_CON0_SET 0x530 +#define MT6358_SCK_TOP_INT_CON0_CLR 0x532 +#define MT6358_SCK_TOP_INT_MASK_CON0 0x534 +#define MT6358_SCK_TOP_INT_MASK_CON0_SET 0x536 +#define MT6358_SCK_TOP_INT_MASK_CON0_CLR 0x538 +#define MT6358_SCK_TOP_INT_STATUS0 0x53a +#define MT6358_SCK_TOP_INT_RAW_STATUS0 0x53c +#define MT6358_SCK_TOP_INT_MISC_CON 0x53e +#define MT6358_EOSC_CALI_CON0 0x540 +#define MT6358_EOSC_CALI_CON1 0x542 +#define MT6358_RTC_MIX_CON0 0x544 +#define MT6358_RTC_MIX_CON1 0x546 +#define MT6358_RTC_MIX_CON2 0x548 +#define MT6358_RTC_DSN_ID 0x580 +#define MT6358_RTC_DSN_REV0 0x582 +#define MT6358_RTC_DBI 0x584 +#define MT6358_RTC_DXI 0x586 +#define MT6358_RTC_BBPU 0x588 +#define MT6358_RTC_IRQ_STA 0x58a +#define MT6358_RTC_IRQ_EN 0x58c +#define MT6358_RTC_CII_EN 0x58e +#define MT6358_RTC_AL_MASK 0x590 +#define MT6358_RTC_TC_SEC 0x592 +#define MT6358_RTC_TC_MIN 0x594 +#define MT6358_RTC_TC_HOU 0x596 +#define MT6358_RTC_TC_DOM 0x598 +#define MT6358_RTC_TC_DOW 0x59a +#define MT6358_RTC_TC_MTH 0x59c +#define MT6358_RTC_TC_YEA 0x59e +#define MT6358_RTC_AL_SEC 0x5a0 +#define MT6358_RTC_AL_MIN 0x5a2 +#define MT6358_RTC_AL_HOU 0x5a4 +#define MT6358_RTC_AL_DOM 0x5a6 +#define MT6358_RTC_AL_DOW 0x5a8 +#define MT6358_RTC_AL_MTH 0x5aa +#define MT6358_RTC_AL_YEA 0x5ac +#define MT6358_RTC_OSC32CON 0x5ae +#define MT6358_RTC_POWERKEY1 0x5b0 +#define MT6358_RTC_POWERKEY2 0x5b2 +#define MT6358_RTC_PDN1 0x5b4 +#define MT6358_RTC_PDN2 0x5b6 +#define MT6358_RTC_SPAR0 0x5b8 +#define MT6358_RTC_SPAR1 0x5ba +#define MT6358_RTC_PROT 0x5bc +#define MT6358_RTC_DIFF 0x5be +#define MT6358_RTC_CALI 0x5c0 +#define MT6358_RTC_WRTGR 0x5c2 +#define MT6358_RTC_CON 0x5c4 +#define MT6358_RTC_SEC_CTRL 0x5c6 +#define MT6358_RTC_INT_CNT 0x5c8 +#define MT6358_RTC_SEC_DAT0 0x5ca +#define MT6358_RTC_SEC_DAT1 0x5cc +#define MT6358_RTC_SEC_DAT2 0x5ce +#define MT6358_RTC_SEC_DSN_ID 0x600 +#define MT6358_RTC_SEC_DSN_REV0 0x602 +#define MT6358_RTC_SEC_DBI 0x604 +#define MT6358_RTC_SEC_DXI 0x606 +#define MT6358_RTC_TC_SEC_SEC 0x608 +#define MT6358_RTC_TC_MIN_SEC 0x60a +#define MT6358_RTC_TC_HOU_SEC 0x60c +#define MT6358_RTC_TC_DOM_SEC 0x60e +#define MT6358_RTC_TC_DOW_SEC 0x610 +#define MT6358_RTC_TC_MTH_SEC 0x612 +#define MT6358_RTC_TC_YEA_SEC 0x614 +#define MT6358_RTC_SEC_CK_PDN 0x616 +#define MT6358_RTC_SEC_WRTGR 0x618 +#define MT6358_DCXO_DSN_ID 0x780 +#define MT6358_DCXO_DSN_REV0 0x782 +#define MT6358_DCXO_DSN_DBI 0x784 +#define MT6358_DCXO_DSN_DXI 0x786 +#define MT6358_DCXO_CW00 0x788 +#define MT6358_DCXO_CW00_SET 0x78a +#define MT6358_DCXO_CW00_CLR 0x78c +#define MT6358_DCXO_CW01 0x78e +#define MT6358_DCXO_CW02 0x790 +#define MT6358_DCXO_CW03 0x792 +#define MT6358_DCXO_CW04 0x794 +#define MT6358_DCXO_CW05 0x796 +#define MT6358_DCXO_CW06 0x798 +#define MT6358_DCXO_CW07 0x79a +#define MT6358_DCXO_CW08 0x79c +#define MT6358_DCXO_CW09 0x79e +#define MT6358_DCXO_CW10 0x7a0 +#define MT6358_DCXO_CW11 0x7a2 +#define MT6358_DCXO_CW11_SET 0x7a4 +#define MT6358_DCXO_CW11_CLR 0x7a6 +#define MT6358_DCXO_CW12 0x7a8 +#define MT6358_DCXO_CW13 0x7aa +#define MT6358_DCXO_CW14 0x7ac +#define MT6358_DCXO_CW15 0x7ae +#define MT6358_DCXO_CW16 0x7b0 +#define MT6358_DCXO_CW17 0x7b2 +#define MT6358_DCXO_CW18 0x7b4 +#define MT6358_DCXO_CW19 0x7b6 +#define MT6358_DCXO_CW20 0x7b8 +#define MT6358_DCXO_CW21 0x7ba +#define MT6358_DCXO_CW22 0x7bc +#define MT6358_DCXO_CW23 0x7be +#define MT6358_DCXO_CW24 0x7c0 +#define MT6358_DCXO_ELR_NUM 0x7c2 +#define MT6358_DCXO_ELR0 0x7c4 +#define MT6358_PSC_TOP_ID 0x900 +#define MT6358_PSC_TOP_REV0 0x902 +#define MT6358_PSC_TOP_DBI 0x904 +#define MT6358_PSC_TOP_DXI 0x906 +#define MT6358_PSC_TPM0 0x908 +#define MT6358_PSC_TPM1 0x90a +#define MT6358_PSC_TOP_CLKCTL_0 0x90c +#define MT6358_PSC_TOP_RSTCTL_0 0x90e +#define MT6358_PSC_TOP_INT_CON0 0x910 +#define MT6358_PSC_TOP_INT_CON0_SET 0x912 +#define MT6358_PSC_TOP_INT_CON0_CLR 0x914 +#define MT6358_PSC_TOP_INT_MASK_CON0 0x916 +#define MT6358_PSC_TOP_INT_MASK_CON0_SET 0x918 +#define MT6358_PSC_TOP_INT_MASK_CON0_CLR 0x91a +#define MT6358_PSC_TOP_INT_STATUS0 0x91c +#define MT6358_PSC_TOP_INT_RAW_STATUS0 0x91e +#define MT6358_PSC_TOP_INT_MISC_CON 0x920 +#define MT6358_PSC_TOP_INT_MISC_CON_SET 0x922 +#define MT6358_PSC_TOP_INT_MISC_CON_CLR 0x924 +#define MT6358_PSC_TOP_MON_CTL 0x926 +#define MT6358_STRUP_ID 0x980 +#define MT6358_STRUP_REV0 0x982 +#define MT6358_STRUP_DBI 0x984 +#define MT6358_STRUP_DSN_FPI 0x986 +#define MT6358_STRUP_ANA_CON0 0x988 +#define MT6358_STRUP_ANA_CON1 0x98a +#define MT6358_STRUP_ELR_NUM 0x98c +#define MT6358_STRUP_ELR_0 0x98e +#define MT6358_STRUP_ELR_1 0x990 +#define MT6358_PSEQ_ID 0xa00 +#define MT6358_PSEQ_REV0 0xa02 +#define MT6358_PSEQ_DBI 0xa04 +#define MT6358_PSEQ_DXI 0xa06 +#define MT6358_PPCCTL0 0xa08 +#define MT6358_PPCCTL1 0xa0a +#define MT6358_PPCCTL2 0xa0c +#define MT6358_PPCCFG0 0xa0e +#define MT6358_PPCTST0 0xa10 +#define MT6358_PORFLAG 0xa12 +#define MT6358_STRUP_CON0 0xa14 +#define MT6358_STRUP_CON1 0xa16 +#define MT6358_STRUP_CON2 0xa18 +#define MT6358_STRUP_CON3 0xa1a +#define MT6358_STRUP_CON4 0xa1c +#define MT6358_STRUP_CON5 0xa1e +#define MT6358_STRUP_CON6 0xa20 +#define MT6358_STRUP_CON7 0xa22 +#define MT6358_CPSCFG0 0xa24 +#define MT6358_CPSDSA0 0xa26 +#define MT6358_CPSDSA1 0xa28 +#define MT6358_CPSDSA2 0xa2a +#define MT6358_CPSDSA3 0xa2c +#define MT6358_CPSDSA4 0xa2e +#define MT6358_CPSDSA5 0xa30 +#define MT6358_CPSDSA6 0xa32 +#define MT6358_CPSDSA7 0xa34 +#define MT6358_STRUP_CON9 0xa36 +#define MT6358_STRUP_CON10 0xa38 +#define MT6358_STRUP_CON11 0xa3a +#define MT6358_STRUP_CON12 0xa3c +#define MT6358_STRUP_CON13 0xa3e +#define MT6358_PWRKEY_PRESS_STS 0xa40 +#define MT6358_STRUP_CON19 0xa42 +#define MT6358_STRUP_CON14 0xa44 +#define MT6358_STRUP_CON15 0xa46 +#define MT6358_STRUP_CON16 0xa48 +#define MT6358_STRUP_CON17 0xa4a +#define MT6358_STRUP_CON18 0xa4c +#define MT6358_PSEQ_ELR_NUM 0xa4e +#define MT6358_PSEQ_ELR0 0xa50 +#define MT6358_PSEQ_ELR1 0xa52 +#define MT6358_PSEQ_ELR2 0xa54 +#define MT6358_PSEQ_ELR3 0xa56 +#define MT6358_PSEQ_ELR4 0xa58 +#define MT6358_PSEQ_ELR5 0xa5a +#define MT6358_PSEQ_ELR6 0xa5c +#define MT6358_PSEQ_ELR7 0xa5e +#define MT6358_PSEQ_ELR10 0xa60 +#define MT6358_PSEQ_ELR11 0xa62 +#define MT6358_CHRDET_ID 0xa80 +#define MT6358_CHRDET_REV0 0xa82 +#define MT6358_CHRDET_DBI 0xa84 +#define MT6358_CHRDET_DXI 0xa86 +#define MT6358_CHR_CON0 0xa88 +#define MT6358_CHR_CON1 0xa8a +#define MT6358_CHR_CON2 0xa8c +#define MT6358_CHR_CON3 0xa8e +#define MT6358_CHR_CON4 0xa90 +#define MT6358_PCHR_VREF_ANA_DA0 0xa92 +#define MT6358_PCHR_VREF_ANA_CON0 0xa94 +#define MT6358_PCHR_VREF_ANA_CON1 0xa96 +#define MT6358_PCHR_VREF_ANA_CON2 0xa98 +#define MT6358_PCHR_VREF_ANA_CON3 0xa9a +#define MT6358_PCHR_VREF_ELR_NUM 0xa9c +#define MT6358_PCHR_VREF_ELR_0 0xa9e +#define MT6358_PCHR_VREF_ELR_1 0xaa0 +#define MT6358_BM_TOP_DSN_ID 0xc00 +#define MT6358_BM_TOP_DSN_REV0 0xc02 +#define MT6358_BM_TOP_DBI 0xc04 +#define MT6358_BM_TOP_DXI 0xc06 +#define MT6358_BM_TPM0 0xc08 +#define MT6358_BM_TPM1 0xc0a +#define MT6358_BM_TOP_CKPDN_CON0 0xc0c +#define MT6358_BM_TOP_CKPDN_CON0_SET 0xc0e +#define MT6358_BM_TOP_CKPDN_CON0_CLR 0xc10 +#define MT6358_BM_TOP_CKSEL_CON0 0xc12 +#define MT6358_BM_TOP_CKSEL_CON0_SET 0xc14 +#define MT6358_BM_TOP_CKSEL_CON0_CLR 0xc16 +#define MT6358_BM_TOP_CKDIVSEL_CON0 0xc18 +#define MT6358_BM_TOP_CKDIVSEL_CON0_SET 0xc1a +#define MT6358_BM_TOP_CKDIVSEL_CON0_CLR 0xc1c +#define MT6358_BM_TOP_CKHWEN_CON0 0xc1e +#define MT6358_BM_TOP_CKHWEN_CON0_SET 0xc20 +#define MT6358_BM_TOP_CKHWEN_CON0_CLR 0xc22 +#define MT6358_BM_TOP_CKTST_CON0 0xc24 +#define MT6358_BM_TOP_RST_CON0 0xc26 +#define MT6358_BM_TOP_RST_CON0_SET 0xc28 +#define MT6358_BM_TOP_RST_CON0_CLR 0xc2a +#define MT6358_BM_TOP_RST_CON1 0xc2c +#define MT6358_BM_TOP_RST_CON1_SET 0xc2e +#define MT6358_BM_TOP_RST_CON1_CLR 0xc30 +#define MT6358_BM_TOP_INT_CON0 0xc32 +#define MT6358_BM_TOP_INT_CON0_SET 0xc34 +#define MT6358_BM_TOP_INT_CON0_CLR 0xc36 +#define MT6358_BM_TOP_INT_CON1 0xc38 +#define MT6358_BM_TOP_INT_CON1_SET 0xc3a +#define MT6358_BM_TOP_INT_CON1_CLR 0xc3c +#define MT6358_BM_TOP_INT_MASK_CON0 0xc3e +#define MT6358_BM_TOP_INT_MASK_CON0_SET 0xc40 +#define MT6358_BM_TOP_INT_MASK_CON0_CLR 0xc42 +#define MT6358_BM_TOP_INT_MASK_CON1 0xc44 +#define MT6358_BM_TOP_INT_MASK_CON1_SET 0xc46 +#define MT6358_BM_TOP_INT_MASK_CON1_CLR 0xc48 +#define MT6358_BM_TOP_INT_STATUS0 0xc4a +#define MT6358_BM_TOP_INT_STATUS1 0xc4c +#define MT6358_BM_TOP_INT_RAW_STATUS0 0xc4e +#define MT6358_BM_TOP_INT_RAW_STATUS1 0xc50 +#define MT6358_BM_TOP_INT_MISC_CON 0xc52 +#define MT6358_BM_TOP_DBG_CON 0xc54 +#define MT6358_BM_TOP_RSV0 0xc56 +#define MT6358_FGADC_ANA_DSN_ID 0xc80 +#define MT6358_FGADC_ANA_DSN_REV0 0xc82 +#define MT6358_FGADC_ANA_DSN_DBI 0xc84 +#define MT6358_FGADC_ANA_DSN_DXI 0xc86 +#define MT6358_FGADC_ANA_CON0 0xc88 +#define MT6358_FGADC_ANA_TEST_CON0 0xc8a +#define MT6358_FGADC_ANA_ELR_NUM 0xc8c +#define MT6358_FGADC_ANA_ELR0 0xc8e +#define MT6358_FGADC_ANA_ELR1 0xc90 +#define MT6358_FGADC0_DSN_ID 0xd00 +#define MT6358_FGADC0_DSN_REV0 0xd02 +#define MT6358_FGADC0_DSN_DBI 0xd04 +#define MT6358_FGADC0_DSN_DXI 0xd06 +#define MT6358_FGADC_CON0 0xd08 +#define MT6358_FGADC_CON1 0xd0a +#define MT6358_FGADC_CON2 0xd0c +#define MT6358_FGADC_CON3 0xd0e +#define MT6358_FGADC_CON4 0xd10 +#define MT6358_FGADC_RST_CON0 0xd12 +#define MT6358_FGADC_CAR_CON0 0xd14 +#define MT6358_FGADC_CAR_CON1 0xd16 +#define MT6358_FGADC_CARTH_CON0 0xd18 +#define MT6358_FGADC_CARTH_CON1 0xd1a +#define MT6358_FGADC_CARTH_CON2 0xd1c +#define MT6358_FGADC_CARTH_CON3 0xd1e +#define MT6358_FGADC_CARTH_CON4 0xd20 +#define MT6358_FGADC_CARTH_CON5 0xd22 +#define MT6358_FGADC_CARTH_CON6 0xd24 +#define MT6358_FGADC_CARTH_CON7 0xd26 +#define MT6358_FGADC_NCAR_CON0 0xd28 +#define MT6358_FGADC_NCAR_CON1 0xd2a +#define MT6358_FGADC_NCAR_CON2 0xd2c +#define MT6358_FGADC_NCAR_CON3 0xd2e +#define MT6358_FGADC_IAVG_CON0 0xd30 +#define MT6358_FGADC_IAVG_CON1 0xd32 +#define MT6358_FGADC_IAVG_CON2 0xd34 +#define MT6358_FGADC_IAVG_CON3 0xd36 +#define MT6358_FGADC_IAVG_CON4 0xd38 +#define MT6358_FGADC_IAVG_CON5 0xd3a +#define MT6358_FGADC_NTER_CON0 0xd3c +#define MT6358_FGADC_NTER_CON1 0xd3e +#define MT6358_FGADC_NTERTH_CON0 0xd40 +#define MT6358_FGADC_NTERTH_CON1 0xd42 +#define MT6358_FGADC_SON_CON0 0xd44 +#define MT6358_FGADC_SON_CON1 0xd46 +#define MT6358_FGADC_SON_CON2 0xd48 +#define MT6358_FGADC_SON_CON3 0xd4a +#define MT6358_FGADC_SOFF_CON0 0xd4c +#define MT6358_FGADC_SOFF_CON1 0xd4e +#define MT6358_FGADC_SOFF_CON2 0xd50 +#define MT6358_FGADC_SOFF_CON3 0xd52 +#define MT6358_FGADC_SOFF_CON4 0xd54 +#define MT6358_FGADC_PWR_CON0 0xd56 +#define MT6358_FGADC_PWR_CON1 0xd58 +#define MT6358_FGADC_ZCV_CON0 0xd5a +#define MT6358_FGADC_ZCV_CON1 0xd5c +#define MT6358_FGADC_ZCV_CON2 0xd5e +#define MT6358_FGADC_ZCV_CON3 0xd60 +#define MT6358_FGADC_ZCVTH_CON0 0xd62 +#define MT6358_FGADC_ZCVTH_CON1 0xd64 +#define MT6358_FGADC1_DSN_ID 0xd80 +#define MT6358_FGADC1_DSN_REV0 0xd82 +#define MT6358_FGADC1_DSN_DBI 0xd84 +#define MT6358_FGADC1_DSN_DXI 0xd86 +#define MT6358_FGADC_R_CON0 0xd88 +#define MT6358_FGADC_CUR_CON0 0xd8a +#define MT6358_FGADC_CUR_CON1 0xd8c +#define MT6358_FGADC_CUR_CON2 0xd8e +#define MT6358_FGADC_CUR_CON3 0xd90 +#define MT6358_FGADC_OFFSET_CON0 0xd92 +#define MT6358_FGADC_OFFSET_CON1 0xd94 +#define MT6358_FGADC_GAIN_CON0 0xd96 +#define MT6358_FGADC_TEST_CON0 0xd98 +#define MT6358_SYSTEM_INFO_CON0 0xd9a +#define MT6358_BATON_ANA_DSN_ID 0xe00 +#define MT6358_BATON_ANA_DSN_REV0 0xe02 +#define MT6358_BATON_ANA_DSN_DBI 0xe04 +#define MT6358_BATON_ANA_DSN_DXI 0xe06 +#define MT6358_BATON_ANA_CON0 0xe08 +#define MT6358_BATON_ANA_MON0 0xe0a +#define MT6358_BIF_ANA_MON0 0xe0c +#define MT6358_BATON_ANA_ELR_NUM 0xe0e +#define MT6358_BATON_ANA_ELR0 0xe10 +#define MT6358_BATON_DSN_ID 0xe80 +#define MT6358_BATON_DSN_REV0 0xe82 +#define MT6358_BATON_DSN_DBI 0xe84 +#define MT6358_BATON_DSN_DXI 0xe86 +#define MT6358_BATON_CON0 0xe88 +#define MT6358_BATON_CON1 0xe8a +#define MT6358_BATON_CON2 0xe8c +#define MT6358_BATON_CON3 0xe8e +#define MT6358_BATON_ELR_NUM 0xe90 +#define MT6358_BATON_ELR0 0xe92 +#define MT6358_BIF_DSN_ID 0xf00 +#define MT6358_BIF_DSN_REV0 0xf02 +#define MT6358_BIF_DSN_DBI 0xf04 +#define MT6358_BIF_DSN_DXI 0xf06 +#define MT6358_BIF_CON0 0xf08 +#define MT6358_BIF_CON1 0xf0a +#define MT6358_BIF_CON2 0xf0c +#define MT6358_BIF_CON3 0xf0e +#define MT6358_BIF_CON4 0xf10 +#define MT6358_BIF_CON5 0xf12 +#define MT6358_BIF_CON6 0xf14 +#define MT6358_BIF_CON7 0xf16 +#define MT6358_BIF_CON8 0xf18 +#define MT6358_BIF_CON9 0xf1a +#define MT6358_BIF_CON10 0xf1c +#define MT6358_BIF_CON11 0xf1e +#define MT6358_BIF_CON12 0xf20 +#define MT6358_BIF_CON13 0xf22 +#define MT6358_BIF_CON14 0xf24 +#define MT6358_BIF_CON15 0xf26 +#define MT6358_BIF_CON16 0xf28 +#define MT6358_BIF_CON17 0xf2a +#define MT6358_BIF_CON18 0xf2c +#define MT6358_BIF_CON19 0xf2e +#define MT6358_BIF_CON20 0xf30 +#define MT6358_BIF_CON21 0xf32 +#define MT6358_BIF_CON22 0xf34 +#define MT6358_BIF_CON23 0xf36 +#define MT6358_BIF_CON24 0xf38 +#define MT6358_BIF_CON25 0xf3a +#define MT6358_BIF_CON26 0xf3c +#define MT6358_BIF_CON27 0xf3e +#define MT6358_BIF_CON28 0xf40 +#define MT6358_BIF_CON29 0xf42 +#define MT6358_BIF_CON30 0xf44 +#define MT6358_BIF_CON31 0xf46 +#define MT6358_BIF_CON32 0xf48 +#define MT6358_BIF_CON33 0xf4a +#define MT6358_BIF_CON34 0xf4c +#define MT6358_BIF_CON35 0xf4e +#define MT6358_BIF_CON36 0xf50 +#define MT6358_BIF_CON37 0xf52 +#define MT6358_BIF_CON38 0xf54 +#define MT6358_BIF_CON39 0xf56 +#define MT6358_HK_TOP_ID 0xf80 +#define MT6358_HK_TOP_REV0 0xf82 +#define MT6358_HK_TOP_DBI 0xf84 +#define MT6358_HK_TOP_DXI 0xf86 +#define MT6358_HK_TPM0 0xf88 +#define MT6358_HK_TPM1 0xf8a +#define MT6358_HK_TOP_CLK_CON0 0xf8c +#define MT6358_HK_TOP_CLK_CON1 0xf8e +#define MT6358_HK_TOP_RST_CON0 0xf90 +#define MT6358_HK_TOP_INT_CON0 0xf92 +#define MT6358_HK_TOP_INT_CON0_SET 0xf94 +#define MT6358_HK_TOP_INT_CON0_CLR 0xf96 +#define MT6358_HK_TOP_INT_MASK_CON0 0xf98 +#define MT6358_HK_TOP_INT_MASK_CON0_SET 0xf9a +#define MT6358_HK_TOP_INT_MASK_CON0_CLR 0xf9c +#define MT6358_HK_TOP_INT_STATUS0 0xf9e +#define MT6358_HK_TOP_INT_RAW_STATUS0 0xfa0 +#define MT6358_HK_TOP_MON_CON0 0xfa2 +#define MT6358_HK_TOP_MON_CON1 0xfa4 +#define MT6358_HK_TOP_MON_CON2 0xfa6 +#define MT6358_HK_TOP_CHR_CON 0xfa8 +#define MT6358_HK_TOP_AUXADC_ANA 0xfaa +#define MT6358_AUXADC_DSN_ID 0x1000 +#define MT6358_AUXADC_DSN_REV0 0x1002 +#define MT6358_AUXADC_DSN_DBI 0x1004 +#define MT6358_AUXADC_DSN_FPI 0x1006 +#define MT6358_AUXADC_ANA_CON0 0x1008 +#define MT6358_AUXADC_DIG_1_DSN_ID 0x1080 +#define MT6358_AUXADC_DIG_1_DSN_REV0 0x1082 +#define MT6358_AUXADC_DIG_1_DSN_DBI 0x1084 +#define MT6358_AUXADC_DIG_1_DSN_DXI 0x1086 +#define MT6358_AUXADC_ADC0 0x1088 +#define MT6358_AUXADC_ADC1 0x108a +#define MT6358_AUXADC_ADC2 0x108c +#define MT6358_AUXADC_ADC3 0x108e +#define MT6358_AUXADC_ADC4 0x1090 +#define MT6358_AUXADC_ADC5 0x1092 +#define MT6358_AUXADC_ADC6 0x1094 +#define MT6358_AUXADC_ADC7 0x1096 +#define MT6358_AUXADC_ADC8 0x1098 +#define MT6358_AUXADC_ADC9 0x109a +#define MT6358_AUXADC_ADC10 0x109c +#define MT6358_AUXADC_ADC11 0x109e +#define MT6358_AUXADC_ADC12 0x10a0 +#define MT6358_AUXADC_ADC13 0x10a2 +#define MT6358_AUXADC_ADC14 0x10a4 +#define MT6358_AUXADC_ADC15 0x10a6 +#define MT6358_AUXADC_ADC16 0x10a8 +#define MT6358_AUXADC_ADC17 0x10aa +#define MT6358_AUXADC_ADC18 0x10ac +#define MT6358_AUXADC_ADC19 0x10ae +#define MT6358_AUXADC_ADC20 0x10b0 +#define MT6358_AUXADC_ADC21 0x10b2 +#define MT6358_AUXADC_ADC22 0x10b4 +#define MT6358_AUXADC_ADC23 0x10b6 +#define MT6358_AUXADC_ADC24 0x10b8 +#define MT6358_AUXADC_ADC25 0x10ba +#define MT6358_AUXADC_ADC26 0x10bc +#define MT6358_AUXADC_ADC27 0x10be +#define MT6358_AUXADC_ADC28 0x10c0 +#define MT6358_AUXADC_ADC29 0x10c2 +#define MT6358_AUXADC_ADC30 0x10c4 +#define MT6358_AUXADC_ADC31 0x10c6 +#define MT6358_AUXADC_ADC32 0x10c8 +#define MT6358_AUXADC_ADC33 0x10ca +#define MT6358_AUXADC_ADC34 0x10cc +#define MT6358_AUXADC_ADC35 0x10ce +#define MT6358_AUXADC_ADC36 0x10d0 +#define MT6358_AUXADC_ADC37 0x10d2 +#define MT6358_AUXADC_ADC38 0x10d4 +#define MT6358_AUXADC_ADC39 0x10d6 +#define MT6358_AUXADC_ADC40 0x10d8 +#define MT6358_AUXADC_STA0 0x10da +#define MT6358_AUXADC_STA1 0x10dc +#define MT6358_AUXADC_STA2 0x10de +#define MT6358_AUXADC_DIG_2_DSN_ID 0x1100 +#define MT6358_AUXADC_DIG_2_DSN_REV0 0x1102 +#define MT6358_AUXADC_DIG_2_DSN_DBI 0x1104 +#define MT6358_AUXADC_DIG_2_DSN_DXI 0x1106 +#define MT6358_AUXADC_RQST0 0x1108 +#define MT6358_AUXADC_RQST1 0x110a +#define MT6358_AUXADC_DIG_3_DSN_ID 0x1180 +#define MT6358_AUXADC_DIG_3_DSN_REV0 0x1182 +#define MT6358_AUXADC_DIG_3_DSN_DBI 0x1184 +#define MT6358_AUXADC_DIG_3_DSN_DXI 0x1186 +#define MT6358_AUXADC_CON0 0x1188 +#define MT6358_AUXADC_CON0_SET 0x118a +#define MT6358_AUXADC_CON0_CLR 0x118c +#define MT6358_AUXADC_CON1 0x118e +#define MT6358_AUXADC_CON2 0x1190 +#define MT6358_AUXADC_CON3 0x1192 +#define MT6358_AUXADC_CON4 0x1194 +#define MT6358_AUXADC_CON5 0x1196 +#define MT6358_AUXADC_CON6 0x1198 +#define MT6358_AUXADC_CON7 0x119a +#define MT6358_AUXADC_CON8 0x119c +#define MT6358_AUXADC_CON9 0x119e +#define MT6358_AUXADC_CON10 0x11a0 +#define MT6358_AUXADC_CON11 0x11a2 +#define MT6358_AUXADC_CON12 0x11a4 +#define MT6358_AUXADC_CON13 0x11a6 +#define MT6358_AUXADC_CON14 0x11a8 +#define MT6358_AUXADC_CON15 0x11aa +#define MT6358_AUXADC_CON16 0x11ac +#define MT6358_AUXADC_CON17 0x11ae +#define MT6358_AUXADC_CON18 0x11b0 +#define MT6358_AUXADC_CON19 0x11b2 +#define MT6358_AUXADC_CON20 0x11b4 +#define MT6358_AUXADC_AUTORPT0 0x11b6 +#define MT6358_AUXADC_ACCDET 0x11b8 +#define MT6358_AUXADC_DBG0 0x11ba +#define MT6358_AUXADC_DIG_3_ELR_NUM 0x11bc +#define MT6358_AUXADC_DIG_3_ELR0 0x11be +#define MT6358_AUXADC_DIG_3_ELR1 0x11c0 +#define MT6358_AUXADC_DIG_3_ELR2 0x11c2 +#define MT6358_AUXADC_DIG_3_ELR3 0x11c4 +#define MT6358_AUXADC_DIG_3_ELR4 0x11c6 +#define MT6358_AUXADC_DIG_3_ELR5 0x11c8 +#define MT6358_AUXADC_DIG_3_ELR6 0x11ca +#define MT6358_AUXADC_DIG_3_ELR7 0x11cc +#define MT6358_AUXADC_DIG_3_ELR8 0x11ce +#define MT6358_AUXADC_DIG_3_ELR9 0x11d0 +#define MT6358_AUXADC_DIG_3_ELR10 0x11d2 +#define MT6358_AUXADC_DIG_3_ELR11 0x11d4 +#define MT6358_AUXADC_DIG_3_ELR12 0x11d6 +#define MT6358_AUXADC_DIG_3_ELR13 0x11d8 +#define MT6358_AUXADC_DIG_4_DSN_ID 0x1200 +#define MT6358_AUXADC_DIG_4_DSN_REV0 0x1202 +#define MT6358_AUXADC_DIG_4_DSN_DBI 0x1204 +#define MT6358_AUXADC_DIG_4_DSN_DXI 0x1206 +#define MT6358_AUXADC_IMP0 0x1208 +#define MT6358_AUXADC_IMP1 0x120a +#define MT6358_AUXADC_IMP2 0x120c +#define MT6358_AUXADC_LBAT0 0x120e +#define MT6358_AUXADC_LBAT1 0x1210 +#define MT6358_AUXADC_LBAT2 0x1212 +#define MT6358_AUXADC_LBAT3 0x1214 +#define MT6358_AUXADC_LBAT4 0x1216 +#define MT6358_AUXADC_LBAT5 0x1218 +#define MT6358_AUXADC_LBAT6 0x121a +#define MT6358_AUXADC_BAT_TEMP_0 0x121c +#define MT6358_AUXADC_BAT_TEMP_1 0x121e +#define MT6358_AUXADC_BAT_TEMP_2 0x1220 +#define MT6358_AUXADC_BAT_TEMP_3 0x1222 +#define MT6358_AUXADC_BAT_TEMP_4 0x1224 +#define MT6358_AUXADC_BAT_TEMP_5 0x1226 +#define MT6358_AUXADC_BAT_TEMP_6 0x1228 +#define MT6358_AUXADC_BAT_TEMP_7 0x122a +#define MT6358_AUXADC_LBAT2_1 0x122c +#define MT6358_AUXADC_LBAT2_2 0x122e +#define MT6358_AUXADC_LBAT2_3 0x1230 +#define MT6358_AUXADC_LBAT2_4 0x1232 +#define MT6358_AUXADC_LBAT2_5 0x1234 +#define MT6358_AUXADC_LBAT2_6 0x1236 +#define MT6358_AUXADC_LBAT2_7 0x1238 +#define MT6358_AUXADC_MDRT_0 0x123a +#define MT6358_AUXADC_MDRT_1 0x123c +#define MT6358_AUXADC_MDRT_2 0x123e +#define MT6358_AUXADC_MDRT_3 0x1240 +#define MT6358_AUXADC_MDRT_4 0x1242 +#define MT6358_AUXADC_DCXO_MDRT_1 0x1244 +#define MT6358_AUXADC_DCXO_MDRT_2 0x1246 +#define MT6358_AUXADC_NAG_0 0x1248 +#define MT6358_AUXADC_NAG_1 0x124a +#define MT6358_AUXADC_NAG_2 0x124c +#define MT6358_AUXADC_NAG_3 0x124e +#define MT6358_AUXADC_NAG_4 0x1250 +#define MT6358_AUXADC_NAG_5 0x1252 +#define MT6358_AUXADC_NAG_6 0x1254 +#define MT6358_AUXADC_NAG_7 0x1256 +#define MT6358_AUXADC_NAG_8 0x1258 +#define MT6358_AUXADC_NAG_9 0x125a +#define MT6358_AUXADC_RSV_1 0x125c +#define MT6358_AUXADC_PRI_NEW 0x125e +#define MT6358_AUXADC_DCM_CON 0x1260 +#define MT6358_AUXADC_SPL_LIST_0 0x1262 +#define MT6358_AUXADC_SPL_LIST_1 0x1264 +#define MT6358_AUXADC_SPL_LIST_2 0x1266 +#define MT6358_BUCK_TOP_DSN_ID 0x1300 +#define MT6358_BUCK_TOP_DSN_REV0 0x1302 +#define MT6358_BUCK_TOP_DBI 0x1304 +#define MT6358_BUCK_TOP_DXI 0x1306 +#define MT6358_BUCK_TOP_PAM0 0x1308 +#define MT6358_BUCK_TOP_PAM1 0x130a +#define MT6358_BUCK_TOP_CLK_CON0 0x130c +#define MT6358_BUCK_TOP_CLK_CON0_SET 0x130e +#define MT6358_BUCK_TOP_CLK_CON0_CLR 0x1310 +#define MT6358_BUCK_TOP_CLK_HWEN_CON0 0x1312 +#define MT6358_BUCK_TOP_CLK_HWEN_CON0_SET 0x1314 +#define MT6358_BUCK_TOP_CLK_HWEN_CON0_CLR 0x1316 +#define MT6358_BUCK_TOP_INT_CON0 0x1318 +#define MT6358_BUCK_TOP_INT_CON0_SET 0x131a +#define MT6358_BUCK_TOP_INT_CON0_CLR 0x131c +#define MT6358_BUCK_TOP_INT_MASK_CON0 0x131e +#define MT6358_BUCK_TOP_INT_MASK_CON0_SET 0x1320 +#define MT6358_BUCK_TOP_INT_MASK_CON0_CLR 0x1322 +#define MT6358_BUCK_TOP_INT_STATUS0 0x1324 +#define MT6358_BUCK_TOP_INT_RAW_STATUS0 0x1326 +#define MT6358_BUCK_TOP_STB_CON 0x1328 +#define MT6358_BUCK_TOP_SLP_CON0 0x132a +#define MT6358_BUCK_TOP_SLP_CON1 0x132c +#define MT6358_BUCK_TOP_SLP_CON2 0x132e +#define MT6358_BUCK_TOP_MINFREQ_CON 0x1330 +#define MT6358_BUCK_TOP_OC_CON0 0x1332 +#define MT6358_BUCK_TOP_K_CON0 0x1334 +#define MT6358_BUCK_TOP_K_CON1 0x1336 +#define MT6358_BUCK_TOP_K_CON2 0x1338 +#define MT6358_BUCK_TOP_WDTDBG0 0x133a +#define MT6358_BUCK_TOP_WDTDBG1 0x133c +#define MT6358_BUCK_TOP_WDTDBG2 0x133e +#define MT6358_BUCK_TOP_WDTDBG3 0x1340 +#define MT6358_BUCK_TOP_WDTDBG4 0x1342 +#define MT6358_BUCK_TOP_ELR_NUM 0x1344 +#define MT6358_BUCK_TOP_ELR0 0x1346 +#define MT6358_BUCK_TOP_ELR1 0x1348 +#define MT6358_BUCK_TOP_ELR2 0x134a +#define MT6358_BUCK_TOP_ELR3 0x134c +#define MT6358_BUCK_VPROC11_DSN_ID 0x1380 +#define MT6358_BUCK_VPROC11_DSN_REV0 0x1382 +#define MT6358_BUCK_VPROC11_DSN_DBI 0x1384 +#define MT6358_BUCK_VPROC11_DSN_DXI 0x1386 +#define MT6358_BUCK_VPROC11_CON0 0x1388 +#define MT6358_BUCK_VPROC11_CON1 0x138a +#define MT6358_BUCK_VPROC11_CFG0 0x138c +#define MT6358_BUCK_VPROC11_CFG1 0x138e +#define MT6358_BUCK_VPROC11_OP_EN 0x1390 +#define MT6358_BUCK_VPROC11_OP_EN_SET 0x1392 +#define MT6358_BUCK_VPROC11_OP_EN_CLR 0x1394 +#define MT6358_BUCK_VPROC11_OP_CFG 0x1396 +#define MT6358_BUCK_VPROC11_OP_CFG_SET 0x1398 +#define MT6358_BUCK_VPROC11_OP_CFG_CLR 0x139a +#define MT6358_BUCK_VPROC11_OC_CFG 0x139c +#define MT6358_BUCK_VPROC11_DBG0 0x139e +#define MT6358_BUCK_VPROC11_DBG1 0x13a0 +#define MT6358_BUCK_VPROC11_DBG2 0x13a2 +#define MT6358_BUCK_VPROC11_ELR_NUM 0x13a4 +#define MT6358_BUCK_VPROC11_ELR0 0x13a6 +#define MT6358_BUCK_VPROC12_DSN_ID 0x1400 +#define MT6358_BUCK_VPROC12_DSN_REV0 0x1402 +#define MT6358_BUCK_VPROC12_DSN_DBI 0x1404 +#define MT6358_BUCK_VPROC12_DSN_DXI 0x1406 +#define MT6358_BUCK_VPROC12_CON0 0x1408 +#define MT6358_BUCK_VPROC12_CON1 0x140a +#define MT6358_BUCK_VPROC12_CFG0 0x140c +#define MT6358_BUCK_VPROC12_CFG1 0x140e +#define MT6358_BUCK_VPROC12_OP_EN 0x1410 +#define MT6358_BUCK_VPROC12_OP_EN_SET 0x1412 +#define MT6358_BUCK_VPROC12_OP_EN_CLR 0x1414 +#define MT6358_BUCK_VPROC12_OP_CFG 0x1416 +#define MT6358_BUCK_VPROC12_OP_CFG_SET 0x1418 +#define MT6358_BUCK_VPROC12_OP_CFG_CLR 0x141a +#define MT6358_BUCK_VPROC12_OC_CFG 0x141c +#define MT6358_BUCK_VPROC12_DBG0 0x141e +#define MT6358_BUCK_VPROC12_DBG1 0x1420 +#define MT6358_BUCK_VPROC12_DBG2 0x1422 +#define MT6358_BUCK_VPROC12_ELR_NUM 0x1424 +#define MT6358_BUCK_VPROC12_ELR0 0x1426 +#define MT6358_BUCK_VCORE_DSN_ID 0x1480 +#define MT6358_BUCK_VCORE_DSN_REV0 0x1482 +#define MT6358_BUCK_VCORE_DSN_DBI 0x1484 +#define MT6358_BUCK_VCORE_DSN_DXI 0x1486 +#define MT6358_BUCK_VCORE_CON0 0x1488 +#define MT6358_BUCK_VCORE_CON1 0x148a +#define MT6358_BUCK_VCORE_CFG0 0x148c +#define MT6358_BUCK_VCORE_CFG1 0x148e +#define MT6358_BUCK_VCORE_OP_EN 0x1490 +#define MT6358_BUCK_VCORE_OP_EN_SET 0x1492 +#define MT6358_BUCK_VCORE_OP_EN_CLR 0x1494 +#define MT6358_BUCK_VCORE_OP_CFG 0x1496 +#define MT6358_BUCK_VCORE_OP_CFG_SET 0x1498 +#define MT6358_BUCK_VCORE_OP_CFG_CLR 0x149a +#define MT6358_BUCK_VCORE_OC_CFG 0x149c +#define MT6358_BUCK_VCORE_DBG0 0x149e +#define MT6358_BUCK_VCORE_DBG1 0x14a0 +#define MT6358_BUCK_VCORE_DBG2 0x14a2 +#define MT6358_BUCK_VCORE_SSHUB_CON0 0x14a4 +#define MT6358_BUCK_VCORE_SSHUB_CON1 0x14a6 +#define MT6358_BUCK_VCORE_ELR_NUM 0x14a8 +#define MT6358_BUCK_VCORE_ELR0 0x14aa +#define MT6358_BUCK_VGPU_DSN_ID 0x1500 +#define MT6358_BUCK_VGPU_DSN_REV0 0x1502 +#define MT6358_BUCK_VGPU_DSN_DBI 0x1504 +#define MT6358_BUCK_VGPU_DSN_DXI 0x1506 +#define MT6358_BUCK_VGPU_CON0 0x1508 +#define MT6358_BUCK_VGPU_CON1 0x150a +#define MT6358_BUCK_VGPU_CFG0 0x150c +#define MT6358_BUCK_VGPU_CFG1 0x150e +#define MT6358_BUCK_VGPU_OP_EN 0x1510 +#define MT6358_BUCK_VGPU_OP_EN_SET 0x1512 +#define MT6358_BUCK_VGPU_OP_EN_CLR 0x1514 +#define MT6358_BUCK_VGPU_OP_CFG 0x1516 +#define MT6358_BUCK_VGPU_OP_CFG_SET 0x1518 +#define MT6358_BUCK_VGPU_OP_CFG_CLR 0x151a +#define MT6358_BUCK_VGPU_OC_CFG 0x151c +#define MT6358_BUCK_VGPU_DBG0 0x151e +#define MT6358_BUCK_VGPU_DBG1 0x1520 +#define MT6358_BUCK_VGPU_DBG2 0x1522 +#define MT6358_BUCK_VGPU_ELR_NUM 0x1524 +#define MT6358_BUCK_VGPU_ELR0 0x1526 +#define MT6358_BUCK_VMODEM_DSN_ID 0x1580 +#define MT6358_BUCK_VMODEM_DSN_REV0 0x1582 +#define MT6358_BUCK_VMODEM_DSN_DBI 0x1584 +#define MT6358_BUCK_VMODEM_DSN_DXI 0x1586 +#define MT6358_BUCK_VMODEM_CON0 0x1588 +#define MT6358_BUCK_VMODEM_CON1 0x158a +#define MT6358_BUCK_VMODEM_CFG0 0x158c +#define MT6358_BUCK_VMODEM_CFG1 0x158e +#define MT6358_BUCK_VMODEM_OP_EN 0x1590 +#define MT6358_BUCK_VMODEM_OP_EN_SET 0x1592 +#define MT6358_BUCK_VMODEM_OP_EN_CLR 0x1594 +#define MT6358_BUCK_VMODEM_OP_CFG 0x1596 +#define MT6358_BUCK_VMODEM_OP_CFG_SET 0x1598 +#define MT6358_BUCK_VMODEM_OP_CFG_CLR 0x159a +#define MT6358_BUCK_VMODEM_OC_CFG 0x159c +#define MT6358_BUCK_VMODEM_DBG0 0x159e +#define MT6358_BUCK_VMODEM_DBG1 0x15a0 +#define MT6358_BUCK_VMODEM_DBG2 0x15a2 +#define MT6358_BUCK_VMODEM_ELR_NUM 0x15a4 +#define MT6358_BUCK_VMODEM_ELR0 0x15a6 +#define MT6358_BUCK_VDRAM1_DSN_ID 0x1600 +#define MT6358_BUCK_VDRAM1_DSN_REV0 0x1602 +#define MT6358_BUCK_VDRAM1_DSN_DBI 0x1604 +#define MT6358_BUCK_VDRAM1_DSN_DXI 0x1606 +#define MT6358_BUCK_VDRAM1_CON0 0x1608 +#define MT6358_BUCK_VDRAM1_CON1 0x160a +#define MT6358_BUCK_VDRAM1_CFG0 0x160c +#define MT6358_BUCK_VDRAM1_CFG1 0x160e +#define MT6358_BUCK_VDRAM1_OP_EN 0x1610 +#define MT6358_BUCK_VDRAM1_OP_EN_SET 0x1612 +#define MT6358_BUCK_VDRAM1_OP_EN_CLR 0x1614 +#define MT6358_BUCK_VDRAM1_OP_CFG 0x1616 +#define MT6358_BUCK_VDRAM1_OP_CFG_SET 0x1618 +#define MT6358_BUCK_VDRAM1_OP_CFG_CLR 0x161a +#define MT6358_BUCK_VDRAM1_OC_CFG 0x161c +#define MT6358_BUCK_VDRAM1_DBG0 0x161e +#define MT6358_BUCK_VDRAM1_DBG1 0x1620 +#define MT6358_BUCK_VDRAM1_DBG2 0x1622 +#define MT6358_BUCK_VDRAM1_ELR_NUM 0x1624 +#define MT6358_BUCK_VDRAM1_ELR0 0x1626 +#define MT6358_BUCK_VS1_DSN_ID 0x1680 +#define MT6358_BUCK_VS1_DSN_REV0 0x1682 +#define MT6358_BUCK_VS1_DSN_DBI 0x1684 +#define MT6358_BUCK_VS1_DSN_DXI 0x1686 +#define MT6358_BUCK_VS1_CON0 0x1688 +#define MT6358_BUCK_VS1_CON1 0x168a +#define MT6358_BUCK_VS1_CFG0 0x168c +#define MT6358_BUCK_VS1_CFG1 0x168e +#define MT6358_BUCK_VS1_OP_EN 0x1690 +#define MT6358_BUCK_VS1_OP_EN_SET 0x1692 +#define MT6358_BUCK_VS1_OP_EN_CLR 0x1694 +#define MT6358_BUCK_VS1_OP_CFG 0x1696 +#define MT6358_BUCK_VS1_OP_CFG_SET 0x1698 +#define MT6358_BUCK_VS1_OP_CFG_CLR 0x169a +#define MT6358_BUCK_VS1_OC_CFG 0x169c +#define MT6358_BUCK_VS1_DBG0 0x169e +#define MT6358_BUCK_VS1_DBG1 0x16a0 +#define MT6358_BUCK_VS1_DBG2 0x16a2 +#define MT6358_BUCK_VS1_VOTER 0x16a4 +#define MT6358_BUCK_VS1_VOTER_SET 0x16a6 +#define MT6358_BUCK_VS1_VOTER_CLR 0x16a8 +#define MT6358_BUCK_VS1_VOTER_CFG 0x16aa +#define MT6358_BUCK_VS1_ELR_NUM 0x16ac +#define MT6358_BUCK_VS1_ELR0 0x16ae +#define MT6358_BUCK_VS2_DSN_ID 0x1700 +#define MT6358_BUCK_VS2_DSN_REV0 0x1702 +#define MT6358_BUCK_VS2_DSN_DBI 0x1704 +#define MT6358_BUCK_VS2_DSN_DXI 0x1706 +#define MT6358_BUCK_VS2_CON0 0x1708 +#define MT6358_BUCK_VS2_CON1 0x170a +#define MT6358_BUCK_VS2_CFG0 0x170c +#define MT6358_BUCK_VS2_CFG1 0x170e +#define MT6358_BUCK_VS2_OP_EN 0x1710 +#define MT6358_BUCK_VS2_OP_EN_SET 0x1712 +#define MT6358_BUCK_VS2_OP_EN_CLR 0x1714 +#define MT6358_BUCK_VS2_OP_CFG 0x1716 +#define MT6358_BUCK_VS2_OP_CFG_SET 0x1718 +#define MT6358_BUCK_VS2_OP_CFG_CLR 0x171a +#define MT6358_BUCK_VS2_OC_CFG 0x171c +#define MT6358_BUCK_VS2_DBG0 0x171e +#define MT6358_BUCK_VS2_DBG1 0x1720 +#define MT6358_BUCK_VS2_DBG2 0x1722 +#define MT6358_BUCK_VS2_VOTER 0x1724 +#define MT6358_BUCK_VS2_VOTER_SET 0x1726 +#define MT6358_BUCK_VS2_VOTER_CLR 0x1728 +#define MT6358_BUCK_VS2_VOTER_CFG 0x172a +#define MT6358_BUCK_VS2_ELR_NUM 0x172c +#define MT6358_BUCK_VS2_ELR0 0x172e +#define MT6358_BUCK_VPA_DSN_ID 0x1780 +#define MT6358_BUCK_VPA_DSN_REV0 0x1782 +#define MT6358_BUCK_VPA_DSN_DBI 0x1784 +#define MT6358_BUCK_VPA_DSN_DXI 0x1786 +#define MT6358_BUCK_VPA_CON0 0x1788 +#define MT6358_BUCK_VPA_CON1 0x178a +#define MT6358_BUCK_VPA_ELR0 MT6358_BUCK_VPA_CON1 +#define MT6358_BUCK_VPA_CFG0 0x178c +#define MT6358_BUCK_VPA_CFG1 0x178e +#define MT6358_BUCK_VPA_OC_CFG 0x1790 +#define MT6358_BUCK_VPA_DBG0 0x1792 +#define MT6358_BUCK_VPA_DBG1 0x1794 +#define MT6358_BUCK_VPA_DBG2 0x1796 +#define MT6358_BUCK_VPA_DLC_CON0 0x1798 +#define MT6358_BUCK_VPA_DLC_CON1 0x179a +#define MT6358_BUCK_VPA_DLC_CON2 0x179c +#define MT6358_BUCK_VPA_MSFG_CON0 0x179e +#define MT6358_BUCK_VPA_MSFG_CON1 0x17a0 +#define MT6358_BUCK_VPA_MSFG_RRATE0 0x17a2 +#define MT6358_BUCK_VPA_MSFG_RRATE1 0x17a4 +#define MT6358_BUCK_VPA_MSFG_RRATE2 0x17a6 +#define MT6358_BUCK_VPA_MSFG_RTHD0 0x17a8 +#define MT6358_BUCK_VPA_MSFG_RTHD1 0x17aa +#define MT6358_BUCK_VPA_MSFG_RTHD2 0x17ac +#define MT6358_BUCK_VPA_MSFG_FRATE0 0x17ae +#define MT6358_BUCK_VPA_MSFG_FRATE1 0x17b0 +#define MT6358_BUCK_VPA_MSFG_FRATE2 0x17b2 +#define MT6358_BUCK_VPA_MSFG_FTHD0 0x17b4 +#define MT6358_BUCK_VPA_MSFG_FTHD1 0x17b6 +#define MT6358_BUCK_VPA_MSFG_FTHD2 0x17b8 +#define MT6358_BUCK_ANA0_DSN_ID 0x1800 +#define MT6358_BUCK_ANA0_DSN_REV0 0x1802 +#define MT6358_BUCK_ANA0_DSN_DBI 0x1804 +#define MT6358_BUCK_ANA0_DSN_FPI 0x1806 +#define MT6358_SMPS_ANA_CON0 0x1808 +#define MT6358_SMPS_ANA_CON1 0x180a +#define MT6358_VPROC_ANA_CON0 0x180c +#define MT6358_VPROC_ANA_CON1 0x180e +#define MT6358_VPROC_ANA_CON2 0x1810 +#define MT6358_VPROC_ANA_CON3 0x1812 +#define MT6358_VPROC_ANA_CON4 0x1814 +#define MT6358_VPROC_ANA_CON5 0x1816 +#define MT6358_VPROC_ANA_CON6 0x1818 +#define MT6358_VPROC_ANA_CON7 0x181a +#define MT6358_VPROC_ANA_CON8 0x181c +#define MT6358_VPROC_ANA_CON9 0x181e +#define MT6358_VPROC_ANA_CON10 0x1820 +#define MT6358_VPROC_ANA_CON11 0x1822 +#define MT6358_VPROC_ANA_CON12 0x1824 +#define MT6358_VPROC_ANA_CON13 0x1826 +#define MT6358_VCORE_VGPU_ANA_CON0 0x1828 +#define MT6358_VCORE_VGPU_ANA_CON1 0x182a +#define MT6358_VCORE_VGPU_ANA_CON2 0x182c +#define MT6358_VCORE_VGPU_ANA_CON3 0x182e +#define MT6358_VCORE_VGPU_ANA_CON4 0x1830 +#define MT6358_VCORE_VGPU_ANA_CON5 0x1832 +#define MT6358_VCORE_VGPU_ANA_CON6 0x1834 +#define MT6358_VCORE_VGPU_ANA_CON7 0x1836 +#define MT6358_VCORE_VGPU_ANA_CON8 0x1838 +#define MT6358_VCORE_VGPU_ANA_CON9 0x183a +#define MT6358_VCORE_VGPU_ANA_CON10 0x183c +#define MT6358_VCORE_VGPU_ANA_CON11 0x183e +#define MT6358_VCORE_VGPU_ANA_CON12 0x1840 +#define MT6358_VCORE_VGPU_ANA_CON13 0x1842 +#define MT6358_BUCK_ANA0_ELR_NUM 0x1844 +#define MT6358_SMPS_ELR_0 0x1846 +#define MT6358_SMPS_ELR_1 0x1848 +#define MT6358_SMPS_ELR_2 0x184a +#define MT6358_SMPS_ELR_3 0x184c +#define MT6358_SMPS_ELR_4 0x184e +#define MT6358_SMPS_ELR_5 0x1850 +#define MT6358_VPROC_ELR_0 0x1852 +#define MT6358_VPROC_ELR_1 0x1854 +#define MT6358_VPROC_ELR_2 0x1856 +#define MT6358_VPROC_ELR_3 0x1858 +#define MT6358_VCORE_VGPU_ELR_0 0x185a +#define MT6358_VCORE_VGPU_ELR_1 0x185c +#define MT6358_VCORE_VGPU_ELR_2 0x185e +#define MT6358_VCORE_VGPU_ELR_3 0x1860 +#define MT6358_BUCK_ANA1_DSN_ID 0x1880 +#define MT6358_BUCK_ANA1_DSN_REV0 0x1882 +#define MT6358_BUCK_ANA1_DSN_DBI 0x1884 +#define MT6358_BUCK_ANA1_DSN_FPI 0x1886 +#define MT6358_VMODEM_ANA_CON0 0x1888 +#define MT6358_VMODEM_ANA_CON1 0x188a +#define MT6358_VMODEM_ANA_CON2 0x188c +#define MT6358_VMODEM_ANA_CON3 0x188e +#define MT6358_VMODEM_ANA_CON4 0x1890 +#define MT6358_VMODEM_ANA_CON5 0x1892 +#define MT6358_VMODEM_ANA_CON6 0x1894 +#define MT6358_VDRAM1_ANA_CON0 0x1896 +#define MT6358_VDRAM1_ANA_CON1 0x1898 +#define MT6358_VDRAM1_ANA_CON2 0x189a +#define MT6358_VDRAM1_ANA_CON3 0x189c +#define MT6358_VDRAM1_ANA_CON4 0x189e +#define MT6358_VDRAM1_ANA_CON5 0x18a0 +#define MT6358_VS1_ANA_CON0 0x18a2 +#define MT6358_VS1_ANA_CON1 0x18a4 +#define MT6358_VS1_ANA_CON2 0x18a6 +#define MT6358_VS1_ANA_CON3 0x18a8 +#define MT6358_VS1_ANA_CON4 0x18aa +#define MT6358_VS1_ANA_CON5 0x18ac +#define MT6358_VS2_ANA_CON0 0x18ae +#define MT6358_VS2_ANA_CON1 0x18b0 +#define MT6358_VS2_ANA_CON2 0x18b2 +#define MT6358_VS2_ANA_CON3 0x18b4 +#define MT6358_VS2_ANA_CON4 0x18b6 +#define MT6358_VS2_ANA_CON5 0x18b8 +#define MT6358_VPA_ANA_CON0 0x18ba +#define MT6358_VPA_ANA_CON1 0x18bc +#define MT6358_VPA_ANA_CON2 0x18be +#define MT6358_VPA_ANA_CON3 0x18c0 +#define MT6358_VPA_ANA_CON4 0x18c2 +#define MT6358_VPA_ANA_CON5 0x18c4 +#define MT6358_BUCK_ANA1_ELR_NUM 0x18c6 +#define MT6358_VMODEM_ELR_0 0x18c8 +#define MT6358_VMODEM_ELR_1 0x18ca +#define MT6358_VDRAM1_ELR_0 0x18cc +#define MT6358_VDRAM1_ELR_1 0x18ce +#define MT6358_VS1_ELR_0 0x18d0 +#define MT6358_VS1_ELR_1 0x18d2 +#define MT6358_VS2_ELR_0 0x18d4 +#define MT6358_VS2_ELR_1 0x18d6 +#define MT6358_VPA_ELR_0 0x18d8 +#define MT6358_LDO_TOP_ID 0x1a00 +#define MT6358_LDO_TOP_REV0 0x1a02 +#define MT6358_LDO_TOP_DBI 0x1a04 +#define MT6358_LDO_TOP_DXI 0x1a06 +#define MT6358_LDO_TPM0 0x1a08 +#define MT6358_LDO_TPM1 0x1a0a +#define MT6358_LDO_TOP_CKPDN_CON0 0x1a0c +#define MT6358_TOP_TOP_CKHWEN_CON0 0x1a0e +#define MT6358_LDO_TOP_CLK_DCM_CON0 0x1a10 +#define MT6358_LDO_TOP_CLK_VFE28_CON0 0x1a12 +#define MT6358_LDO_TOP_CLK_VXO22_CON0 0x1a14 +#define MT6358_LDO_TOP_CLK_VRF18_CON0 0x1a16 +#define MT6358_LDO_TOP_CLK_VRF12_CON0 0x1a18 +#define MT6358_LDO_TOP_CLK_VEFUSE_CON0 0x1a1a +#define MT6358_LDO_TOP_CLK_VCN33_CON0 0x1a1c +#define MT6358_LDO_TOP_CLK_VCN28_CON0 0x1a1e +#define MT6358_LDO_TOP_CLK_VCN18_CON0 0x1a20 +#define MT6358_LDO_TOP_CLK_VCAMA1_CON0 0x1a22 +#define MT6358_LDO_TOP_CLK_VCAMA2_CON0 0x1a24 +#define MT6358_LDO_TOP_CLK_VCAMD_CON0 0x1a26 +#define MT6358_LDO_TOP_CLK_VCAMIO_CON0 0x1a28 +#define MT6358_LDO_TOP_CLK_VLDO28_CON0 0x1a2a +#define MT6358_LDO_TOP_CLK_VA12_CON0 0x1a2c +#define MT6358_LDO_TOP_CLK_VAUX18_CON0 0x1a2e +#define MT6358_LDO_TOP_CLK_VAUD28_CON0 0x1a30 +#define MT6358_LDO_TOP_CLK_VIO28_CON0 0x1a32 +#define MT6358_LDO_TOP_CLK_VIO18_CON0 0x1a34 +#define MT6358_LDO_TOP_CLK_VSRAM_PROC11_CON0 0x1a36 +#define MT6358_LDO_TOP_CLK_VSRAM_PROC12_CON0 0x1a38 +#define MT6358_LDO_TOP_CLK_VSRAM_OTHERS_CON0 0x1a3a +#define MT6358_LDO_TOP_CLK_VSRAM_GPU_CON0 0x1a3c +#define MT6358_LDO_TOP_CLK_VDRAM2_CON0 0x1a3e +#define MT6358_LDO_TOP_CLK_VMC_CON0 0x1a40 +#define MT6358_LDO_TOP_CLK_VMCH_CON0 0x1a42 +#define MT6358_LDO_TOP_CLK_VEMC_CON0 0x1a44 +#define MT6358_LDO_TOP_CLK_VSIM1_CON0 0x1a46 +#define MT6358_LDO_TOP_CLK_VSIM2_CON0 0x1a48 +#define MT6358_LDO_TOP_CLK_VIBR_CON0 0x1a4a +#define MT6358_LDO_TOP_CLK_VUSB_CON0 0x1a4c +#define MT6358_LDO_TOP_CLK_VBIF28_CON0 0x1a4e +#define MT6358_LDO_TOP_INT_CON0 0x1a50 +#define MT6358_LDO_TOP_INT_CON0_SET 0x1a52 +#define MT6358_LDO_TOP_INT_CON0_CLR 0x1a54 +#define MT6358_LDO_TOP_INT_CON1 0x1a56 +#define MT6358_LDO_TOP_INT_CON1_SET 0x1a58 +#define MT6358_LDO_TOP_INT_CON1_CLR 0x1a5a +#define MT6358_LDO_TOP_INT_MASK_CON0 0x1a5c +#define MT6358_LDO_TOP_INT_MASK_CON0_SET 0x1a5e +#define MT6358_LDO_TOP_INT_MASK_CON0_CLR 0x1a60 +#define MT6358_LDO_TOP_INT_MASK_CON1 0x1a62 +#define MT6358_LDO_TOP_INT_MASK_CON1_SET 0x1a64 +#define MT6358_LDO_TOP_INT_MASK_CON1_CLR 0x1a66 +#define MT6358_LDO_TOP_INT_STATUS0 0x1a68 +#define MT6358_LDO_TOP_INT_STATUS1 0x1a6a +#define MT6358_LDO_TOP_INT_RAW_STATUS0 0x1a6c +#define MT6358_LDO_TOP_INT_RAW_STATUS1 0x1a6e +#define MT6358_LDO_TEST_CON0 0x1a70 +#define MT6358_LDO_TOP_WDT_CON0 0x1a72 +#define MT6358_LDO_TOP_RSV_CON0 0x1a74 +#define MT6358_LDO_TOP_RSV_CON1 0x1a76 +#define MT6358_LDO_OCFB0 0x1a78 +#define MT6358_LDO_LP_PROTECTION 0x1a7a +#define MT6358_LDO_DUMMY_LOAD_GATED 0x1a7c +#define MT6358_LDO_GON0_DSN_ID 0x1a80 +#define MT6358_LDO_GON0_DSN_REV0 0x1a82 +#define MT6358_LDO_GON0_DSN_DBI 0x1a84 +#define MT6358_LDO_GON0_DSN_DXI 0x1a86 +#define MT6358_LDO_VXO22_CON0 0x1a88 +#define MT6358_LDO_VXO22_OP_EN 0x1a8a +#define MT6358_LDO_VXO22_OP_EN_SET 0x1a8c +#define MT6358_LDO_VXO22_OP_EN_CLR 0x1a8e +#define MT6358_LDO_VXO22_OP_CFG 0x1a90 +#define MT6358_LDO_VXO22_OP_CFG_SET 0x1a92 +#define MT6358_LDO_VXO22_OP_CFG_CLR 0x1a94 +#define MT6358_LDO_VXO22_CON1 0x1a96 +#define MT6358_LDO_VXO22_CON2 0x1a98 +#define MT6358_LDO_VXO22_CON3 0x1a9a +#define MT6358_LDO_VA12_CON0 0x1a9c +#define MT6358_LDO_VA12_OP_EN 0x1a9e +#define MT6358_LDO_VA12_OP_EN_SET 0x1aa0 +#define MT6358_LDO_VA12_OP_EN_CLR 0x1aa2 +#define MT6358_LDO_VA12_OP_CFG 0x1aa4 +#define MT6358_LDO_VA12_OP_CFG_SET 0x1aa6 +#define MT6358_LDO_VA12_OP_CFG_CLR 0x1aa8 +#define MT6358_LDO_VA12_CON1 0x1aaa +#define MT6358_LDO_VA12_CON2 0x1aac +#define MT6358_LDO_VA12_CON3 0x1aae +#define MT6358_LDO_VAUX18_CON0 0x1ab0 +#define MT6358_LDO_VAUX18_OP_EN 0x1ab2 +#define MT6358_LDO_VAUX18_OP_EN_SET 0x1ab4 +#define MT6358_LDO_VAUX18_OP_EN_CLR 0x1ab6 +#define MT6358_LDO_VAUX18_OP_CFG 0x1ab8 +#define MT6358_LDO_VAUX18_OP_CFG_SET 0x1aba +#define MT6358_LDO_VAUX18_OP_CFG_CLR 0x1abc +#define MT6358_LDO_VAUX18_CON1 0x1abe +#define MT6358_LDO_VAUX18_CON2 0x1ac0 +#define MT6358_LDO_VAUX18_CON3 0x1ac2 +#define MT6358_LDO_VAUD28_CON0 0x1ac4 +#define MT6358_LDO_VAUD28_OP_EN 0x1ac6 +#define MT6358_LDO_VAUD28_OP_EN_SET 0x1ac8 +#define MT6358_LDO_VAUD28_OP_EN_CLR 0x1aca +#define MT6358_LDO_VAUD28_OP_CFG 0x1acc +#define MT6358_LDO_VAUD28_OP_CFG_SET 0x1ace +#define MT6358_LDO_VAUD28_OP_CFG_CLR 0x1ad0 +#define MT6358_LDO_VAUD28_CON1 0x1ad2 +#define MT6358_LDO_VAUD28_CON2 0x1ad4 +#define MT6358_LDO_VAUD28_CON3 0x1ad6 +#define MT6358_LDO_VIO28_CON0 0x1ad8 +#define MT6358_LDO_VIO28_OP_EN 0x1ada +#define MT6358_LDO_VIO28_OP_EN_SET 0x1adc +#define MT6358_LDO_VIO28_OP_EN_CLR 0x1ade +#define MT6358_LDO_VIO28_OP_CFG 0x1ae0 +#define MT6358_LDO_VIO28_OP_CFG_SET 0x1ae2 +#define MT6358_LDO_VIO28_OP_CFG_CLR 0x1ae4 +#define MT6358_LDO_VIO28_CON1 0x1ae6 +#define MT6358_LDO_VIO28_CON2 0x1ae8 +#define MT6358_LDO_VIO28_CON3 0x1aea +#define MT6358_LDO_VIO18_CON0 0x1aec +#define MT6358_LDO_VIO18_OP_EN 0x1aee +#define MT6358_LDO_VIO18_OP_EN_SET 0x1af0 +#define MT6358_LDO_VIO18_OP_EN_CLR 0x1af2 +#define MT6358_LDO_VIO18_OP_CFG 0x1af4 +#define MT6358_LDO_VIO18_OP_CFG_SET 0x1af6 +#define MT6358_LDO_VIO18_OP_CFG_CLR 0x1af8 +#define MT6358_LDO_VIO18_CON1 0x1afa +#define MT6358_LDO_VIO18_CON2 0x1afc +#define MT6358_LDO_VIO18_CON3 0x1afe +#define MT6358_LDO_GON1_DSN_ID 0x1b00 +#define MT6358_LDO_GON1_DSN_REV0 0x1b02 +#define MT6358_LDO_GON1_DSN_DBI 0x1b04 +#define MT6358_LDO_GON1_DSN_DXI 0x1b06 +#define MT6358_LDO_VDRAM2_CON0 0x1b08 +#define MT6358_LDO_VDRAM2_OP_EN 0x1b0a +#define MT6358_LDO_VDRAM2_OP_EN_SET 0x1b0c +#define MT6358_LDO_VDRAM2_OP_EN_CLR 0x1b0e +#define MT6358_LDO_VDRAM2_OP_CFG 0x1b10 +#define MT6358_LDO_VDRAM2_OP_CFG_SET 0x1b12 +#define MT6358_LDO_VDRAM2_OP_CFG_CLR 0x1b14 +#define MT6358_LDO_VDRAM2_CON1 0x1b16 +#define MT6358_LDO_VDRAM2_CON2 0x1b18 +#define MT6358_LDO_VDRAM2_CON3 0x1b1a +#define MT6358_LDO_VEMC_CON0 0x1b1c +#define MT6358_LDO_VEMC_OP_EN 0x1b1e +#define MT6358_LDO_VEMC_OP_EN_SET 0x1b20 +#define MT6358_LDO_VEMC_OP_EN_CLR 0x1b22 +#define MT6358_LDO_VEMC_OP_CFG 0x1b24 +#define MT6358_LDO_VEMC_OP_CFG_SET 0x1b26 +#define MT6358_LDO_VEMC_OP_CFG_CLR 0x1b28 +#define MT6358_LDO_VEMC_CON1 0x1b2a +#define MT6358_LDO_VEMC_CON2 0x1b2c +#define MT6358_LDO_VEMC_CON3 0x1b2e +#define MT6358_LDO_VUSB_CON0_0 0x1b30 +#define MT6358_LDO_VUSB_OP_EN 0x1b32 +#define MT6358_LDO_VUSB_OP_EN_SET 0x1b34 +#define MT6358_LDO_VUSB_OP_EN_CLR 0x1b36 +#define MT6358_LDO_VUSB_OP_CFG 0x1b38 +#define MT6358_LDO_VUSB_OP_CFG_SET 0x1b3a +#define MT6358_LDO_VUSB_OP_CFG_CLR 0x1b3c +#define MT6358_LDO_VUSB_CON0_1 0x1b3e +#define MT6358_LDO_VUSB_CON1 0x1b40 +#define MT6358_LDO_VUSB_CON2 0x1b42 +#define MT6358_LDO_VUSB_CON3 0x1b44 +#define MT6358_LDO_VSRAM_PROC11_CON0 0x1b46 +#define MT6358_LDO_VSRAM_PROC11_CON2 0x1b48 +#define MT6358_LDO_VSRAM_PROC11_CFG0 0x1b4a +#define MT6358_LDO_VSRAM_PROC11_CFG1 0x1b4c +#define MT6358_LDO_VSRAM_PROC11_OP_EN 0x1b4e +#define MT6358_LDO_VSRAM_PROC11_OP_EN_SET 0x1b50 +#define MT6358_LDO_VSRAM_PROC11_OP_EN_CLR 0x1b52 +#define MT6358_LDO_VSRAM_PROC11_OP_CFG 0x1b54 +#define MT6358_LDO_VSRAM_PROC11_OP_CFG_SET 0x1b56 +#define MT6358_LDO_VSRAM_PROC11_OP_CFG_CLR 0x1b58 +#define MT6358_LDO_VSRAM_PROC11_CON3 0x1b5a +#define MT6358_LDO_VSRAM_PROC11_CON4 0x1b5c +#define MT6358_LDO_VSRAM_PROC11_CON5 0x1b5e +#define MT6358_LDO_VSRAM_PROC11_DBG0 0x1b60 +#define MT6358_LDO_VSRAM_PROC11_DBG1 0x1b62 +#define MT6358_LDO_VSRAM_PROC11_TRACKING_CON0 0x1b64 +#define MT6358_LDO_VSRAM_PROC11_TRACKING_CON1 0x1b66 +#define MT6358_LDO_VSRAM_PROC11_TRACKING_CON2 0x1b68 +#define MT6358_LDO_VSRAM_PROC11_TRACKING_CON3 0x1b6a +#define MT6358_LDO_VSRAM_PROC12_TRACKING_CON0 0x1b6c +#define MT6358_LDO_VSRAM_PROC12_TRACKING_CON1 0x1b6e +#define MT6358_LDO_VSRAM_PROC12_TRACKING_CON2 0x1b70 +#define MT6358_LDO_VSRAM_PROC12_TRACKING_CON3 0x1b72 +#define MT6358_LDO_VSRAM_WAKEUP_CON0 0x1b74 +#define MT6358_LDO_GON1_ELR_NUM 0x1b76 +#define MT6358_LDO_VDRAM2_ELR0 0x1b78 +#define MT6358_LDO_VDRAM2_ELR1 0x1b7a +#define MT6358_LDO_STRUP_ELR0 0x1b7c +#define MT6358_LDO_GON2_DSN_ID 0x1b80 +#define MT6358_LDO_GON2_DSN_REV0 0x1b82 +#define MT6358_LDO_GON2_DSN_DBI 0x1b84 +#define MT6358_LDO_GON2_DSN_DXI 0x1b86 +#define MT6358_LDO_VSRAM_PROC12_CON0 0x1b88 +#define MT6358_LDO_VSRAM_PROC12_CON2 0x1b8a +#define MT6358_LDO_VSRAM_PROC12_CFG0 0x1b8c +#define MT6358_LDO_VSRAM_PROC12_CFG1 0x1b8e +#define MT6358_LDO_VSRAM_PROC12_OP_EN 0x1b90 +#define MT6358_LDO_VSRAM_PROC12_OP_EN_SET 0x1b92 +#define MT6358_LDO_VSRAM_PROC12_OP_EN_CLR 0x1b94 +#define MT6358_LDO_VSRAM_PROC12_OP_CFG 0x1b96 +#define MT6358_LDO_VSRAM_PROC12_OP_CFG_SET 0x1b98 +#define MT6358_LDO_VSRAM_PROC12_OP_CFG_CLR 0x1b9a +#define MT6358_LDO_VSRAM_PROC12_CON3 0x1b9c +#define MT6358_LDO_VSRAM_PROC12_CON4 0x1b9e +#define MT6358_LDO_VSRAM_PROC12_CON5 0x1ba0 +#define MT6358_LDO_VSRAM_PROC12_DBG0 0x1ba2 +#define MT6358_LDO_VSRAM_PROC12_DBG1 0x1ba4 +#define MT6358_LDO_VSRAM_OTHERS_CON0 0x1ba6 +#define MT6358_LDO_VSRAM_OTHERS_CON2 0x1ba8 +#define MT6358_LDO_VSRAM_OTHERS_CFG0 0x1baa +#define MT6358_LDO_VSRAM_OTHERS_CFG1 0x1bac +#define MT6358_LDO_VSRAM_OTHERS_OP_EN 0x1bae +#define MT6358_LDO_VSRAM_OTHERS_OP_EN_SET 0x1bb0 +#define MT6358_LDO_VSRAM_OTHERS_OP_EN_CLR 0x1bb2 +#define MT6358_LDO_VSRAM_OTHERS_OP_CFG 0x1bb4 +#define MT6358_LDO_VSRAM_OTHERS_OP_CFG_SET 0x1bb6 +#define MT6358_LDO_VSRAM_OTHERS_OP_CFG_CLR 0x1bb8 +#define MT6358_LDO_VSRAM_OTHERS_CON3 0x1bba +#define MT6358_LDO_VSRAM_OTHERS_CON4 0x1bbc +#define MT6358_LDO_VSRAM_OTHERS_CON5 0x1bbe +#define MT6358_LDO_VSRAM_OTHERS_DBG0 0x1bc0 +#define MT6358_LDO_VSRAM_OTHERS_DBG1 0x1bc2 +#define MT6358_LDO_VSRAM_OTHERS_SSHUB_CON0 0x1bc4 +#define MT6358_LDO_VSRAM_OTHERS_SSHUB_CON1 0x1bc6 +#define MT6358_LDO_VSRAM_GPU_CON0 0x1bc8 +#define MT6358_LDO_VSRAM_GPU_CON2 0x1bca +#define MT6358_LDO_VSRAM_GPU_CFG0 0x1bcc +#define MT6358_LDO_VSRAM_GPU_CFG1 0x1bce +#define MT6358_LDO_VSRAM_GPU_OP_EN 0x1bd0 +#define MT6358_LDO_VSRAM_GPU_OP_EN_SET 0x1bd2 +#define MT6358_LDO_VSRAM_GPU_OP_EN_CLR 0x1bd4 +#define MT6358_LDO_VSRAM_GPU_OP_CFG 0x1bd6 +#define MT6358_LDO_VSRAM_GPU_OP_CFG_SET 0x1bd8 +#define MT6358_LDO_VSRAM_GPU_OP_CFG_CLR 0x1bda +#define MT6358_LDO_VSRAM_GPU_CON3 0x1bdc +#define MT6358_LDO_VSRAM_GPU_CON4 0x1bde +#define MT6358_LDO_VSRAM_GPU_CON5 0x1be0 +#define MT6358_LDO_VSRAM_GPU_DBG0 0x1be2 +#define MT6358_LDO_VSRAM_GPU_DBG1 0x1be4 +#define MT6358_LDO_VSRAM_R2R_PDN_DIS 0x1be6 +#define MT6358_LDO_VSRAM_WDT_DBG0 0x1be8 +#define MT6358_LDO_VSRAM_WDT_DBG1 0x1bea +#define MT6358_LDO_GON2_ELR_NUM 0x1bec +#define MT6358_LDO_VSRAM_CON0 0x1bee +#define MT6358_LDO_VSRAM_CON1 0x1bf0 +#define MT6358_LDO_VSRAM_CON2 0x1bf2 +#define MT6358_LDO_VSRAM_CON3 0x1bf4 +#define MT6358_LDO_VSRAM_CON4 0x1bf6 +#define MT6358_LDO_GOFF0_DSN_ID 0x1c00 +#define MT6358_LDO_GOFF0_DSN_REV0 0x1c02 +#define MT6358_LDO_GOFF0_DSN_DBI 0x1c04 +#define MT6358_LDO_GOFF0_DSN_DXI 0x1c06 +#define MT6358_LDO_VFE28_CON0 0x1c08 +#define MT6358_LDO_VFE28_OP_EN 0x1c0a +#define MT6358_LDO_VFE28_OP_EN_SET 0x1c0c +#define MT6358_LDO_VFE28_OP_EN_CLR 0x1c0e +#define MT6358_LDO_VFE28_OP_CFG 0x1c10 +#define MT6358_LDO_VFE28_OP_CFG_SET 0x1c12 +#define MT6358_LDO_VFE28_OP_CFG_CLR 0x1c14 +#define MT6358_LDO_VFE28_CON1 0x1c16 +#define MT6358_LDO_VFE28_CON2 0x1c18 +#define MT6358_LDO_VFE28_CON3 0x1c1a +#define MT6358_LDO_VRF18_CON0 0x1c1c +#define MT6358_LDO_VRF18_OP_EN 0x1c1e +#define MT6358_LDO_VRF18_OP_EN_SET 0x1c20 +#define MT6358_LDO_VRF18_OP_EN_CLR 0x1c22 +#define MT6358_LDO_VRF18_OP_CFG 0x1c24 +#define MT6358_LDO_VRF18_OP_CFG_SET 0x1c26 +#define MT6358_LDO_VRF18_OP_CFG_CLR 0x1c28 +#define MT6358_LDO_VRF18_CON1 0x1c2a +#define MT6358_LDO_VRF18_CON2 0x1c2c +#define MT6358_LDO_VRF18_CON3 0x1c2e +#define MT6358_LDO_VRF12_CON0 0x1c30 +#define MT6358_LDO_VRF12_OP_EN 0x1c32 +#define MT6358_LDO_VRF12_OP_EN_SET 0x1c34 +#define MT6358_LDO_VRF12_OP_EN_CLR 0x1c36 +#define MT6358_LDO_VRF12_OP_CFG 0x1c38 +#define MT6358_LDO_VRF12_OP_CFG_SET 0x1c3a +#define MT6358_LDO_VRF12_OP_CFG_CLR 0x1c3c +#define MT6358_LDO_VRF12_CON1 0x1c3e +#define MT6358_LDO_VRF12_CON2 0x1c40 +#define MT6358_LDO_VRF12_CON3 0x1c42 +#define MT6358_LDO_VEFUSE_CON0 0x1c44 +#define MT6358_LDO_VEFUSE_OP_EN 0x1c46 +#define MT6358_LDO_VEFUSE_OP_EN_SET 0x1c48 +#define MT6358_LDO_VEFUSE_OP_EN_CLR 0x1c4a +#define MT6358_LDO_VEFUSE_OP_CFG 0x1c4c +#define MT6358_LDO_VEFUSE_OP_CFG_SET 0x1c4e +#define MT6358_LDO_VEFUSE_OP_CFG_CLR 0x1c50 +#define MT6358_LDO_VEFUSE_CON1 0x1c52 +#define MT6358_LDO_VEFUSE_CON2 0x1c54 +#define MT6358_LDO_VEFUSE_CON3 0x1c56 +#define MT6358_LDO_VCN18_CON0 0x1c58 +#define MT6358_LDO_VCN18_OP_EN 0x1c5a +#define MT6358_LDO_VCN18_OP_EN_SET 0x1c5c +#define MT6358_LDO_VCN18_OP_EN_CLR 0x1c5e +#define MT6358_LDO_VCN18_OP_CFG 0x1c60 +#define MT6358_LDO_VCN18_OP_CFG_SET 0x1c62 +#define MT6358_LDO_VCN18_OP_CFG_CLR 0x1c64 +#define MT6358_LDO_VCN18_CON1 0x1c66 +#define MT6358_LDO_VCN18_CON2 0x1c68 +#define MT6358_LDO_VCN18_CON3 0x1c6a +#define MT6358_LDO_VCAMA1_CON0 0x1c6c +#define MT6358_LDO_VCAMA1_OP_EN 0x1c6e +#define MT6358_LDO_VCAMA1_OP_EN_SET 0x1c70 +#define MT6358_LDO_VCAMA1_OP_EN_CLR 0x1c72 +#define MT6358_LDO_VCAMA1_OP_CFG 0x1c74 +#define MT6358_LDO_VCAMA1_OP_CFG_SET 0x1c76 +#define MT6358_LDO_VCAMA1_OP_CFG_CLR 0x1c78 +#define MT6358_LDO_VCAMA1_CON1 0x1c7a +#define MT6358_LDO_VCAMA1_CON2 0x1c7c +#define MT6358_LDO_VCAMA1_CON3 0x1c7e +#define MT6358_LDO_GOFF1_DSN_ID 0x1c80 +#define MT6358_LDO_GOFF1_DSN_REV0 0x1c82 +#define MT6358_LDO_GOFF1_DSN_DBI 0x1c84 +#define MT6358_LDO_GOFF1_DSN_DXI 0x1c86 +#define MT6358_LDO_VCAMA2_CON0 0x1c88 +#define MT6358_LDO_VCAMA2_OP_EN 0x1c8a +#define MT6358_LDO_VCAMA2_OP_EN_SET 0x1c8c +#define MT6358_LDO_VCAMA2_OP_EN_CLR 0x1c8e +#define MT6358_LDO_VCAMA2_OP_CFG 0x1c90 +#define MT6358_LDO_VCAMA2_OP_CFG_SET 0x1c92 +#define MT6358_LDO_VCAMA2_OP_CFG_CLR 0x1c94 +#define MT6358_LDO_VCAMA2_CON1 0x1c96 +#define MT6358_LDO_VCAMA2_CON2 0x1c98 +#define MT6358_LDO_VCAMA2_CON3 0x1c9a +#define MT6358_LDO_VCAMD_CON0 0x1c9c +#define MT6358_LDO_VCAMD_OP_EN 0x1c9e +#define MT6358_LDO_VCAMD_OP_EN_SET 0x1ca0 +#define MT6358_LDO_VCAMD_OP_EN_CLR 0x1ca2 +#define MT6358_LDO_VCAMD_OP_CFG 0x1ca4 +#define MT6358_LDO_VCAMD_OP_CFG_SET 0x1ca6 +#define MT6358_LDO_VCAMD_OP_CFG_CLR 0x1ca8 +#define MT6358_LDO_VCAMD_CON1 0x1caa +#define MT6358_LDO_VCAMD_CON2 0x1cac +#define MT6358_LDO_VCAMD_CON3 0x1cae +#define MT6358_LDO_VCAMIO_CON0 0x1cb0 +#define MT6358_LDO_VCAMIO_OP_EN 0x1cb2 +#define MT6358_LDO_VCAMIO_OP_EN_SET 0x1cb4 +#define MT6358_LDO_VCAMIO_OP_EN_CLR 0x1cb6 +#define MT6358_LDO_VCAMIO_OP_CFG 0x1cb8 +#define MT6358_LDO_VCAMIO_OP_CFG_SET 0x1cba +#define MT6358_LDO_VCAMIO_OP_CFG_CLR 0x1cbc +#define MT6358_LDO_VCAMIO_CON1 0x1cbe +#define MT6358_LDO_VCAMIO_CON2 0x1cc0 +#define MT6358_LDO_VCAMIO_CON3 0x1cc2 +#define MT6358_LDO_VMC_CON0 0x1cc4 +#define MT6358_LDO_VMC_OP_EN 0x1cc6 +#define MT6358_LDO_VMC_OP_EN_SET 0x1cc8 +#define MT6358_LDO_VMC_OP_EN_CLR 0x1cca +#define MT6358_LDO_VMC_OP_CFG 0x1ccc +#define MT6358_LDO_VMC_OP_CFG_SET 0x1cce +#define MT6358_LDO_VMC_OP_CFG_CLR 0x1cd0 +#define MT6358_LDO_VMC_CON1 0x1cd2 +#define MT6358_LDO_VMC_CON2 0x1cd4 +#define MT6358_LDO_VMC_CON3 0x1cd6 +#define MT6358_LDO_VMCH_CON0 0x1cd8 +#define MT6358_LDO_VMCH_OP_EN 0x1cda +#define MT6358_LDO_VMCH_OP_EN_SET 0x1cdc +#define MT6358_LDO_VMCH_OP_EN_CLR 0x1cde +#define MT6358_LDO_VMCH_OP_CFG 0x1ce0 +#define MT6358_LDO_VMCH_OP_CFG_SET 0x1ce2 +#define MT6358_LDO_VMCH_OP_CFG_CLR 0x1ce4 +#define MT6358_LDO_VMCH_CON1 0x1ce6 +#define MT6358_LDO_VMCH_CON2 0x1ce8 +#define MT6358_LDO_VMCH_CON3 0x1cea +#define MT6358_LDO_GOFF2_DSN_ID 0x1d00 +#define MT6358_LDO_GOFF2_DSN_REV0 0x1d02 +#define MT6358_LDO_GOFF2_DSN_DBI 0x1d04 +#define MT6358_LDO_GOFF2_DSN_DXI 0x1d06 +#define MT6358_LDO_VIBR_CON0 0x1d08 +#define MT6358_LDO_VIBR_OP_EN 0x1d0a +#define MT6358_LDO_VIBR_OP_EN_SET 0x1d0c +#define MT6358_LDO_VIBR_OP_EN_CLR 0x1d0e +#define MT6358_LDO_VIBR_OP_CFG 0x1d10 +#define MT6358_LDO_VIBR_OP_CFG_SET 0x1d12 +#define MT6358_LDO_VIBR_OP_CFG_CLR 0x1d14 +#define MT6358_LDO_VIBR_CON1 0x1d16 +#define MT6358_LDO_VIBR_CON2 0x1d18 +#define MT6358_LDO_VIBR_CON3 0x1d1a +#define MT6358_LDO_VCN33_CON0_0 0x1d1c +#define MT6358_LDO_VCN33_OP_EN 0x1d1e +#define MT6358_LDO_VCN33_OP_EN_SET 0x1d20 +#define MT6358_LDO_VCN33_OP_EN_CLR 0x1d22 +#define MT6358_LDO_VCN33_OP_CFG 0x1d24 +#define MT6358_LDO_VCN33_OP_CFG_SET 0x1d26 +#define MT6358_LDO_VCN33_OP_CFG_CLR 0x1d28 +#define MT6358_LDO_VCN33_CON0_1 0x1d2a +#define MT6358_LDO_VCN33_CON1 0x1d2c +#define MT6358_LDO_VCN33_BT_CON1 MT6358_LDO_VCN33_CON1 +#define MT6358_LDO_VCN33_WIFI_CON1 MT6358_LDO_VCN33_CON1 +#define MT6358_LDO_VCN33_CON2 0x1d2e +#define MT6358_LDO_VCN33_CON3 0x1d30 +#define MT6358_LDO_VLDO28_CON0_0 0x1d32 +#define MT6358_LDO_VLDO28_OP_EN 0x1d34 +#define MT6358_LDO_VLDO28_OP_EN_SET 0x1d36 +#define MT6358_LDO_VLDO28_OP_EN_CLR 0x1d38 +#define MT6358_LDO_VLDO28_OP_CFG 0x1d3a +#define MT6358_LDO_VLDO28_OP_CFG_SET 0x1d3c +#define MT6358_LDO_VLDO28_OP_CFG_CLR 0x1d3e +#define MT6358_LDO_VLDO28_CON0_1 0x1d40 +#define MT6358_LDO_VLDO28_CON1 0x1d42 +#define MT6358_LDO_VLDO28_CON2 0x1d44 +#define MT6358_LDO_VLDO28_CON3 0x1d46 +#define MT6358_LDO_VSIM1_CON0 0x1d48 +#define MT6358_LDO_VSIM1_OP_EN 0x1d4a +#define MT6358_LDO_VSIM1_OP_EN_SET 0x1d4c +#define MT6358_LDO_VSIM1_OP_EN_CLR 0x1d4e +#define MT6358_LDO_VSIM1_OP_CFG 0x1d50 +#define MT6358_LDO_VSIM1_OP_CFG_SET 0x1d52 +#define MT6358_LDO_VSIM1_OP_CFG_CLR 0x1d54 +#define MT6358_LDO_VSIM1_CON1 0x1d56 +#define MT6358_LDO_VSIM1_CON2 0x1d58 +#define MT6358_LDO_VSIM1_CON3 0x1d5a +#define MT6358_LDO_VSIM2_CON0 0x1d5c +#define MT6358_LDO_VSIM2_OP_EN 0x1d5e +#define MT6358_LDO_VSIM2_OP_EN_SET 0x1d60 +#define MT6358_LDO_VSIM2_OP_EN_CLR 0x1d62 +#define MT6358_LDO_VSIM2_OP_CFG 0x1d64 +#define MT6358_LDO_VSIM2_OP_CFG_SET 0x1d66 +#define MT6358_LDO_VSIM2_OP_CFG_CLR 0x1d68 +#define MT6358_LDO_VSIM2_CON1 0x1d6a +#define MT6358_LDO_VSIM2_CON2 0x1d6c +#define MT6358_LDO_VSIM2_CON3 0x1d6e +#define MT6358_LDO_VMCH_EINT_SD_CFG 0x1d70 +#define MT6358_LDO_VSIM1_EINT_SD_CFG 0x1d72 +#define MT6358_LDO_VSIM2_EINT_SD_CFG 0x1d74 +#define MT6358_LDO_GOFF2_RSV_CON0 0x1d76 +#define MT6358_LDO_GOFF2_RSV_CON1 0x1d78 +#define MT6358_LDO_GOFF3_DSN_ID 0x1d80 +#define MT6358_LDO_GOFF3_DSN_REV0 0x1d82 +#define MT6358_LDO_GOFF3_DSN_DBI 0x1d84 +#define MT6358_LDO_GOFF3_DSN_DXI 0x1d86 +#define MT6358_LDO_VCN28_CON0 0x1d88 +#define MT6358_LDO_VCN28_OP_EN 0x1d8a +#define MT6358_LDO_VCN28_OP_EN_SET 0x1d8c +#define MT6358_LDO_VCN28_OP_EN_CLR 0x1d8e +#define MT6358_LDO_VCN28_OP_CFG 0x1d90 +#define MT6358_LDO_VCN28_OP_CFG_SET 0x1d92 +#define MT6358_LDO_VCN28_OP_CFG_CLR 0x1d94 +#define MT6358_LDO_VCN28_CON1 0x1d96 +#define MT6358_LDO_VCN28_CON2 0x1d98 +#define MT6358_LDO_VCN28_CON3 0x1d9a +#define MT6358_VRTC28_CON0 0x1d9c +#define MT6358_LDO_VBIF28_CON0 0x1d9e +#define MT6358_LDO_VBIF28_OP_EN 0x1da0 +#define MT6358_LDO_VBIF28_OP_EN_SET 0x1da2 +#define MT6358_LDO_VBIF28_OP_EN_CLR 0x1da4 +#define MT6358_LDO_VBIF28_OP_CFG 0x1da6 +#define MT6358_LDO_VBIF28_OP_CFG_SET 0x1da8 +#define MT6358_LDO_VBIF28_OP_CFG_CLR 0x1daa +#define MT6358_LDO_VBIF28_CON1 0x1dac +#define MT6358_LDO_VBIF28_CON2 0x1dae +#define MT6358_LDO_VBIF28_CON3 0x1db0 +#define MT6358_LDO_GOFF3_RSV_CON0 0x1db2 +#define MT6358_LDO_GOFF3_RSV_CON1 0x1db4 +#define MT6358_LDO_ANA0_DSN_ID 0x1e00 +#define MT6358_LDO_ANA0_DSN_REV0 0x1e02 +#define MT6358_LDO_ANA0_DSN_DBI 0x1e04 +#define MT6358_LDO_ANA0_DSN_FPI 0x1e06 +#define MT6358_VCAMA1_ANA_CON0 0x1e08 +#define MT6358_VCAMA1_ANA_CON1 0x1e0a +#define MT6358_VCAMA2_ANA_CON0 0x1e0c +#define MT6358_VCAMA2_ANA_CON1 0x1e0e +#define MT6358_VFE28_ANA_CON0 0x1e10 +#define MT6358_VFE28_ANA_CON1 0x1e12 +#define MT6358_VCN28_ANA_CON0 0x1e14 +#define MT6358_VCN28_ANA_CON1 0x1e16 +#define MT6358_VBIF28_ANA_CON0 0x1e18 +#define MT6358_VBIF28_ANA_CON1 0x1e1a +#define MT6358_VAUD28_ANA_CON0 0x1e1c +#define MT6358_VAUD28_ANA_CON1 0x1e1e +#define MT6358_VAUX18_ANA_CON0 0x1e20 +#define MT6358_VAUX18_ANA_CON1 0x1e22 +#define MT6358_VXO22_ANA_CON0 0x1e24 +#define MT6358_VXO22_ANA_CON1 0x1e26 +#define MT6358_VCN33_ANA_CON0 0x1e28 +#define MT6358_VCN33_ANA_CON1 0x1e2a +#define MT6358_VSIM1_ANA_CON0 0x1e2c +#define MT6358_VSIM1_ANA_CON1 0x1e2e +#define MT6358_VSIM2_ANA_CON0 0x1e30 +#define MT6358_VSIM2_ANA_CON1 0x1e32 +#define MT6358_VUSB_ANA_CON0 0x1e34 +#define MT6358_VUSB_ANA_CON1 0x1e36 +#define MT6358_VEMC_ANA_CON0 0x1e38 +#define MT6358_VEMC_ANA_CON1 0x1e3a +#define MT6358_VLDO28_ANA_CON0 0x1e3c +#define MT6358_VLDO28_ANA_CON1 0x1e3e +#define MT6358_VIO28_ANA_CON0 0x1e40 +#define MT6358_VIO28_ANA_CON1 0x1e42 +#define MT6358_VIBR_ANA_CON0 0x1e44 +#define MT6358_VIBR_ANA_CON1 0x1e46 +#define MT6358_VMCH_ANA_CON0 0x1e48 +#define MT6358_VMCH_ANA_CON1 0x1e4a +#define MT6358_VMC_ANA_CON0 0x1e4c +#define MT6358_VMC_ANA_CON1 0x1e4e +#define MT6358_LDO_ANA0_ELR_NUM 0x1e50 +#define MT6358_VCAMA1_ELR_0 0x1e52 +#define MT6358_VCAMA2_ELR_0 0x1e54 +#define MT6358_VFE28_ELR_0 0x1e56 +#define MT6358_VCN28_ELR_0 0x1e58 +#define MT6358_VBIF28_ELR_0 0x1e5a +#define MT6358_VAUD28_ELR_0 0x1e5c +#define MT6358_VAUX18_ELR_0 0x1e5e +#define MT6358_VXO22_ELR_0 0x1e60 +#define MT6358_VCN33_ELR_0 0x1e62 +#define MT6358_VSIM1_ELR_0 0x1e64 +#define MT6358_VSIM2_ELR_0 0x1e66 +#define MT6358_VUSB_ELR_0 0x1e68 +#define MT6358_VEMC_ELR_0 0x1e6a +#define MT6358_VLDO28_ELR_0 0x1e6c +#define MT6358_VIO28_ELR_0 0x1e6e +#define MT6358_VIBR_ELR_0 0x1e70 +#define MT6358_VMCH_ELR_0 0x1e72 +#define MT6358_VMC_ELR_0 0x1e74 +#define MT6358_LDO_ANA1_DSN_ID 0x1e80 +#define MT6358_LDO_ANA1_DSN_REV0 0x1e82 +#define MT6358_LDO_ANA1_DSN_DBI 0x1e84 +#define MT6358_LDO_ANA1_DSN_FPI 0x1e86 +#define MT6358_VRF18_ANA_CON0 0x1e88 +#define MT6358_VRF18_ANA_CON1 0x1e8a +#define MT6358_VCN18_ANA_CON0 0x1e8c +#define MT6358_VCN18_ANA_CON1 0x1e8e +#define MT6358_VCAMIO_ANA_CON0 0x1e90 +#define MT6358_VCAMIO_ANA_CON1 0x1e92 +#define MT6358_VIO18_ANA_CON0 0x1e94 +#define MT6358_VIO18_ANA_CON1 0x1e96 +#define MT6358_VEFUSE_ANA_CON0 0x1e98 +#define MT6358_VEFUSE_ANA_CON1 0x1e9a +#define MT6358_VRF12_ANA_CON0 0x1e9c +#define MT6358_VRF12_ANA_CON1 0x1e9e +#define MT6358_VSRAM_PROC11_ANA_CON0 0x1ea0 +#define MT6358_VSRAM_PROC11_ANA_CON1 0x1ea2 +#define MT6358_VSRAM_PROC12_ANA_CON0 0x1ea4 +#define MT6358_VSRAM_OTHERS_ANA_CON0 0x1ea6 +#define MT6358_VSRAM_GPU_ANA_CON0 0x1ea8 +#define MT6358_VDRAM2_ANA_CON0 0x1eaa +#define MT6358_VDRAM2_ANA_CON1 0x1eac +#define MT6358_VCAMD_ANA_CON0 0x1eae +#define MT6358_VCAMD_ANA_CON1 0x1eb0 +#define MT6358_VA12_ANA_CON0 0x1eb2 +#define MT6358_VA12_ANA_CON1 0x1eb4 +#define MT6358_LDO_ANA1_ELR_NUM 0x1eb6 +#define MT6358_VRF18_ELR_0 0x1eb8 +#define MT6358_VCN18_ELR_0 0x1eba +#define MT6358_VCAMIO_ELR_0 0x1ebc +#define MT6358_VIO18_ELR_0 0x1ebe +#define MT6358_VEFUSE_ELR_0 0x1ec0 +#define MT6358_VRF12_ELR_0 0x1ec2 +#define MT6358_VDRAM2_ELR_0 0x1ec4 +#define MT6358_VCAMD_ELR_0 0x1ec6 +#define MT6358_VA12_ELR_0 0x1ec8 +#define MT6358_VRTC28_ELR_0 0x1eca +#define MT6358_DUMMYLOAD_DSN_ID 0x1f00 +#define MT6358_DUMMYLOAD_DSN_REV0 0x1f02 +#define MT6358_DUMMYLOAD_DSN_DBI 0x1f04 +#define MT6358_DUMMYLOAD_DSN_FPI 0x1f06 +#define MT6358_DUMMYLOAD_ANA_CON0 0x1f08 +#define MT6358_ISINK0_CON1 0x1f0a +#define MT6358_ISINK1_CON1 0x1f0c +#define MT6358_ISINK_ANA1_SMPL 0x1f0e +#define MT6358_ISINK_EN_CTRL_SMPL 0x1f10 +#define MT6358_DUMMYLOAD_ELR_NUM 0x1f12 +#define MT6358_DUMMYLOAD_ELR_0 0x1f14 +#define MT6358_AUD_TOP_ID 0x2200 +#define MT6358_AUD_TOP_REV0 0x2202 +#define MT6358_AUD_TOP_DBI 0x2204 +#define MT6358_AUD_TOP_DXI 0x2206 +#define MT6358_AUD_TOP_CKPDN_TPM0 0x2208 +#define MT6358_AUD_TOP_CKPDN_TPM1 0x220a +#define MT6358_AUD_TOP_CKPDN_CON0 0x220c +#define MT6358_AUD_TOP_CKPDN_CON0_SET 0x220e +#define MT6358_AUD_TOP_CKPDN_CON0_CLR 0x2210 +#define MT6358_AUD_TOP_CKSEL_CON0 0x2212 +#define MT6358_AUD_TOP_CKSEL_CON0_SET 0x2214 +#define MT6358_AUD_TOP_CKSEL_CON0_CLR 0x2216 +#define MT6358_AUD_TOP_CKTST_CON0 0x2218 +#define MT6358_AUD_TOP_CLK_HWEN_CON0 0x221a +#define MT6358_AUD_TOP_CLK_HWEN_CON0_SET 0x221c +#define MT6358_AUD_TOP_CLK_HWEN_CON0_CLR 0x221e +#define MT6358_AUD_TOP_RST_CON0 0x2220 +#define MT6358_AUD_TOP_RST_CON0_SET 0x2222 +#define MT6358_AUD_TOP_RST_CON0_CLR 0x2224 +#define MT6358_AUD_TOP_RST_BANK_CON0 0x2226 +#define MT6358_AUD_TOP_INT_CON0 0x2228 +#define MT6358_AUD_TOP_INT_CON0_SET 0x222a +#define MT6358_AUD_TOP_INT_CON0_CLR 0x222c +#define MT6358_AUD_TOP_INT_MASK_CON0 0x222e +#define MT6358_AUD_TOP_INT_MASK_CON0_SET 0x2230 +#define MT6358_AUD_TOP_INT_MASK_CON0_CLR 0x2232 +#define MT6358_AUD_TOP_INT_STATUS0 0x2234 +#define MT6358_AUD_TOP_INT_RAW_STATUS0 0x2236 +#define MT6358_AUD_TOP_INT_MISC_CON0 0x2238 +#define MT6358_AUDNCP_CLKDIV_CON0 0x223a +#define MT6358_AUDNCP_CLKDIV_CON1 0x223c +#define MT6358_AUDNCP_CLKDIV_CON2 0x223e +#define MT6358_AUDNCP_CLKDIV_CON3 0x2240 +#define MT6358_AUDNCP_CLKDIV_CON4 0x2242 +#define MT6358_AUD_TOP_MON_CON0 0x2244 +#define MT6358_AUDIO_DIG_DSN_ID 0x2280 +#define MT6358_AUDIO_DIG_DSN_REV0 0x2282 +#define MT6358_AUDIO_DIG_DSN_DBI 0x2284 +#define MT6358_AUDIO_DIG_DSN_DXI 0x2286 +#define MT6358_AFE_UL_DL_CON0 0x2288 +#define MT6358_AFE_DL_SRC2_CON0_L 0x228a +#define MT6358_AFE_UL_SRC_CON0_H 0x228c +#define MT6358_AFE_UL_SRC_CON0_L 0x228e +#define MT6358_AFE_TOP_CON0 0x2290 +#define MT6358_AUDIO_TOP_CON0 0x2292 +#define MT6358_AFE_MON_DEBUG0 0x2294 +#define MT6358_AFUNC_AUD_CON0 0x2296 +#define MT6358_AFUNC_AUD_CON1 0x2298 +#define MT6358_AFUNC_AUD_CON2 0x229a +#define MT6358_AFUNC_AUD_CON3 0x229c +#define MT6358_AFUNC_AUD_CON4 0x229e +#define MT6358_AFUNC_AUD_CON5 0x22a0 +#define MT6358_AFUNC_AUD_CON6 0x22a2 +#define MT6358_AFUNC_AUD_MON0 0x22a4 +#define MT6358_AUDRC_TUNE_MON0 0x22a6 +#define MT6358_AFE_ADDA_MTKAIF_FIFO_CFG0 0x22a8 +#define MT6358_AFE_ADDA_MTKAIF_FIFO_LOG_MON1 0x22aa +#define MT6358_AFE_ADDA_MTKAIF_MON0 0x22ac +#define MT6358_AFE_ADDA_MTKAIF_MON1 0x22ae +#define MT6358_AFE_ADDA_MTKAIF_MON2 0x22b0 +#define MT6358_AFE_ADDA_MTKAIF_MON3 0x22b2 +#define MT6358_AFE_ADDA_MTKAIF_CFG0 0x22b4 +#define MT6358_AFE_ADDA_MTKAIF_RX_CFG0 0x22b6 +#define MT6358_AFE_ADDA_MTKAIF_RX_CFG1 0x22b8 +#define MT6358_AFE_ADDA_MTKAIF_RX_CFG2 0x22ba +#define MT6358_AFE_ADDA_MTKAIF_RX_CFG3 0x22bc +#define MT6358_AFE_ADDA_MTKAIF_TX_CFG1 0x22be +#define MT6358_AFE_SGEN_CFG0 0x22c0 +#define MT6358_AFE_SGEN_CFG1 0x22c2 +#define MT6358_AFE_ADC_ASYNC_FIFO_CFG 0x22c4 +#define MT6358_AFE_DCCLK_CFG0 0x22c6 +#define MT6358_AFE_DCCLK_CFG1 0x22c8 +#define MT6358_AUDIO_DIG_CFG 0x22ca +#define MT6358_AFE_AUD_PAD_TOP 0x22cc +#define MT6358_AFE_AUD_PAD_TOP_MON 0x22ce +#define MT6358_AFE_AUD_PAD_TOP_MON1 0x22d0 +#define MT6358_AFE_DL_NLE_CFG 0x22d2 +#define MT6358_AFE_DL_NLE_MON 0x22d4 +#define MT6358_AFE_CG_EN_MON 0x22d6 +#define MT6358_AUDIO_DIG_2ND_DSN_ID 0x2300 +#define MT6358_AUDIO_DIG_2ND_DSN_REV0 0x2302 +#define MT6358_AUDIO_DIG_2ND_DSN_DBI 0x2304 +#define MT6358_AUDIO_DIG_2ND_DSN_DXI 0x2306 +#define MT6358_AFE_PMIC_NEWIF_CFG3 0x2308 +#define MT6358_AFE_VOW_TOP 0x230a +#define MT6358_AFE_VOW_CFG0 0x230c +#define MT6358_AFE_VOW_CFG1 0x230e +#define MT6358_AFE_VOW_CFG2 0x2310 +#define MT6358_AFE_VOW_CFG3 0x2312 +#define MT6358_AFE_VOW_CFG4 0x2314 +#define MT6358_AFE_VOW_CFG5 0x2316 +#define MT6358_AFE_VOW_CFG6 0x2318 +#define MT6358_AFE_VOW_MON0 0x231a +#define MT6358_AFE_VOW_MON1 0x231c +#define MT6358_AFE_VOW_MON2 0x231e +#define MT6358_AFE_VOW_MON3 0x2320 +#define MT6358_AFE_VOW_MON4 0x2322 +#define MT6358_AFE_VOW_MON5 0x2324 +#define MT6358_AFE_VOW_SN_INI_CFG 0x2326 +#define MT6358_AFE_VOW_TGEN_CFG0 0x2328 +#define MT6358_AFE_VOW_POSDIV_CFG0 0x232a +#define MT6358_AFE_VOW_HPF_CFG0 0x232c +#define MT6358_AFE_VOW_PERIODIC_CFG0 0x232e +#define MT6358_AFE_VOW_PERIODIC_CFG1 0x2330 +#define MT6358_AFE_VOW_PERIODIC_CFG2 0x2332 +#define MT6358_AFE_VOW_PERIODIC_CFG3 0x2334 +#define MT6358_AFE_VOW_PERIODIC_CFG4 0x2336 +#define MT6358_AFE_VOW_PERIODIC_CFG5 0x2338 +#define MT6358_AFE_VOW_PERIODIC_CFG6 0x233a +#define MT6358_AFE_VOW_PERIODIC_CFG7 0x233c +#define MT6358_AFE_VOW_PERIODIC_CFG8 0x233e +#define MT6358_AFE_VOW_PERIODIC_CFG9 0x2340 +#define MT6358_AFE_VOW_PERIODIC_CFG10 0x2342 +#define MT6358_AFE_VOW_PERIODIC_CFG11 0x2344 +#define MT6358_AFE_VOW_PERIODIC_CFG12 0x2346 +#define MT6358_AFE_VOW_PERIODIC_CFG13 0x2348 +#define MT6358_AFE_VOW_PERIODIC_CFG14 0x234a +#define MT6358_AFE_VOW_PERIODIC_CFG15 0x234c +#define MT6358_AFE_VOW_PERIODIC_CFG16 0x234e +#define MT6358_AFE_VOW_PERIODIC_CFG17 0x2350 +#define MT6358_AFE_VOW_PERIODIC_CFG18 0x2352 +#define MT6358_AFE_VOW_PERIODIC_CFG19 0x2354 +#define MT6358_AFE_VOW_PERIODIC_CFG20 0x2356 +#define MT6358_AFE_VOW_PERIODIC_CFG21 0x2358 +#define MT6358_AFE_VOW_PERIODIC_CFG22 0x235a +#define MT6358_AFE_VOW_PERIODIC_CFG23 0x235c +#define MT6358_AFE_VOW_PERIODIC_MON0 0x235e +#define MT6358_AFE_VOW_PERIODIC_MON1 0x2360 +#define MT6358_AUDENC_DSN_ID 0x2380 +#define MT6358_AUDENC_DSN_REV0 0x2382 +#define MT6358_AUDENC_DSN_DBI 0x2384 +#define MT6358_AUDENC_DSN_FPI 0x2386 +#define MT6358_AUDENC_ANA_CON0 0x2388 +#define MT6358_AUDENC_ANA_CON1 0x238a +#define MT6358_AUDENC_ANA_CON2 0x238c +#define MT6358_AUDENC_ANA_CON3 0x238e +#define MT6358_AUDENC_ANA_CON4 0x2390 +#define MT6358_AUDENC_ANA_CON5 0x2392 +#define MT6358_AUDENC_ANA_CON6 0x2394 +#define MT6358_AUDENC_ANA_CON7 0x2396 +#define MT6358_AUDENC_ANA_CON8 0x2398 +#define MT6358_AUDENC_ANA_CON9 0x239a +#define MT6358_AUDENC_ANA_CON10 0x239c +#define MT6358_AUDENC_ANA_CON11 0x239e +#define MT6358_AUDENC_ANA_CON12 0x23a0 +#define MT6358_AUDDEC_DSN_ID 0x2400 +#define MT6358_AUDDEC_DSN_REV0 0x2402 +#define MT6358_AUDDEC_DSN_DBI 0x2404 +#define MT6358_AUDDEC_DSN_FPI 0x2406 +#define MT6358_AUDDEC_ANA_CON0 0x2408 +#define MT6358_AUDDEC_ANA_CON1 0x240a +#define MT6358_AUDDEC_ANA_CON2 0x240c +#define MT6358_AUDDEC_ANA_CON3 0x240e +#define MT6358_AUDDEC_ANA_CON4 0x2410 +#define MT6358_AUDDEC_ANA_CON5 0x2412 +#define MT6358_AUDDEC_ANA_CON6 0x2414 +#define MT6358_AUDDEC_ANA_CON7 0x2416 +#define MT6358_AUDDEC_ANA_CON8 0x2418 +#define MT6358_AUDDEC_ANA_CON9 0x241a +#define MT6358_AUDDEC_ANA_CON10 0x241c +#define MT6358_AUDDEC_ANA_CON11 0x241e +#define MT6358_AUDDEC_ANA_CON12 0x2420 +#define MT6358_AUDDEC_ANA_CON13 0x2422 +#define MT6358_AUDDEC_ANA_CON14 0x2424 +#define MT6358_AUDDEC_ANA_CON15 0x2426 +#define MT6358_AUDDEC_ELR_NUM 0x2428 +#define MT6358_AUDDEC_ELR_0 0x242a +#define MT6358_AUDZCD_DSN_ID 0x2480 +#define MT6358_AUDZCD_DSN_REV0 0x2482 +#define MT6358_AUDZCD_DSN_DBI 0x2484 +#define MT6358_AUDZCD_DSN_FPI 0x2486 +#define MT6358_ZCD_CON0 0x2488 +#define MT6358_ZCD_CON1 0x248a +#define MT6358_ZCD_CON2 0x248c +#define MT6358_ZCD_CON3 0x248e +#define MT6358_ZCD_CON4 0x2490 +#define MT6358_ZCD_CON5 0x2492 +#define MT6358_ACCDET_DSN_DIG_ID 0x2500 +#define MT6358_ACCDET_DSN_DIG_REV0 0x2502 +#define MT6358_ACCDET_DSN_DBI 0x2504 +#define MT6358_ACCDET_DSN_FPI 0x2506 +#define MT6358_ACCDET_CON0 0x2508 +#define MT6358_ACCDET_CON1 0x250a +#define MT6358_ACCDET_CON2 0x250c +#define MT6358_ACCDET_CON3 0x250e +#define MT6358_ACCDET_CON4 0x2510 +#define MT6358_ACCDET_CON5 0x2512 +#define MT6358_ACCDET_CON6 0x2514 +#define MT6358_ACCDET_CON7 0x2516 +#define MT6358_ACCDET_CON8 0x2518 +#define MT6358_ACCDET_CON9 0x251a +#define MT6358_ACCDET_CON10 0x251c +#define MT6358_ACCDET_CON11 0x251e +#define MT6358_ACCDET_CON12 0x2520 +#define MT6358_ACCDET_CON13 0x2522 +#define MT6358_ACCDET_CON14 0x2524 +#define MT6358_ACCDET_CON15 0x2526 +#define MT6358_ACCDET_CON16 0x2528 +#define MT6358_ACCDET_CON17 0x252a +#define MT6358_ACCDET_CON18 0x252c +#define MT6358_ACCDET_CON19 0x252e +#define MT6358_ACCDET_CON20 0x2530 +#define MT6358_ACCDET_CON21 0x2532 +#define MT6358_ACCDET_CON22 0x2534 +#define MT6358_ACCDET_CON23 0x2536 +#define MT6358_ACCDET_CON24 0x2538 +#define MT6358_ACCDET_CON25 0x253a +#define MT6358_ACCDET_CON26 0x253c +#define MT6358_ACCDET_CON27 0x253e +#define MT6358_ACCDET_CON28 0x2540 + +#endif /* __MFD_MT6358_REGISTERS_H__ */ diff --git a/include/linux/regulator/mt6358-regulator.h b/include/linux/regulator/mt6358-regulator.h new file mode 100644 index 000000000000..09dc55f310f0 --- /dev/null +++ b/include/linux/regulator/mt6358-regulator.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2018 MediaTek Inc. + * Author: Hsin-Hsiung Wang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __LINUX_REGULATOR_MT6358_H +#define __LINUX_REGULATOR_MT6358_H + +enum { + MT6358_ID_VDRAM1 = 0, + MT6358_ID_VCORE, + MT6358_ID_VPA, + MT6358_ID_VPROC11, + MT6358_ID_VPROC12, + MT6358_ID_VGPU, + MT6358_ID_VS2, + MT6358_ID_VMODEM, + MT6358_ID_VS1, + MT6358_ID_VDRAM2 = 9, + MT6358_ID_VSIM1, + MT6358_ID_VIBR, + MT6358_ID_VRF12, + MT6358_ID_VIO18, + MT6358_ID_VUSB, + MT6358_ID_VCAMIO, + MT6358_ID_VCAMD, + MT6358_ID_VCN18, + MT6358_ID_VFE28, + MT6358_ID_VSRAM_PROC11, + MT6358_ID_VCN28, + MT6358_ID_VSRAM_OTHERS, + MT6358_ID_VSRAM_GPU, + MT6358_ID_VXO22, + MT6358_ID_VEFUSE, + MT6358_ID_VAUX18, + MT6358_ID_VMCH, + MT6358_ID_VBIF28, + MT6358_ID_VSRAM_PROC12, + MT6358_ID_VCAMA1, + MT6358_ID_VEMC, + MT6358_ID_VIO28, + MT6358_ID_VA12, + MT6358_ID_VRF18, + MT6358_ID_VCN33_BT, + MT6358_ID_VCN33_WIFI, + MT6358_ID_VCAMA2, + MT6358_ID_VMC, + MT6358_ID_VLDO28, + MT6358_ID_VAUD28, + MT6358_ID_VSIM2, + MT6358_ID_RG_MAX, +}; + +#define MT6358_MAX_REGULATOR MT6358_ID_RG_MAX + +#endif /* __LINUX_REGULATOR_MT6358_H */