ARM: rockchip: fix kernel hang during smp initialization
[ Upstream commit 7cdb433bb44cdc87dc5260cdf15bf03cc1cd1814 ] In order to bring up secondary CPUs main CPU write trampoline code to SRAM. The trampoline code is written while secondary CPUs are powered on (at least that true for RK3188 CPU). Sometimes that leads to kernel hang. Probably because secondary CPU execute trampoline code while kernel doesn't expect. The patch moves SRAM initialization step to the point where all secondary CPUs are powered down. That fixes rarely hangs on RK3188: [ 0.091568] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000 [ 0.091996] rockchip_smp_prepare_cpus: ncores 4 Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com> Link: https://lore.kernel.org/r/20250703140453.1273027-1-al.kochet@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
committed by
Greg Kroah-Hartman
parent
9b02fdb0f6
commit
888a453c2a
@@ -279,11 +279,6 @@ static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
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}
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if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
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if (rockchip_smp_prepare_sram(node)) {
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of_node_put(node);
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return;
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}
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/* enable the SCU power domain */
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pmu_set_power_domain(PMU_PWRDN_SCU, true);
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@@ -316,11 +311,19 @@ static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
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asm ("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr));
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ncores = ((l2ctlr >> 24) & 0x3) + 1;
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}
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of_node_put(node);
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/* Make sure that all cores except the first are really off */
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for (i = 1; i < ncores; i++)
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pmu_set_power_domain(0 + i, false);
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if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
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if (rockchip_smp_prepare_sram(node)) {
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of_node_put(node);
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return;
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}
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}
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of_node_put(node);
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}
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static void __init rk3036_smp_prepare_cpus(unsigned int max_cpus)
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