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UPSTREAM: arm64: Add missing ISB after invalidating TLB in enter_vhe

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Although there has been a bit of back and forth on the subject, it
appears that invalidating TLBs requires an ISB instruction after the
TLBI/DSB sequence when FEAT_ETS is not implemented by the CPU.

From the bible:

  | In an implementation that does not implement FEAT_ETS, a TLB
  | maintenance instruction executed by a PE, PEx, can complete at any
  | time after it is issued, but is only guaranteed to be finished for a
  | PE, PEx, after the execution of DSB by the PEx followed by a Context
  | synchronization event

Add the missing ISB in enter_vhe(), just in case.

Fixes: f359182291c7 ("arm64: Provide an 'upgrade to VHE' stub hypercall")
Suggested-by: Will Deacon <will@kernel.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Link: https://lore.kernel.org/r/20210224093738.3629662-4-maz@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
(cherry picked from commit 430251cc864beb11ac5b6d2f5c6ef54ddd432612)
Bug: 187129171
Signed-off-by: Connor O'Brien <connoro@google.com>
Change-Id: Id50f6f18605f0110afcee58a0cda34260235cccd
This commit is contained in:
Marc Zyngier
2021-02-24 09:37:38 +00:00
committed by Connor O'Brien
parent b1843022a9
commit 9bf26f0ace
1 changed files with 1 additions and 0 deletions
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1
arch/arm64/kernel/hyp-stub.S
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@@ -153,6 +153,7 @@ SYM_CODE_START_LOCAL(enter_vhe)
// Invalidate TLBs before enabling the MMU
tlbi vmalle1
dsb nsh
isb
// Enable the EL2 S1 MMU, as set up from EL1
mrs_s x0, SYS_SCTLR_EL12