iio: adc: ad7768-1: Ensure SYNC_IN pulse minimum timing requirement
[ Upstream commit 7e54d932873d91a55d1b89b7389876d78aeeab32 ] The SYNC_IN pulse width must be at least 1.5 x Tmclk, corresponding to ~2.5 µs at the lowest supported MCLK frequency. Add a 3 µs delay to ensure reliable synchronization timing even for the worst-case scenario. Signed-off-by: Jonathan Santos <Jonathan.Santos@analog.com> Reviewed-by: David Lechner <dlechner@baylibre.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/d3ee92a533cd1207cf5c5cc4d7bdbb5c6c267f68.1749063024.git.Jonathan.Santos@analog.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
committed by
Greg Kroah-Hartman
parent
8ed372c3de
commit
c90222e5b6
@@ -202,6 +202,24 @@ static int ad7768_spi_reg_write(struct ad7768_state *st,
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return spi_write(st->spi, st->data.d8, 2);
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}
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static int ad7768_send_sync_pulse(struct ad7768_state *st)
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{
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/*
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* The datasheet specifies a minimum SYNC_IN pulse width of 1.5 × Tmclk,
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* where Tmclk is the MCLK period. The supported MCLK frequencies range
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* from 0.6 MHz to 17 MHz, which corresponds to a minimum SYNC_IN pulse
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* width of approximately 2.5 µs in the worst-case scenario (0.6 MHz).
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*
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* Add a delay to ensure the pulse width is always sufficient to
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* trigger synchronization.
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*/
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gpiod_set_value_cansleep(st->gpio_sync_in, 1);
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fsleep(3);
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gpiod_set_value_cansleep(st->gpio_sync_in, 0);
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return 0;
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}
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static int ad7768_set_mode(struct ad7768_state *st,
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enum ad7768_conv_mode mode)
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{
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@@ -287,10 +305,7 @@ static int ad7768_set_dig_fil(struct ad7768_state *st,
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return ret;
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/* A sync-in pulse is required every time the filter dec rate changes */
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gpiod_set_value(st->gpio_sync_in, 1);
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gpiod_set_value(st->gpio_sync_in, 0);
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return 0;
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return ad7768_send_sync_pulse(st);
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}
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static int ad7768_set_freq(struct ad7768_state *st,
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