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media: tc358743: Increase FIFO trigger level to 374

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[ Upstream commit 86addd25314a1e77dbdcfddfeed0bab2f27da0e2 ]

The existing fixed value of 16 worked for UYVY 720P60 over
2 lanes at 594MHz, or UYVY 1080P60 over 4 lanes. (RGB888
1080P60 needs 6 lanes at 594MHz).
It doesn't allow for lower resolutions to work as the FIFO
underflows.

374 is required for 1080P24 or 1080P30 UYVY over 2 lanes @
972Mbit/s, but >374 means that the FIFO underflows on 1080P50
UYVY over 2 lanes @ 972Mbit/s.

Whilst it would be nice to compute it, the required information
isn't published by Toshiba.

Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Dave Stevenson
2025-06-11 19:37:14 +01:00
committed by Greg Kroah-Hartman
parent 10ad86fd99
commit e02a4eff7e
1 changed files with 13 additions and 2 deletions
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15
drivers/media/i2c/tc358743.c
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@@ -1960,8 +1960,19 @@ static int tc358743_probe_of(struct tc358743_state *state)
state->pdata.refclk_hz = clk_get_rate(refclk);
state->pdata.ddc5v_delay = DDC5V_DELAY_100_MS;
state->pdata.enable_hdcp = false;
/* A FIFO level of 16 should be enough for 2-lane 720p60 at 594 MHz. */
state->pdata.fifo_level = 16;
/*
* Ideally the FIFO trigger level should be set based on the input and
* output data rates, but the calculations required are buried in
* Toshiba's register settings spreadsheet.
* A value of 16 works with a 594Mbps data rate for 720p60 (using 2
* lanes) and 1080p60 (using 4 lanes), but fails when the data rate
* is increased, or a lower pixel clock is used that result in CSI
* reading out faster than the data is arriving.
*
* A value of 374 works with both those modes at 594Mbps, and with most
* modes on 972Mbps.
*/
state->pdata.fifo_level = 374;
/*
* The PLL input clock is obtained by dividing refclk by pll_prd.
* It must be between 6 MHz and 40 MHz, lower frequency is better.