From 7ad73e130644155f6b571c44c30fff614aa38ea8 Mon Sep 17 00:00:00 2001 From: UtsavBalar1231 Date: Fri, 28 Aug 2020 19:54:51 +0530 Subject: [PATCH] Revert "ARM: dts: Make crypto address part of host controller node" This reverts commit 4abe03d70b5af292fb823b1f250989510aa99232. Signed-off-by: UtsavBalar1231 --- arch/arm64/boot/dts/qcom/atoll.dtsi | 9 +++++---- arch/arm64/boot/dts/qcom/sdmmagpie.dtsi | 9 +++++---- arch/arm64/boot/dts/qcom/sm6150.dtsi | 9 +++++---- arch/arm64/boot/dts/qcom/sm8150.dtsi | 5 +++-- 4 files changed, 18 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/atoll.dtsi b/arch/arm64/boot/dts/qcom/atoll.dtsi index 4f2f8b1c7b09..3c8b470205c1 100644 --- a/arch/arm64/boot/dts/qcom/atoll.dtsi +++ b/arch/arm64/boot/dts/qcom/atoll.dtsi @@ -2679,12 +2679,13 @@ sdhc_1: sdhci@7c4000 { compatible = "qcom,sdhci-msm-v5"; - reg = <0x7c4000 0x1000>, <0x7c5000 0x1000>, <0x7c8000 0x8000>; - reg-names = "hc_mem", "cmdq_mem", "cmdq_ice"; + reg = <0x7c4000 0x1000>, <0x7c5000 0x1000>; + reg-names = "hc_mem", "cmdq_mem"; interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; + sdhc-msm-crypto = <&sdcc1_ice>; qcom,bus-width = <8>; qcom,large-address-bus; @@ -2834,11 +2835,11 @@ ufshc_mem: ufshc@1d84000 { compatible = "qcom,ufshc"; - reg = <0x1d84000 0x3000>, <0x1d90000 0x8000>; - reg-names = "ufs_mem", "ufs_ice"; + reg = <0x1d84000 0x3000>; interrupts = <0 265 0>; phys = <&ufsphy_mem>; phy-names = "ufsphy"; + ufs-qcom-crypto = <&ufs_ice>; lanes-per-direction = <1>; dev-ref-clk-freq = <0>; /* 19.2 MHz */ diff --git a/arch/arm64/boot/dts/qcom/sdmmagpie.dtsi b/arch/arm64/boot/dts/qcom/sdmmagpie.dtsi index da9805d4cd81..3259d7cccc7e 100644 --- a/arch/arm64/boot/dts/qcom/sdmmagpie.dtsi +++ b/arch/arm64/boot/dts/qcom/sdmmagpie.dtsi @@ -2121,12 +2121,13 @@ sdhc_1: sdhci@7c4000 { compatible = "qcom,sdhci-msm-v5"; - reg = <0x7c4000 0x1000>, <0x7c5000 0x1000>, <0x7C8000 0x8000>; - reg-names = "hc_mem", "cmdq_mem", "cmdq_ice"; + reg = <0x7c4000 0x1000>, <0x7c5000 0x1000>; + reg-names = "hc_mem", "cmdq_mem"; interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; + sdhc-msm-crypto = <&sdcc1_ice>; qcom,bus-width = <8>; qcom,large-address-bus; @@ -2338,11 +2339,11 @@ ufshc_mem: ufshc@1d84000 { compatible = "qcom,ufshc"; - reg = <0x1d84000 0x3000>, <0x1d90000 0x8000>; - reg-names = "ufs_mem", "ufs_ice"; + reg = <0x1d84000 0x3000>; interrupts = <0 265 0>; phys = <&ufsphy_mem>; phy-names = "ufsphy"; + ufs-qcom-crypto = <&ufs_ice>; lanes-per-direction = <1>; dev-ref-clk-freq = <0>; /* 19.2 MHz */ diff --git a/arch/arm64/boot/dts/qcom/sm6150.dtsi b/arch/arm64/boot/dts/qcom/sm6150.dtsi index 6822b9dc4ce0..ee7812be6fcc 100644 --- a/arch/arm64/boot/dts/qcom/sm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150.dtsi @@ -1409,11 +1409,12 @@ sdhc_1: sdhci@7c4000 { compatible = "qcom,sdhci-msm-v5"; - reg = <0x7c4000 0x1000>, <0x7c5000 0x1000>, <0x7C8000 0x8000>; - reg-names = "hc_mem", "cmdq_mem", "cmdq_ice"; + reg = <0x7c4000 0x1000>, <0x7c5000 0x1000>; + reg-names = "hc_mem", "cmdq_mem"; interrupts = <0 641 0>, <0 644 0>; interrupt-names = "hc_irq", "pwr_irq"; + sdhc-msm-crypto = <&sdcc1_ice>; qcom,bus-width = <8>; qcom,large-address-bus; @@ -1622,11 +1623,11 @@ ufshc_mem: ufshc@1d84000 { compatible = "qcom,ufshc"; - reg = <0x1d84000 0x3000>, <0x1d90000 0x8000>; - reg-names = "ufs_mem", "ufs_ice"; + reg = <0x1d84000 0x3000>; interrupts = <0 265 0>; phys = <&ufsphy_mem>; phy-names = "ufsphy"; + ufs-qcom-crypto = <&ufs_ice>; lanes-per-direction = <1>; dev-ref-clk-freq = <0>; /* 19.2 MHz */ diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 8428b869d768..bcc15b5f454e 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -2281,6 +2281,7 @@ reg = <0x1d87000 0xda8>; /* PHY regs */ reg-names = "phy_mem"; #phy-cells = <0>; + ufs-qcom-crypto = <&ufs_ice>; lanes-per-direction = <2>; @@ -2296,11 +2297,11 @@ ufshc_mem: ufshc@1d84000 { compatible = "qcom,ufshc"; - reg = <0x1d84000 0x2500>, <0x1d90000 0x8000>; - reg-names = "ufs_mem", "ufs_ice"; + reg = <0x1d84000 0x2500>; interrupts = <0 265 0>; phys = <&ufsphy_mem>; phy-names = "ufsphy"; + ufs-qcom-crypto = <&ufs_ice>; lanes-per-direction = <2>; dev-ref-clk-freq = <0>; /* 19.2 MHz */