840 lines
22 KiB
Plaintext
840 lines
22 KiB
Plaintext
/* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "skeleton64.dtsi"
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#include <dt-bindings/clock/qcom,gcc-sdmshrike.h>
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#include <dt-bindings/clock/qcom,scc-sm8150.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
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#include "quin-vm-common.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/msm/msm-bus-ids.h>
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/ {
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model = "Qualcomm Technologies, Inc. SA8195 Virtual Machine";
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qcom,msm-name = "SA8195P";
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qcom,msm-id = <405 0x20000>;
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aliases {
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sdhc2 = &sdhc_2; /* SDC2 SD Card slot */
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};
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};
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&soc {
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pdc: interrupt-controller@0xb220000{
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compatible = "qcom,pdc-virt";
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reg = <0xb220000 0x400>;
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#interrupt-cells = <3>;
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interrupt-controller;
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qcom,pdc-pins = <7 519>, <8 520>, <9 521>, <10 522>, <11 523>;
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};
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clock_virt: qcom,virtio-gcc {
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compatible = "virtio,mmio";
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reg = <0x1c200000 0x1000>;
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interrupts = <0 48 0>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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clock_virt_scc: qcom,virtio-scc {
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compatible = "virtio,mmio";
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reg = <0x1c300000 0x1000>;
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interrupts = <0 49 0>;
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#clock-cells = <1>;
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};
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regulator_virt: virtio_regulator@1c700000 {
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compatible = "virtio,mmio";
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reg = <0x1c700000 0x1000>;
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interrupts = <0 42 0>;
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usb30_prim_gdsc: usb30_prim_gdsc {
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regulator-name = "usb30_prim_gdsc";
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};
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usb30_sec_gdsc: usb30_sec_gdsc {
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regulator-name = "usb30_sec_gdsc";
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};
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pcie_0_gdsc: pcie_0_gdsc {
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regulator-name = "pcie_0_gdsc";
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};
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pcie_1_gdsc: pcie_1_gdsc {
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regulator-name = "pcie_1_gdsc";
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};
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pcie_2_gdsc: pcie_2_gdsc {
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regulator-name = "pcie_2_gdsc";
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};
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pcie_3_gdsc: pcie_3_gdsc {
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regulator-name = "pcie_3_gdsc";
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};
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L2A: pm8195_1_l2: regulator-pm8195-1-l2 {
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regulator-name = "ldoa2";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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};
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L9A: pm8195_1_l9: regulator-pm8195-1-l9 {
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regulator-name = "ldoa9";
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regulator-min-microvolt = <1150000>;
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regulator-max-microvolt = <1250000>;
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regulator-allow-set-load;
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};
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L10A: pm8195_1_l10: regulator-pm8195-1-l10 {
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regulator-name = "ldoa10";
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regulator-min-microvolt = <2700000>;
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regulator-max-microvolt = <3544000>;
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};
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L12A: pm8195_1_l12: regulator-pm8195-1-l12 {
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regulator-name = "ldoa12";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1890000>;
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};
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L7C: pm8195_2_l7: regulator-pm8195-2-l7 {
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regulator-name = "ldoc7";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <2040000>;
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};
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L5E: pm8195_3_l5: regulator-pm8195-3-l5 {
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regulator-name = "ldoe5";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <920000>;
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regulator-allow-set-load;
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};
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L16E: pm8195_3_l16: regulator-pm8195-3-l16 {
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regulator-name = "ldoe16";
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regulator-min-microvolt = <2921000>;
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regulator-max-microvolt = <3300000>;
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};
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S2A: pm8195_1_s2: regulator-pm8195-1-s2 {
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regulator-name = "smpa2";
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regulator-min-microvolt = <1179000>;
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regulator-max-microvolt = <1379000>;
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};
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S5A: pm8195_1_s5: regulator-pm8195-1-s5 {
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regulator-name = "smpa5";
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <1000000>;
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};
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S5C: pm8195_2_s5: regulator-pm8195-2-s5 {
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regulator-name = "smpc5";
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regulator-min-microvolt = <1713000>;
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regulator-max-microvolt = <2040000>;
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};
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};
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apps_smmu: apps-smmu@0x15000000 {
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compatible = "qcom,qsmmu-v500";
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reg = <0x15000000 0x100000>,
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<0x15182000 0x20>;
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reg-names = "base", "tcu-base";
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#iommu-cells = <2>;
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qcom,skip-init;
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qcom,use-3-lvl-tables;
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qcom,disable-atos;
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#global-interrupts = <1>;
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#size-cells = <1>;
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#address-cells = <1>;
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ranges;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 777 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 778 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 779 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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qcom,sps {
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compatible = "qcom,msm-sps-4k";
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qcom,pipe-attr-ee;
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status = "disabled";
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};
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/* PWR_CTR2_VDD_1P8 supply */
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vreg_conn_1p8: vreg_conn_1p8 {
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compatible = "regulator-fixed";
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regulator-name = "vreg_conn_1p8";
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pinctrl-names = "default";
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pinctrl-0 = <&conn_power_1p8_active>;
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startup-delay-us = <4000>;
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enable-active-high;
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gpio = <&tlmm 173 0>;
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};
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/* PWR_CTR1_VDD_PA supply */
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vreg_conn_pa: vreg_conn_pa {
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compatible = "regulator-fixed";
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regulator-name = "vreg_conn_pa";
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pinctrl-names = "default";
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pinctrl-0 = <&conn_power_pa_active>;
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startup-delay-us = <4000>;
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enable-active-high;
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gpio = <&tlmm 174 0>;
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};
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/* Rome 3.3V supply */
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vreg_wlan: vreg_wlan {
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compatible = "qcom,stub-regulator";
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regulator-name = "vreg_wlan";
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};
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VDD_CX_LEVEL:
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S3E_LEVEL: pm8195_3_s3_level: regulator-pm8195-3-s3-level {
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compatible = "qcom,stub-regulator";
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regulator-name = "pm8195_3_s3_level";
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regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
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regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
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};
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qcom_seecom: qseecom@87a00000 {
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compatible = "qcom,qseecom";
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reg = <0x87a00000 0x2100000>;
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reg-names = "secapp-region";
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memory-region = <&qseecom_mem>;
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qcom,hlos-num-ce-hw-instances = <1>;
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qcom,hlos-ce-hw-instance = <0>;
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qcom,qsee-ce-hw-instance = <0>;
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qcom,disk-encrypt-pipe-pair = <2>;
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qcom,no-clock-support;
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qcom,qsee-reentrancy-support = <2>;
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};
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sdhc_2: sdhci@8804000 {
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compatible = "qcom,sdhci-msm-v5";
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reg = <0x8804000 0x1000>;
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reg-names = "hc_mem";
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interrupts = <0 204 0>, <0 222 0>;
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interrupt-names = "hc_irq", "pwr_irq";
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qcom,bus-width = <4>;
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qcom,large-address-bus;
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qcom,clk-rates = <400000 20000000 25000000
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50000000 100000000 200000000>;
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qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50",
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"SDR104";
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qcom,devfreq,freq-table = <50000000 200000000>;
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qcom,msm-bus,name = "sdhc2";
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qcom,msm-bus,num-cases = <8>;
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qcom,msm-bus,num-paths = <2>;
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qcom,msm-bus,vectors-KBps =
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/* No vote */
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<81 512 0 0>, <1 608 0 0>,
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/* 400 KB/s*/
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<81 512 1046 1600>,
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<1 608 1600 1600>,
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/* 20 MB/s */
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<81 512 52286 80000>,
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<1 608 80000 80000>,
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/* 25 MB/s */
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<81 512 65360 100000>,
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<1 608 100000 100000>,
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/* 50 MB/s */
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<81 512 130718 200000>,
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<1 608 100000 100000>,
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/* 100 MB/s */
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<81 512 261438 200000>,
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<1 608 130000 130000>,
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/* 200 MB/s */
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<81 512 261438 400000>,
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<1 608 300000 300000>,
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/* Max. bandwidth */
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<81 512 1338562 4096000>,
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<1 608 1338562 4096000>;
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qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
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100000000 200000000 4294967295>;
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qcom,restore-after-cx-collapse;
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/* PM QoS */
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qcom,pm-qos-irq-type = "affine_irq";
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qcom,pm-qos-irq-latency = <70 70>;
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qcom,pm-qos-cpu-groups = <0x0f 0xf0>;
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qcom,pm-qos-legacy-latency-us = <70 70>, <70 70>;
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clocks = <&clock_virt GCC_SDCC2_AHB_CLK>,
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<&clock_virt GCC_SDCC2_APPS_CLK>;
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clock-names = "iface_clk", "core_clk";
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vdd-supply = <&pm8195_1_l10>;
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qcom,vdd-voltage-level = <2950000 2960000>;
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qcom,vdd-current-level = <200 800000>;
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vdd-io-supply = <&pm8195_1_l2>;
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qcom,vdd-io-voltage-level = <1808000 2960000>;
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qcom,vdd-io-current-level = <200 22000>;
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pinctrl-names = "active", "sleep";
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pinctrl-0 = <&sdc2_clk_on
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&sdc2_cmd_on &sdc2_data_on &storage_cd_default>;
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pinctrl-1 = <&sdc2_clk_off
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&sdc2_cmd_off &sdc2_data_off &storage_cd_default>;
|
|
|
|
broken-cd;
|
|
status = "disabled";
|
|
};
|
|
|
|
subsys_notif_virt: qcom,subsys_notif_virt@2D000000 {
|
|
compatible = "qcom,subsys-notif-virt";
|
|
reg = <0x2D000000 0x400>;
|
|
reg-names = "vdev_base";
|
|
adsp {
|
|
subsys-name = "adsp";
|
|
interrupts = <0 43 0>;
|
|
interrupt-names = "state-irq";
|
|
type = "virtual";
|
|
offset = <0>;
|
|
};
|
|
wlan {
|
|
subsys-name = "wlan";
|
|
type = "native";
|
|
offset = <512>;
|
|
};
|
|
};
|
|
|
|
bluetooth: bt_qca6174 {
|
|
compatible = "qca,qca6174";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&bt_en_active>;
|
|
/* BT_EN */
|
|
qca,bt-reset-gpio = <&tlmm 172 0>;
|
|
/* PWR_CTR1_VDD_PA */
|
|
qca,bt-vdd-pa-supply = <&vreg_conn_pa>;
|
|
/* PWR_CTR2_VDD_1P8 */
|
|
qca,bt-chip-pwd-supply = <&vreg_conn_1p8>;
|
|
|
|
qca,bt-vdd-vl-supply = <&pm8195_1_s5>;
|
|
qca,bt-vdd-vm-supply = <&pm8195_1_s2>;
|
|
qca,bt-vdd-vh-supply = <&pm8195_2_l7>;
|
|
|
|
qca,bt-vdd-vl-voltage-level = <1000000 1000000>;
|
|
qca,bt-vdd-vm-voltage-level = <1370000 1370000>;
|
|
qca,bt-vdd-vh-voltage-level = <1900000 1900000>;
|
|
|
|
qca,bt-vdd-vl-current-level = <0>;
|
|
qca,bt-vdd-vm-current-level = <0>;
|
|
qca,bt-vdd-vh-current-level = <450000>;
|
|
status = "ok";
|
|
};
|
|
|
|
cnss_pcie: qcom,cnss-qca-converged {
|
|
compatible = "qcom,cnss-qca-converged";
|
|
|
|
qcom,converged-dt;
|
|
qcom,wlan-rc-num = <0>;
|
|
qcom,bus-type=<0>;
|
|
qcom,notify-modem-status;
|
|
qcom,msm-bus,name = "msm-cnss";
|
|
qcom,msm-bus,num-cases = <6>;
|
|
qcom,msm-bus,num-paths = <1>;
|
|
qcom,msm-bus,vectors-KBps =
|
|
/* no vote */
|
|
<MSM_BUS_MASTER_PCIE MSM_BUS_SLAVE_FIRST 0 0>,
|
|
/* idle: 0-18 Mbps, ddr freq: 100 MHz */
|
|
<MSM_BUS_MASTER_PCIE MSM_BUS_SLAVE_FIRST 2250 400000>,
|
|
/* low: 18-60 Mbps, ddr freq: 200 MHz*/
|
|
<MSM_BUS_MASTER_PCIE MSM_BUS_SLAVE_FIRST 7500 800000>,
|
|
/* medium: 60-240 Mbps, ddr freq: 451.2 MHz */
|
|
<MSM_BUS_MASTER_PCIE MSM_BUS_SLAVE_FIRST 30000 1804800>,
|
|
/* high: 240 - 800 Mbps, ddr freq: 451.2 MHz */
|
|
<MSM_BUS_MASTER_PCIE MSM_BUS_SLAVE_FIRST 100000 1804800>,
|
|
/* very high: 800 - 1400 Mbps, ddr freq: 1555.2 MHz */
|
|
<MSM_BUS_MASTER_PCIE MSM_BUS_SLAVE_FIRST 175000 6220800>;
|
|
|
|
#address-cells=<1>;
|
|
#size-cells=<1>;
|
|
ranges = <0x10000000 0x10000000 0x10000000>,
|
|
<0x20000000 0x20000000 0x10000>,
|
|
<0xa0000000 0xa0000000 0x10000000>,
|
|
<0xb0000000 0xb0000000 0x10000>;
|
|
|
|
vdd-wlan-ctrl1-supply = <&vreg_conn_pa>;
|
|
vdd-wlan-ctrl2-supply = <&vreg_conn_1p8>;
|
|
vdd-wlan-supply = <&vreg_wlan>;
|
|
vdd-wlan-aon-supply = <&pm8195_1_s5>;
|
|
vdd-wlan-rfa1-supply = <&pm8195_1_s2>;
|
|
vdd-wlan-rfa2-supply = <&pm8195_2_s5>;
|
|
vdd-wlan-rfa3-supply = <&pm8195_2_l7>;
|
|
|
|
wlan_vregs = "vdd-wlan-ctrl1", "vdd-wlan-ctrl2";
|
|
qcom,vdd-wlan-ctrl1-info = <0 0 0 0>;
|
|
qcom,vdd-wlan-ctrl2-info = <0 0 0 0>;
|
|
wlan-en-gpio = <&tlmm 169 0>;
|
|
pinctrl-names = "wlan_en_active", "wlan_en_sleep";
|
|
pinctrl-0 = <&cnss_wlan_en_active>;
|
|
pinctrl-1 = <&cnss_wlan_en_sleep>;
|
|
|
|
chip_cfg@0 {
|
|
reg = <0x10000000 0x10000000>,
|
|
<0x20000000 0x10000>;
|
|
reg-names = "smmu_iova_base", "smmu_iova_ipa";
|
|
|
|
supported-ids = <0x003e>;
|
|
wlan_vregs = "vdd-wlan";
|
|
qcom,vdd-wlan-info = <0 0 0 10>;
|
|
|
|
qcom,smmu-s1-enable;
|
|
qcom,wlan-ramdump-dynamic = <0x200000>;
|
|
};
|
|
|
|
chip_cfg@1 {
|
|
reg = <0xa0000000 0x10000000>,
|
|
<0xb0000000 0x10000>;
|
|
reg-names = "smmu_iova_base", "smmu_iova_ipa";
|
|
|
|
supported-ids = <0x1101>;
|
|
wlan_vregs = "vdd-wlan-aon", "vdd-wlan-rfa1",
|
|
"vdd-wlan-rfa2", "vdd-wlan-rfa3";
|
|
qcom,vdd-wlan-aon-info = <1000000 1000000 0 0>;
|
|
qcom,vdd-wlan-rfa1-info = <1370000 1370000 0 0>;
|
|
qcom,vdd-wlan-rfa2-info = <2040000 2040000 0 0>;
|
|
qcom,vdd-wlan-rfa3-info = <1900000 1900000 450000 0>;
|
|
qcom,wlan-ramdump-dynamic = <0x400000>;
|
|
mhi,max-channels = <30>;
|
|
mhi,timeout = <10000>;
|
|
|
|
mhi_channels {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
mhi_chan@0 {
|
|
reg = <0>;
|
|
label = "LOOPBACK";
|
|
mhi,num-elements = <32>;
|
|
mhi,event-ring = <1>;
|
|
mhi,chan-dir = <1>;
|
|
mhi,data-type = <0>;
|
|
mhi,doorbell-mode = <2>;
|
|
mhi,ee = <0x14>;
|
|
};
|
|
|
|
mhi_chan@1 {
|
|
reg = <1>;
|
|
label = "LOOPBACK";
|
|
mhi,num-elements = <32>;
|
|
mhi,event-ring = <1>;
|
|
mhi,chan-dir = <2>;
|
|
mhi,data-type = <0>;
|
|
mhi,doorbell-mode = <2>;
|
|
mhi,ee = <0x14>;
|
|
};
|
|
|
|
mhi_chan@4 {
|
|
reg = <4>;
|
|
label = "DIAG";
|
|
mhi,num-elements = <32>;
|
|
mhi,event-ring = <1>;
|
|
mhi,chan-dir = <1>;
|
|
mhi,data-type = <0>;
|
|
mhi,doorbell-mode = <2>;
|
|
mhi,ee = <0x14>;
|
|
};
|
|
|
|
mhi_chan@5 {
|
|
reg = <5>;
|
|
label = "DIAG";
|
|
mhi,num-elements = <32>;
|
|
mhi,event-ring = <1>;
|
|
mhi,chan-dir = <2>;
|
|
mhi,data-type = <0>;
|
|
mhi,doorbell-mode = <2>;
|
|
mhi,ee = <0x14>;
|
|
};
|
|
|
|
mhi_chan@20 {
|
|
reg = <20>;
|
|
label = "IPCR";
|
|
mhi,num-elements = <32>;
|
|
mhi,event-ring = <1>;
|
|
mhi,chan-dir = <1>;
|
|
mhi,data-type = <1>;
|
|
mhi,doorbell-mode = <2>;
|
|
mhi,ee = <0x14>;
|
|
mhi,auto-start;
|
|
};
|
|
|
|
mhi_chan@21 {
|
|
reg = <21>;
|
|
label = "IPCR";
|
|
mhi,num-elements = <32>;
|
|
mhi,event-ring = <1>;
|
|
mhi,chan-dir = <2>;
|
|
mhi,data-type = <0>;
|
|
mhi,doorbell-mode = <2>;
|
|
mhi,ee = <0x14>;
|
|
mhi,auto-queue;
|
|
mhi,auto-start;
|
|
};
|
|
};
|
|
|
|
mhi_events {
|
|
mhi_event@0 {
|
|
mhi,num-elements = <32>;
|
|
mhi,intmod = <1>;
|
|
mhi,msi = <1>;
|
|
mhi,priority = <1>;
|
|
mhi,brstmode = <2>;
|
|
mhi,data-type = <1>;
|
|
};
|
|
|
|
mhi_event@1 {
|
|
mhi,num-elements = <256>;
|
|
mhi,intmod = <1>;
|
|
mhi,msi = <2>;
|
|
mhi,priority = <1>;
|
|
mhi,brstmode = <2>;
|
|
};
|
|
};
|
|
};
|
|
|
|
chip_cfg@2 {
|
|
reg = <0xa0000000 0x10000000>,
|
|
<0xb0000000 0x10000>;
|
|
reg-names = "smmu_iova_base", "smmu_iova_ipa";
|
|
|
|
supported-ids = <0x1102>;
|
|
wlan_vregs = "vdd-wlan-aon", "vdd-wlan-rfa1",
|
|
"vdd-wlan-rfa2", "vdd-wlan-rfa3";
|
|
qcom,vdd-wlan-aon-info = <1000000 1000000 0 0>;
|
|
qcom,vdd-wlan-rfa1-info = <1370000 1370000 0 0>;
|
|
qcom,vdd-wlan-rfa2-info = <2040000 2040000 0 0>;
|
|
qcom,vdd-wlan-rfa3-info = <1900000 1900000 0 0>;
|
|
|
|
qcom,wlan-ramdump-dynamic = <0x300000>;
|
|
mhi,max-channels = <30>;
|
|
mhi,timeout = <10000>;
|
|
mhi,ee = <0x3>, <0x4>;
|
|
mhi,ee-names = "SBL", "RDDM";
|
|
mhi,bhie-offset = <0x0324>;
|
|
|
|
mhi_channels {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
mhi_chan@0 {
|
|
reg = <0>;
|
|
label = "LOOPBACK";
|
|
mhi,num-elements = <32>;
|
|
mhi,event-ring = <1>;
|
|
mhi,chan-dir = <1>;
|
|
mhi,data-type = <0>;
|
|
mhi,doorbell-mode = <2>;
|
|
mhi,ee = <0x14>;
|
|
};
|
|
|
|
mhi_chan@1 {
|
|
reg = <1>;
|
|
label = "LOOPBACK";
|
|
mhi,num-elements = <32>;
|
|
mhi,event-ring = <1>;
|
|
mhi,chan-dir = <2>;
|
|
mhi,data-type = <0>;
|
|
mhi,doorbell-mode = <2>;
|
|
mhi,ee = <0x14>;
|
|
};
|
|
|
|
mhi_chan@4 {
|
|
reg = <4>;
|
|
label = "DIAG";
|
|
mhi,num-elements = <32>;
|
|
mhi,event-ring = <1>;
|
|
mhi,chan-dir = <1>;
|
|
mhi,data-type = <0>;
|
|
mhi,doorbell-mode = <2>;
|
|
mhi,ee = <0x14>;
|
|
};
|
|
|
|
mhi_chan@5 {
|
|
reg = <5>;
|
|
label = "DIAG";
|
|
mhi,num-elements = <32>;
|
|
mhi,event-ring = <1>;
|
|
mhi,chan-dir = <2>;
|
|
mhi,data-type = <0>;
|
|
mhi,doorbell-mode = <2>;
|
|
mhi,ee = <0x14>;
|
|
};
|
|
|
|
mhi_chan@16 {
|
|
reg = <16>;
|
|
label = "IPCR";
|
|
mhi,num-elements = <32>;
|
|
mhi,event-ring = <1>;
|
|
mhi,chan-dir = <1>;
|
|
mhi,data-type = <1>;
|
|
mhi,doorbell-mode = <2>;
|
|
mhi,ee = <0x14>;
|
|
mhi,auto-start;
|
|
};
|
|
|
|
mhi_chan@17 {
|
|
reg = <17>;
|
|
label = "IPCR";
|
|
mhi,num-elements = <32>;
|
|
mhi,event-ring = <1>;
|
|
mhi,chan-dir = <2>;
|
|
mhi,data-type = <0>;
|
|
mhi,doorbell-mode = <2>;
|
|
mhi,ee = <0x14>;
|
|
mhi,auto-queue;
|
|
mhi,auto-start;
|
|
};
|
|
};
|
|
|
|
mhi_events {
|
|
mhi_event@0 {
|
|
mhi,num-elements = <32>;
|
|
mhi,intmod = <1>;
|
|
mhi,msi = <1>;
|
|
mhi,priority = <1>;
|
|
mhi,brstmode = <2>;
|
|
mhi,data-type = <1>;
|
|
};
|
|
|
|
mhi_event@1 {
|
|
mhi,num-elements = <256>;
|
|
mhi,intmod = <1>;
|
|
mhi,msi = <2>;
|
|
mhi,priority = <1>;
|
|
mhi,brstmode = <2>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom_rng: qrng@793000 {
|
|
compatible = "qcom,msm-rng";
|
|
reg = <0x793000 0x1000>;
|
|
qcom,msm-rng-iface-clk;
|
|
qcom,no-qrng-config;
|
|
qcom,msm-bus,name = "msm-rng-noc";
|
|
qcom,msm-bus,num-cases = <2>;
|
|
qcom,msm-bus,num-paths = <1>;
|
|
qcom,msm-bus,vectors-KBps =
|
|
<1 618 0 0>, /* No vote */
|
|
<1 618 0 300000>; /* 75 MHz */
|
|
clocks = <&clock_virt GCC_PRNG_AHB_CLK>;
|
|
clock-names = "iface_clk";
|
|
};
|
|
|
|
tcsr_compute_signal_glb: syscon@0x1fd8000 {
|
|
compatible = "syscon";
|
|
reg = <0x1fd8000 0x1000>;
|
|
};
|
|
|
|
tcsr_compute_signal_sender0: syscon@0x1fd9000 {
|
|
compatible = "syscon";
|
|
reg = <0x1fd9000 0x1000>;
|
|
};
|
|
|
|
tcsr_compute_signal_sender1: syscon@0x1fdd000 {
|
|
compatible = "syscon";
|
|
reg = <0x1fdd000 0x1000>;
|
|
};
|
|
|
|
tcsr_compute_signal_receiver0: syscon@0x1fdb000 {
|
|
compatible = "syscon";
|
|
reg = <0x1fdb000 0x1000>;
|
|
};
|
|
|
|
tcsr_compute_signal_receiver1: syscon@0x1fdf000 {
|
|
compatible = "syscon";
|
|
reg = <0x1fdf000 0x1000>;
|
|
};
|
|
|
|
hgsl_tcsr_sender0: hgsl_tcsr_sender0 {
|
|
compatible = "qcom,hgsl-tcsr-sender";
|
|
syscon = <&tcsr_compute_signal_sender0>;
|
|
syscon-glb = <&tcsr_compute_signal_glb>;
|
|
};
|
|
|
|
hgsl_tcsr_sender1: hgsl_tcsr_sender1 {
|
|
compatible = "qcom,hgsl-tcsr-sender";
|
|
syscon = <&tcsr_compute_signal_sender1>;
|
|
syscon-glb = <&tcsr_compute_signal_glb>;
|
|
};
|
|
|
|
hgsl_tcsr_receiver0: hgsl_tcsr_receiver0 {
|
|
compatible = "qcom,hgsl-tcsr-receiver";
|
|
syscon = <&tcsr_compute_signal_receiver0>;
|
|
interrupts = <0 238 0>;
|
|
};
|
|
|
|
hgsl_tcsr_receiver1: hgsl_tcsr_receiver1 {
|
|
compatible = "qcom,hgsl-tcsr-receiver";
|
|
syscon = <&tcsr_compute_signal_receiver1>;
|
|
interrupts = <0 239 0>;
|
|
};
|
|
|
|
msm_gpu_hyp: qcom,hgsl@0x2c00000 {
|
|
compatible = "qcom,hgsl";
|
|
reg = <0x2c00000 0x8>, <0x2c8f000 0x4>;
|
|
reg-names = "hgsl_reg_hwinf", "hgsl_reg_gmucx";
|
|
|
|
qcom,glb-db-senders = <&hgsl_tcsr_sender0
|
|
&hgsl_tcsr_sender1>;
|
|
qcom,glb-db-receivers = <&hgsl_tcsr_receiver0
|
|
&hgsl_tcsr_receiver1>;
|
|
};
|
|
};
|
|
|
|
#include "sdmshrike-pinctrl.dtsi"
|
|
#include "sm8150-slpi-pinctrl.dtsi"
|
|
#include "sa8155-vm-qupv3.dtsi"
|
|
#include "sa8195-vm-usb.dtsi"
|
|
#include "sa8155-vm-audio.dtsi"
|
|
#include "sa8195-vm-pcie.dtsi"
|
|
#include "pm8195-vm.dtsi"
|
|
|
|
&tlmm {
|
|
dirconn-list = <37 216 1>;
|
|
};
|