audio: 2024/02/29 Fortemedia table check in
<change list>
TK4
- Handset (Ricky)
1. HAWB Modify TdDRC expander as short term for BWE noise issue on (max to max-2)
- Handsfree (Ricky)
1. HHSWB fine tune (max-1 to min) for EVT1.1
2. HHWB fine tune for EVT1.1
TX/RX: PreEQ, TdDRC, EQ
- Headset (Gene)
1. HE WB: Mitigate the NB call RX noise after speech due to noise from NW and boosted by BWE.
2. HE WB: Enable 120Hz HFP for both TX and RX
3. HE WB Rx FNS level from 0x0006 to 0x000F for CCA BWE
- BT (Gene)
1. BTWB and BTWB_NREC WB Rx FNS level from 0x0006 to 0x000F for CCA BWE
CM4
- Headset (Gene)
1. HE WB: Mitigate the NB call RX noise after speech due to noise from NW and boosted by BWE.
2. HE WB: Enable 120Hz HFP for both TX and RX
3. HE WB Rx FNS level from 0x0006 to 0x000F for CCA BWE
- BT (Gene)
1. BTWB and BTWB_NREC WB Rx FNS level from 0x0006 to 0x000F for CCA BWE
KM4
- Headset (Gene)
1. HE WB: Mitigate the NB call RX noise after speech due to noise from NW and boosted by BWE.
2. HE WB: Enable 120Hz HFP for both TX and RX
3. HE WB Rx FNS level from 0x0006 to 0x000F for CCA BWE
Bug: 327555914
Test: Verified by Acoustic team
Change-Id: I2939312348ac6d9a13ac4be86460d49839b545ca
Signed-off-by: Carter Hsu <carterhsu@google.com>
(cherry picked from commit 2678747eae
)
This commit is contained in:
parent
2bda846652
commit
32eb2b8931
23 changed files with 761 additions and 761 deletions
Binary file not shown.
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@ -3,7 +3,7 @@
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#EXPORT_FLAG BLUETOOTH
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#PARAM_MODE FULL
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#SAVE_MODE 3
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#SAVE_TIME 2024-02-02 11:42:47
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#SAVE_TIME 2024-02-29 15:54:35
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#CASE_NAME BLUETOOTH-BT_HAC-VOICE_GENERIC-NB
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#PARAM_TYPE TX+2RX
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@ -44140,7 +44140,7 @@
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19 0x0020 //RX_PP_RESRV_1
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20 0x0600 //RX_N_SN_EST
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21 0x000C //RX_N2_SN_EST
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22 0x0006 //RX_NS_LVL_CTRL
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22 0x000F //RX_NS_LVL_CTRL
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23 0xF800 //RX_THR_SN_EST
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24 0x7CCD //RX_LAMBDA_PFILT
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25 0x000A //RX_MUTE_PERIOD
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@ -57615,7 +57615,7 @@
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19 0x0020 //RX_PP_RESRV_1
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20 0x0600 //RX_N_SN_EST
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21 0x000C //RX_N2_SN_EST
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22 0x0006 //RX_NS_LVL_CTRL
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22 0x000F //RX_NS_LVL_CTRL
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23 0xF800 //RX_THR_SN_EST
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24 0x7CCD //RX_LAMBDA_PFILT
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25 0x000A //RX_MUTE_PERIOD
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@ -3,7 +3,7 @@
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#EXPORT_FLAG HANDSET
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#PARAM_MODE FULL
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#SAVE_MODE 3
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#SAVE_TIME 2024-02-02 11:42:46
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#SAVE_TIME 2024-02-29 16:13:14
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#CASE_NAME HANDSET-HANDSET-VOICE_GENERIC-NB
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#PARAM_TYPE TX+2RX
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@ -3693,7 +3693,7 @@
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986 0x0000 //TX_EASSA_AEC_NSSA_REFG_REFBLK_0
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987 0x0000 //TX_EASSA_AEC_NSSA_REFG_REFBLK_1
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#RX
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0 0x243C //RX_RECVFUNC_MODE_0
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0 0x247C //RX_RECVFUNC_MODE_0
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1 0x0002 //RX_RECVFUNC_MODE_1
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2 0x0001 //RX_SAMPLINGFREQ_SIG
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3 0x0001 //RX_SAMPLINGFREQ_PROC
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@ -3855,20 +3855,20 @@
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7 0x1000 //RX_TDDRC_ALPHA_UP_2
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8 0x1000 //RX_TDDRC_ALPHA_UP_3
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9 0x1000 //RX_TDDRC_ALPHA_UP_4
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27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1
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27 0x7000 //RX_TDDRC_ALPHA_DWN_1
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28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2
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29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3
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32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4
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33 0x5A9D //RX_TDDRC_LIMITER_THRD
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34 0x0800 //RX_TDDRC_LIMITER_GAIN
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112 0x0000 //RX_TDDRC_THRD_0
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113 0x0001 //RX_TDDRC_THRD_1
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113 0x0008 //RX_TDDRC_THRD_1
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114 0x1800 //RX_TDDRC_THRD_2
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115 0x1800 //RX_TDDRC_THRD_3
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116 0x3000 //RX_TDDRC_SLANT_0
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117 0x7FFF //RX_TDDRC_SLANT_1
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118 0x1000 //RX_TDDRC_ALPHA_UP_0
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119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0
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119 0x7000 //RX_TDDRC_ALPHA_DWN_0
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120 0x0000 //RX_TDDRC_HMNC_FLAG
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121 0x199A //RX_TDDRC_HMNC_GAIN
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122 0x0001 //RX_TDDRC_SMT_FLAG
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@ -3954,20 +3954,20 @@
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7 0x1000 //RX_TDDRC_ALPHA_UP_2
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8 0x1000 //RX_TDDRC_ALPHA_UP_3
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9 0x1000 //RX_TDDRC_ALPHA_UP_4
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27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1
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27 0x7000 //RX_TDDRC_ALPHA_DWN_1
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28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2
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29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3
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32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4
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33 0x5A9D //RX_TDDRC_LIMITER_THRD
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34 0x0800 //RX_TDDRC_LIMITER_GAIN
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112 0x0000 //RX_TDDRC_THRD_0
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113 0x0001 //RX_TDDRC_THRD_1
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113 0x0008 //RX_TDDRC_THRD_1
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114 0x1800 //RX_TDDRC_THRD_2
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115 0x1800 //RX_TDDRC_THRD_3
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116 0x3000 //RX_TDDRC_SLANT_0
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117 0x7FFF //RX_TDDRC_SLANT_1
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118 0x1000 //RX_TDDRC_ALPHA_UP_0
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119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0
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119 0x7000 //RX_TDDRC_ALPHA_DWN_0
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120 0x0000 //RX_TDDRC_HMNC_FLAG
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121 0x199A //RX_TDDRC_HMNC_GAIN
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122 0x0001 //RX_TDDRC_SMT_FLAG
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@ -4053,20 +4053,20 @@
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7 0x1000 //RX_TDDRC_ALPHA_UP_2
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8 0x1000 //RX_TDDRC_ALPHA_UP_3
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9 0x1000 //RX_TDDRC_ALPHA_UP_4
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27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1
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27 0x7000 //RX_TDDRC_ALPHA_DWN_1
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28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2
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29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3
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32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4
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33 0x5A9D //RX_TDDRC_LIMITER_THRD
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34 0x0800 //RX_TDDRC_LIMITER_GAIN
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112 0x0000 //RX_TDDRC_THRD_0
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113 0x0001 //RX_TDDRC_THRD_1
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113 0x0008 //RX_TDDRC_THRD_1
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114 0x1800 //RX_TDDRC_THRD_2
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115 0x1800 //RX_TDDRC_THRD_3
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116 0x3000 //RX_TDDRC_SLANT_0
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117 0x7FFF //RX_TDDRC_SLANT_1
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118 0x1000 //RX_TDDRC_ALPHA_UP_0
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119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0
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119 0x7000 //RX_TDDRC_ALPHA_DWN_0
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120 0x0000 //RX_TDDRC_HMNC_FLAG
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121 0x199A //RX_TDDRC_HMNC_GAIN
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122 0x0001 //RX_TDDRC_SMT_FLAG
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@ -4152,20 +4152,20 @@
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7 0x1000 //RX_TDDRC_ALPHA_UP_2
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8 0x1000 //RX_TDDRC_ALPHA_UP_3
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9 0x1000 //RX_TDDRC_ALPHA_UP_4
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27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1
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27 0x7000 //RX_TDDRC_ALPHA_DWN_1
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28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2
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29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3
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32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4
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33 0x5A9D //RX_TDDRC_LIMITER_THRD
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34 0x0800 //RX_TDDRC_LIMITER_GAIN
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112 0x0000 //RX_TDDRC_THRD_0
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113 0x0001 //RX_TDDRC_THRD_1
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113 0x0008 //RX_TDDRC_THRD_1
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114 0x1800 //RX_TDDRC_THRD_2
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115 0x1800 //RX_TDDRC_THRD_3
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116 0x3000 //RX_TDDRC_SLANT_0
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117 0x7FFF //RX_TDDRC_SLANT_1
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118 0x1000 //RX_TDDRC_ALPHA_UP_0
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119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0
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119 0x7000 //RX_TDDRC_ALPHA_DWN_0
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120 0x0000 //RX_TDDRC_HMNC_FLAG
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121 0x199A //RX_TDDRC_HMNC_GAIN
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122 0x0001 //RX_TDDRC_SMT_FLAG
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@ -4251,20 +4251,20 @@
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7 0x1000 //RX_TDDRC_ALPHA_UP_2
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8 0x1000 //RX_TDDRC_ALPHA_UP_3
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9 0x1000 //RX_TDDRC_ALPHA_UP_4
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27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1
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27 0x1000 //RX_TDDRC_ALPHA_DWN_1
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28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2
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29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3
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32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4
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33 0x5A9D //RX_TDDRC_LIMITER_THRD
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34 0x0800 //RX_TDDRC_LIMITER_GAIN
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112 0x0000 //RX_TDDRC_THRD_0
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113 0x0001 //RX_TDDRC_THRD_1
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112 0x0008 //RX_TDDRC_THRD_0
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113 0x0800 //RX_TDDRC_THRD_1
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114 0x1800 //RX_TDDRC_THRD_2
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115 0x1800 //RX_TDDRC_THRD_3
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116 0x3000 //RX_TDDRC_SLANT_0
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117 0x7FFF //RX_TDDRC_SLANT_1
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118 0x1000 //RX_TDDRC_ALPHA_UP_0
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119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0
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119 0x7000 //RX_TDDRC_ALPHA_DWN_0
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120 0x0000 //RX_TDDRC_HMNC_FLAG
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121 0x199A //RX_TDDRC_HMNC_GAIN
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122 0x0001 //RX_TDDRC_SMT_FLAG
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7 0x1000 //RX_TDDRC_ALPHA_UP_2
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8 0x1000 //RX_TDDRC_ALPHA_UP_3
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9 0x1000 //RX_TDDRC_ALPHA_UP_4
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27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1
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27 0x1000 //RX_TDDRC_ALPHA_DWN_1
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28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2
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29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3
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32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4
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33 0x5A9D //RX_TDDRC_LIMITER_THRD
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34 0x0800 //RX_TDDRC_LIMITER_GAIN
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112 0x0000 //RX_TDDRC_THRD_0
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113 0x0001 //RX_TDDRC_THRD_1
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112 0x0008 //RX_TDDRC_THRD_0
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113 0x0800 //RX_TDDRC_THRD_1
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114 0x1800 //RX_TDDRC_THRD_2
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115 0x1800 //RX_TDDRC_THRD_3
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116 0x3000 //RX_TDDRC_SLANT_0
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117 0x7FFF //RX_TDDRC_SLANT_1
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118 0x1000 //RX_TDDRC_ALPHA_UP_0
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119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0
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119 0x7000 //RX_TDDRC_ALPHA_DWN_0
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120 0x0000 //RX_TDDRC_HMNC_FLAG
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121 0x199A //RX_TDDRC_HMNC_GAIN
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122 0x0001 //RX_TDDRC_SMT_FLAG
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7 0x1000 //RX_TDDRC_ALPHA_UP_2
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8 0x1000 //RX_TDDRC_ALPHA_UP_3
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9 0x1000 //RX_TDDRC_ALPHA_UP_4
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27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1
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27 0x1000 //RX_TDDRC_ALPHA_DWN_1
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28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2
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29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3
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32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4
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33 0x5A9D //RX_TDDRC_LIMITER_THRD
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34 0x0800 //RX_TDDRC_LIMITER_GAIN
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112 0x0000 //RX_TDDRC_THRD_0
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113 0x0001 //RX_TDDRC_THRD_1
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112 0x0008 //RX_TDDRC_THRD_0
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113 0x0800 //RX_TDDRC_THRD_1
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114 0x1800 //RX_TDDRC_THRD_2
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115 0x1800 //RX_TDDRC_THRD_3
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116 0x3000 //RX_TDDRC_SLANT_0
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117 0x7FFF //RX_TDDRC_SLANT_1
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118 0x1000 //RX_TDDRC_ALPHA_UP_0
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119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0
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119 0x7000 //RX_TDDRC_ALPHA_DWN_0
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120 0x0000 //RX_TDDRC_HMNC_FLAG
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121 0x199A //RX_TDDRC_HMNC_GAIN
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122 0x0001 //RX_TDDRC_SMT_FLAG
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129 0x0100 //RX_SPK_VOL
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130 0x0000 //RX_VOL_RESRV_0
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#RX 2
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157 0x243C //RX_RECVFUNC_MODE_0
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157 0x247C //RX_RECVFUNC_MODE_0
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158 0x0002 //RX_RECVFUNC_MODE_1
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159 0x0001 //RX_SAMPLINGFREQ_SIG
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160 0x0001 //RX_SAMPLINGFREQ_PROC
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190 0x5A9D //RX_TDDRC_LIMITER_THRD
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191 0x0800 //RX_TDDRC_LIMITER_GAIN
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269 0x0000 //RX_TDDRC_THRD_0
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270 0x0001 //RX_TDDRC_THRD_1
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270 0x0008 //RX_TDDRC_THRD_1
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271 0x1800 //RX_TDDRC_THRD_2
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272 0x1800 //RX_TDDRC_THRD_3
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273 0x3000 //RX_TDDRC_SLANT_0
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190 0x5A9D //RX_TDDRC_LIMITER_THRD
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191 0x0800 //RX_TDDRC_LIMITER_GAIN
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269 0x0000 //RX_TDDRC_THRD_0
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270 0x0001 //RX_TDDRC_THRD_1
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270 0x0008 //RX_TDDRC_THRD_1
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271 0x1800 //RX_TDDRC_THRD_2
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272 0x1800 //RX_TDDRC_THRD_3
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273 0x3000 //RX_TDDRC_SLANT_0
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190 0x5A9D //RX_TDDRC_LIMITER_THRD
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191 0x0800 //RX_TDDRC_LIMITER_GAIN
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269 0x0000 //RX_TDDRC_THRD_0
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270 0x0001 //RX_TDDRC_THRD_1
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270 0x0008 //RX_TDDRC_THRD_1
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271 0x1800 //RX_TDDRC_THRD_2
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272 0x1800 //RX_TDDRC_THRD_3
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273 0x3000 //RX_TDDRC_SLANT_0
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190 0x5A9D //RX_TDDRC_LIMITER_THRD
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191 0x0800 //RX_TDDRC_LIMITER_GAIN
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269 0x0000 //RX_TDDRC_THRD_0
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270 0x0001 //RX_TDDRC_THRD_1
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270 0x0008 //RX_TDDRC_THRD_1
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271 0x1800 //RX_TDDRC_THRD_2
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272 0x1800 //RX_TDDRC_THRD_3
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273 0x3000 //RX_TDDRC_SLANT_0
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@ -5108,8 +5108,8 @@
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189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4
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190 0x5A9D //RX_TDDRC_LIMITER_THRD
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191 0x0800 //RX_TDDRC_LIMITER_GAIN
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269 0x0000 //RX_TDDRC_THRD_0
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270 0x0001 //RX_TDDRC_THRD_1
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269 0x0008 //RX_TDDRC_THRD_0
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270 0x0800 //RX_TDDRC_THRD_1
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271 0x1800 //RX_TDDRC_THRD_2
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272 0x1800 //RX_TDDRC_THRD_3
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273 0x3000 //RX_TDDRC_SLANT_0
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@ -5207,8 +5207,8 @@
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189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4
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190 0x5A9D //RX_TDDRC_LIMITER_THRD
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191 0x0800 //RX_TDDRC_LIMITER_GAIN
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269 0x0000 //RX_TDDRC_THRD_0
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270 0x0001 //RX_TDDRC_THRD_1
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269 0x0008 //RX_TDDRC_THRD_0
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270 0x0800 //RX_TDDRC_THRD_1
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271 0x1800 //RX_TDDRC_THRD_2
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272 0x1800 //RX_TDDRC_THRD_3
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273 0x3000 //RX_TDDRC_SLANT_0
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@ -5306,8 +5306,8 @@
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189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4
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190 0x5A9D //RX_TDDRC_LIMITER_THRD
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191 0x0800 //RX_TDDRC_LIMITER_GAIN
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269 0x0000 //RX_TDDRC_THRD_0
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270 0x0001 //RX_TDDRC_THRD_1
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269 0x0008 //RX_TDDRC_THRD_0
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270 0x0800 //RX_TDDRC_THRD_1
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271 0x1800 //RX_TDDRC_THRD_2
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272 0x1800 //RX_TDDRC_THRD_3
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273 0x3000 //RX_TDDRC_SLANT_0
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@ -14473,7 +14473,7 @@
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986 0x0000 //TX_EASSA_AEC_NSSA_REFG_REFBLK_0
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987 0x0000 //TX_EASSA_AEC_NSSA_REFG_REFBLK_1
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#RX
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0 0x243C //RX_RECVFUNC_MODE_0
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0 0x247C //RX_RECVFUNC_MODE_0
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1 0x0002 //RX_RECVFUNC_MODE_1
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2 0x0001 //RX_SAMPLINGFREQ_SIG
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3 0x0001 //RX_SAMPLINGFREQ_PROC
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@ -14635,20 +14635,20 @@
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|||
7 0x1000 //RX_TDDRC_ALPHA_UP_2
|
||||
8 0x1000 //RX_TDDRC_ALPHA_UP_3
|
||||
9 0x1000 //RX_TDDRC_ALPHA_UP_4
|
||||
27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1
|
||||
27 0x7000 //RX_TDDRC_ALPHA_DWN_1
|
||||
28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2
|
||||
29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3
|
||||
32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4
|
||||
33 0x5A9D //RX_TDDRC_LIMITER_THRD
|
||||
34 0x0800 //RX_TDDRC_LIMITER_GAIN
|
||||
112 0x0000 //RX_TDDRC_THRD_0
|
||||
113 0x0001 //RX_TDDRC_THRD_1
|
||||
113 0x0008 //RX_TDDRC_THRD_1
|
||||
114 0x1800 //RX_TDDRC_THRD_2
|
||||
115 0x1800 //RX_TDDRC_THRD_3
|
||||
116 0x3000 //RX_TDDRC_SLANT_0
|
||||
117 0x7FFF //RX_TDDRC_SLANT_1
|
||||
118 0x1000 //RX_TDDRC_ALPHA_UP_0
|
||||
119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0
|
||||
119 0x7000 //RX_TDDRC_ALPHA_DWN_0
|
||||
120 0x0000 //RX_TDDRC_HMNC_FLAG
|
||||
121 0x199A //RX_TDDRC_HMNC_GAIN
|
||||
122 0x0001 //RX_TDDRC_SMT_FLAG
|
||||
|
@ -14734,20 +14734,20 @@
|
|||
7 0x1000 //RX_TDDRC_ALPHA_UP_2
|
||||
8 0x1000 //RX_TDDRC_ALPHA_UP_3
|
||||
9 0x1000 //RX_TDDRC_ALPHA_UP_4
|
||||
27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1
|
||||
27 0x7000 //RX_TDDRC_ALPHA_DWN_1
|
||||
28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2
|
||||
29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3
|
||||
32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4
|
||||
33 0x5A9D //RX_TDDRC_LIMITER_THRD
|
||||
34 0x0800 //RX_TDDRC_LIMITER_GAIN
|
||||
112 0x0000 //RX_TDDRC_THRD_0
|
||||
113 0x0001 //RX_TDDRC_THRD_1
|
||||
113 0x0008 //RX_TDDRC_THRD_1
|
||||
114 0x1800 //RX_TDDRC_THRD_2
|
||||
115 0x1800 //RX_TDDRC_THRD_3
|
||||
116 0x3000 //RX_TDDRC_SLANT_0
|
||||
117 0x7FFF //RX_TDDRC_SLANT_1
|
||||
118 0x1000 //RX_TDDRC_ALPHA_UP_0
|
||||
119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0
|
||||
119 0x7000 //RX_TDDRC_ALPHA_DWN_0
|
||||
120 0x0000 //RX_TDDRC_HMNC_FLAG
|
||||
121 0x199A //RX_TDDRC_HMNC_GAIN
|
||||
122 0x0001 //RX_TDDRC_SMT_FLAG
|
||||
|
@ -14833,20 +14833,20 @@
|
|||
7 0x1000 //RX_TDDRC_ALPHA_UP_2
|
||||
8 0x1000 //RX_TDDRC_ALPHA_UP_3
|
||||
9 0x1000 //RX_TDDRC_ALPHA_UP_4
|
||||
27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1
|
||||
27 0x7000 //RX_TDDRC_ALPHA_DWN_1
|
||||
28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2
|
||||
29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3
|
||||
32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4
|
||||
33 0x5A9D //RX_TDDRC_LIMITER_THRD
|
||||
34 0x0800 //RX_TDDRC_LIMITER_GAIN
|
||||
112 0x0000 //RX_TDDRC_THRD_0
|
||||
113 0x0001 //RX_TDDRC_THRD_1
|
||||
113 0x0008 //RX_TDDRC_THRD_1
|
||||
114 0x1800 //RX_TDDRC_THRD_2
|
||||
115 0x1800 //RX_TDDRC_THRD_3
|
||||
116 0x3000 //RX_TDDRC_SLANT_0
|
||||
117 0x7FFF //RX_TDDRC_SLANT_1
|
||||
118 0x1000 //RX_TDDRC_ALPHA_UP_0
|
||||
119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0
|
||||
119 0x7000 //RX_TDDRC_ALPHA_DWN_0
|
||||
120 0x0000 //RX_TDDRC_HMNC_FLAG
|
||||
121 0x199A //RX_TDDRC_HMNC_GAIN
|
||||
122 0x0001 //RX_TDDRC_SMT_FLAG
|
||||
|
@ -14932,20 +14932,20 @@
|
|||
7 0x1000 //RX_TDDRC_ALPHA_UP_2
|
||||
8 0x1000 //RX_TDDRC_ALPHA_UP_3
|
||||
9 0x1000 //RX_TDDRC_ALPHA_UP_4
|
||||
27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1
|
||||
27 0x7000 //RX_TDDRC_ALPHA_DWN_1
|
||||
28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2
|
||||
29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3
|
||||
32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4
|
||||
33 0x5A9D //RX_TDDRC_LIMITER_THRD
|
||||
34 0x0800 //RX_TDDRC_LIMITER_GAIN
|
||||
112 0x0000 //RX_TDDRC_THRD_0
|
||||
113 0x0001 //RX_TDDRC_THRD_1
|
||||
113 0x0008 //RX_TDDRC_THRD_1
|
||||
114 0x1800 //RX_TDDRC_THRD_2
|
||||
115 0x1800 //RX_TDDRC_THRD_3
|
||||
116 0x3000 //RX_TDDRC_SLANT_0
|
||||
117 0x7FFF //RX_TDDRC_SLANT_1
|
||||
118 0x1000 //RX_TDDRC_ALPHA_UP_0
|
||||
119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0
|
||||
119 0x7000 //RX_TDDRC_ALPHA_DWN_0
|
||||
120 0x0000 //RX_TDDRC_HMNC_FLAG
|
||||
121 0x199A //RX_TDDRC_HMNC_GAIN
|
||||
122 0x0001 //RX_TDDRC_SMT_FLAG
|
||||
|
@ -15031,20 +15031,20 @@
|
|||
7 0x1000 //RX_TDDRC_ALPHA_UP_2
|
||||
8 0x1000 //RX_TDDRC_ALPHA_UP_3
|
||||
9 0x1000 //RX_TDDRC_ALPHA_UP_4
|
||||
27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1
|
||||
27 0x1000 //RX_TDDRC_ALPHA_DWN_1
|
||||
28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2
|
||||
29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3
|
||||
32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4
|
||||
33 0x5A9D //RX_TDDRC_LIMITER_THRD
|
||||
34 0x0800 //RX_TDDRC_LIMITER_GAIN
|
||||
112 0x0000 //RX_TDDRC_THRD_0
|
||||
113 0x0001 //RX_TDDRC_THRD_1
|
||||
112 0x0008 //RX_TDDRC_THRD_0
|
||||
113 0x0800 //RX_TDDRC_THRD_1
|
||||
114 0x1800 //RX_TDDRC_THRD_2
|
||||
115 0x1800 //RX_TDDRC_THRD_3
|
||||
116 0x3000 //RX_TDDRC_SLANT_0
|
||||
117 0x7FFF //RX_TDDRC_SLANT_1
|
||||
118 0x1000 //RX_TDDRC_ALPHA_UP_0
|
||||
119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0
|
||||
119 0x7000 //RX_TDDRC_ALPHA_DWN_0
|
||||
120 0x0000 //RX_TDDRC_HMNC_FLAG
|
||||
121 0x199A //RX_TDDRC_HMNC_GAIN
|
||||
122 0x0001 //RX_TDDRC_SMT_FLAG
|
||||
|
@ -15130,20 +15130,20 @@
|
|||
7 0x1000 //RX_TDDRC_ALPHA_UP_2
|
||||
8 0x1000 //RX_TDDRC_ALPHA_UP_3
|
||||
9 0x1000 //RX_TDDRC_ALPHA_UP_4
|
||||
27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1
|
||||
27 0x1000 //RX_TDDRC_ALPHA_DWN_1
|
||||
28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2
|
||||
29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3
|
||||
32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4
|
||||
33 0x5A9D //RX_TDDRC_LIMITER_THRD
|
||||
34 0x0800 //RX_TDDRC_LIMITER_GAIN
|
||||
112 0x0000 //RX_TDDRC_THRD_0
|
||||
113 0x0001 //RX_TDDRC_THRD_1
|
||||
112 0x0008 //RX_TDDRC_THRD_0
|
||||
113 0x0800 //RX_TDDRC_THRD_1
|
||||
114 0x1800 //RX_TDDRC_THRD_2
|
||||
115 0x1800 //RX_TDDRC_THRD_3
|
||||
116 0x3000 //RX_TDDRC_SLANT_0
|
||||
117 0x7FFF //RX_TDDRC_SLANT_1
|
||||
118 0x1000 //RX_TDDRC_ALPHA_UP_0
|
||||
119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0
|
||||
119 0x7000 //RX_TDDRC_ALPHA_DWN_0
|
||||
120 0x0000 //RX_TDDRC_HMNC_FLAG
|
||||
121 0x199A //RX_TDDRC_HMNC_GAIN
|
||||
122 0x0001 //RX_TDDRC_SMT_FLAG
|
||||
|
@ -15229,20 +15229,20 @@
|
|||
7 0x1000 //RX_TDDRC_ALPHA_UP_2
|
||||
8 0x1000 //RX_TDDRC_ALPHA_UP_3
|
||||
9 0x1000 //RX_TDDRC_ALPHA_UP_4
|
||||
27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1
|
||||
27 0x1000 //RX_TDDRC_ALPHA_DWN_1
|
||||
28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2
|
||||
29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3
|
||||
32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4
|
||||
33 0x5A9D //RX_TDDRC_LIMITER_THRD
|
||||
34 0x0800 //RX_TDDRC_LIMITER_GAIN
|
||||
112 0x0000 //RX_TDDRC_THRD_0
|
||||
113 0x0001 //RX_TDDRC_THRD_1
|
||||
112 0x0008 //RX_TDDRC_THRD_0
|
||||
113 0x0800 //RX_TDDRC_THRD_1
|
||||
114 0x1800 //RX_TDDRC_THRD_2
|
||||
115 0x1800 //RX_TDDRC_THRD_3
|
||||
116 0x3000 //RX_TDDRC_SLANT_0
|
||||
117 0x7FFF //RX_TDDRC_SLANT_1
|
||||
118 0x1000 //RX_TDDRC_ALPHA_UP_0
|
||||
119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0
|
||||
119 0x7000 //RX_TDDRC_ALPHA_DWN_0
|
||||
120 0x0000 //RX_TDDRC_HMNC_FLAG
|
||||
121 0x199A //RX_TDDRC_HMNC_GAIN
|
||||
122 0x0001 //RX_TDDRC_SMT_FLAG
|
||||
|
@ -15324,7 +15324,7 @@
|
|||
129 0x0100 //RX_SPK_VOL
|
||||
130 0x0000 //RX_VOL_RESRV_0
|
||||
#RX 2
|
||||
157 0x243C //RX_RECVFUNC_MODE_0
|
||||
157 0x247C //RX_RECVFUNC_MODE_0
|
||||
158 0x0002 //RX_RECVFUNC_MODE_1
|
||||
159 0x0001 //RX_SAMPLINGFREQ_SIG
|
||||
160 0x0001 //RX_SAMPLINGFREQ_PROC
|
||||
|
@ -15493,7 +15493,7 @@
|
|||
190 0x5A9D //RX_TDDRC_LIMITER_THRD
|
||||
191 0x0800 //RX_TDDRC_LIMITER_GAIN
|
||||
269 0x0000 //RX_TDDRC_THRD_0
|
||||
270 0x0001 //RX_TDDRC_THRD_1
|
||||
270 0x0008 //RX_TDDRC_THRD_1
|
||||
271 0x1800 //RX_TDDRC_THRD_2
|
||||
272 0x1800 //RX_TDDRC_THRD_3
|
||||
273 0x3000 //RX_TDDRC_SLANT_0
|
||||
|
@ -15592,7 +15592,7 @@
|
|||
190 0x5A9D //RX_TDDRC_LIMITER_THRD
|
||||
191 0x0800 //RX_TDDRC_LIMITER_GAIN
|
||||
269 0x0000 //RX_TDDRC_THRD_0
|
||||
270 0x0001 //RX_TDDRC_THRD_1
|
||||
270 0x0008 //RX_TDDRC_THRD_1
|
||||
271 0x1800 //RX_TDDRC_THRD_2
|
||||
272 0x1800 //RX_TDDRC_THRD_3
|
||||
273 0x3000 //RX_TDDRC_SLANT_0
|
||||
|
@ -15691,7 +15691,7 @@
|
|||
190 0x5A9D //RX_TDDRC_LIMITER_THRD
|
||||
191 0x0800 //RX_TDDRC_LIMITER_GAIN
|
||||
269 0x0000 //RX_TDDRC_THRD_0
|
||||
270 0x0001 //RX_TDDRC_THRD_1
|
||||
270 0x0008 //RX_TDDRC_THRD_1
|
||||
271 0x1800 //RX_TDDRC_THRD_2
|
||||
272 0x1800 //RX_TDDRC_THRD_3
|
||||
273 0x3000 //RX_TDDRC_SLANT_0
|
||||
|
@ -15790,7 +15790,7 @@
|
|||
190 0x5A9D //RX_TDDRC_LIMITER_THRD
|
||||
191 0x0800 //RX_TDDRC_LIMITER_GAIN
|
||||
269 0x0000 //RX_TDDRC_THRD_0
|
||||
270 0x0001 //RX_TDDRC_THRD_1
|
||||
270 0x0008 //RX_TDDRC_THRD_1
|
||||
271 0x1800 //RX_TDDRC_THRD_2
|
||||
272 0x1800 //RX_TDDRC_THRD_3
|
||||
273 0x3000 //RX_TDDRC_SLANT_0
|
||||
|
@ -15888,8 +15888,8 @@
|
|||
189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4
|
||||
190 0x5A9D //RX_TDDRC_LIMITER_THRD
|
||||
191 0x0800 //RX_TDDRC_LIMITER_GAIN
|
||||
269 0x0000 //RX_TDDRC_THRD_0
|
||||
270 0x0001 //RX_TDDRC_THRD_1
|
||||
269 0x0008 //RX_TDDRC_THRD_0
|
||||
270 0x0800 //RX_TDDRC_THRD_1
|
||||
271 0x1800 //RX_TDDRC_THRD_2
|
||||
272 0x1800 //RX_TDDRC_THRD_3
|
||||
273 0x3000 //RX_TDDRC_SLANT_0
|
||||
|
@ -15987,8 +15987,8 @@
|
|||
189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4
|
||||
190 0x5A9D //RX_TDDRC_LIMITER_THRD
|
||||
191 0x0800 //RX_TDDRC_LIMITER_GAIN
|
||||
269 0x0000 //RX_TDDRC_THRD_0
|
||||
270 0x0001 //RX_TDDRC_THRD_1
|
||||
269 0x0008 //RX_TDDRC_THRD_0
|
||||
270 0x0800 //RX_TDDRC_THRD_1
|
||||
271 0x1800 //RX_TDDRC_THRD_2
|
||||
272 0x1800 //RX_TDDRC_THRD_3
|
||||
273 0x3000 //RX_TDDRC_SLANT_0
|
||||
|
@ -16086,8 +16086,8 @@
|
|||
189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4
|
||||
190 0x5A9D //RX_TDDRC_LIMITER_THRD
|
||||
191 0x0800 //RX_TDDRC_LIMITER_GAIN
|
||||
269 0x0000 //RX_TDDRC_THRD_0
|
||||
270 0x0001 //RX_TDDRC_THRD_1
|
||||
269 0x0008 //RX_TDDRC_THRD_0
|
||||
270 0x0800 //RX_TDDRC_THRD_1
|
||||
271 0x1800 //RX_TDDRC_THRD_2
|
||||
272 0x1800 //RX_TDDRC_THRD_3
|
||||
273 0x3000 //RX_TDDRC_SLANT_0
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
#EXPORT_FLAG HANDSFREE
|
||||
#PARAM_MODE FULL
|
||||
#SAVE_MODE 3
|
||||
#SAVE_TIME 2024-02-02 11:42:45
|
||||
#SAVE_TIME 2024-02-29 16:12:53
|
||||
|
||||
#CASE_NAME HANDSFREE-HANDSFREE-VOICE_GENERIC-NB
|
||||
#PARAM_TYPE TX+2RX
|
||||
|
|
Binary file not shown.
|
@ -3,7 +3,7 @@
|
|||
#EXPORT_FLAG HEADSET
|
||||
#PARAM_MODE FULL
|
||||
#SAVE_MODE 3
|
||||
#SAVE_TIME 2024-02-23 16:34:33
|
||||
#SAVE_TIME 2024-02-29 15:49:04
|
||||
|
||||
#CASE_NAME HEADSET-USB_BLACKBIRD-VOICE_GENERIC-NB
|
||||
#PARAM_TYPE TX+2RX
|
||||
|
@ -3557,7 +3557,7 @@
|
|||
850 0x0000 //TX_FFP_RESRV_4
|
||||
851 0x0000 //TX_FFP_RESRV_5
|
||||
852 0x0000 //TX_FFP_RESRV_6
|
||||
853 0x0001 //TX_FILTINDX
|
||||
853 0x0002 //TX_FILTINDX
|
||||
854 0x0000 //TX_TDDRC_THRD_0
|
||||
855 0x0000 //TX_TDDRC_THRD_1
|
||||
856 0x2000 //TX_TDDRC_THRD_2
|
||||
|
@ -3693,7 +3693,7 @@
|
|||
986 0x0000 //TX_EASSA_AEC_NSSA_REFG_REFBLK_0
|
||||
987 0x0000 //TX_EASSA_AEC_NSSA_REFG_REFBLK_1
|
||||
#RX
|
||||
0 0xA43C //RX_RECVFUNC_MODE_0
|
||||
0 0xA47C //RX_RECVFUNC_MODE_0
|
||||
1 0x0000 //RX_RECVFUNC_MODE_1
|
||||
2 0x0001 //RX_SAMPLINGFREQ_SIG
|
||||
3 0x0001 //RX_SAMPLINGFREQ_PROC
|
||||
|
@ -3715,7 +3715,7 @@
|
|||
19 0x0020 //RX_PP_RESRV_1
|
||||
20 0x0600 //RX_N_SN_EST
|
||||
21 0x000C //RX_N2_SN_EST
|
||||
22 0x0006 //RX_NS_LVL_CTRL
|
||||
22 0x000F //RX_NS_LVL_CTRL
|
||||
23 0xF800 //RX_THR_SN_EST
|
||||
24 0x7CCD //RX_LAMBDA_PFILT
|
||||
25 0x000A //RX_MUTE_PERIOD
|
||||
|
@ -4251,14 +4251,14 @@
|
|||
7 0x1000 //RX_TDDRC_ALPHA_UP_2
|
||||
8 0x1000 //RX_TDDRC_ALPHA_UP_3
|
||||
9 0x1000 //RX_TDDRC_ALPHA_UP_4
|
||||
27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1
|
||||
28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2
|
||||
27 0x1000 //RX_TDDRC_ALPHA_DWN_1
|
||||
28 0x32B0 //RX_TDDRC_ALPHA_DWN_2
|
||||
29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3
|
||||
32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4
|
||||
33 0x7220 //RX_TDDRC_LIMITER_THRD
|
||||
34 0x0800 //RX_TDDRC_LIMITER_GAIN
|
||||
112 0x0000 //RX_TDDRC_THRD_0
|
||||
113 0x0000 //RX_TDDRC_THRD_1
|
||||
112 0x0008 //RX_TDDRC_THRD_0
|
||||
113 0x0800 //RX_TDDRC_THRD_1
|
||||
114 0x1800 //RX_TDDRC_THRD_2
|
||||
115 0x1800 //RX_TDDRC_THRD_3
|
||||
116 0x7FFF //RX_TDDRC_SLANT_0
|
||||
|
@ -4350,14 +4350,14 @@
|
|||
7 0x1000 //RX_TDDRC_ALPHA_UP_2
|
||||
8 0x1000 //RX_TDDRC_ALPHA_UP_3
|
||||
9 0x1000 //RX_TDDRC_ALPHA_UP_4
|
||||
27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1
|
||||
28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2
|
||||
27 0x1000 //RX_TDDRC_ALPHA_DWN_1
|
||||
28 0x32B0 //RX_TDDRC_ALPHA_DWN_2
|
||||
29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3
|
||||
32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4
|
||||
33 0x7220 //RX_TDDRC_LIMITER_THRD
|
||||
34 0x0800 //RX_TDDRC_LIMITER_GAIN
|
||||
112 0x0000 //RX_TDDRC_THRD_0
|
||||
113 0x0000 //RX_TDDRC_THRD_1
|
||||
112 0x0008 //RX_TDDRC_THRD_0
|
||||
113 0x0800 //RX_TDDRC_THRD_1
|
||||
114 0x1800 //RX_TDDRC_THRD_2
|
||||
115 0x1800 //RX_TDDRC_THRD_3
|
||||
116 0x7FFF //RX_TDDRC_SLANT_0
|
||||
|
@ -4449,14 +4449,14 @@
|
|||
7 0x1000 //RX_TDDRC_ALPHA_UP_2
|
||||
8 0x1000 //RX_TDDRC_ALPHA_UP_3
|
||||
9 0x1000 //RX_TDDRC_ALPHA_UP_4
|
||||
27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1
|
||||
28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2
|
||||
27 0x1000 //RX_TDDRC_ALPHA_DWN_1
|
||||
28 0x32B0 //RX_TDDRC_ALPHA_DWN_2
|
||||
29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3
|
||||
32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4
|
||||
33 0x7220 //RX_TDDRC_LIMITER_THRD
|
||||
34 0x0800 //RX_TDDRC_LIMITER_GAIN
|
||||
112 0x0000 //RX_TDDRC_THRD_0
|
||||
113 0x0000 //RX_TDDRC_THRD_1
|
||||
112 0x0008 //RX_TDDRC_THRD_0
|
||||
113 0x0800 //RX_TDDRC_THRD_1
|
||||
114 0x1800 //RX_TDDRC_THRD_2
|
||||
115 0x1800 //RX_TDDRC_THRD_3
|
||||
116 0x7FFF //RX_TDDRC_SLANT_0
|
||||
|
@ -5102,14 +5102,14 @@
|
|||
164 0x1000 //RX_TDDRC_ALPHA_UP_2
|
||||
165 0x1000 //RX_TDDRC_ALPHA_UP_3
|
||||
166 0x1000 //RX_TDDRC_ALPHA_UP_4
|
||||
184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1
|
||||
185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2
|
||||
184 0x1000 //RX_TDDRC_ALPHA_DWN_1
|
||||
185 0x32B0 //RX_TDDRC_ALPHA_DWN_2
|
||||
186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3
|
||||
189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4
|
||||
190 0x7220 //RX_TDDRC_LIMITER_THRD
|
||||
191 0x0800 //RX_TDDRC_LIMITER_GAIN
|
||||
269 0x0000 //RX_TDDRC_THRD_0
|
||||
270 0x0000 //RX_TDDRC_THRD_1
|
||||
269 0x0008 //RX_TDDRC_THRD_0
|
||||
270 0x0800 //RX_TDDRC_THRD_1
|
||||
271 0x1800 //RX_TDDRC_THRD_2
|
||||
272 0x1800 //RX_TDDRC_THRD_3
|
||||
273 0x7FFF //RX_TDDRC_SLANT_0
|
||||
|
@ -5201,14 +5201,14 @@
|
|||
164 0x1000 //RX_TDDRC_ALPHA_UP_2
|
||||
165 0x1000 //RX_TDDRC_ALPHA_UP_3
|
||||
166 0x1000 //RX_TDDRC_ALPHA_UP_4
|
||||
184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1
|
||||
185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2
|
||||
184 0x1000 //RX_TDDRC_ALPHA_DWN_1
|
||||
185 0x32B0 //RX_TDDRC_ALPHA_DWN_2
|
||||
186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3
|
||||
189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4
|
||||
190 0x7220 //RX_TDDRC_LIMITER_THRD
|
||||
191 0x0800 //RX_TDDRC_LIMITER_GAIN
|
||||
269 0x0000 //RX_TDDRC_THRD_0
|
||||
270 0x0000 //RX_TDDRC_THRD_1
|
||||
269 0x0008 //RX_TDDRC_THRD_0
|
||||
270 0x0800 //RX_TDDRC_THRD_1
|
||||
271 0x1800 //RX_TDDRC_THRD_2
|
||||
272 0x1800 //RX_TDDRC_THRD_3
|
||||
273 0x7FFF //RX_TDDRC_SLANT_0
|
||||
|
@ -5300,14 +5300,14 @@
|
|||
164 0x1000 //RX_TDDRC_ALPHA_UP_2
|
||||
165 0x1000 //RX_TDDRC_ALPHA_UP_3
|
||||
166 0x1000 //RX_TDDRC_ALPHA_UP_4
|
||||
184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1
|
||||
185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2
|
||||
184 0x1000 //RX_TDDRC_ALPHA_DWN_1
|
||||
185 0x32B0 //RX_TDDRC_ALPHA_DWN_2
|
||||
186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3
|
||||
189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4
|
||||
190 0x7220 //RX_TDDRC_LIMITER_THRD
|
||||
191 0x0800 //RX_TDDRC_LIMITER_GAIN
|
||||
269 0x0000 //RX_TDDRC_THRD_0
|
||||
270 0x0000 //RX_TDDRC_THRD_1
|
||||
269 0x0008 //RX_TDDRC_THRD_0
|
||||
270 0x0800 //RX_TDDRC_THRD_1
|
||||
271 0x1800 //RX_TDDRC_THRD_2
|
||||
272 0x1800 //RX_TDDRC_THRD_3
|
||||
273 0x7FFF //RX_TDDRC_SLANT_0
|
||||
|
@ -17190,7 +17190,7 @@
|
|||
19 0x0020 //RX_PP_RESRV_1
|
||||
20 0x0600 //RX_N_SN_EST
|
||||
21 0x000C //RX_N2_SN_EST
|
||||
22 0x0006 //RX_NS_LVL_CTRL
|
||||
22 0x000F //RX_NS_LVL_CTRL
|
||||
23 0xF800 //RX_THR_SN_EST
|
||||
24 0x7CCD //RX_LAMBDA_PFILT
|
||||
25 0x000A //RX_MUTE_PERIOD
|
||||
|
@ -30665,7 +30665,7 @@
|
|||
19 0x0020 //RX_PP_RESRV_1
|
||||
20 0x0600 //RX_N_SN_EST
|
||||
21 0x000C //RX_N2_SN_EST
|
||||
22 0x0006 //RX_NS_LVL_CTRL
|
||||
22 0x000F //RX_NS_LVL_CTRL
|
||||
23 0xF800 //RX_THR_SN_EST
|
||||
24 0x7CCD //RX_LAMBDA_PFILT
|
||||
25 0x000A //RX_MUTE_PERIOD
|
||||
|
@ -98040,7 +98040,7 @@
|
|||
19 0x0020 //RX_PP_RESRV_1
|
||||
20 0x0600 //RX_N_SN_EST
|
||||
21 0x000C //RX_N2_SN_EST
|
||||
22 0x0006 //RX_NS_LVL_CTRL
|
||||
22 0x000F //RX_NS_LVL_CTRL
|
||||
23 0xF800 //RX_THR_SN_EST
|
||||
24 0x7CCD //RX_LAMBDA_PFILT
|
||||
25 0x000A //RX_MUTE_PERIOD
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue