Merge changes Idf292dbb,I544b8942 into main

* changes:
  thermal: Reduce LIGHT-tier's ceiling before 43 degC for camera
  thermal: Update cdev ceiling to match latest EM table
This commit is contained in:
Treehugger Robot 2024-01-26 09:26:39 +00:00 committed by Android (Google) Code Review
commit ba8615a5fe

View file

@ -207,7 +207,7 @@
"MaxReleaseStep": 1, "MaxReleaseStep": 1,
"MaxThrottleStep": 1, "MaxThrottleStep": 1,
"BindedPowerRail": "S4M_VDD_CPUCL0", "BindedPowerRail": "S4M_VDD_CPUCL0",
"CdevCeiling": [0, 2, 2, 2, 2, 2, 2] "CdevCeiling": [0, 4, 4, 4, 4, 4, 4]
}, },
{ {
"CdevRequest": "thermal-cpufreq-1", "CdevRequest": "thermal-cpufreq-1",
@ -215,7 +215,7 @@
"MaxReleaseStep": 1, "MaxReleaseStep": 1,
"MaxThrottleStep": 2, "MaxThrottleStep": 2,
"BindedPowerRail": "S2M_VDD_CPUCL1", "BindedPowerRail": "S2M_VDD_CPUCL1",
"CdevCeiling": [0, 6, 6, 6, 6, 6, 6] "CdevCeiling": [0, 8, 8, 8, 8, 8, 8]
}, },
{ {
"CdevRequest": "thermal-cpufreq-2", "CdevRequest": "thermal-cpufreq-2",
@ -223,7 +223,7 @@
"MaxReleaseStep": 1, "MaxReleaseStep": 1,
"MaxThrottleStep": 2, "MaxThrottleStep": 2,
"BindedPowerRail": "S3M_VDD_CPUCL2", "BindedPowerRail": "S3M_VDD_CPUCL2",
"CdevCeiling": [0, 8, 8, 8, 8, 8, 8] "CdevCeiling": [0, 12, 12, 12, 12, 12, 12]
} }
] ]
}, },
@ -258,21 +258,21 @@
"CdevWeightForPID": [0.292, 0.292, 0.292, 0.292, 0.292, 0.292, 0.292], "CdevWeightForPID": [0.292, 0.292, 0.292, 0.292, 0.292, 0.292, 0.292],
"MaxReleaseStep": 1, "MaxReleaseStep": 1,
"MaxThrottleStep": 1, "MaxThrottleStep": 1,
"CdevCeiling": [0, 6, 6, 6, 6, 6, 6] "CdevCeiling": [0, 8, 8, 8, 8, 8, 8]
}, },
{ {
"CdevRequest": "thermal-cpufreq-1", "CdevRequest": "thermal-cpufreq-1",
"CdevWeightForPID": [0.804, 0.804, 0.804, 0.804, 0.804, 0.804, 0.804], "CdevWeightForPID": [0.804, 0.804, 0.804, 0.804, 0.804, 0.804, 0.804],
"MaxReleaseStep": 1, "MaxReleaseStep": 1,
"MaxThrottleStep": 2, "MaxThrottleStep": 2,
"CdevCeiling": [0, 9, 9, 9, 9, 9, 9] "CdevCeiling": [0, 11, 11, 11, 11, 11, 11]
}, },
{ {
"CdevRequest": "thermal-cpufreq-2", "CdevRequest": "thermal-cpufreq-2",
"CdevWeightForPID": [0.342, 0.342, 0.342, 0.342, 0.342, 0.342, 0.342], "CdevWeightForPID": [0.342, 0.342, 0.342, 0.342, 0.342, 0.342, 0.342],
"MaxReleaseStep": 1, "MaxReleaseStep": 1,
"MaxThrottleStep": 2, "MaxThrottleStep": 2,
"CdevCeiling": [0, 12, 12, 12, 12, 12, 12] "CdevCeiling": [0, 16, 16, 16, 16, 16, 16]
} }
], ],
"Profile": [ "Profile": [
@ -349,21 +349,21 @@
"CdevWeightForPID": [0.156, 0.156, 0.156, 0.156, 0.156, 0.156, 0.156], "CdevWeightForPID": [0.156, 0.156, 0.156, 0.156, 0.156, 0.156, 0.156],
"MaxReleaseStep": 1, "MaxReleaseStep": 1,
"MaxThrottleStep": 1, "MaxThrottleStep": 1,
"CdevCeiling": [0, 8, 8, 8, 8, 8, 8] "CdevCeiling": [0, 10, 10, 10, 10, 10, 10]
}, },
{ {
"CdevRequest": "thermal-cpufreq-1", "CdevRequest": "thermal-cpufreq-1",
"CdevWeightForPID": [0.428, 0.428, 0.428, 0.428, 0.428, 0.428, 0.428], "CdevWeightForPID": [0.428, 0.428, 0.428, 0.428, 0.428, 0.428, 0.428],
"MaxReleaseStep": 1, "MaxReleaseStep": 1,
"MaxThrottleStep": 2, "MaxThrottleStep": 2,
"CdevCeiling": [0, 11, 11, 11, 11, 11, 11] "CdevCeiling": [0, 14, 14, 14, 14, 14, 14]
}, },
{ {
"CdevRequest": "thermal-cpufreq-2", "CdevRequest": "thermal-cpufreq-2",
"CdevWeightForPID": [0.225, 0.225, 0.225, 0.225, 0.225, 0.225, 0.225], "CdevWeightForPID": [0.225, 0.225, 0.225, 0.225, 0.225, 0.225, 0.225],
"MaxReleaseStep": 1, "MaxReleaseStep": 1,
"MaxThrottleStep": 2, "MaxThrottleStep": 2,
"CdevCeiling": [0, 13, 13, 13, 13, 13, 13] "CdevCeiling": [0, 17, 17, 17, 17, 17, 17]
} }
], ],
"Profile": [ "Profile": [
@ -397,7 +397,7 @@
], ],
"MaxReleaseStep": 1, "MaxReleaseStep": 1,
"MaxThrottleStep": 1, "MaxThrottleStep": 1,
"CdevCeiling": [0, 6, 6, 6, 6, 6, 6] "CdevCeiling": [0, 4, 4, 4, 4, 4, 4]
}, },
{ {
"CdevRequest": "thermal-cpufreq-1", "CdevRequest": "thermal-cpufreq-1",
@ -406,7 +406,7 @@
], ],
"MaxReleaseStep": 1, "MaxReleaseStep": 1,
"MaxThrottleStep": 2, "MaxThrottleStep": 2,
"CdevCeiling": [0, 9, 9, 9, 9, 9, 9] "CdevCeiling": [0, 8, 8, 8, 8, 8, 8]
}, },
{ {
"CdevRequest": "thermal-cpufreq-2", "CdevRequest": "thermal-cpufreq-2",
@ -453,8 +453,8 @@
"MaxReleaseStep": 1, "MaxReleaseStep": 1,
"MaxThrottleStep": 1, "MaxThrottleStep": 1,
"BindedPowerRail": "S4M_VDD_CPUCL0", "BindedPowerRail": "S4M_VDD_CPUCL0",
"CdevCeiling": [0, 8, 8, 8, 8, 9, 9], "CdevCeiling": [0, 10, 10, 10, 10, 11, 11],
"LimitInfo": [0, 0, 0, 0, 0, 9, 9] "LimitInfo": [0, 0, 0, 0, 0, 11, 11]
}, },
{ {
"CdevRequest": "thermal-cpufreq-1", "CdevRequest": "thermal-cpufreq-1",
@ -462,8 +462,8 @@
"MaxReleaseStep": 1, "MaxReleaseStep": 1,
"MaxThrottleStep": 2, "MaxThrottleStep": 2,
"BindedPowerRail": "S2M_VDD_CPUCL1", "BindedPowerRail": "S2M_VDD_CPUCL1",
"CdevCeiling": [0, 11, 11, 11, 11, 14, 14], "CdevCeiling": [0, 14, 14, 14, 14, 16, 16],
"LimitInfo": [0, 0, 0, 0, 0, 14, 14] "LimitInfo": [0, 0, 0, 0, 0, 16, 16]
}, },
{ {
"CdevRequest": "thermal-cpufreq-2", "CdevRequest": "thermal-cpufreq-2",
@ -471,8 +471,8 @@
"MaxReleaseStep": 1, "MaxReleaseStep": 1,
"MaxThrottleStep": 2, "MaxThrottleStep": 2,
"BindedPowerRail": "S3M_VDD_CPUCL2", "BindedPowerRail": "S3M_VDD_CPUCL2",
"CdevCeiling": [0, 13, 13, 13, 13, 14, 14], "CdevCeiling": [0, 17, 17, 17, 17, 17, 17],
"LimitInfo": [0, 0, 0, 0, 0, 14, 14] "LimitInfo": [0, 0, 0, 0, 0, 17, 17]
}, },
{ {
"CdevRequest": "thermal-gpufreq-0", "CdevRequest": "thermal-gpufreq-0",