From 14b33156337e8bd526815be91a3caaabdd472375 Mon Sep 17 00:00:00 2001 From: Sayanna Chandula Date: Wed, 6 Apr 2022 18:42:05 +0000 Subject: [PATCH] thermal: Reconfigure GPU DFS clock to divide by 4 Program the GPU Light register to make clock divider to be divided by 4 Bug: 223909471 Test: Local test to verify register value Signed-off-by: Sayanna Chandula Change-Id: If6b3fe9d6cd73cd110e1b6c123b2925c261b5b2a --- conf/init.gs201.rc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/conf/init.gs201.rc b/conf/init.gs201.rc index 835d13b4..d45d8467 100644 --- a/conf/init.gs201.rc +++ b/conf/init.gs201.rc @@ -873,7 +873,7 @@ on property:vendor.thermal.link_ready=1 write /sys/devices/virtual/pmic/mitigation/clock_ratio/tpu_light_clk_ratio 0xfff041c1 #DFS write /sys/devices/virtual/pmic/mitigation/clock_ratio/cpu1_heavy_clk_ratio 0xfff041c1 #DFS write /sys/devices/virtual/pmic/mitigation/clock_ratio/cpu2_heavy_clk_ratio 0xfff041c1 #DFS - write /sys/devices/virtual/pmic/mitigation/clock_ratio/gpu_light_clk_ratio 0xfff04381 #DFS + write /sys/devices/virtual/pmic/mitigation/clock_ratio/gpu_light_clk_ratio 0xfff041c1 #DFS write /sys/devices/virtual/pmic/mitigation/clock_ratio/cpu2_light_clk_ratio 0xfff041c3 #OCP write /sys/devices/virtual/pmic/mitigation/clock_ratio/gpu_heavy_clk_ratio 0xfff04385 #OCP write /sys/devices/virtual/pmic/mitigation/clock_ratio/tpu_heavy_clk_ratio 0xfff041c3 #OCP