From ea926b06e26716baab0ee9efe765aeb123e3fd8e Mon Sep 17 00:00:00 2001 From: George Lee Date: Thu, 10 Mar 2022 15:27:09 -0800 Subject: [PATCH] thermal: Reconfigure DFS Clock to divide by 4 1. Reconfigure DFS clock divider to divide by 4. 2. OCP_WARN_CPU2 was repurposed for DFS usage. Since SOFT_OCP_WARN_CPU2 was not used by BCL, it will be repurposed to replace OCP_WARN_CPU2. Bug: 223909471 Test: Local test to verify register value Signed-off-by: George Lee Change-Id: Ie9960c30b102d67f0ade156631386b656ff82790 --- conf/init.gs201.rc | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/conf/init.gs201.rc b/conf/init.gs201.rc index 3ad3fede..c0923bad 100644 --- a/conf/init.gs201.rc +++ b/conf/init.gs201.rc @@ -870,18 +870,20 @@ on fs on property:vendor.thermal.link_ready=1 # BCL - write /sys/devices/virtual/pmic/mitigation/clock_ratio/tpu_light_clk_ratio 0xfff041c5 - write /sys/devices/virtual/pmic/mitigation/clock_ratio/cpu2_light_clk_ratio 0xfff041c5 - write /sys/devices/virtual/pmic/mitigation/clock_ratio/gpu_heavy_clk_ratio 0xfff04385 - write /sys/devices/virtual/pmic/mitigation/clock_ratio/tpu_heavy_clk_ratio 0xfff041c3 - write /sys/devices/virtual/pmic/mitigation/clock_ratio/cpu2_heavy_clk_ratio 0xfff041c3 + write /sys/devices/virtual/pmic/mitigation/clock_ratio/tpu_light_clk_ratio 0xfff041c1 #DFS + write /sys/devices/virtual/pmic/mitigation/clock_ratio/cpu1_heavy_clk_ratio 0xfff041c1 #DFS + write /sys/devices/virtual/pmic/mitigation/clock_ratio/cpu2_heavy_clk_ratio 0xfff041c1 #DFS + write /sys/devices/virtual/pmic/mitigation/clock_ratio/gpu_light_clk_ratio 0xfff04381 #DFS + write /sys/devices/virtual/pmic/mitigation/clock_ratio/cpu2_light_clk_ratio 0xfff041c3 #OCP + write /sys/devices/virtual/pmic/mitigation/clock_ratio/gpu_heavy_clk_ratio 0xfff04385 #OCP + write /sys/devices/virtual/pmic/mitigation/clock_ratio/tpu_heavy_clk_ratio 0xfff041c3 #OCP write /sys/devices/virtual/pmic/mitigation/triggered_lvl/smpl_lvl 3100 - write /sys/devices/virtual/pmic/mitigation/triggered_lvl/soft_ocp_cpu2_lvl 9000 + write /sys/devices/virtual/pmic/mitigation/triggered_lvl/soft_ocp_cpu2_lvl 12000 write /sys/devices/virtual/pmic/mitigation/triggered_lvl/soft_ocp_gpu_lvl 9000 write /sys/devices/virtual/pmic/mitigation/triggered_lvl/soft_ocp_tpu_lvl 8500 - write /sys/devices/virtual/pmic/mitigation/clock_div/tpu_clk_div 0x201 - write /sys/devices/virtual/pmic/mitigation/clock_div/gpu_clk_div 0x801 - write /sys/devices/virtual/pmic/mitigation/clock_div/cpu2_clk_div 0x801 + write /sys/devices/virtual/pmic/mitigation/clock_div/tpu_clk_div 0x1 + write /sys/devices/virtual/pmic/mitigation/clock_div/gpu_clk_div 0x1 + write /sys/devices/virtual/pmic/mitigation/clock_div/cpu2_clk_div 0x1 chown system system /dev/thermal/tz-by-name/soc/mode chown system system /dev/thermal/tz-by-name/vdroop2/trip_point_0_temp chown system system /dev/thermal/tz-by-name/vdroop2/trip_point_0_hyst