Evolution-X-Tensor/device_google_gs201
2
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

thermal: Reconfigure DFS Clock to divide by 4 am: ea926b06e2

Browse source 
Original change: https://googleplex-android-review.googlesource.com/c/device/google/gs201/+/17161495

Change-Id: I4995f7a6685b1c09fecfa086ab149b08120a5444
Signed-off-by: Automerger Merge Worker <android-build-automerger-merge-worker@system.gserviceaccount.com>
This commit is contained in:
George Lee 2022-04-01 18:56:22 +00:00 • committed by Automerger Merge Worker
commit fcee0fde99
1 changed files with 11 additions and 9 deletions
Download patch file Download diff file Expand all files Collapse all files

20
conf/init.gs201.rc
View file

@ -870,18 +870,20 @@ on fs
on property:vendor.thermal.link_ready=1 on property:vendor.thermal.link_ready=1
# BCL # BCL
write /sys/devices/virtual/pmic/mitigation/clock_ratio/tpu_light_clk_ratio 0xfff041c5 write /sys/devices/virtual/pmic/mitigation/clock_ratio/tpu_light_clk_ratio 0xfff041c1 #DFS
write /sys/devices/virtual/pmic/mitigation/clock_ratio/cpu2_light_clk_ratio 0xfff041c5 write /sys/devices/virtual/pmic/mitigation/clock_ratio/cpu1_heavy_clk_ratio 0xfff041c1 #DFS
write /sys/devices/virtual/pmic/mitigation/clock_ratio/gpu_heavy_clk_ratio 0xfff04385 write /sys/devices/virtual/pmic/mitigation/clock_ratio/cpu2_heavy_clk_ratio 0xfff041c1 #DFS
write /sys/devices/virtual/pmic/mitigation/clock_ratio/tpu_heavy_clk_ratio 0xfff041c3 write /sys/devices/virtual/pmic/mitigation/clock_ratio/gpu_light_clk_ratio 0xfff04381 #DFS
write /sys/devices/virtual/pmic/mitigation/clock_ratio/cpu2_heavy_clk_ratio 0xfff041c3 write /sys/devices/virtual/pmic/mitigation/clock_ratio/cpu2_light_clk_ratio 0xfff041c3 #OCP
write /sys/devices/virtual/pmic/mitigation/clock_ratio/gpu_heavy_clk_ratio 0xfff04385 #OCP
write /sys/devices/virtual/pmic/mitigation/clock_ratio/tpu_heavy_clk_ratio 0xfff041c3 #OCP
write /sys/devices/virtual/pmic/mitigation/triggered_lvl/smpl_lvl 3100 write /sys/devices/virtual/pmic/mitigation/triggered_lvl/smpl_lvl 3100
write /sys/devices/virtual/pmic/mitigation/triggered_lvl/soft_ocp_cpu2_lvl 9000 write /sys/devices/virtual/pmic/mitigation/triggered_lvl/soft_ocp_cpu2_lvl 12000
write /sys/devices/virtual/pmic/mitigation/triggered_lvl/soft_ocp_gpu_lvl 9000 write /sys/devices/virtual/pmic/mitigation/triggered_lvl/soft_ocp_gpu_lvl 9000
write /sys/devices/virtual/pmic/mitigation/triggered_lvl/soft_ocp_tpu_lvl 8500 write /sys/devices/virtual/pmic/mitigation/triggered_lvl/soft_ocp_tpu_lvl 8500
write /sys/devices/virtual/pmic/mitigation/clock_div/tpu_clk_div 0x201 write /sys/devices/virtual/pmic/mitigation/clock_div/tpu_clk_div 0x1
write /sys/devices/virtual/pmic/mitigation/clock_div/gpu_clk_div 0x801 write /sys/devices/virtual/pmic/mitigation/clock_div/gpu_clk_div 0x1
write /sys/devices/virtual/pmic/mitigation/clock_div/cpu2_clk_div 0x801 write /sys/devices/virtual/pmic/mitigation/clock_div/cpu2_clk_div 0x1
chown system system /dev/thermal/tz-by-name/soc/mode chown system system /dev/thermal/tz-by-name/soc/mode
chown system system /dev/thermal/tz-by-name/vdroop2/trip_point_0_temp chown system system /dev/thermal/tz-by-name/vdroop2/trip_point_0_temp
chown system system /dev/thermal/tz-by-name/vdroop2/trip_point_0_hyst chown system system /dev/thermal/tz-by-name/vdroop2/trip_point_0_hyst