Snap for 8657279 from 4530d72094
to udc-release
Change-Id: I3ae1e53883619ae96652e4513cba61aca2322bc5
This commit is contained in:
commit
1ee2f5f43e
22 changed files with 7860 additions and 7764 deletions
Binary file not shown.
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@ -1,7 +1,7 @@
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||||||
#PLATFORM_NAME gChip
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#PLATFORM_NAME gChip
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||||||
#EXPORT_FLAG BLUETOOTH
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#EXPORT_FLAG BLUETOOTH
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||||||
#SINGLE_API_VER 1.2.1
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#SINGLE_API_VER 1.2.1
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||||||
#SAVE_TIME 2022-05-11 22:41:37
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#SAVE_TIME 2022-05-26 18:06:40
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||||||
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||||||
#CASE_NAME BLUETOOTH-RESERVE1-VOICE_GENERIC-FB
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#CASE_NAME BLUETOOTH-RESERVE1-VOICE_GENERIC-FB
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||||||
#PARAM_MODE FULL
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#PARAM_MODE FULL
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||||||
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@ -3544,7 +3544,7 @@
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||||||
863 0x199A //TX_TDDRC_HMNC_GAIN
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863 0x199A //TX_TDDRC_HMNC_GAIN
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||||||
864 0x0000 //TX_TDDRC_SMT_FLAG
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864 0x0000 //TX_TDDRC_SMT_FLAG
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||||||
865 0x0CCD //TX_TDDRC_SMT_W
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865 0x0CCD //TX_TDDRC_SMT_W
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||||||
866 0x0C97 //TX_TDDRC_DRC_GAIN
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866 0x0FDA //TX_TDDRC_DRC_GAIN
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||||||
867 0x7FFF //TX_TDDRC_LMT_THRD
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867 0x7FFF //TX_TDDRC_LMT_THRD
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||||||
868 0x0000 //TX_TDDRC_LMT_ALPHA
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868 0x0000 //TX_TDDRC_LMT_ALPHA
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||||||
869 0x0000 //TX_TFMASKLTH
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869 0x0000 //TX_TFMASKLTH
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||||||
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@ -6214,7 +6214,7 @@
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||||||
863 0x199A //TX_TDDRC_HMNC_GAIN
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863 0x199A //TX_TDDRC_HMNC_GAIN
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||||||
864 0x0000 //TX_TDDRC_SMT_FLAG
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864 0x0000 //TX_TDDRC_SMT_FLAG
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||||||
865 0x0CCD //TX_TDDRC_SMT_W
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865 0x0CCD //TX_TDDRC_SMT_W
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||||||
866 0x0D56 //TX_TDDRC_DRC_GAIN
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866 0x10CA //TX_TDDRC_DRC_GAIN
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||||||
867 0x7FFF //TX_TDDRC_LMT_THRD
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867 0x7FFF //TX_TDDRC_LMT_THRD
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||||||
868 0x0000 //TX_TDDRC_LMT_ALPHA
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868 0x0000 //TX_TDDRC_LMT_ALPHA
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||||||
869 0x0000 //TX_TFMASKLTH
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869 0x0000 //TX_TFMASKLTH
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||||||
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@ -8333,8 +8333,8 @@
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||||||
312 0x7FFF //TX_A_POST_FILT_0
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312 0x7FFF //TX_A_POST_FILT_0
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||||||
313 0x2000 //TX_A_POST_FILT_1
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313 0x2000 //TX_A_POST_FILT_1
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||||||
314 0x7FFF //TX_A_POST_FILT_S_0
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314 0x7FFF //TX_A_POST_FILT_S_0
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||||||
315 0x7FFF //TX_A_POST_FILT_S_1
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315 0x1800 //TX_A_POST_FILT_S_1
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||||||
316 0x7FFF //TX_A_POST_FILT_S_2
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316 0x1000 //TX_A_POST_FILT_S_2
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||||||
317 0x7FFF //TX_A_POST_FILT_S_3
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317 0x7FFF //TX_A_POST_FILT_S_3
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||||||
318 0x7FFF //TX_A_POST_FILT_S_4
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318 0x7FFF //TX_A_POST_FILT_S_4
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||||||
319 0x7FFF //TX_A_POST_FILT_S_5
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319 0x7FFF //TX_A_POST_FILT_S_5
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||||||
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@ -8342,7 +8342,7 @@
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||||||
321 0x7FFF //TX_A_POST_FILT_S_7
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321 0x7FFF //TX_A_POST_FILT_S_7
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||||||
322 0x2000 //TX_B_POST_FILT_0
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322 0x2000 //TX_B_POST_FILT_0
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||||||
323 0x6000 //TX_B_POST_FILT_1
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323 0x6000 //TX_B_POST_FILT_1
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||||||
324 0x6000 //TX_B_POST_FILT_2
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324 0x3000 //TX_B_POST_FILT_2
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||||||
325 0x6000 //TX_B_POST_FILT_3
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325 0x6000 //TX_B_POST_FILT_3
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||||||
326 0x4000 //TX_B_POST_FILT_4
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326 0x4000 //TX_B_POST_FILT_4
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||||||
327 0x1000 //TX_B_POST_FILT_5
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327 0x1000 //TX_B_POST_FILT_5
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||||||
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@ -8365,7 +8365,7 @@
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||||||
344 0x7F00 //TX_LAMBDA_PFILT_S_5
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344 0x7F00 //TX_LAMBDA_PFILT_S_5
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||||||
345 0x7F00 //TX_LAMBDA_PFILT_S_6
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345 0x7F00 //TX_LAMBDA_PFILT_S_6
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346 0x7F00 //TX_LAMBDA_PFILT_S_7
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346 0x7F00 //TX_LAMBDA_PFILT_S_7
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||||||
347 0x1000 //TX_K_PEPPER
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347 0x3E80 //TX_K_PEPPER
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||||||
348 0x0400 //TX_A_PEPPER
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348 0x0400 //TX_A_PEPPER
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||||||
349 0x1EAA //TX_K_PEPPER_HF
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349 0x1EAA //TX_K_PEPPER_HF
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||||||
350 0x0600 //TX_A_PEPPER_HF
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350 0x0600 //TX_A_PEPPER_HF
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||||||
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@ -8390,9 +8390,9 @@
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||||||
369 0x7FFF //TX_NOISE_TH_0_3
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369 0x7FFF //TX_NOISE_TH_0_3
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||||||
370 0x07D0 //TX_NOISE_TH_1
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370 0x07D0 //TX_NOISE_TH_1
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||||||
371 0x01F4 //TX_NOISE_TH_2
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371 0x01F4 //TX_NOISE_TH_2
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||||||
372 0x36B0 //TX_NOISE_TH_3
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372 0x2EE0 //TX_NOISE_TH_3
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||||||
373 0x2710 //TX_NOISE_TH_4
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373 0x2710 //TX_NOISE_TH_4
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||||||
374 0x2CEC //TX_NOISE_TH_5
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374 0x7FFF //TX_NOISE_TH_5
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375 0x7FFF //TX_NOISE_TH_5_2
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375 0x7FFF //TX_NOISE_TH_5_2
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||||||
376 0x0000 //TX_NOISE_TH_5_3
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376 0x0000 //TX_NOISE_TH_5_3
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||||||
377 0x7FFF //TX_NOISE_TH_5_4
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377 0x7FFF //TX_NOISE_TH_5_4
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||||||
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@ -8599,8 +8599,8 @@
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578 0x5355 //TX_FDEQ_GAIN_11
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578 0x5355 //TX_FDEQ_GAIN_11
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||||||
579 0x5B5F //TX_FDEQ_GAIN_12
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579 0x5B5F //TX_FDEQ_GAIN_12
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||||||
580 0x5F84 //TX_FDEQ_GAIN_13
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580 0x5F84 //TX_FDEQ_GAIN_13
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||||||
581 0x847C //TX_FDEQ_GAIN_14
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581 0x8476 //TX_FDEQ_GAIN_14
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||||||
582 0x7178 //TX_FDEQ_GAIN_15
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582 0x6A71 //TX_FDEQ_GAIN_15
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||||||
583 0x4848 //TX_FDEQ_GAIN_16
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583 0x4848 //TX_FDEQ_GAIN_16
|
||||||
584 0x4848 //TX_FDEQ_GAIN_17
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584 0x4848 //TX_FDEQ_GAIN_17
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||||||
585 0x4848 //TX_FDEQ_GAIN_18
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585 0x4848 //TX_FDEQ_GAIN_18
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@ -8884,7 +8884,7 @@
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863 0x199A //TX_TDDRC_HMNC_GAIN
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863 0x199A //TX_TDDRC_HMNC_GAIN
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||||||
864 0x0000 //TX_TDDRC_SMT_FLAG
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864 0x0000 //TX_TDDRC_SMT_FLAG
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865 0x0CCD //TX_TDDRC_SMT_W
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865 0x0CCD //TX_TDDRC_SMT_W
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||||||
866 0x0FDA //TX_TDDRC_DRC_GAIN
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866 0x1380 //TX_TDDRC_DRC_GAIN
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867 0x7FFF //TX_TDDRC_LMT_THRD
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867 0x7FFF //TX_TDDRC_LMT_THRD
|
||||||
868 0x0000 //TX_TDDRC_LMT_ALPHA
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868 0x0000 //TX_TDDRC_LMT_ALPHA
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||||||
869 0x0000 //TX_TFMASKLTH
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869 0x0000 //TX_TFMASKLTH
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||||||
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@ -56393,8 +56393,8 @@
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312 0x7FFF //TX_A_POST_FILT_0
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312 0x7FFF //TX_A_POST_FILT_0
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||||||
313 0x2000 //TX_A_POST_FILT_1
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313 0x2000 //TX_A_POST_FILT_1
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||||||
314 0x7FFF //TX_A_POST_FILT_S_0
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314 0x7FFF //TX_A_POST_FILT_S_0
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||||||
315 0x7FFF //TX_A_POST_FILT_S_1
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315 0x1800 //TX_A_POST_FILT_S_1
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||||||
316 0x7FFF //TX_A_POST_FILT_S_2
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316 0x1000 //TX_A_POST_FILT_S_2
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||||||
317 0x7FFF //TX_A_POST_FILT_S_3
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317 0x7FFF //TX_A_POST_FILT_S_3
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||||||
318 0x7FFF //TX_A_POST_FILT_S_4
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318 0x7FFF //TX_A_POST_FILT_S_4
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319 0x7FFF //TX_A_POST_FILT_S_5
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319 0x7FFF //TX_A_POST_FILT_S_5
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||||||
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@ -56402,7 +56402,7 @@
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321 0x7FFF //TX_A_POST_FILT_S_7
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321 0x7FFF //TX_A_POST_FILT_S_7
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||||||
322 0x2000 //TX_B_POST_FILT_0
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322 0x2000 //TX_B_POST_FILT_0
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||||||
323 0x6000 //TX_B_POST_FILT_1
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323 0x6000 //TX_B_POST_FILT_1
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||||||
324 0x6000 //TX_B_POST_FILT_2
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324 0x3000 //TX_B_POST_FILT_2
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||||||
325 0x6000 //TX_B_POST_FILT_3
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325 0x6000 //TX_B_POST_FILT_3
|
||||||
326 0x4000 //TX_B_POST_FILT_4
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326 0x4000 //TX_B_POST_FILT_4
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||||||
327 0x1000 //TX_B_POST_FILT_5
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327 0x1000 //TX_B_POST_FILT_5
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||||||
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@ -56425,7 +56425,7 @@
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||||||
344 0x7F00 //TX_LAMBDA_PFILT_S_5
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344 0x7F00 //TX_LAMBDA_PFILT_S_5
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||||||
345 0x7F00 //TX_LAMBDA_PFILT_S_6
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345 0x7F00 //TX_LAMBDA_PFILT_S_6
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||||||
346 0x7F00 //TX_LAMBDA_PFILT_S_7
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346 0x7F00 //TX_LAMBDA_PFILT_S_7
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||||||
347 0x1000 //TX_K_PEPPER
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347 0x3E80 //TX_K_PEPPER
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||||||
348 0x0400 //TX_A_PEPPER
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348 0x0400 //TX_A_PEPPER
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||||||
349 0x1EAA //TX_K_PEPPER_HF
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349 0x1EAA //TX_K_PEPPER_HF
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||||||
350 0x0600 //TX_A_PEPPER_HF
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350 0x0600 //TX_A_PEPPER_HF
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||||||
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@ -56450,9 +56450,9 @@
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||||||
369 0x7FFF //TX_NOISE_TH_0_3
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369 0x7FFF //TX_NOISE_TH_0_3
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||||||
370 0x07D0 //TX_NOISE_TH_1
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370 0x07D0 //TX_NOISE_TH_1
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||||||
371 0x01F4 //TX_NOISE_TH_2
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371 0x01F4 //TX_NOISE_TH_2
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||||||
372 0x36B0 //TX_NOISE_TH_3
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372 0x2EE0 //TX_NOISE_TH_3
|
||||||
373 0x2710 //TX_NOISE_TH_4
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373 0x2710 //TX_NOISE_TH_4
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||||||
374 0x2CEC //TX_NOISE_TH_5
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374 0x7FFF //TX_NOISE_TH_5
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||||||
375 0x7FFF //TX_NOISE_TH_5_2
|
375 0x7FFF //TX_NOISE_TH_5_2
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||||||
376 0x0000 //TX_NOISE_TH_5_3
|
376 0x0000 //TX_NOISE_TH_5_3
|
||||||
377 0x7FFF //TX_NOISE_TH_5_4
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377 0x7FFF //TX_NOISE_TH_5_4
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||||||
|
@ -56659,8 +56659,8 @@
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578 0x5355 //TX_FDEQ_GAIN_11
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578 0x5355 //TX_FDEQ_GAIN_11
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||||||
579 0x5B5F //TX_FDEQ_GAIN_12
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579 0x5B5F //TX_FDEQ_GAIN_12
|
||||||
580 0x5F84 //TX_FDEQ_GAIN_13
|
580 0x5F84 //TX_FDEQ_GAIN_13
|
||||||
581 0x847C //TX_FDEQ_GAIN_14
|
581 0x8476 //TX_FDEQ_GAIN_14
|
||||||
582 0x7178 //TX_FDEQ_GAIN_15
|
582 0x6A71 //TX_FDEQ_GAIN_15
|
||||||
583 0x4848 //TX_FDEQ_GAIN_16
|
583 0x4848 //TX_FDEQ_GAIN_16
|
||||||
584 0x4848 //TX_FDEQ_GAIN_17
|
584 0x4848 //TX_FDEQ_GAIN_17
|
||||||
585 0x4848 //TX_FDEQ_GAIN_18
|
585 0x4848 //TX_FDEQ_GAIN_18
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||||||
|
@ -56944,7 +56944,7 @@
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863 0x199A //TX_TDDRC_HMNC_GAIN
|
863 0x199A //TX_TDDRC_HMNC_GAIN
|
||||||
864 0x0000 //TX_TDDRC_SMT_FLAG
|
864 0x0000 //TX_TDDRC_SMT_FLAG
|
||||||
865 0x0CCD //TX_TDDRC_SMT_W
|
865 0x0CCD //TX_TDDRC_SMT_W
|
||||||
866 0x0FDA //TX_TDDRC_DRC_GAIN
|
866 0x1380 //TX_TDDRC_DRC_GAIN
|
||||||
867 0x7FFF //TX_TDDRC_LMT_THRD
|
867 0x7FFF //TX_TDDRC_LMT_THRD
|
||||||
868 0x0000 //TX_TDDRC_LMT_ALPHA
|
868 0x0000 //TX_TDDRC_LMT_ALPHA
|
||||||
869 0x0000 //TX_TFMASKLTH
|
869 0x0000 //TX_TFMASKLTH
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||||||
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|
@ -167,11 +167,20 @@
|
||||||
"Path": "/proc/vendor_sched/nnapi_uclamp_min",
|
"Path": "/proc/vendor_sched/nnapi_uclamp_min",
|
||||||
"Values": [
|
"Values": [
|
||||||
"180",
|
"180",
|
||||||
"512"
|
"650"
|
||||||
],
|
],
|
||||||
"DefaultIndex": 0,
|
"DefaultIndex": 0,
|
||||||
"ResetOnInit": true
|
"ResetOnInit": true
|
||||||
},
|
},
|
||||||
|
{
|
||||||
|
"Name": "PMQoSCpuDmaLatency",
|
||||||
|
"Path": "/dev/cpu_dma_latency",
|
||||||
|
"Values": [
|
||||||
|
"44",
|
||||||
|
"1000"
|
||||||
|
],
|
||||||
|
"HoldFd": true
|
||||||
|
},
|
||||||
{
|
{
|
||||||
"Name": "CDPreferIdle",
|
"Name": "CDPreferIdle",
|
||||||
"Path": "/proc/vendor_sched/cam_prefer_idle",
|
"Path": "/proc/vendor_sched/cam_prefer_idle",
|
||||||
|
@ -1653,7 +1662,13 @@
|
||||||
"PowerHint": "ML_ACC",
|
"PowerHint": "ML_ACC",
|
||||||
"Node": "MLUclampBoost",
|
"Node": "MLUclampBoost",
|
||||||
"Duration": 2000,
|
"Duration": 2000,
|
||||||
"Value": "512"
|
"Value": "650"
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"PowerHint": "ML_ACC",
|
||||||
|
"Node": "PMQoSCpuDmaLatency",
|
||||||
|
"Duration": 2000,
|
||||||
|
"Value": "44"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"PowerHint": "DEVICE_IDLE",
|
"PowerHint": "DEVICE_IDLE",
|
||||||
|
@ -1674,13 +1689,14 @@
|
||||||
"PID_On": true,
|
"PID_On": true,
|
||||||
"PID_Po": 2.0,
|
"PID_Po": 2.0,
|
||||||
"PID_Pu": 1.0,
|
"PID_Pu": 1.0,
|
||||||
"PID_I": 0.001,
|
"PID_I": 0.0,
|
||||||
"PID_I_Init": 200,
|
"PID_I_Init": 200,
|
||||||
"PID_I_High": 512,
|
"PID_I_High": 512,
|
||||||
"PID_I_Low": -30,
|
"PID_I_Low": -30,
|
||||||
"PID_Do": 500.0,
|
"PID_Do": 500.0,
|
||||||
"PID_Du": 0.0,
|
"PID_Du": 0.0,
|
||||||
"UclampMin_On": true,
|
"UclampMin_On": true,
|
||||||
|
"UclampMin_Init": 185,
|
||||||
"UclampMin_High": 384,
|
"UclampMin_High": 384,
|
||||||
"UclampMin_Low": 2,
|
"UclampMin_Low": 2,
|
||||||
"SamplingWindow_P": 1,
|
"SamplingWindow_P": 1,
|
||||||
|
@ -1697,13 +1713,14 @@
|
||||||
"PID_On": true,
|
"PID_On": true,
|
||||||
"PID_Po": 2.0,
|
"PID_Po": 2.0,
|
||||||
"PID_Pu": 1.0,
|
"PID_Pu": 1.0,
|
||||||
"PID_I": 0.001,
|
"PID_I": 0.0,
|
||||||
"PID_I_Init": 200,
|
"PID_I_Init": 200,
|
||||||
"PID_I_High": 512,
|
"PID_I_High": 512,
|
||||||
"PID_I_Low": -30,
|
"PID_I_Low": -30,
|
||||||
"PID_Do": 500.0,
|
"PID_Do": 500.0,
|
||||||
"PID_Du": 0.0,
|
"PID_Du": 0.0,
|
||||||
"UclampMin_On": true,
|
"UclampMin_On": true,
|
||||||
|
"UclampMin_Init": 129,
|
||||||
"UclampMin_High": 384,
|
"UclampMin_High": 384,
|
||||||
"UclampMin_Low": 2,
|
"UclampMin_Low": 2,
|
||||||
"SamplingWindow_P": 1,
|
"SamplingWindow_P": 1,
|
||||||
|
@ -1720,13 +1737,14 @@
|
||||||
"PID_On": true,
|
"PID_On": true,
|
||||||
"PID_Po": 2.0,
|
"PID_Po": 2.0,
|
||||||
"PID_Pu": 1.0,
|
"PID_Pu": 1.0,
|
||||||
"PID_I": 0.001,
|
"PID_I": 0.0,
|
||||||
"PID_I_Init": 200,
|
"PID_I_Init": 200,
|
||||||
"PID_I_High": 512,
|
"PID_I_High": 512,
|
||||||
"PID_I_Low": -30,
|
"PID_I_Low": -30,
|
||||||
"PID_Do": 500.0,
|
"PID_Do": 500.0,
|
||||||
"PID_Du": 0.0,
|
"PID_Du": 0.0,
|
||||||
"UclampMin_On": true,
|
"UclampMin_On": true,
|
||||||
|
"UclampMin_Init": 129,
|
||||||
"UclampMin_High": 384,
|
"UclampMin_High": 384,
|
||||||
"UclampMin_Low": 2,
|
"UclampMin_Low": 2,
|
||||||
"SamplingWindow_P": 1,
|
"SamplingWindow_P": 1,
|
||||||
|
@ -1753,6 +1771,7 @@
|
||||||
"SamplingWindow_I": 1,
|
"SamplingWindow_I": 1,
|
||||||
"SamplingWindow_D": 1,
|
"SamplingWindow_D": 1,
|
||||||
"UclampMin_On": true,
|
"UclampMin_On": true,
|
||||||
|
"UclampMin_Init": 200,
|
||||||
"UclampMin_High": 157,
|
"UclampMin_High": 157,
|
||||||
"UclampMin_Low": 157,
|
"UclampMin_Low": 157,
|
||||||
"ReportingRateLimitNs": 1,
|
"ReportingRateLimitNs": 1,
|
||||||
|
@ -1776,6 +1795,7 @@
|
||||||
"SamplingWindow_I": 1,
|
"SamplingWindow_I": 1,
|
||||||
"SamplingWindow_D": 1,
|
"SamplingWindow_D": 1,
|
||||||
"UclampMin_On": true,
|
"UclampMin_On": true,
|
||||||
|
"UclampMin_Init": 200,
|
||||||
"UclampMin_High": 42,
|
"UclampMin_High": 42,
|
||||||
"UclampMin_Low": 42,
|
"UclampMin_Low": 42,
|
||||||
"ReportingRateLimitNs": 1,
|
"ReportingRateLimitNs": 1,
|
||||||
|
@ -1799,6 +1819,7 @@
|
||||||
"SamplingWindow_I": 1,
|
"SamplingWindow_I": 1,
|
||||||
"SamplingWindow_D": 1,
|
"SamplingWindow_D": 1,
|
||||||
"UclampMin_On": true,
|
"UclampMin_On": true,
|
||||||
|
"UclampMin_Init": 200,
|
||||||
"UclampMin_High": 0,
|
"UclampMin_High": 0,
|
||||||
"UclampMin_Low": 0,
|
"UclampMin_Low": 0,
|
||||||
"ReportingRateLimitNs": 1,
|
"ReportingRateLimitNs": 1,
|
||||||
|
|
|
@ -185,11 +185,20 @@
|
||||||
"Path": "/proc/vendor_sched/nnapi_uclamp_min",
|
"Path": "/proc/vendor_sched/nnapi_uclamp_min",
|
||||||
"Values": [
|
"Values": [
|
||||||
"180",
|
"180",
|
||||||
"512"
|
"650"
|
||||||
],
|
],
|
||||||
"DefaultIndex": 0,
|
"DefaultIndex": 0,
|
||||||
"ResetOnInit": true
|
"ResetOnInit": true
|
||||||
},
|
},
|
||||||
|
{
|
||||||
|
"Name": "PMQoSCpuDmaLatency",
|
||||||
|
"Path": "/dev/cpu_dma_latency",
|
||||||
|
"Values": [
|
||||||
|
"44",
|
||||||
|
"1000"
|
||||||
|
],
|
||||||
|
"HoldFd": true
|
||||||
|
},
|
||||||
{
|
{
|
||||||
"Name": "CDPreferIdle",
|
"Name": "CDPreferIdle",
|
||||||
"Path": "/proc/vendor_sched/cam_prefer_idle",
|
"Path": "/proc/vendor_sched/cam_prefer_idle",
|
||||||
|
@ -1675,7 +1684,13 @@
|
||||||
"PowerHint": "ML_ACC",
|
"PowerHint": "ML_ACC",
|
||||||
"Node": "MLUclampBoost",
|
"Node": "MLUclampBoost",
|
||||||
"Duration": 2000,
|
"Duration": 2000,
|
||||||
"Value": "512"
|
"Value": "650"
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"PowerHint": "ML_ACC",
|
||||||
|
"Node": "PMQoSCpuDmaLatency",
|
||||||
|
"Duration": 2000,
|
||||||
|
"Value": "44"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"PowerHint": "DEVICE_IDLE",
|
"PowerHint": "DEVICE_IDLE",
|
||||||
|
@ -1696,13 +1711,14 @@
|
||||||
"PID_On": true,
|
"PID_On": true,
|
||||||
"PID_Po": 2.0,
|
"PID_Po": 2.0,
|
||||||
"PID_Pu": 1.0,
|
"PID_Pu": 1.0,
|
||||||
"PID_I": 0.001,
|
"PID_I": 0.0,
|
||||||
"PID_I_Init": 200,
|
"PID_I_Init": 200,
|
||||||
"PID_I_High": 512,
|
"PID_I_High": 512,
|
||||||
"PID_I_Low": -30,
|
"PID_I_Low": -30,
|
||||||
"PID_Do": 500.0,
|
"PID_Do": 500.0,
|
||||||
"PID_Du": 0.0,
|
"PID_Du": 0.0,
|
||||||
"UclampMin_On": true,
|
"UclampMin_On": true,
|
||||||
|
"UclampMin_Init": 185,
|
||||||
"UclampMin_High": 384,
|
"UclampMin_High": 384,
|
||||||
"UclampMin_Low": 2,
|
"UclampMin_Low": 2,
|
||||||
"SamplingWindow_P": 1,
|
"SamplingWindow_P": 1,
|
||||||
|
@ -1719,13 +1735,14 @@
|
||||||
"PID_On": true,
|
"PID_On": true,
|
||||||
"PID_Po": 2.0,
|
"PID_Po": 2.0,
|
||||||
"PID_Pu": 1.0,
|
"PID_Pu": 1.0,
|
||||||
"PID_I": 0.001,
|
"PID_I": 0.0,
|
||||||
"PID_I_Init": 200,
|
"PID_I_Init": 200,
|
||||||
"PID_I_High": 512,
|
"PID_I_High": 512,
|
||||||
"PID_I_Low": -30,
|
"PID_I_Low": -30,
|
||||||
"PID_Do": 500.0,
|
"PID_Do": 500.0,
|
||||||
"PID_Du": 0.0,
|
"PID_Du": 0.0,
|
||||||
"UclampMin_On": true,
|
"UclampMin_On": true,
|
||||||
|
"UclampMin_Init": 129,
|
||||||
"UclampMin_High": 384,
|
"UclampMin_High": 384,
|
||||||
"UclampMin_Low": 2,
|
"UclampMin_Low": 2,
|
||||||
"SamplingWindow_P": 1,
|
"SamplingWindow_P": 1,
|
||||||
|
@ -1742,13 +1759,14 @@
|
||||||
"PID_On": true,
|
"PID_On": true,
|
||||||
"PID_Po": 2.0,
|
"PID_Po": 2.0,
|
||||||
"PID_Pu": 1.0,
|
"PID_Pu": 1.0,
|
||||||
"PID_I": 0.001,
|
"PID_I": 0.0,
|
||||||
"PID_I_Init": 200,
|
"PID_I_Init": 200,
|
||||||
"PID_I_High": 512,
|
"PID_I_High": 512,
|
||||||
"PID_I_Low": -30,
|
"PID_I_Low": -30,
|
||||||
"PID_Do": 500.0,
|
"PID_Do": 500.0,
|
||||||
"PID_Du": 0.0,
|
"PID_Du": 0.0,
|
||||||
"UclampMin_On": true,
|
"UclampMin_On": true,
|
||||||
|
"UclampMin_Init": 129,
|
||||||
"UclampMin_High": 384,
|
"UclampMin_High": 384,
|
||||||
"UclampMin_Low": 2,
|
"UclampMin_Low": 2,
|
||||||
"SamplingWindow_P": 1,
|
"SamplingWindow_P": 1,
|
||||||
|
@ -1775,6 +1793,7 @@
|
||||||
"SamplingWindow_I": 1,
|
"SamplingWindow_I": 1,
|
||||||
"SamplingWindow_D": 1,
|
"SamplingWindow_D": 1,
|
||||||
"UclampMin_On": true,
|
"UclampMin_On": true,
|
||||||
|
"UclampMin_Init": 200,
|
||||||
"UclampMin_High": 157,
|
"UclampMin_High": 157,
|
||||||
"UclampMin_Low": 157,
|
"UclampMin_Low": 157,
|
||||||
"ReportingRateLimitNs": 1,
|
"ReportingRateLimitNs": 1,
|
||||||
|
@ -1798,6 +1817,7 @@
|
||||||
"SamplingWindow_I": 1,
|
"SamplingWindow_I": 1,
|
||||||
"SamplingWindow_D": 1,
|
"SamplingWindow_D": 1,
|
||||||
"UclampMin_On": true,
|
"UclampMin_On": true,
|
||||||
|
"UclampMin_Init": 200,
|
||||||
"UclampMin_High": 42,
|
"UclampMin_High": 42,
|
||||||
"UclampMin_Low": 42,
|
"UclampMin_Low": 42,
|
||||||
"ReportingRateLimitNs": 1,
|
"ReportingRateLimitNs": 1,
|
||||||
|
@ -1821,6 +1841,7 @@
|
||||||
"SamplingWindow_I": 1,
|
"SamplingWindow_I": 1,
|
||||||
"SamplingWindow_D": 1,
|
"SamplingWindow_D": 1,
|
||||||
"UclampMin_On": true,
|
"UclampMin_On": true,
|
||||||
|
"UclampMin_Init": 200,
|
||||||
"UclampMin_High": 0,
|
"UclampMin_High": 0,
|
||||||
"UclampMin_Low": 0,
|
"UclampMin_Low": 0,
|
||||||
"ReportingRateLimitNs": 1,
|
"ReportingRateLimitNs": 1,
|
||||||
|
|
|
@ -1095,13 +1095,14 @@
|
||||||
"PID_On": true,
|
"PID_On": true,
|
||||||
"PID_Po": 2.0,
|
"PID_Po": 2.0,
|
||||||
"PID_Pu": 1.0,
|
"PID_Pu": 1.0,
|
||||||
"PID_I": 0.001,
|
"PID_I": 0.0,
|
||||||
"PID_I_Init": 200,
|
"PID_I_Init": 200,
|
||||||
"PID_I_High": 512,
|
"PID_I_High": 512,
|
||||||
"PID_I_Low": -30,
|
"PID_I_Low": -30,
|
||||||
"PID_Do": 500.0,
|
"PID_Do": 500.0,
|
||||||
"PID_Du": 0.0,
|
"PID_Du": 0.0,
|
||||||
"UclampMin_On": true,
|
"UclampMin_On": true,
|
||||||
|
"UclampMin_Init": 185,
|
||||||
"UclampMin_High": 384,
|
"UclampMin_High": 384,
|
||||||
"UclampMin_Low": 2,
|
"UclampMin_Low": 2,
|
||||||
"SamplingWindow_P": 1,
|
"SamplingWindow_P": 1,
|
||||||
|
@ -1118,13 +1119,14 @@
|
||||||
"PID_On": true,
|
"PID_On": true,
|
||||||
"PID_Po": 2.0,
|
"PID_Po": 2.0,
|
||||||
"PID_Pu": 1.0,
|
"PID_Pu": 1.0,
|
||||||
"PID_I": 0.001,
|
"PID_I": 0.0,
|
||||||
"PID_I_Init": 200,
|
"PID_I_Init": 200,
|
||||||
"PID_I_High": 512,
|
"PID_I_High": 512,
|
||||||
"PID_I_Low": -30,
|
"PID_I_Low": -30,
|
||||||
"PID_Do": 500.0,
|
"PID_Do": 500.0,
|
||||||
"PID_Du": 0.0,
|
"PID_Du": 0.0,
|
||||||
"UclampMin_On": true,
|
"UclampMin_On": true,
|
||||||
|
"UclampMin_Init": 129,
|
||||||
"UclampMin_High": 384,
|
"UclampMin_High": 384,
|
||||||
"UclampMin_Low": 2,
|
"UclampMin_Low": 2,
|
||||||
"SamplingWindow_P": 1,
|
"SamplingWindow_P": 1,
|
||||||
|
@ -1141,13 +1143,14 @@
|
||||||
"PID_On": true,
|
"PID_On": true,
|
||||||
"PID_Po": 2.0,
|
"PID_Po": 2.0,
|
||||||
"PID_Pu": 1.0,
|
"PID_Pu": 1.0,
|
||||||
"PID_I": 0.001,
|
"PID_I": 0.0,
|
||||||
"PID_I_Init": 200,
|
"PID_I_Init": 200,
|
||||||
"PID_I_High": 512,
|
"PID_I_High": 512,
|
||||||
"PID_I_Low": -30,
|
"PID_I_Low": -30,
|
||||||
"PID_Do": 500.0,
|
"PID_Do": 500.0,
|
||||||
"PID_Du": 0.0,
|
"PID_Du": 0.0,
|
||||||
"UclampMin_On": true,
|
"UclampMin_On": true,
|
||||||
|
"UclampMin_Init": 129,
|
||||||
"UclampMin_High": 384,
|
"UclampMin_High": 384,
|
||||||
"UclampMin_Low": 2,
|
"UclampMin_Low": 2,
|
||||||
"SamplingWindow_P": 1,
|
"SamplingWindow_P": 1,
|
||||||
|
@ -1174,6 +1177,7 @@
|
||||||
"SamplingWindow_I": 1,
|
"SamplingWindow_I": 1,
|
||||||
"SamplingWindow_D": 1,
|
"SamplingWindow_D": 1,
|
||||||
"UclampMin_On": true,
|
"UclampMin_On": true,
|
||||||
|
"UclampMin_Init": 200,
|
||||||
"UclampMin_High": 157,
|
"UclampMin_High": 157,
|
||||||
"UclampMin_Low": 157,
|
"UclampMin_Low": 157,
|
||||||
"ReportingRateLimitNs": 1,
|
"ReportingRateLimitNs": 1,
|
||||||
|
@ -1197,6 +1201,7 @@
|
||||||
"SamplingWindow_I": 1,
|
"SamplingWindow_I": 1,
|
||||||
"SamplingWindow_D": 1,
|
"SamplingWindow_D": 1,
|
||||||
"UclampMin_On": true,
|
"UclampMin_On": true,
|
||||||
|
"UclampMin_Init": 200,
|
||||||
"UclampMin_High": 42,
|
"UclampMin_High": 42,
|
||||||
"UclampMin_Low": 42,
|
"UclampMin_Low": 42,
|
||||||
"ReportingRateLimitNs": 1,
|
"ReportingRateLimitNs": 1,
|
||||||
|
@ -1220,6 +1225,7 @@
|
||||||
"SamplingWindow_I": 1,
|
"SamplingWindow_I": 1,
|
||||||
"SamplingWindow_D": 1,
|
"SamplingWindow_D": 1,
|
||||||
"UclampMin_On": true,
|
"UclampMin_On": true,
|
||||||
|
"UclampMin_Init": 200,
|
||||||
"UclampMin_High": 0,
|
"UclampMin_High": 0,
|
||||||
"UclampMin_Low": 0,
|
"UclampMin_Low": 0,
|
||||||
"ReportingRateLimitNs": 1,
|
"ReportingRateLimitNs": 1,
|
||||||
|
|
|
@ -167,11 +167,20 @@
|
||||||
"Path": "/proc/vendor_sched/nnapi_uclamp_min",
|
"Path": "/proc/vendor_sched/nnapi_uclamp_min",
|
||||||
"Values": [
|
"Values": [
|
||||||
"180",
|
"180",
|
||||||
"512"
|
"650"
|
||||||
],
|
],
|
||||||
"DefaultIndex": 0,
|
"DefaultIndex": 0,
|
||||||
"ResetOnInit": true
|
"ResetOnInit": true
|
||||||
},
|
},
|
||||||
|
{
|
||||||
|
"Name": "PMQoSCpuDmaLatency",
|
||||||
|
"Path": "/dev/cpu_dma_latency",
|
||||||
|
"Values": [
|
||||||
|
"44",
|
||||||
|
"1000"
|
||||||
|
],
|
||||||
|
"HoldFd": true
|
||||||
|
},
|
||||||
{
|
{
|
||||||
"Name": "CDPreferIdle",
|
"Name": "CDPreferIdle",
|
||||||
"Path": "/proc/vendor_sched/cam_prefer_idle",
|
"Path": "/proc/vendor_sched/cam_prefer_idle",
|
||||||
|
@ -1637,7 +1646,13 @@
|
||||||
"PowerHint": "ML_ACC",
|
"PowerHint": "ML_ACC",
|
||||||
"Node": "MLUclampBoost",
|
"Node": "MLUclampBoost",
|
||||||
"Duration": 2000,
|
"Duration": 2000,
|
||||||
"Value": "512"
|
"Value": "650"
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"PowerHint": "ML_ACC",
|
||||||
|
"Node": "PMQoSCpuDmaLatency",
|
||||||
|
"Duration": 2000,
|
||||||
|
"Value": "44"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"PowerHint": "DEVICE_IDLE",
|
"PowerHint": "DEVICE_IDLE",
|
||||||
|
@ -1658,13 +1673,14 @@
|
||||||
"PID_On": true,
|
"PID_On": true,
|
||||||
"PID_Po": 2.0,
|
"PID_Po": 2.0,
|
||||||
"PID_Pu": 1.0,
|
"PID_Pu": 1.0,
|
||||||
"PID_I": 0.001,
|
"PID_I": 0.0,
|
||||||
"PID_I_Init": 200,
|
"PID_I_Init": 200,
|
||||||
"PID_I_High": 512,
|
"PID_I_High": 512,
|
||||||
"PID_I_Low": -30,
|
"PID_I_Low": -30,
|
||||||
"PID_Do": 500.0,
|
"PID_Do": 500.0,
|
||||||
"PID_Du": 0.0,
|
"PID_Du": 0.0,
|
||||||
"UclampMin_On": true,
|
"UclampMin_On": true,
|
||||||
|
"UclampMin_Init": 185,
|
||||||
"UclampMin_High": 384,
|
"UclampMin_High": 384,
|
||||||
"UclampMin_Low": 2,
|
"UclampMin_Low": 2,
|
||||||
"SamplingWindow_P": 1,
|
"SamplingWindow_P": 1,
|
||||||
|
@ -1681,13 +1697,14 @@
|
||||||
"PID_On": true,
|
"PID_On": true,
|
||||||
"PID_Po": 2.0,
|
"PID_Po": 2.0,
|
||||||
"PID_Pu": 1.0,
|
"PID_Pu": 1.0,
|
||||||
"PID_I": 0.001,
|
"PID_I": 0.0,
|
||||||
"PID_I_Init": 200,
|
"PID_I_Init": 200,
|
||||||
"PID_I_High": 512,
|
"PID_I_High": 512,
|
||||||
"PID_I_Low": -30,
|
"PID_I_Low": -30,
|
||||||
"PID_Do": 500.0,
|
"PID_Do": 500.0,
|
||||||
"PID_Du": 0.0,
|
"PID_Du": 0.0,
|
||||||
"UclampMin_On": true,
|
"UclampMin_On": true,
|
||||||
|
"UclampMin_Init": 129,
|
||||||
"UclampMin_High": 384,
|
"UclampMin_High": 384,
|
||||||
"UclampMin_Low": 2,
|
"UclampMin_Low": 2,
|
||||||
"SamplingWindow_P": 1,
|
"SamplingWindow_P": 1,
|
||||||
|
@ -1704,13 +1721,14 @@
|
||||||
"PID_On": true,
|
"PID_On": true,
|
||||||
"PID_Po": 2.0,
|
"PID_Po": 2.0,
|
||||||
"PID_Pu": 1.0,
|
"PID_Pu": 1.0,
|
||||||
"PID_I": 0.001,
|
"PID_I": 0.0,
|
||||||
"PID_I_Init": 200,
|
"PID_I_Init": 200,
|
||||||
"PID_I_High": 512,
|
"PID_I_High": 512,
|
||||||
"PID_I_Low": -30,
|
"PID_I_Low": -30,
|
||||||
"PID_Do": 500.0,
|
"PID_Do": 500.0,
|
||||||
"PID_Du": 0.0,
|
"PID_Du": 0.0,
|
||||||
"UclampMin_On": true,
|
"UclampMin_On": true,
|
||||||
|
"UclampMin_Init": 129,
|
||||||
"UclampMin_High": 384,
|
"UclampMin_High": 384,
|
||||||
"UclampMin_Low": 2,
|
"UclampMin_Low": 2,
|
||||||
"SamplingWindow_P": 1,
|
"SamplingWindow_P": 1,
|
||||||
|
@ -1737,6 +1755,7 @@
|
||||||
"SamplingWindow_I": 1,
|
"SamplingWindow_I": 1,
|
||||||
"SamplingWindow_D": 1,
|
"SamplingWindow_D": 1,
|
||||||
"UclampMin_On": true,
|
"UclampMin_On": true,
|
||||||
|
"UclampMin_Init": 200,
|
||||||
"UclampMin_High": 157,
|
"UclampMin_High": 157,
|
||||||
"UclampMin_Low": 157,
|
"UclampMin_Low": 157,
|
||||||
"ReportingRateLimitNs": 1,
|
"ReportingRateLimitNs": 1,
|
||||||
|
@ -1760,6 +1779,7 @@
|
||||||
"SamplingWindow_I": 1,
|
"SamplingWindow_I": 1,
|
||||||
"SamplingWindow_D": 1,
|
"SamplingWindow_D": 1,
|
||||||
"UclampMin_On": true,
|
"UclampMin_On": true,
|
||||||
|
"UclampMin_Init": 200,
|
||||||
"UclampMin_High": 42,
|
"UclampMin_High": 42,
|
||||||
"UclampMin_Low": 42,
|
"UclampMin_Low": 42,
|
||||||
"ReportingRateLimitNs": 1,
|
"ReportingRateLimitNs": 1,
|
||||||
|
@ -1783,6 +1803,7 @@
|
||||||
"SamplingWindow_I": 1,
|
"SamplingWindow_I": 1,
|
||||||
"SamplingWindow_D": 1,
|
"SamplingWindow_D": 1,
|
||||||
"UclampMin_On": true,
|
"UclampMin_On": true,
|
||||||
|
"UclampMin_Init": 200,
|
||||||
"UclampMin_High": 0,
|
"UclampMin_High": 0,
|
||||||
"UclampMin_Low": 0,
|
"UclampMin_Low": 0,
|
||||||
"ReportingRateLimitNs": 1,
|
"ReportingRateLimitNs": 1,
|
||||||
|
|
|
@ -185,11 +185,20 @@
|
||||||
"Path": "/proc/vendor_sched/nnapi_uclamp_min",
|
"Path": "/proc/vendor_sched/nnapi_uclamp_min",
|
||||||
"Values": [
|
"Values": [
|
||||||
"180",
|
"180",
|
||||||
"512"
|
"650"
|
||||||
],
|
],
|
||||||
"DefaultIndex": 0,
|
"DefaultIndex": 0,
|
||||||
"ResetOnInit": true
|
"ResetOnInit": true
|
||||||
},
|
},
|
||||||
|
{
|
||||||
|
"Name": "PMQoSCpuDmaLatency",
|
||||||
|
"Path": "/dev/cpu_dma_latency",
|
||||||
|
"Values": [
|
||||||
|
"44",
|
||||||
|
"1000"
|
||||||
|
],
|
||||||
|
"HoldFd": true
|
||||||
|
},
|
||||||
{
|
{
|
||||||
"Name": "CDPreferIdle",
|
"Name": "CDPreferIdle",
|
||||||
"Path": "/proc/vendor_sched/cam_prefer_idle",
|
"Path": "/proc/vendor_sched/cam_prefer_idle",
|
||||||
|
@ -1659,7 +1668,13 @@
|
||||||
"PowerHint": "ML_ACC",
|
"PowerHint": "ML_ACC",
|
||||||
"Node": "MLUclampBoost",
|
"Node": "MLUclampBoost",
|
||||||
"Duration": 2000,
|
"Duration": 2000,
|
||||||
"Value": "512"
|
"Value": "650"
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"PowerHint": "ML_ACC",
|
||||||
|
"Node": "PMQoSCpuDmaLatency",
|
||||||
|
"Duration": 2000,
|
||||||
|
"Value": "44"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"PowerHint": "DEVICE_IDLE",
|
"PowerHint": "DEVICE_IDLE",
|
||||||
|
@ -1680,13 +1695,14 @@
|
||||||
"PID_On": true,
|
"PID_On": true,
|
||||||
"PID_Po": 2.0,
|
"PID_Po": 2.0,
|
||||||
"PID_Pu": 1.0,
|
"PID_Pu": 1.0,
|
||||||
"PID_I": 0.001,
|
"PID_I": 0.0,
|
||||||
"PID_I_Init": 200,
|
"PID_I_Init": 200,
|
||||||
"PID_I_High": 512,
|
"PID_I_High": 512,
|
||||||
"PID_I_Low": -30,
|
"PID_I_Low": -30,
|
||||||
"PID_Do": 500.0,
|
"PID_Do": 500.0,
|
||||||
"PID_Du": 0.0,
|
"PID_Du": 0.0,
|
||||||
"UclampMin_On": true,
|
"UclampMin_On": true,
|
||||||
|
"UclampMin_Init": 185,
|
||||||
"UclampMin_High": 384,
|
"UclampMin_High": 384,
|
||||||
"UclampMin_Low": 2,
|
"UclampMin_Low": 2,
|
||||||
"SamplingWindow_P": 1,
|
"SamplingWindow_P": 1,
|
||||||
|
@ -1703,13 +1719,14 @@
|
||||||
"PID_On": true,
|
"PID_On": true,
|
||||||
"PID_Po": 2.0,
|
"PID_Po": 2.0,
|
||||||
"PID_Pu": 1.0,
|
"PID_Pu": 1.0,
|
||||||
"PID_I": 0.001,
|
"PID_I": 0.0,
|
||||||
"PID_I_Init": 200,
|
"PID_I_Init": 200,
|
||||||
"PID_I_High": 512,
|
"PID_I_High": 512,
|
||||||
"PID_I_Low": -30,
|
"PID_I_Low": -30,
|
||||||
"PID_Do": 500.0,
|
"PID_Do": 500.0,
|
||||||
"PID_Du": 0.0,
|
"PID_Du": 0.0,
|
||||||
"UclampMin_On": true,
|
"UclampMin_On": true,
|
||||||
|
"UclampMin_Init": 129,
|
||||||
"UclampMin_High": 384,
|
"UclampMin_High": 384,
|
||||||
"UclampMin_Low": 2,
|
"UclampMin_Low": 2,
|
||||||
"SamplingWindow_P": 1,
|
"SamplingWindow_P": 1,
|
||||||
|
@ -1726,13 +1743,14 @@
|
||||||
"PID_On": true,
|
"PID_On": true,
|
||||||
"PID_Po": 2.0,
|
"PID_Po": 2.0,
|
||||||
"PID_Pu": 1.0,
|
"PID_Pu": 1.0,
|
||||||
"PID_I": 0.001,
|
"PID_I": 0.0,
|
||||||
"PID_I_Init": 200,
|
"PID_I_Init": 200,
|
||||||
"PID_I_High": 512,
|
"PID_I_High": 512,
|
||||||
"PID_I_Low": -30,
|
"PID_I_Low": -30,
|
||||||
"PID_Do": 500.0,
|
"PID_Do": 500.0,
|
||||||
"PID_Du": 0.0,
|
"PID_Du": 0.0,
|
||||||
"UclampMin_On": true,
|
"UclampMin_On": true,
|
||||||
|
"UclampMin_Init": 129,
|
||||||
"UclampMin_High": 384,
|
"UclampMin_High": 384,
|
||||||
"UclampMin_Low": 2,
|
"UclampMin_Low": 2,
|
||||||
"SamplingWindow_P": 1,
|
"SamplingWindow_P": 1,
|
||||||
|
@ -1759,6 +1777,7 @@
|
||||||
"SamplingWindow_I": 1,
|
"SamplingWindow_I": 1,
|
||||||
"SamplingWindow_D": 1,
|
"SamplingWindow_D": 1,
|
||||||
"UclampMin_On": true,
|
"UclampMin_On": true,
|
||||||
|
"UclampMin_Init": 200,
|
||||||
"UclampMin_High": 157,
|
"UclampMin_High": 157,
|
||||||
"UclampMin_Low": 157,
|
"UclampMin_Low": 157,
|
||||||
"ReportingRateLimitNs": 1,
|
"ReportingRateLimitNs": 1,
|
||||||
|
@ -1782,6 +1801,7 @@
|
||||||
"SamplingWindow_I": 1,
|
"SamplingWindow_I": 1,
|
||||||
"SamplingWindow_D": 1,
|
"SamplingWindow_D": 1,
|
||||||
"UclampMin_On": true,
|
"UclampMin_On": true,
|
||||||
|
"UclampMin_Init": 200,
|
||||||
"UclampMin_High": 42,
|
"UclampMin_High": 42,
|
||||||
"UclampMin_Low": 42,
|
"UclampMin_Low": 42,
|
||||||
"ReportingRateLimitNs": 1,
|
"ReportingRateLimitNs": 1,
|
||||||
|
@ -1805,6 +1825,7 @@
|
||||||
"SamplingWindow_I": 1,
|
"SamplingWindow_I": 1,
|
||||||
"SamplingWindow_D": 1,
|
"SamplingWindow_D": 1,
|
||||||
"UclampMin_On": true,
|
"UclampMin_On": true,
|
||||||
|
"UclampMin_Init": 200,
|
||||||
"UclampMin_High": 0,
|
"UclampMin_High": 0,
|
||||||
"UclampMin_Low": 0,
|
"UclampMin_Low": 0,
|
||||||
"ReportingRateLimitNs": 1,
|
"ReportingRateLimitNs": 1,
|
||||||
|
|
|
@ -1095,13 +1095,14 @@
|
||||||
"PID_On": true,
|
"PID_On": true,
|
||||||
"PID_Po": 2.0,
|
"PID_Po": 2.0,
|
||||||
"PID_Pu": 1.0,
|
"PID_Pu": 1.0,
|
||||||
"PID_I": 0.001,
|
"PID_I": 0.0,
|
||||||
"PID_I_Init": 200,
|
"PID_I_Init": 200,
|
||||||
"PID_I_High": 512,
|
"PID_I_High": 512,
|
||||||
"PID_I_Low": -30,
|
"PID_I_Low": -30,
|
||||||
"PID_Do": 500.0,
|
"PID_Do": 500.0,
|
||||||
"PID_Du": 0.0,
|
"PID_Du": 0.0,
|
||||||
"UclampMin_On": true,
|
"UclampMin_On": true,
|
||||||
|
"UclampMin_Init": 185,
|
||||||
"UclampMin_High": 384,
|
"UclampMin_High": 384,
|
||||||
"UclampMin_Low": 2,
|
"UclampMin_Low": 2,
|
||||||
"SamplingWindow_P": 1,
|
"SamplingWindow_P": 1,
|
||||||
|
@ -1118,13 +1119,14 @@
|
||||||
"PID_On": true,
|
"PID_On": true,
|
||||||
"PID_Po": 2.0,
|
"PID_Po": 2.0,
|
||||||
"PID_Pu": 1.0,
|
"PID_Pu": 1.0,
|
||||||
"PID_I": 0.001,
|
"PID_I": 0.0,
|
||||||
"PID_I_Init": 200,
|
"PID_I_Init": 200,
|
||||||
"PID_I_High": 512,
|
"PID_I_High": 512,
|
||||||
"PID_I_Low": -30,
|
"PID_I_Low": -30,
|
||||||
"PID_Do": 500.0,
|
"PID_Do": 500.0,
|
||||||
"PID_Du": 0.0,
|
"PID_Du": 0.0,
|
||||||
"UclampMin_On": true,
|
"UclampMin_On": true,
|
||||||
|
"UclampMin_Init": 129,
|
||||||
"UclampMin_High": 384,
|
"UclampMin_High": 384,
|
||||||
"UclampMin_Low": 2,
|
"UclampMin_Low": 2,
|
||||||
"SamplingWindow_P": 1,
|
"SamplingWindow_P": 1,
|
||||||
|
@ -1141,13 +1143,14 @@
|
||||||
"PID_On": true,
|
"PID_On": true,
|
||||||
"PID_Po": 2.0,
|
"PID_Po": 2.0,
|
||||||
"PID_Pu": 1.0,
|
"PID_Pu": 1.0,
|
||||||
"PID_I": 0.001,
|
"PID_I": 0.0,
|
||||||
"PID_I_Init": 200,
|
"PID_I_Init": 200,
|
||||||
"PID_I_High": 512,
|
"PID_I_High": 512,
|
||||||
"PID_I_Low": -30,
|
"PID_I_Low": -30,
|
||||||
"PID_Do": 500.0,
|
"PID_Do": 500.0,
|
||||||
"PID_Du": 0.0,
|
"PID_Du": 0.0,
|
||||||
"UclampMin_On": true,
|
"UclampMin_On": true,
|
||||||
|
"UclampMin_Init": 129,
|
||||||
"UclampMin_High": 384,
|
"UclampMin_High": 384,
|
||||||
"UclampMin_Low": 2,
|
"UclampMin_Low": 2,
|
||||||
"SamplingWindow_P": 1,
|
"SamplingWindow_P": 1,
|
||||||
|
@ -1174,6 +1177,7 @@
|
||||||
"SamplingWindow_I": 1,
|
"SamplingWindow_I": 1,
|
||||||
"SamplingWindow_D": 1,
|
"SamplingWindow_D": 1,
|
||||||
"UclampMin_On": true,
|
"UclampMin_On": true,
|
||||||
|
"UclampMin_Init": 200,
|
||||||
"UclampMin_High": 157,
|
"UclampMin_High": 157,
|
||||||
"UclampMin_Low": 157,
|
"UclampMin_Low": 157,
|
||||||
"ReportingRateLimitNs": 1,
|
"ReportingRateLimitNs": 1,
|
||||||
|
@ -1197,6 +1201,7 @@
|
||||||
"SamplingWindow_I": 1,
|
"SamplingWindow_I": 1,
|
||||||
"SamplingWindow_D": 1,
|
"SamplingWindow_D": 1,
|
||||||
"UclampMin_On": true,
|
"UclampMin_On": true,
|
||||||
|
"UclampMin_Init": 200,
|
||||||
"UclampMin_High": 42,
|
"UclampMin_High": 42,
|
||||||
"UclampMin_Low": 42,
|
"UclampMin_Low": 42,
|
||||||
"ReportingRateLimitNs": 1,
|
"ReportingRateLimitNs": 1,
|
||||||
|
@ -1220,6 +1225,7 @@
|
||||||
"SamplingWindow_I": 1,
|
"SamplingWindow_I": 1,
|
||||||
"SamplingWindow_D": 1,
|
"SamplingWindow_D": 1,
|
||||||
"UclampMin_On": true,
|
"UclampMin_On": true,
|
||||||
|
"UclampMin_Init": 200,
|
||||||
"UclampMin_High": 0,
|
"UclampMin_High": 0,
|
||||||
"UclampMin_Low": 0,
|
"UclampMin_Low": 0,
|
||||||
"ReportingRateLimitNs": 1,
|
"ReportingRateLimitNs": 1,
|
||||||
|
|
Loading…
Add table
Add a link
Reference in a new issue