From a5146d127e2a7a014d96074d7c747f2bc73adf7d Mon Sep 17 00:00:00 2001 From: Wilson Sung Date: Thu, 14 Sep 2023 22:49:06 +0800 Subject: [PATCH] Initialize Tegu Copy tegu from caimito c3019ae Bug: 298309659 Change-Id: I7d168ff0c60b7c3696239c12534ea3cfac239c1a --- Android.bp | 31 + Android.mk | 30 + AndroidProducts.mk | 23 + NOTICE | 190 + OWNERS | 4 + aosp_tegu.mk | 32 + aosp_tegu_fullmte.mk | 5 + audio/tegu/audio-tables.mk | 73 + audio/tegu/config/audio_effects.xml | 63 + .../config/audio_platform_configuration.xml | 304 + .../config/audio_policy_configuration.xml | 255 + ...cy_configuration_a2dp_offload_disabled.xml | 234 + ...icy_configuration_bluetooth_legacy_hal.xml | 234 + audio/tegu/config/mixer_paths.xml | 902 + audio/tegu/config/mixer_paths_factory.xml | 461 + .../config/sound_trigger_configuration.xml | 33 + .../tegu/cs35l41/crus_sp_cal_mixer_paths.xml | 315 + .../cs35l41/fw/R-cs35l41-dsp1-spk-cali.bin | Bin 0 -> 1632 bytes .../cs35l41/fw/R-cs35l41-dsp1-spk-diag.bin | Bin 0 -> 2672 bytes .../cs35l41/fw/R-cs35l41-dsp1-spk-prot.bin | Bin 0 -> 5156 bytes .../tegu/cs35l41/fw/cs35l41-dsp1-spk-cali.bin | Bin 0 -> 1632 bytes .../cs35l41/fw/cs35l41-dsp1-spk-cali.wmfw | Bin 0 -> 34200 bytes .../tegu/cs35l41/fw/cs35l41-dsp1-spk-diag.bin | Bin 0 -> 2632 bytes .../cs35l41/fw/cs35l41-dsp1-spk-diag.wmfw | Bin 0 -> 31980 bytes .../tegu/cs35l41/fw/cs35l41-dsp1-spk-prot.bin | Bin 0 -> 5156 bytes .../cs35l41/fw/cs35l41-dsp1-spk-prot.wmfw | Bin 0 -> 34200 bytes audio/tegu/cs35l41/fw/fast_switch1.txt | 1 + audio/tegu/cs35l41/fw/fast_switch2.txt | 1 + audio/tegu/cs35l41/fw/fast_switch3.txt | 1 + audio/tegu/cs35l41/fw/fast_switch4.txt | 1 + audio/tegu/cs35l41/fw/fast_switch5.txt | 1 + audio/tegu/cs35l41/fw/fast_switch6.txt | 1 + audio/tegu/cs35l41/fw/fast_switch7.txt | 1 + audio/tegu/cs35l41/fw/fast_switch8.txt | 1 + audio/tegu/factory-audio-tables.mk | 22 + audio/tegu/tuning/bluenote/exported.xml | 298 + audio/tegu/tuning/bluenote/recording.gatf | Bin 0 -> 175684 bytes audio/tegu/tuning/bluenote/template.xml | 284 + .../tuning_constraints_combination.xml | 1284 + audio/tegu/tuning/fortemedia/BLUETOOTH.dat | Bin 0 -> 223718 bytes audio/tegu/tuning/fortemedia/BLUETOOTH.mods | 56075 ++++++++++ audio/tegu/tuning/fortemedia/HANDSET.dat | Bin 0 -> 202414 bytes audio/tegu/tuning/fortemedia/HANDSET.mods | 50735 +++++++++ audio/tegu/tuning/fortemedia/HANDSFREE.dat | Bin 0 -> 74590 bytes audio/tegu/tuning/fortemedia/HANDSFREE.mods | 18695 ++++ audio/tegu/tuning/fortemedia/HEADSET.dat | Bin 0 -> 340890 bytes audio/tegu/tuning/fortemedia/HEADSET.mods | 85445 ++++++++++++++++ audio/tegu/tuning/fortemedia/mcps.dat | Bin 0 -> 292 bytes audio/tegu/tuning/waves/tests/test_config.ini | 58 + audio/tegu/tuning/waves/tests/test_preset.mps | Bin 0 -> 186955 bytes audio/tegu/tuning/waves/waves_config.ini | 64 + audio/tegu/tuning/waves/waves_preset.mps | Bin 0 -> 192460 bytes bluetooth/bt_vendor_overlay.conf | 22 + bluetooth/bt_vendor_overlay_komodo.conf | 19 + bluetooth/bt_vendor_overlay_tegu.conf | 19 + bluetooth/le_audio_codec_capabilities.xml | 91 + board-info.txt | 1 + conf/init.recovery.device.rc | 1 + conf/init.tegu.rc | 37 + device-tegu-common.mk | 33 + device-tegu.mk | 251 + factory_tegu.mk | 38 + .../device_framework_matrix_product.xml | 17 + fingerprint/ultrasonic_udfps.mk | 39 + fullmte-common.mk | 2 + fullmte-vars.mk | 4 + location/gps.cer | 161 + location/gps.xml | 101 + location/gps.xml.hk3 | 101 + location/gps.xml.sb3 | 101 + location/gps_user.xml | 100 + location/gps_user.xml.hk3 | 100 + location/gps_user.xml.sb3 | 100 + location/lhd.conf | 33 + location/lhd_user.conf | 31 + location/scd.conf | 6 + location/scd_user.conf | 5 + manifest.xml | 125 + media_profiles_tegu.xml | 1821 + nfc/libnfc-hal-st-disable.conf | 152 + nfc/libnfc-hal-st.conf | 169 + nfc/libnfc-nci.conf | 121 + nfc/libse-gto-hal-disable.conf | 2 + nfc/libse-gto-hal.conf | 2 + nfc/manifest_se.xml | 7 + perf/powerhint-tegu.json | 2387 + powerstats/tegu/Android.bp | 42 + powerstats/tegu/service.cpp | 74 + rro_overlays/WifiOverlay/Android.bp | 18 + rro_overlays/WifiOverlay/AndroidManifest.xml | 27 + rro_overlays/WifiOverlay/OWNERS | 4 + .../WifiOverlay/res/values/config.xml | 166 + tegu/BoardConfig.mk | 28 + .../base/core/res/res/values/config.xml | 259 + .../packages/SystemUI/res/values/config.xml | 66 + .../packages/apps/Nfc/res/values/config.xml | 25 + .../thermal_info_config_charge_komodo.json | 197 + ...ermal_info_config_charge_ripcurrent24.json | 19 + ...rmal_info_config_charge_ripcurrentpro.json | 19 + thermal/thermal_info_config_charge_tegu.json | 197 + thermal/thermal_info_config_charge_tokay.json | 197 + thermal/thermal_info_config_komodo.json | 926 + thermal/thermal_info_config_ripcurrent24.json | 561 + .../thermal_info_config_ripcurrentpro.json | 561 + thermal/thermal_info_config_tegu.json | 926 + thermal/thermal_info_config_tokay.json | 926 + uwb/Android.bp | 71 + uwb/calibration-CE.conf | 73 + uwb/calibration-FCC.conf | 73 + uwb/calibration-JP.conf | 39 + uwb/calibration-RESTRICTED.conf | 3 + uwb/calibration-TW.conf | 39 + uwb/calibration-default.conf | 72 + uwb/calibration.conf | 33 + uwb/configuration.conf | 146 + uwb/uwb_calibration.mk | 24 + wifi/BoardConfig-wifi.mk | 40 + wifi/p2p_supplicant_overlay.conf | 10 + wifi/wpa_supplicant_overlay.conf | 10 + 119 files changed, 228227 insertions(+) create mode 100644 Android.bp create mode 100644 Android.mk create mode 100644 AndroidProducts.mk create mode 100644 NOTICE create mode 100644 OWNERS create mode 100644 aosp_tegu.mk create mode 100644 aosp_tegu_fullmte.mk create mode 100644 audio/tegu/audio-tables.mk create mode 100644 audio/tegu/config/audio_effects.xml create mode 100644 audio/tegu/config/audio_platform_configuration.xml create mode 100644 audio/tegu/config/audio_policy_configuration.xml create mode 100644 audio/tegu/config/audio_policy_configuration_a2dp_offload_disabled.xml create mode 100644 audio/tegu/config/audio_policy_configuration_bluetooth_legacy_hal.xml create mode 100644 audio/tegu/config/mixer_paths.xml create mode 100644 audio/tegu/config/mixer_paths_factory.xml create mode 100644 audio/tegu/config/sound_trigger_configuration.xml create mode 100644 audio/tegu/cs35l41/crus_sp_cal_mixer_paths.xml create mode 100644 audio/tegu/cs35l41/fw/R-cs35l41-dsp1-spk-cali.bin create mode 100644 audio/tegu/cs35l41/fw/R-cs35l41-dsp1-spk-diag.bin create mode 100644 audio/tegu/cs35l41/fw/R-cs35l41-dsp1-spk-prot.bin create mode 100644 audio/tegu/cs35l41/fw/cs35l41-dsp1-spk-cali.bin create mode 100644 audio/tegu/cs35l41/fw/cs35l41-dsp1-spk-cali.wmfw create mode 100644 audio/tegu/cs35l41/fw/cs35l41-dsp1-spk-diag.bin create mode 100644 audio/tegu/cs35l41/fw/cs35l41-dsp1-spk-diag.wmfw create mode 100644 audio/tegu/cs35l41/fw/cs35l41-dsp1-spk-prot.bin create mode 100644 audio/tegu/cs35l41/fw/cs35l41-dsp1-spk-prot.wmfw create mode 100644 audio/tegu/cs35l41/fw/fast_switch1.txt create mode 100644 audio/tegu/cs35l41/fw/fast_switch2.txt create mode 100644 audio/tegu/cs35l41/fw/fast_switch3.txt create mode 100644 audio/tegu/cs35l41/fw/fast_switch4.txt create mode 100644 audio/tegu/cs35l41/fw/fast_switch5.txt create mode 100644 audio/tegu/cs35l41/fw/fast_switch6.txt create mode 100644 audio/tegu/cs35l41/fw/fast_switch7.txt create mode 100644 audio/tegu/cs35l41/fw/fast_switch8.txt create mode 100644 audio/tegu/factory-audio-tables.mk create mode 100644 audio/tegu/tuning/bluenote/exported.xml create mode 100644 audio/tegu/tuning/bluenote/recording.gatf create mode 100644 audio/tegu/tuning/bluenote/template.xml create mode 100644 audio/tegu/tuning/bluenote/tuning_constraints_combination.xml create mode 100644 audio/tegu/tuning/fortemedia/BLUETOOTH.dat create mode 100644 audio/tegu/tuning/fortemedia/BLUETOOTH.mods create mode 100644 audio/tegu/tuning/fortemedia/HANDSET.dat create mode 100644 audio/tegu/tuning/fortemedia/HANDSET.mods create mode 100644 audio/tegu/tuning/fortemedia/HANDSFREE.dat create mode 100644 audio/tegu/tuning/fortemedia/HANDSFREE.mods create mode 100644 audio/tegu/tuning/fortemedia/HEADSET.dat create mode 100644 audio/tegu/tuning/fortemedia/HEADSET.mods create mode 100644 audio/tegu/tuning/fortemedia/mcps.dat create mode 100644 audio/tegu/tuning/waves/tests/test_config.ini create mode 100644 audio/tegu/tuning/waves/tests/test_preset.mps create mode 100644 audio/tegu/tuning/waves/waves_config.ini create mode 100644 audio/tegu/tuning/waves/waves_preset.mps create mode 100644 bluetooth/bt_vendor_overlay.conf create mode 100644 bluetooth/bt_vendor_overlay_komodo.conf create mode 100644 bluetooth/bt_vendor_overlay_tegu.conf create mode 100644 bluetooth/le_audio_codec_capabilities.xml create mode 100644 board-info.txt create mode 100644 conf/init.recovery.device.rc create mode 100644 conf/init.tegu.rc create mode 100644 device-tegu-common.mk create mode 100644 device-tegu.mk create mode 100644 factory_tegu.mk create mode 100644 fingerprint/device_framework_matrix_product.xml create mode 100644 fingerprint/ultrasonic_udfps.mk create mode 100644 fullmte-common.mk create mode 100644 fullmte-vars.mk create mode 100644 location/gps.cer create mode 100644 location/gps.xml create mode 100644 location/gps.xml.hk3 create mode 100644 location/gps.xml.sb3 create mode 100644 location/gps_user.xml create mode 100644 location/gps_user.xml.hk3 create mode 100644 location/gps_user.xml.sb3 create mode 100644 location/lhd.conf create mode 100644 location/lhd_user.conf create mode 100644 location/scd.conf create mode 100644 location/scd_user.conf create mode 100644 manifest.xml create mode 100644 media_profiles_tegu.xml create mode 100644 nfc/libnfc-hal-st-disable.conf create mode 100644 nfc/libnfc-hal-st.conf create mode 100644 nfc/libnfc-nci.conf create mode 100644 nfc/libse-gto-hal-disable.conf create mode 100644 nfc/libse-gto-hal.conf create mode 100644 nfc/manifest_se.xml create mode 100644 perf/powerhint-tegu.json create mode 100644 powerstats/tegu/Android.bp create mode 100644 powerstats/tegu/service.cpp create mode 100644 rro_overlays/WifiOverlay/Android.bp create mode 100644 rro_overlays/WifiOverlay/AndroidManifest.xml create mode 100644 rro_overlays/WifiOverlay/OWNERS create mode 100644 rro_overlays/WifiOverlay/res/values/config.xml create mode 100644 tegu/BoardConfig.mk create mode 100644 tegu/overlay/frameworks/base/core/res/res/values/config.xml create mode 100644 tegu/overlay/frameworks/base/packages/SystemUI/res/values/config.xml create mode 100644 tegu/overlay/packages/apps/Nfc/res/values/config.xml create mode 100644 thermal/thermal_info_config_charge_komodo.json create mode 100644 thermal/thermal_info_config_charge_ripcurrent24.json create mode 100644 thermal/thermal_info_config_charge_ripcurrentpro.json create mode 100644 thermal/thermal_info_config_charge_tegu.json create mode 100644 thermal/thermal_info_config_charge_tokay.json create mode 100644 thermal/thermal_info_config_komodo.json create mode 100644 thermal/thermal_info_config_ripcurrent24.json create mode 100644 thermal/thermal_info_config_ripcurrentpro.json create mode 100644 thermal/thermal_info_config_tegu.json create mode 100644 thermal/thermal_info_config_tokay.json create mode 100644 uwb/Android.bp create mode 100644 uwb/calibration-CE.conf create mode 100644 uwb/calibration-FCC.conf create mode 100644 uwb/calibration-JP.conf create mode 100644 uwb/calibration-RESTRICTED.conf create mode 100644 uwb/calibration-TW.conf create mode 100644 uwb/calibration-default.conf create mode 100644 uwb/calibration.conf create mode 100644 uwb/configuration.conf create mode 100644 uwb/uwb_calibration.mk create mode 100644 wifi/BoardConfig-wifi.mk create mode 100644 wifi/p2p_supplicant_overlay.conf create mode 100644 wifi/wpa_supplicant_overlay.conf diff --git a/Android.bp b/Android.bp new file mode 100644 index 0000000..db73c08 --- /dev/null +++ b/Android.bp @@ -0,0 +1,31 @@ +// +// Copyright (C) 2021 The Android Open Source Project +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package { + default_applicable_licenses: ["device_google_tegu_license"], +} + +// Added automatically by a large-scale-change +// See: http://go/android-license-faq +license { + name: "device_google_tegu_license", + visibility: [":__subpackages__"], + license_kinds: [ + "SPDX-license-identifier-Apache-2.0", + ], + license_text: [ + "NOTICE", + ], +} diff --git a/Android.mk b/Android.mk new file mode 100644 index 0000000..c6302b2 --- /dev/null +++ b/Android.mk @@ -0,0 +1,30 @@ +# +# Copyright (C) 2011 The Android Open-Source Project +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +# WARNING: Everything listed here will be built on ALL platforms, +# including x86, the universal, and the SDK. Modules must be uniquely +# named (liblights.panda), and must build everywhere, or limit themselves +# to only building on ARM if they include assembly. Individual makefiles +# are responsible for having their own logic, for fine-grained control. + +LOCAL_PATH := $(call my-dir) + +# if some modules are built directly from this directory (not subdirectories), +# their rules should be written here. + +ifneq (,$(filter $(TARGET_DEVICE),tegu)) + include $(call all-makefiles-under,$(LOCAL_PATH)) +endif diff --git a/AndroidProducts.mk b/AndroidProducts.mk new file mode 100644 index 0000000..5741edd --- /dev/null +++ b/AndroidProducts.mk @@ -0,0 +1,23 @@ +# +# Copyright (C) 2019 The Android Open-Source Project +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +PRODUCT_MAKEFILES := \ + $(LOCAL_DIR)/aosp_tegu.mk \ + $(LOCAL_DIR)/aosp_tegu_fullmte.mk \ + $(LOCAL_DIR)/factory_tegu.mk \ + +COMMON_LUNCH_CHOICES := \ + aosp_tegu-userdebug diff --git a/NOTICE b/NOTICE new file mode 100644 index 0000000..316b4eb --- /dev/null +++ b/NOTICE @@ -0,0 +1,190 @@ + + Copyright (c) 2014, The Android Open Source Project + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + + + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. Definitions. + + "License" shall mean the terms and conditions for use, reproduction, + and distribution as defined by Sections 1 through 9 of this document. + + "Licensor" shall mean the copyright owner or entity authorized by + the copyright owner that is granting the License. + + "Legal Entity" shall mean the union of the acting entity and all + other entities that control, are controlled by, or are under common + control with that entity. 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For the purposes + of this License, Derivative Works shall not include works that remain + separable from, or merely link (or bind by name) to the interfaces of, + the Work and Derivative Works thereof. + + "Contribution" shall mean any work of authorship, including + the original version of the Work and any modifications or additions + to that Work or Derivative Works thereof, that is intentionally + submitted to Licensor for inclusion in the Work by the copyright owner + or by an individual or Legal Entity authorized to submit on behalf of + the copyright owner. For the purposes of this definition, "submitted" + means any form of electronic, verbal, or written communication sent + to the Licensor or its representatives, including but not limited to + communication on electronic mailing lists, source code control systems, + and issue tracking systems that are managed by, or on behalf of, the + Licensor for the purpose of discussing and improving the Work, but + excluding communication that is conspicuously marked or otherwise + designated in writing by the copyright owner as "Not a Contribution." + + "Contributor" shall mean Licensor and any individual or Legal Entity + on behalf of whom a Contribution has been received by Licensor and + subsequently incorporated within the Work. + + 2. Grant of Copyright License. Subject to the terms and conditions of + this License, each Contributor hereby grants to You a perpetual, + worldwide, non-exclusive, no-charge, royalty-free, irrevocable + copyright license to reproduce, prepare Derivative Works of, + publicly display, publicly perform, sublicense, and distribute the + Work and such Derivative Works in Source or Object form. + + 3. Grant of Patent License. Subject to the terms and conditions of + this License, each Contributor hereby grants to You a perpetual, + worldwide, non-exclusive, no-charge, royalty-free, irrevocable + (except as stated in this section) patent license to make, have made, + use, offer to sell, sell, import, and otherwise transfer the Work, + where such license applies only to those patent claims licensable + by such Contributor that are necessarily infringed by their + Contribution(s) alone or by combination of their Contribution(s) + with the Work to which such Contribution(s) was submitted. If You + institute patent litigation against any entity (including a + cross-claim or counterclaim in a lawsuit) alleging that the Work + or a Contribution incorporated within the Work constitutes direct + or contributory patent infringement, then any patent licenses + granted to You under this License for that Work shall terminate + as of the date such litigation is filed. + + 4. Redistribution. You may reproduce and distribute copies of the + Work or Derivative Works thereof in any medium, with or without + modifications, and in Source or Object form, provided that You + meet the following conditions: + + (a) You must give any other recipients of the Work or + Derivative Works a copy of this License; and + + (b) You must cause any modified files to carry prominent notices + stating that You changed the files; and + + (c) You must retain, in the Source form of any Derivative Works + that You distribute, all copyright, patent, trademark, and + attribution notices from the Source form of the Work, + excluding those notices that do not pertain to any part of + the Derivative Works; and + + (d) If the Work includes a "NOTICE" text file as part of its + distribution, then any Derivative Works that You distribute must + include a readable copy of the attribution notices contained + within such NOTICE file, excluding those notices that do not + pertain to any part of the Derivative Works, in at least one + of the following places: within a NOTICE text file distributed + as part of the Derivative Works; within the Source form or + documentation, if provided along with the Derivative Works; or, + within a display generated by the Derivative Works, if and + wherever such third-party notices normally appear. The contents + of the NOTICE file are for informational purposes only and + do not modify the License. You may add Your own attribution + notices within Derivative Works that You distribute, alongside + or as an addendum to the NOTICE text from the Work, provided + that such additional attribution notices cannot be construed + as modifying the License. + + You may add Your own copyright statement to Your modifications and + may provide additional or different license terms and conditions + for use, reproduction, or distribution of Your modifications, or + for any such Derivative Works as a whole, provided Your use, + reproduction, and distribution of the Work otherwise complies with + the conditions stated in this License. + + 5. Submission of Contributions. Unless You explicitly state otherwise, + any Contribution intentionally submitted for inclusion in the Work + by You to the Licensor shall be under the terms and conditions of + this License, without any additional terms or conditions. + Notwithstanding the above, nothing herein shall supersede or modify + the terms of any separate license agreement you may have executed + with Licensor regarding such Contributions. + + 6. Trademarks. This License does not grant permission to use the trade + names, trademarks, service marks, or product names of the Licensor, + except as required for reasonable and customary use in describing the + origin of the Work and reproducing the content of the NOTICE file. + + 7. Disclaimer of Warranty. Unless required by applicable law or + agreed to in writing, Licensor provides the Work (and each + Contributor provides its Contributions) on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied, including, without limitation, any warranties or conditions + of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A + PARTICULAR PURPOSE. You are solely responsible for determining the + appropriateness of using or redistributing the Work and assume any + risks associated with Your exercise of permissions under this License. + + 8. Limitation of Liability. In no event and under no legal theory, + whether in tort (including negligence), contract, or otherwise, + unless required by applicable law (such as deliberate and grossly + negligent acts) or agreed to in writing, shall any Contributor be + liable to You for damages, including any direct, indirect, special, + incidental, or consequential damages of any character arising as a + result of this License or out of the use or inability to use the + Work (including but not limited to damages for loss of goodwill, + work stoppage, computer failure or malfunction, or any and all + other commercial damages or losses), even if such Contributor + has been advised of the possibility of such damages. + + 9. Accepting Warranty or Additional Liability. While redistributing + the Work or Derivative Works thereof, You may choose to offer, + and charge a fee for, acceptance of support, warranty, indemnity, + or other liability obligations and/or rights consistent with this + License. However, in accepting such obligations, You may act only + on Your own behalf and on Your sole responsibility, not on behalf + of any other Contributor, and only if You agree to indemnify, + defend, and hold each Contributor harmless for any liability + incurred by, or claims asserted against, such Contributor by reason + of your accepting any such warranty or additional liability. + + END OF TERMS AND CONDITIONS + diff --git a/OWNERS b/OWNERS new file mode 100644 index 0000000..492973e --- /dev/null +++ b/OWNERS @@ -0,0 +1,4 @@ +per-file perf/*,thermal/*= jenhaochen@google.com,wvw@google.com,joaodias@google.com + +# per-file for Pixel device makefiles, see go/pixel-device-mk-owner-checklist for details. +per-file *.mk,*/BoardConfig.mk=file:device/google/gs-common:master:/OWNERS diff --git a/aosp_tegu.mk b/aosp_tegu.mk new file mode 100644 index 0000000..f52e085 --- /dev/null +++ b/aosp_tegu.mk @@ -0,0 +1,32 @@ +# +# Copyright 2021 The Android Open-Source Project +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +TARGET_LINUX_KERNEL_VERSION := 6.1 + +USE_SWIFTSHADER := false +BOARD_USES_SWIFTSHADER := false + +$(call inherit-product, device/google/zumapro/aosp_common.mk) +$(call inherit-product, device/google/tegu/device-tegu.mk) + +PRODUCT_NAME := aosp_tegu +PRODUCT_DEVICE := tegu +PRODUCT_MODEL := AOSP on tegu +PRODUCT_BRAND := Android +PRODUCT_MANUFACTURER := Google + +DEVICE_MANIFEST_FILE := \ + device/google/tegu/manifest.xml diff --git a/aosp_tegu_fullmte.mk b/aosp_tegu_fullmte.mk new file mode 100644 index 0000000..117ef9f --- /dev/null +++ b/aosp_tegu_fullmte.mk @@ -0,0 +1,5 @@ +include device/google/tegu/fullmte-vars.mk +$(call inherit-product, device/google/tegu/aosp_tegu.mk) +$(call inherit-product, device/google/tegu/fullmte-common.mk) + +PRODUCT_NAME := aosp_tegu_fullmte diff --git a/audio/tegu/audio-tables.mk b/audio/tegu/audio-tables.mk new file mode 100644 index 0000000..8774603 --- /dev/null +++ b/audio/tegu/audio-tables.mk @@ -0,0 +1,73 @@ +# +# Copyright (C) 2020 The Android Open-Source Project +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +AUDIO_TABLE_FOLDER := tegu + +# Platform Configuration for AudioHAL / SoundTriggerHAL +PRODUCT_COPY_FILES += \ + device/google/tegu/audio/$(AUDIO_TABLE_FOLDER)/config/audio_policy_configuration_bluetooth_legacy_hal.xml:$(TARGET_COPY_OUT_VENDOR)/etc/audio_policy_configuration_bluetooth_legacy_hal.xml \ + device/google/tegu/audio/$(AUDIO_TABLE_FOLDER)/config/audio_policy_configuration.xml:$(TARGET_COPY_OUT_VENDOR)/etc/audio_policy_configuration.xml \ + device/google/tegu/audio/$(AUDIO_TABLE_FOLDER)/config/audio_policy_configuration_a2dp_offload_disabled.xml:$(TARGET_COPY_OUT_VENDOR)/etc/audio_policy_configuration_a2dp_offload_disabled.xml \ + device/google/tegu/audio/$(AUDIO_TABLE_FOLDER)/config/audio_platform_configuration.xml:$(TARGET_COPY_OUT_VENDOR)/etc/audio_platform_configuration.xml \ + device/google/tegu/audio/$(AUDIO_TABLE_FOLDER)/config/sound_trigger_configuration.xml:$(TARGET_COPY_OUT_VENDOR)/etc/sound_trigger_configuration.xml + +# AudioEffectHAL Configuration +PRODUCT_COPY_FILES += \ + device/google/tegu/audio/$(AUDIO_TABLE_FOLDER)/config/audio_effects.xml:$(TARGET_COPY_OUT_VENDOR)/etc/audio_effects.xml + +# Mixer Path Configuration for AudioHAL +PRODUCT_COPY_FILES += \ + device/google/tegu/audio/$(AUDIO_TABLE_FOLDER)/config/mixer_paths.xml:$(TARGET_COPY_OUT_VENDOR)/etc/mixer_paths.xml + +# Speaker firmware files +SPK_FIRMWARE_PATH := $(AUDIO_TABLE_FOLDER)/cs35l41/fw +SPK_FIRMWARE_FULL_PATH := device/google/tegu/audio/$(SPK_FIRMWARE_PATH) + +PRODUCT_COPY_FILES += $(call copy-files,$(wildcard $(SPK_FIRMWARE_FULL_PATH)/*),$(TARGET_COPY_OUT_VENDOR)/firmware) + +# Audio tuning +PRODUCT_COPY_FILES += \ + device/google/tegu/audio/$(AUDIO_TABLE_FOLDER)/tuning/bluenote/recording.gatf:$(TARGET_COPY_OUT_VENDOR)/etc/aoc/recording.gatf \ + device/google/tegu/audio/$(AUDIO_TABLE_FOLDER)/tuning/fortemedia/BLUETOOTH.dat:$(TARGET_COPY_OUT_VENDOR)/etc/aoc/BLUETOOTH.dat \ + device/google/tegu/audio/$(AUDIO_TABLE_FOLDER)/tuning/fortemedia/HANDSFREE.dat:$(TARGET_COPY_OUT_VENDOR)/etc/aoc/HANDSFREE.dat \ + device/google/tegu/audio/$(AUDIO_TABLE_FOLDER)/tuning/fortemedia/HANDSET.dat:$(TARGET_COPY_OUT_VENDOR)/etc/aoc/HANDSET.dat \ + device/google/tegu/audio/$(AUDIO_TABLE_FOLDER)/tuning/fortemedia/HEADSET.dat:$(TARGET_COPY_OUT_VENDOR)/etc/aoc/HEADSET.dat \ + device/google/tegu/audio/$(AUDIO_TABLE_FOLDER)/tuning/fortemedia/mcps.dat:$(TARGET_COPY_OUT_VENDOR)/etc/aoc/mcps.dat \ + device/google/tegu/audio/$(AUDIO_TABLE_FOLDER)/tuning/waves/waves_config.ini:$(TARGET_COPY_OUT_VENDOR)/etc/waves_config.ini \ + device/google/tegu/audio/$(AUDIO_TABLE_FOLDER)/tuning/waves/waves_preset.mps:$(TARGET_COPY_OUT_VENDOR)/etc/waves_preset.mps + +# userdebug specific +ifneq (,$(filter userdebug eng, $(TARGET_BUILD_VARIANT))) +PRODUCT_COPY_FILES += \ + device/google/tegu/audio/$(AUDIO_TABLE_FOLDER)/tuning/fortemedia/BLUETOOTH.mods:$(TARGET_COPY_OUT_VENDOR)/etc/aoc/BLUETOOTH.mods \ + device/google/tegu/audio/$(AUDIO_TABLE_FOLDER)/tuning/fortemedia/HANDSFREE.mods:$(TARGET_COPY_OUT_VENDOR)/etc/aoc/HANDSFREE.mods \ + device/google/tegu/audio/$(AUDIO_TABLE_FOLDER)/tuning/fortemedia/HANDSET.mods:$(TARGET_COPY_OUT_VENDOR)/etc/aoc/HANDSET.mods \ + device/google/tegu/audio/$(AUDIO_TABLE_FOLDER)/tuning/fortemedia/HEADSET.mods:$(TARGET_COPY_OUT_VENDOR)/etc/aoc/HEADSET.mods + +#Bluenote files +PRODUCT_COPY_FILES += \ + device/google/tegu/audio/$(AUDIO_TABLE_FOLDER)/tuning/bluenote/template.xml:$(TARGET_COPY_OUT_VENDOR)/etc/aoc/template.xml \ + device/google/tegu/audio/$(AUDIO_TABLE_FOLDER)/tuning/bluenote/tuning_constraints_combination.xml:$(TARGET_COPY_OUT_VENDOR)/etc/aoc/tuning_constraints_combination.xml + +# Mixer Path Configuration for Audio Speaker Calibration Tool crus_sp_cal +PRODUCT_COPY_FILES += \ + device/google/tegu/audio/$(AUDIO_TABLE_FOLDER)/cs35l41/crus_sp_cal_mixer_paths.xml:$(TARGET_COPY_OUT_VENDOR)/etc/crus_sp_cal_mixer_paths.xml + +PRODUCT_COPY_FILES += \ + device/google/tegu/audio/$(AUDIO_TABLE_FOLDER)/tuning/waves/tests/test_config.ini:$(TARGET_COPY_OUT_VENDOR)/etc/test_config.ini \ + device/google/tegu/audio/$(AUDIO_TABLE_FOLDER)/tuning/waves/tests/test_preset.mps:$(TARGET_COPY_OUT_VENDOR)/etc/test_preset.mps + +endif diff --git a/audio/tegu/config/audio_effects.xml b/audio/tegu/config/audio_effects.xml new file mode 100644 index 0000000..1718057 --- /dev/null +++ b/audio/tegu/config/audio_effects.xml @@ -0,0 +1,63 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/audio/tegu/config/audio_platform_configuration.xml b/audio/tegu/config/audio_platform_configuration.xml new file mode 100644 index 0000000..dee8e62 --- /dev/null +++ b/audio/tegu/config/audio_platform_configuration.xml @@ -0,0 +1,304 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/audio/tegu/config/audio_policy_configuration.xml b/audio/tegu/config/audio_policy_configuration.xml new file mode 100644 index 0000000..776cdb4 --- /dev/null +++ b/audio/tegu/config/audio_policy_configuration.xml @@ -0,0 +1,255 @@ + + + + + + + + + Speaker + Speaker Safe + Earpiece + Built-In Mic + Built-In Back Mic + Telephony Tx + Voice Call And Telephony Rx + Echo Ref In + + Speaker + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/audio/tegu/config/audio_policy_configuration_a2dp_offload_disabled.xml b/audio/tegu/config/audio_policy_configuration_a2dp_offload_disabled.xml new file mode 100644 index 0000000..7834dde --- /dev/null +++ b/audio/tegu/config/audio_policy_configuration_a2dp_offload_disabled.xml @@ -0,0 +1,234 @@ + + + + + + + + + Speaker + Speaker Safe + Earpiece + Built-In Mic + Built-In Back Mic + Telephony Tx + Voice Call And Telephony Rx + Echo Ref In + + Speaker + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/audio/tegu/config/audio_policy_configuration_bluetooth_legacy_hal.xml b/audio/tegu/config/audio_policy_configuration_bluetooth_legacy_hal.xml new file mode 100644 index 0000000..f4deda7 --- /dev/null +++ b/audio/tegu/config/audio_policy_configuration_bluetooth_legacy_hal.xml @@ -0,0 +1,234 @@ + + + + + + + + + Speaker + Speaker Safe + Earpiece + Built-In Mic + Built-In Back Mic + Telephony Tx + Voice Call And Telephony Rx + Echo Ref In + + Speaker + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/audio/tegu/config/mixer_paths.xml b/audio/tegu/config/mixer_paths.xml new file mode 100644 index 0000000..d636a6e --- /dev/null +++ b/audio/tegu/config/mixer_paths.xml @@ -0,0 +1,902 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + > + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/audio/tegu/config/mixer_paths_factory.xml b/audio/tegu/config/mixer_paths_factory.xml new file mode 100644 index 0000000..6cc52e9 --- /dev/null +++ b/audio/tegu/config/mixer_paths_factory.xml @@ -0,0 +1,461 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/audio/tegu/config/sound_trigger_configuration.xml b/audio/tegu/config/sound_trigger_configuration.xml new file mode 100644 index 0000000..dbee090 --- /dev/null +++ b/audio/tegu/config/sound_trigger_configuration.xml @@ -0,0 +1,33 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/audio/tegu/cs35l41/crus_sp_cal_mixer_paths.xml b/audio/tegu/cs35l41/crus_sp_cal_mixer_paths.xml new file mode 100644 index 0000000..bbf1685 --- /dev/null +++ b/audio/tegu/cs35l41/crus_sp_cal_mixer_paths.xml @@ -0,0 +1,315 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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znu$d(LfD?$IxjR7YC&9V8!1cJB>2&X> z4Aj1v9d71fK3jh}9|Lx~X?HWb?BjiQWX(9xYat5flVg4XTnKYuuI`fqWyXPX(7^3q zYK}{@*#~|CKLxWtC^do{vKqecF+i^?%=y6^*LP+dJT(sOZf1Ua?Ie$K-g=C>>2Y{M z=g10vev*3WDOd@sU^TT<(#@>F&0K_=+4MBEQyMojtIf^KX>~LA{ek8F$ZP&dFSY)x zQ{68mf8jNs<*~m~ll_hPzthwHIo|sp)Mx+H{poi3>L*M(N57_HFvp;xhfA~KRO<-pL literal 0 HcmV?d00001 diff --git a/audio/tegu/tuning/fortemedia/BLUETOOTH.mods b/audio/tegu/tuning/fortemedia/BLUETOOTH.mods new file mode 100644 index 0000000..c2f94a8 --- /dev/null +++ b/audio/tegu/tuning/fortemedia/BLUETOOTH.mods @@ -0,0 +1,56075 @@ +#PLATFORM_NAME gChip +#EXPORT_FLAG BLUETOOTH +#SINGLE_API_VER 1.2.0 +#SAVE_TIME 2022-02-11 16:24:43 + +#CASE_NAME BLUETOOTH-RESERVE1-VOICE_GENERIC-FB +#PARAM_MODE FULL +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0001 //TX_OPERATION_MODE_0 +1 0x0000 //TX_OPERATION_MODE_1 +2 0x0000 //TX_PATCH_REG +3 0x0000 //TX_SENDFUNC_MODE_0 +4 0x0000 //TX_SENDFUNC_MODE_1 +5 0x0001 //TX_NUM_MIC +6 0x0000 //TX_SAMPLINGFREQ_SIG +7 0x0000 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x0078 //TX_DIST2REF1 +22 0x0000 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0800 //TX_PGA_0 +28 0x0800 //TX_PGA_1 +29 0x0800 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0000 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0000 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0000 //TX_MICS_OF_PAIR0 +38 0x0000 //TX_MICS_OF_PAIR1 +39 0x0000 //TX_MICS_OF_PAIR2 +40 0x0000 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0001 //TX_MIC_DATA_SRC1 +43 0x0002 //TX_MIC_DATA_SRC2 +44 0x0003 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x0000 //TX_HD_BIN_MASK +53 0x0000 //TX_HD_SUBAND_MASK +54 0x0000 //TX_HD_FRAME_AVG_MASK +55 0x0000 //TX_HD_MIN_FRQ +56 0x0000 //TX_HD_ALPHA_PSD +57 0x0000 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0x0000 //TX_T_PSDVAT +63 0x0000 //TX_CNT +64 0x0000 //TX_ANTI_HOWL_GAIN +65 0x0000 //TX_MICFORBFMARK_0 +66 0x0000 //TX_MICFORBFMARK_1 +67 0x0000 //TX_MICFORBFMARK_2 +68 0x0000 //TX_MICFORBFMARK_3 +69 0x0000 //TX_MICFORBFMARK_4 +70 0x0000 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x0000 //TX_DIST2REF_11 +73 0x0000 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0800 //TX_MIC_REFBLK_VOLUME +108 0x0800 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x0000 //TX_ADCS_GAIN +112 0x0000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x7FFF //TX_BLMIC_BLKFACTOR +116 0x7FFF //TX_BRMIC_BLKFACTOR +117 0x000A //TX_MICBLK_START_BIN +118 0x0041 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0015 //TX_FENE_HOLD +123 0x0000 //TX_FE_ENER_TH_MTS +124 0x0000 //TX_FE_ENER_TH_EXP +125 0x0000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x0000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0020 //TX_MIC_BLOCK_N +128 0x7652 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x7800 //TX_THR_PITCH_DET_0 +131 0x7000 //TX_THR_PITCH_DET_1 +132 0x6000 //TX_THR_PITCH_DET_2 +133 0x0000 //TX_PITCH_BFR_LEN +134 0x0000 //TX_SBD_PITCH_DET +135 0x0000 //TX_TD_AEC_L +136 0x0000 //TX_MU0_UNP_TD_AEC +137 0x0000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x0028 //TX_TAIL_LENGTH +147 0x2000 //TX_AEC_REF_GAIN_0 +148 0x2000 //TX_AEC_REF_GAIN_1 +149 0x2000 //TX_AEC_REF_GAIN_2 +150 0x4000 //TX_EAD_THR +151 0x0200 //TX_THR_RE_EST +152 0x0100 //TX_MIN_EQ_RE_EST_0 +153 0x0100 //TX_MIN_EQ_RE_EST_1 +154 0x0100 //TX_MIN_EQ_RE_EST_2 +155 0x0100 //TX_MIN_EQ_RE_EST_3 +156 0x0100 //TX_MIN_EQ_RE_EST_4 +157 0x0100 //TX_MIN_EQ_RE_EST_5 +158 0x0100 //TX_MIN_EQ_RE_EST_6 +159 0x0100 //TX_MIN_EQ_RE_EST_7 +160 0x0100 //TX_MIN_EQ_RE_EST_8 +161 0x0100 //TX_MIN_EQ_RE_EST_9 +162 0x0100 //TX_MIN_EQ_RE_EST_10 +163 0x0100 //TX_MIN_EQ_RE_EST_11 +164 0x0100 //TX_MIN_EQ_RE_EST_12 +165 0x4000 //TX_LAMBDA_RE_EST +166 0x0000 //TX_LAMBDA_CB_NLE +167 0x0000 //TX_C_POST_FLT +168 0x728A //TX_GAIN_NP +169 0x0008 //TX_SE_HOLD_N +170 0x0050 //TX_DT_HOLD_N +171 0x03E8 //TX_DT2_HOLD_N +172 0x0000 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x0000 //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0000 //TX_FRQ_LIN_LEN +184 0x0000 //TX_FRQ_AEC_LEN_RHO +185 0x0000 //TX_MU0_UNP_FRQ_AEC +186 0x0000 //TX_MU0_PTD_FRQ_AEC +187 0x0000 //TX_MINENOISETH +188 0x0000 //TX_MU0_RE_EST +189 0x0000 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x0000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x7333 //TX_DTD_THR1_0 +198 0x7333 //TX_DTD_THR1_1 +199 0x7333 //TX_DTD_THR1_2 +200 0x7333 //TX_DTD_THR1_3 +201 0x7333 //TX_DTD_THR1_4 +202 0x7333 //TX_DTD_THR1_5 +203 0x7333 //TX_DTD_THR1_6 +204 0x0CCD //TX_DTD_THR2_0 +205 0x0CCD //TX_DTD_THR2_1 +206 0x0CCD //TX_DTD_THR2_2 +207 0x0CCD //TX_DTD_THR2_3 +208 0x0CCD //TX_DTD_THR2_4 +209 0x0CCD //TX_DTD_THR2_5 +210 0x0CCD //TX_DTD_THR2_6 +211 0x7FFF //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x0400 //TX_DT_CUT_K +214 0x0000 //TX_DT_CUT_THR +215 0x0000 //TX_COMFORT_G +216 0x0000 //TX_POWER_YOUT_TH +217 0x0000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x0400 //TX_ADPT_STRICT_L +222 0x0200 //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x0800 //TX_B_POST_FILT_ECHO_L +229 0x0800 //TX_B_POST_FILT_ECHO_H +230 0x0000 //TX_MIN_G_CTRL_ECHO +231 0x7FFF //TX_B_LESSCUT_RTO_ECHO +232 0x0000 //TX_EPD_OFFSET_00 +233 0x0000 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x0000 //TX_MIN_EQ_RE_EST_13 +237 0x0000 //TX_DTD_THR1_7 +238 0x0000 //TX_DTD_THR2_7 +239 0x0000 //TX_DT_RESRV_7 +240 0x0000 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xF200 //TX_THR_SN_EST_0 +243 0xF400 //TX_THR_SN_EST_1 +244 0xF800 //TX_THR_SN_EST_2 +245 0xF600 //TX_THR_SN_EST_3 +246 0xF800 //TX_THR_SN_EST_4 +247 0xF800 //TX_THR_SN_EST_5 +248 0xF800 //TX_THR_SN_EST_6 +249 0xF800 //TX_THR_SN_EST_7 +250 0x0100 //TX_DELTA_THR_SN_EST_0 +251 0x0100 //TX_DELTA_THR_SN_EST_1 +252 0x0100 //TX_DELTA_THR_SN_EST_2 +253 0x0200 //TX_DELTA_THR_SN_EST_3 +254 0x0200 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0000 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x4000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x4000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0A00 //TX_N_SN_EST +267 0x0000 //TX_INBEAM_T +268 0x0000 //TX_INBEAMHOLDT +269 0x1FFF //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x1000 //TX_NE_RTO_TH_L +274 0x1000 //TX_MAINREFRTOH_TH_H +275 0x1000 //TX_MAINREFRTOH_TH_L +276 0x2000 //TX_MAINREFRTO_TH_H +277 0x1400 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x0000 //TX_B_POST_FLT_0 +280 0x0000 //TX_B_POST_FLT_1 +281 0x001A //TX_NS_LVL_CTRL_0 +282 0x0014 //TX_NS_LVL_CTRL_1 +283 0x0014 //TX_NS_LVL_CTRL_2 +284 0x000C //TX_NS_LVL_CTRL_3 +285 0x000C //TX_NS_LVL_CTRL_4 +286 0x000C //TX_NS_LVL_CTRL_5 +287 0x001A //TX_NS_LVL_CTRL_6 +288 0x000C //TX_NS_LVL_CTRL_7 +289 0x000E //TX_MIN_GAIN_S_0 +290 0x0014 //TX_MIN_GAIN_S_1 +291 0x0014 //TX_MIN_GAIN_S_2 +292 0x0014 //TX_MIN_GAIN_S_3 +293 0x0014 //TX_MIN_GAIN_S_4 +294 0x0014 //TX_MIN_GAIN_S_5 +295 0x0014 //TX_MIN_GAIN_S_6 +296 0x0014 //TX_MIN_GAIN_S_7 +297 0x0000 //TX_NMOS_SUP +298 0x0064 //TX_NS_MAX_PRI_SNR_TH +299 0x7FFF //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x7FFF //TX_SNRI_SUP_1 +302 0x7FFF //TX_SNRI_SUP_2 +303 0x4000 //TX_SNRI_SUP_3 +304 0x4000 //TX_SNRI_SUP_4 +305 0x4000 //TX_SNRI_SUP_5 +306 0x7FFF //TX_SNRI_SUP_6 +307 0x4000 //TX_SNRI_SUP_7 +308 0x1200 //TX_THR_LFNS +309 0x0028 //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x7FFF //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x7FFF //TX_A_POST_FILT_1 +314 0x4000 //TX_A_POST_FILT_S_0 +315 0x1000 //TX_A_POST_FILT_S_1 +316 0x1000 //TX_A_POST_FILT_S_2 +317 0x6666 //TX_A_POST_FILT_S_3 +318 0x6666 //TX_A_POST_FILT_S_4 +319 0x6666 //TX_A_POST_FILT_S_5 +320 0x199A //TX_A_POST_FILT_S_6 +321 0x6666 //TX_A_POST_FILT_S_7 +322 0x2000 //TX_B_POST_FILT_0 +323 0x2000 //TX_B_POST_FILT_1 +324 0x2000 //TX_B_POST_FILT_2 +325 0x2000 //TX_B_POST_FILT_3 +326 0x2000 //TX_B_POST_FILT_4 +327 0x2000 //TX_B_POST_FILT_5 +328 0x2000 //TX_B_POST_FILT_6 +329 0x2000 //TX_B_POST_FILT_7 +330 0x7FFF //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x7FFF //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7E00 //TX_LAMBDA_PFILT +339 0x7E00 //TX_LAMBDA_PFILT_S_0 +340 0x7E00 //TX_LAMBDA_PFILT_S_1 +341 0x7E00 //TX_LAMBDA_PFILT_S_2 +342 0x7E00 //TX_LAMBDA_PFILT_S_3 +343 0x7E00 //TX_LAMBDA_PFILT_S_4 +344 0x7E00 //TX_LAMBDA_PFILT_S_5 +345 0x7E00 //TX_LAMBDA_PFILT_S_6 +346 0x7E00 //TX_LAMBDA_PFILT_S_7 +347 0x01F4 //TX_K_PEPPER +348 0x0400 //TX_A_PEPPER +349 0x0FA0 //TX_K_PEPPER_HF +350 0x0400 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x4000 //TX_HMNC_BST_THR +353 0x0000 //TX_DT_BINVAD_TH_0 +354 0x0000 //TX_DT_BINVAD_TH_1 +355 0x0000 //TX_DT_BINVAD_TH_2 +356 0x0000 //TX_DT_BINVAD_TH_3 +357 0x0000 //TX_DT_BINVAD_ENDF +358 0x0000 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0001 //TX_BF_SGRAD_FLG +362 0x0000 //TX_BF_DVG_TH +363 0x0000 //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x05A0 //TX_NDETCT +367 0x000A //TX_NOISE_TH_0 +368 0x1388 //TX_NOISE_TH_0_2 +369 0x3A98 //TX_NOISE_TH_0_3 +370 0x0C80 //TX_NOISE_TH_1 +371 0x0032 //TX_NOISE_TH_2 +372 0x3D54 //TX_NOISE_TH_3 +373 0x012C //TX_NOISE_TH_4 +374 0x07D0 //TX_NOISE_TH_5 +375 0x6590 //TX_NOISE_TH_5_2 +376 0x7FFF //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x00C8 //TX_NOISE_TH_6 +379 0x000A //TX_MINENOISE_TH +380 0x0000 //TX_MORENS_TFMASK_TH +381 0x0000 //TX_DRC_QUIET_FLOOR +382 0x0000 //TX_RATIODTL_CUT_TH +383 0x0000 //TX_DT_CUT_K1 +384 0x0640 //TX_OUT_ENER_S_TH_CLEAN +385 0x0640 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0640 //TX_OUT_ENER_S_TH_NOISY +387 0x0190 //TX_OUT_ENER_TH_NOISE +388 0x07D0 //TX_OUT_ENER_TH_SPEECH +389 0x0000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x0000 //TX_POST_MASK_SUP_HSNE +392 0x0000 //TX_TAIL_DET_TH +393 0x0000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0000 //TX_SUPHIGH_TH +396 0x0000 //TX_MASK_G_R +397 0x0000 //TX_EXTRA_NS_L +398 0x0000 //TX_C_POST_FLT_MASK +399 0x0000 //TX_A_POST_FLT_WNS +400 0x0000 //TX_MIN_G_LOW300HZ +401 0x0010 //TX_MAXLEVEL_CNG +402 0x0000 //TX_STN_NOISE_TH +403 0x0000 //TX_POST_MASK_SUP +404 0x0000 //TX_POST_MASK_ADJUST +405 0x0014 //TX_NS_ENOISE_MIC0_TH +406 0x0014 //TX_MINENOISE_MIC0_TH +407 0x0226 //TX_MINENOISE_MIC0_S_TH +408 0x2879 //TX_MIN_G_CTRL_SSNS +409 0x0400 //TX_METAL_RTO_THR +410 0x0080 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x0800 //TX_RHO_UPB +415 0x0B40 //TX_N_HOLD_HS +416 0x005A //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0000 //TX_EXTRA_GAIN_MICBLOCK +419 0x0333 //TX_THR_STD_NSR +420 0x0219 //TX_THR_STD_PLH +421 0x09C4 //TX_N_HOLD_STD +422 0x0166 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0800 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x0000 //TX_SB_RTO_MEAN_TH_RUB +428 0x2000 //TX_WTA_EN_RTO_TH +429 0x1400 //TX_TOP_ENER_TH_F +430 0x0064 //TX_DESIRED_TALK_HOLDT +431 0x1000 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0000 //TX_HS_VAD_BIN +435 0x0000 //TX_THR_VAD_HS +436 0x0000 //TX_MEAN_RTO_MIN_TH2 +437 0x0000 //TX_SILENCE_T +438 0x4000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x099A //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x001E //TX_DOA_VAD_THR_1 +445 0x001E //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x00B4 //TX_SRC_DOA_RNG_HIGH_0B +453 0x005A //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x00B4 //TX_SRC_DOA_RNG_HIGH_0C +456 0x005A //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x00B4 //TX_SRC_DOA_RNG_HIGH_0D +459 0x005A //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0172 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x0D9A //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x071C //TX_DOA_TRACK_HT +477 0x0280 //TX_N1_HOLD_HF +478 0x0140 //TX_N2_HOLD_HF +479 0x2AAB //TX_BF_RESET_THR_HF +480 0x4000 //TX_DOA_SMOOTH +481 0x0000 //TX_MU_BF +482 0x0200 //TX_BF_MU_LF_B2 +483 0x0000 //TX_BF_FC_END_BIN_B2 +484 0x0000 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0000 //TX_N_DOA_SEED +488 0x0000 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x0000 //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x0000 //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x0000 //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x0168 //TX_NOR_OFF_THR +498 0x0CCD //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0004 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0230 //TX_NOR_OFF_TH1 +503 0xD333 //TX_WIDE_MASK_TH +504 0x4650 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x6000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x000A //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x6666 //TX_MICTOBFGAIN0 +513 0x0014 //TX_FASTMUE_TH +514 0x0000 //TX_DEREVERB_LF_MU +515 0x0000 //TX_DEREVERB_HF_MU +516 0x0000 //TX_DEREVERB_DELAY +517 0x0000 //TX_DEREVERB_COEF_LEN +518 0x0000 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x0000 //TX_GSC_RTOH_TH +523 0x0000 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x0000 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0028 //TX_SNR_THR +531 0x03E8 //TX_ENGY_THR +532 0x0000 //TX_CORR_HIGH_TH +533 0x0000 //TX_ENGY_THR_2 +534 0x0000 //TX_MEAN_RTO_THR +535 0x0000 //TX_WNS_ENOISE_MIC0_TH +536 0x0000 //TX_RATIOMICL_TH +537 0x0000 //TX_CALIG_HS +538 0x000A //TX_LVL_CTRL +539 0x0000 //TX_WIND_SUPRTO +540 0x0000 //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x0000 //TX_RATIOMICH_TH +543 0x0000 //TX_WIND_INBEAM_L_TH +544 0x0000 //TX_WIND_INBEAM_H_TH +545 0x0000 //TX_WNS_RESRV_0 +546 0x0000 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0000 //TX_BF_LESSCUT_BBIN +554 0x0000 //TX_BF_LESSCUT_EBIN +555 0x0000 //TX_POSTBFB0 +556 0x0000 //TX_POSTBFB +557 0x0000 //TX_POSTBFE +558 0x0000 //TX_SPEECH_SNR_TH +559 0x0000 //TX_PB_MAX_PRI_SNR_TH +560 0x0000 //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0020 //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4848 //TX_FDEQ_GAIN_5 +573 0x4848 //TX_FDEQ_GAIN_6 +574 0x4848 //TX_FDEQ_GAIN_7 +575 0x4848 //TX_FDEQ_GAIN_8 +576 0x4848 //TX_FDEQ_GAIN_9 +577 0x4848 //TX_FDEQ_GAIN_10 +578 0x4848 //TX_FDEQ_GAIN_11 +579 0x4848 //TX_FDEQ_GAIN_12 +580 0x4848 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0000 //TX_FDEQ_BIN_0 +592 0x0000 //TX_FDEQ_BIN_1 +593 0x0000 //TX_FDEQ_BIN_2 +594 0x0000 //TX_FDEQ_BIN_3 +595 0x0000 //TX_FDEQ_BIN_4 +596 0x0000 //TX_FDEQ_BIN_5 +597 0x0000 //TX_FDEQ_BIN_6 +598 0x0000 //TX_FDEQ_BIN_7 +599 0x0000 //TX_FDEQ_BIN_8 +600 0x0000 //TX_FDEQ_BIN_9 +601 0x0000 //TX_FDEQ_BIN_10 +602 0x0000 //TX_FDEQ_BIN_11 +603 0x0000 //TX_FDEQ_BIN_12 +604 0x0000 //TX_FDEQ_BIN_13 +605 0x0000 //TX_FDEQ_BIN_14 +606 0x0000 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4848 //TX_PREEQ_GAIN_MIC0_8 +626 0x4848 //TX_PREEQ_GAIN_MIC0_9 +627 0x4848 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0000 //TX_PREEQ_BIN_MIC0_0 +642 0x0000 //TX_PREEQ_BIN_MIC0_1 +643 0x0000 //TX_PREEQ_BIN_MIC0_2 +644 0x0000 //TX_PREEQ_BIN_MIC0_3 +645 0x0000 //TX_PREEQ_BIN_MIC0_4 +646 0x0000 //TX_PREEQ_BIN_MIC0_5 +647 0x0000 //TX_PREEQ_BIN_MIC0_6 +648 0x0000 //TX_PREEQ_BIN_MIC0_7 +649 0x0000 //TX_PREEQ_BIN_MIC0_8 +650 0x0000 //TX_PREEQ_BIN_MIC0_9 +651 0x0000 //TX_PREEQ_BIN_MIC0_10 +652 0x0000 //TX_PREEQ_BIN_MIC0_11 +653 0x0000 //TX_PREEQ_BIN_MIC0_12 +654 0x0000 //TX_PREEQ_BIN_MIC0_13 +655 0x0000 //TX_PREEQ_BIN_MIC0_14 +656 0x0000 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0000 //TX_PREEQ_BIN_MIC1_0 +691 0x0000 //TX_PREEQ_BIN_MIC1_1 +692 0x0000 //TX_PREEQ_BIN_MIC1_2 +693 0x0000 //TX_PREEQ_BIN_MIC1_3 +694 0x0000 //TX_PREEQ_BIN_MIC1_4 +695 0x0000 //TX_PREEQ_BIN_MIC1_5 +696 0x0000 //TX_PREEQ_BIN_MIC1_6 +697 0x0000 //TX_PREEQ_BIN_MIC1_7 +698 0x0000 //TX_PREEQ_BIN_MIC1_8 +699 0x0000 //TX_PREEQ_BIN_MIC1_9 +700 0x0000 //TX_PREEQ_BIN_MIC1_10 +701 0x0000 //TX_PREEQ_BIN_MIC1_11 +702 0x0000 //TX_PREEQ_BIN_MIC1_12 +703 0x0000 //TX_PREEQ_BIN_MIC1_13 +704 0x0000 //TX_PREEQ_BIN_MIC1_14 +705 0x0000 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0000 //TX_PREEQ_BIN_MIC2_0 +740 0x0000 //TX_PREEQ_BIN_MIC2_1 +741 0x0000 //TX_PREEQ_BIN_MIC2_2 +742 0x0000 //TX_PREEQ_BIN_MIC2_3 +743 0x0000 //TX_PREEQ_BIN_MIC2_4 +744 0x0000 //TX_PREEQ_BIN_MIC2_5 +745 0x0000 //TX_PREEQ_BIN_MIC2_6 +746 0x0000 //TX_PREEQ_BIN_MIC2_7 +747 0x0000 //TX_PREEQ_BIN_MIC2_8 +748 0x0000 //TX_PREEQ_BIN_MIC2_9 +749 0x0000 //TX_PREEQ_BIN_MIC2_10 +750 0x0000 //TX_PREEQ_BIN_MIC2_11 +751 0x0000 //TX_PREEQ_BIN_MIC2_12 +752 0x0000 //TX_PREEQ_BIN_MIC2_13 +753 0x0000 //TX_PREEQ_BIN_MIC2_14 +754 0x0000 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x2000 //TX_NND_WEIGHT +765 0x0064 //TX_MIC_CALIBRATION_0 +766 0x006A //TX_MIC_CALIBRATION_1 +767 0x006A //TX_MIC_CALIBRATION_2 +768 0x006B //TX_MIC_CALIBRATION_3 +769 0x0048 //TX_MIC_PWR_BIAS_0 +770 0x003C //TX_MIC_PWR_BIAS_1 +771 0x003C //TX_MIC_PWR_BIAS_2 +772 0x003C //TX_MIC_PWR_BIAS_3 +773 0x0000 //TX_GAIN_LIMIT_0 +774 0x0009 //TX_GAIN_LIMIT_1 +775 0x000C //TX_GAIN_LIMIT_2 +776 0x000F //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F3D //TX_BVE_NOVAD0_ALPHAUP +783 0x3000 //TX_TDDRC_ALPHA_UP_01 +784 0x3000 //TX_TDDRC_ALPHA_UP_02 +785 0x3000 //TX_TDDRC_ALPHA_UP_03 +786 0x3000 //TX_TDDRC_ALPHA_UP_04 +787 0x7FB0 //TX_TDDRC_ALPHA_DWN_01 +788 0x7FB0 //TX_TDDRC_ALPHA_DWN_02 +789 0x7FB0 //TX_TDDRC_ALPHA_DWN_03 +790 0x7FB0 //TX_TDDRC_ALPHA_DWN_04 +791 0x65AD //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0002 //TX_DEADMIC_SILENCE_TH +817 0x0147 //TX_MIC_DEGRADE_TH +818 0x0078 //TX_DEADMIC_CNT +819 0x0078 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x0000 //TX_KS_NOISEPASTE_FACTOR +824 0x0000 //TX_KS_CONFIG +825 0x0000 //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x0000 //TX_FFP_FP_K_METAL +834 0x0000 //TX_A_POST_FLT_FP +835 0x0000 //TX_RTO_OUTBEAM_TH +836 0x0000 //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0000 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0000 //TX_FFP_RESRV_2 +849 0x0000 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0000 //TX_FILTINDX +854 0x0000 //TX_TDDRC_THRD_0 +855 0x0000 //TX_TDDRC_THRD_1 +856 0x0E80 //TX_TDDRC_THRD_2 +857 0x3800 //TX_TDDRC_THRD_3 +858 0x2A00 //TX_TDDRC_SLANT_0 +859 0x6E00 //TX_TDDRC_SLANT_1 +860 0x3000 //TX_TDDRC_ALPHA_UP_00 +861 0x7FB0 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x0000 //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0000 //TX_TDDRC_SMT_W +866 0x0100 //TX_TDDRC_DRC_GAIN +867 0x0000 //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x1EB8 //TX_TFMASKLTH +870 0x170A //TX_TFMASKLTHL +871 0x4000 //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0x0CCD //TX_TFMASKTH_BLESSCUT +876 0x4000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x0000 //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x0000 //TX_FASTNS_OUTIN_TH +884 0x0000 //TX_FASTNS_TFMASK_TH +885 0x0000 //TX_FASTNS_TFMASKBIN_TH1 +886 0x0000 //TX_FASTNS_TFMASKBIN_TH2 +887 0x0000 //TX_FASTNS_TFMASKBIN_TH3 +888 0x00C8 //TX_FASTNS_ARSPC_TH +889 0xD99A //TX_FASTNS_MASK5_TH +890 0x051F //TX_POSTSSA_MIN_G_VR_MASK +891 0x7FFF //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x0000 //TX_SENDFUNC_REG_MICMUTE +898 0x0000 //TX_SENDFUNC_REG_MICMUTE1 +899 0x0000 //TX_MICMUTE_RATIO_THR +900 0x0000 //TX_MICMUTE_AMP_THR +901 0x0000 //TX_MICMUTE_HPF_IND +902 0x0000 //TX_MICMUTE_LOG_EYR_TH +903 0x0000 //TX_MICMUTE_CVG_TIME +904 0x0000 //TX_MICMUTE_RELEASE_TIME +905 0x0000 //TX_MIC_VOLUME_MIC0MUTE +906 0x0000 //TX_MICMUTE_EPD_OFFSET_0 +907 0x0000 //TX_MICMUTE_FRQ_AEC_L +908 0x0000 //TX_MICMUTE_EAD_THR +909 0x0000 //TX_MICMUTE_LAMBDA_CB_NLE +910 0x0000 //TX_MICMUTE_LAMBDA_RE_EST +911 0x0000 //TX_DTD_THR1_MICMUTE_0 +912 0x0000 //TX_DTD_THR1_MICMUTE_1 +913 0x0000 //TX_DTD_THR1_MICMUTE_2 +914 0x0000 //TX_DTD_THR1_MICMUTE_3 +915 0x0000 //TX_DTD_THR2_MICMUTE_0 +916 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x0000 //TX_MICMUTE_C_POST_FLT +922 0x0000 //TX_MICMUTE_DT_CUT_K +923 0x0000 //TX_MICMUTE_DT_CUT_THR +924 0x0000 //TX_MICMUTE_DT_CUT_K2 +925 0x0000 //TX_MICMUTE_DT_CUT_THR2 +926 0x0000 //TX_MICMUTE_DT2_HOLD_N +927 0x0000 //TX_MICMUTE_RATIODTH_THCUT +928 0x0000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x0000 //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0000 //TX_MICMUTE_C_POST_FLT_MASK +931 0x0000 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0000 //TX_MICMUTE_DT_CUT_K1 +933 0x0000 //TX_MICMUTE_N2_SN_EST +934 0x0000 //TX_MICMUTE_THR_SN_EST_0 +935 0x0000 //TX_MICMUTE_MIN_G_CTRL_0 +936 0x0000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x0000 //TX_MICMUTE_B_POST_FILT_0 +938 0x0000 //TX_MIC1RUB_AMP_THR +939 0x0000 //TX_MIC1MUTE_RATIO_THR +940 0x0000 //TX_MIC1MUTE_AMP_THR +941 0x0000 //TX_MIC1MUTE_CVG_TIME +942 0x0000 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x0000 //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0000 //RX_SAMPLINGFREQ_SIG +3 0x0000 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7652 //RX_A_HP +12 0x4000 //RX_B_PE +13 0x7800 //RX_THR_PITCH_DET_0 +14 0x7000 //RX_THR_PITCH_DET_1 +15 0x6000 //RX_THR_PITCH_DET_2 +16 0x0000 //RX_PITCH_BFR_LEN +17 0x0000 //RX_SBD_PITCH_DET +18 0x0000 //RX_PP_RESRV_0 +19 0x0000 //RX_PP_RESRV_1 +20 0xF800 //RX_N_SN_EST +21 0x0000 //RX_N2_SN_EST +22 0x000F //RX_NS_LVL_CTRL +23 0xF800 //RX_THR_SN_EST +24 0x7E00 //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0000 //RX_FENS_RESRV_1 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +30 0x0000 //RX_EXTRA_NS_L +31 0x0000 //RX_EXTRA_NS_A +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0x65AD //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x0000 //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0000 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x0080 //RX_MIN_G_FP +128 0x2000 //RX_MAX_G_FP +129 0x000C //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0010 //RX_MAXLEVEL_CNG +132 0x0000 //RX_BWE_UV_TH +133 0x0000 //RX_BWE_UV_TH2 +134 0x0000 //RX_BWE_UV_TH3 +135 0x0000 //RX_BWE_V_TH +136 0x0000 //RX_BWE_GAIN1_V_TH1 +137 0x0000 //RX_BWE_GAIN1_V_TH2 +138 0x0000 //RX_BWE_UV_EQ +139 0x0000 //RX_BWE_V_EQ +140 0x0000 //RX_BWE_TONE_TH +141 0x0000 //RX_BWE_UV_HOLD_T +142 0x0000 //RX_BWE_GAIN2_ALPHA +143 0x0000 //RX_BWE_GAIN3_ALPHA +144 0x0000 //RX_BWE_CUTOFF +145 0x0000 //RX_BWE_GAINFILL +146 0x0000 //RX_BWE_MAXTH_TONE +147 0x0000 //RX_BWE_EQ_0 +148 0x0000 //RX_BWE_EQ_1 +149 0x0000 //RX_BWE_EQ_2 +150 0x0000 //RX_BWE_EQ_3 +151 0x0000 //RX_BWE_EQ_4 +152 0x0000 //RX_BWE_EQ_5 +153 0x0000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0x65AD //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x000C //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0x65AD //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0014 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0x65AD //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0021 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0x65AD //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0037 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0x65AD //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x005B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0x65AD //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0099 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0x65AD //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x0000 //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0000 //RX_SAMPLINGFREQ_SIG +160 0x0000 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7652 //RX_A_HP +169 0x4000 //RX_B_PE +170 0x7800 //RX_THR_PITCH_DET_0 +171 0x7000 //RX_THR_PITCH_DET_1 +172 0x6000 //RX_THR_PITCH_DET_2 +173 0x0000 //RX_PITCH_BFR_LEN +174 0x0000 //RX_SBD_PITCH_DET +175 0x0000 //RX_PP_RESRV_0 +176 0x0000 //RX_PP_RESRV_1 +177 0xF800 //RX_N_SN_EST +178 0x0000 //RX_N2_SN_EST +179 0x000F //RX_NS_LVL_CTRL +180 0xF800 //RX_THR_SN_EST +181 0x7E00 //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0000 //RX_FENS_RESRV_1 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +187 0x0000 //RX_EXTRA_NS_L +188 0x0000 //RX_EXTRA_NS_A +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0x65AD //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x0000 //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0000 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x0080 //RX_MIN_G_FP +285 0x2000 //RX_MAX_G_FP +286 0x000C //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0010 //RX_MAXLEVEL_CNG +289 0x0000 //RX_BWE_UV_TH +290 0x0000 //RX_BWE_UV_TH2 +291 0x0000 //RX_BWE_UV_TH3 +292 0x0000 //RX_BWE_V_TH +293 0x0000 //RX_BWE_GAIN1_V_TH1 +294 0x0000 //RX_BWE_GAIN1_V_TH2 +295 0x0000 //RX_BWE_UV_EQ +296 0x0000 //RX_BWE_V_EQ +297 0x0000 //RX_BWE_TONE_TH +298 0x0000 //RX_BWE_UV_HOLD_T +299 0x0000 //RX_BWE_GAIN2_ALPHA +300 0x0000 //RX_BWE_GAIN3_ALPHA +301 0x0000 //RX_BWE_CUTOFF +302 0x0000 //RX_BWE_GAINFILL +303 0x0000 //RX_BWE_MAXTH_TONE +304 0x0000 //RX_BWE_EQ_0 +305 0x0000 //RX_BWE_EQ_1 +306 0x0000 //RX_BWE_EQ_2 +307 0x0000 //RX_BWE_EQ_3 +308 0x0000 //RX_BWE_EQ_4 +309 0x0000 //RX_BWE_EQ_5 +310 0x0000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0x65AD //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x000C //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0x65AD //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0014 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0x65AD //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0021 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0x65AD //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0037 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0x65AD //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x005B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0x65AD //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0099 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0x65AD //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME BLUETOOTH-BT_HAC-VOICE_GENERIC-NB +#PARAM_MODE FULL +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0001 //TX_OPERATION_MODE_0 +1 0x0001 //TX_OPERATION_MODE_1 +2 0x0033 //TX_PATCH_REG +3 0x2F7C //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0003 //TX_NUM_MIC +6 0x0000 //TX_SAMPLINGFREQ_SIG +7 0x0000 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x00A4 //TX_DIST2REF1 +22 0x0017 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x1000 //TX_PGA_0 +28 0x1000 //TX_PGA_1 +29 0x1000 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0001 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0002 //TX_MIC_DATA_SRC0 +42 0x0000 //TX_MIC_DATA_SRC1 +43 0x0001 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3A66 //TX_DIST2REF_11 +73 0x053D //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0200 //TX_MIC_REFBLK_VOLUME +108 0x0CAE //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0000 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7652 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x5000 //TX_THR_PITCH_DET_0 +131 0x4800 //TX_THR_PITCH_DET_1 +132 0x4000 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x0028 //TX_TAIL_LENGTH +147 0x0100 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x7500 //TX_EAD_THR +151 0x1000 //TX_THR_RE_EST +152 0x0200 //TX_MIN_EQ_RE_EST_0 +153 0x0200 //TX_MIN_EQ_RE_EST_1 +154 0x0200 //TX_MIN_EQ_RE_EST_2 +155 0x0200 //TX_MIN_EQ_RE_EST_3 +156 0x0200 //TX_MIN_EQ_RE_EST_4 +157 0x0200 //TX_MIN_EQ_RE_EST_5 +158 0x0200 //TX_MIN_EQ_RE_EST_6 +159 0x1800 //TX_MIN_EQ_RE_EST_7 +160 0x1800 //TX_MIN_EQ_RE_EST_8 +161 0x3000 //TX_MIN_EQ_RE_EST_9 +162 0x4000 //TX_MIN_EQ_RE_EST_10 +163 0x6000 //TX_MIN_EQ_RE_EST_11 +164 0x7FFF //TX_MIN_EQ_RE_EST_12 +165 0x2000 //TX_LAMBDA_RE_EST +166 0x0000 //TX_LAMBDA_CB_NLE +167 0x7FFF //TX_C_POST_FLT +168 0x2000 //TX_GAIN_NP +169 0x0180 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x05DC //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x6590 //TX_DTD_THR1_0 +198 0x6590 //TX_DTD_THR1_1 +199 0x6590 //TX_DTD_THR1_2 +200 0x7FF0 //TX_DTD_THR1_3 +201 0x7FF0 //TX_DTD_THR1_4 +202 0x7FF0 //TX_DTD_THR1_5 +203 0x7FF0 //TX_DTD_THR1_6 +204 0x0CCD //TX_DTD_THR2_0 +205 0x0CCD //TX_DTD_THR2_1 +206 0x0CCD //TX_DTD_THR2_2 +207 0x0CCD //TX_DTD_THR2_3 +208 0x0CCD //TX_DTD_THR2_4 +209 0x0CCD //TX_DTD_THR2_5 +210 0x0CCD //TX_DTD_THR2_6 +211 0x7FFF //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x157C //TX_DT_CUT_K +214 0x0100 //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x1000 //TX_ADPT_STRICT_L +222 0x1000 //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x0800 //TX_B_POST_FILT_ECHO_L +229 0x2000 //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x1000 //TX_B_LESSCUT_RTO_ECHO +232 0x0000 //TX_EPD_OFFSET_00 +233 0x0000 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x0000 //TX_DTD_THR1_7 +238 0x0000 //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xF800 //TX_THR_SN_EST_0 +243 0xFA00 //TX_THR_SN_EST_1 +244 0xFA00 //TX_THR_SN_EST_2 +245 0xF900 //TX_THR_SN_EST_3 +246 0xFA00 //TX_THR_SN_EST_4 +247 0xFA00 //TX_THR_SN_EST_5 +248 0xF800 //TX_THR_SN_EST_6 +249 0xF800 //TX_THR_SN_EST_7 +250 0x0050 //TX_DELTA_THR_SN_EST_0 +251 0x0200 //TX_DELTA_THR_SN_EST_1 +252 0x0200 //TX_DELTA_THR_SN_EST_2 +253 0x0100 //TX_DELTA_THR_SN_EST_3 +254 0x0200 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x01A0 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x4000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x4000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x7F00 //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0800 //TX_MAINREFRTO_TH_EQ +279 0x1000 //TX_B_POST_FLT_0 +280 0x1000 //TX_B_POST_FLT_1 +281 0x0010 //TX_NS_LVL_CTRL_0 +282 0x0017 //TX_NS_LVL_CTRL_1 +283 0x0015 //TX_NS_LVL_CTRL_2 +284 0x0012 //TX_NS_LVL_CTRL_3 +285 0x0012 //TX_NS_LVL_CTRL_4 +286 0x0011 //TX_NS_LVL_CTRL_5 +287 0x0012 //TX_NS_LVL_CTRL_6 +288 0x0011 //TX_NS_LVL_CTRL_7 +289 0x000F //TX_MIN_GAIN_S_0 +290 0x000D //TX_MIN_GAIN_S_1 +291 0x000F //TX_MIN_GAIN_S_2 +292 0x000F //TX_MIN_GAIN_S_3 +293 0x000F //TX_MIN_GAIN_S_4 +294 0x0010 //TX_MIN_GAIN_S_5 +295 0x000F //TX_MIN_GAIN_S_6 +296 0x000F //TX_MIN_GAIN_S_7 +297 0x4000 //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x1000 //TX_SNRI_SUP_1 +302 0x4000 //TX_SNRI_SUP_2 +303 0x2400 //TX_SNRI_SUP_3 +304 0x4000 //TX_SNRI_SUP_4 +305 0x4000 //TX_SNRI_SUP_5 +306 0x4000 //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x0018 //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x4000 //TX_A_POST_FILT_S_0 +315 0x2000 //TX_A_POST_FILT_S_1 +316 0x4000 //TX_A_POST_FILT_S_2 +317 0x1000 //TX_A_POST_FILT_S_3 +318 0x3000 //TX_A_POST_FILT_S_4 +319 0x5000 //TX_A_POST_FILT_S_5 +320 0x5000 //TX_A_POST_FILT_S_6 +321 0x7000 //TX_A_POST_FILT_S_7 +322 0x1000 //TX_B_POST_FILT_0 +323 0x1000 //TX_B_POST_FILT_1 +324 0x1000 //TX_B_POST_FILT_2 +325 0x5000 //TX_B_POST_FILT_3 +326 0x3000 //TX_B_POST_FILT_4 +327 0x1000 //TX_B_POST_FILT_5 +328 0x1000 //TX_B_POST_FILT_6 +329 0x2000 //TX_B_POST_FILT_7 +330 0x4000 //TX_B_LESSCUT_RTO_S_0 +331 0x6000 //TX_B_LESSCUT_RTO_S_1 +332 0x6000 //TX_B_LESSCUT_RTO_S_2 +333 0x6000 //TX_B_LESSCUT_RTO_S_3 +334 0x6000 //TX_B_LESSCUT_RTO_S_4 +335 0x6000 //TX_B_LESSCUT_RTO_S_5 +336 0x6000 //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7E00 //TX_LAMBDA_PFILT +339 0x7D00 //TX_LAMBDA_PFILT_S_0 +340 0x7400 //TX_LAMBDA_PFILT_S_1 +341 0x7900 //TX_LAMBDA_PFILT_S_2 +342 0x7000 //TX_LAMBDA_PFILT_S_3 +343 0x7D00 //TX_LAMBDA_PFILT_S_4 +344 0x7D00 //TX_LAMBDA_PFILT_S_5 +345 0x7900 //TX_LAMBDA_PFILT_S_6 +346 0x7D00 //TX_LAMBDA_PFILT_S_7 +347 0x0200 //TX_K_PEPPER +348 0x0800 //TX_A_PEPPER +349 0x1EAA //TX_K_PEPPER_HF +350 0x0600 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0800 //TX_DT_BINVAD_TH_0 +354 0x0800 //TX_DT_BINVAD_TH_1 +355 0x0800 //TX_DT_BINVAD_TH_2 +356 0x0800 //TX_DT_BINVAD_TH_3 +357 0x0FA0 //TX_DT_BINVAD_ENDF +358 0x0400 //TX_C_POST_FLT_DT +359 0x4000 //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0064 //TX_NDETCT +367 0x0050 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x07D0 //TX_NOISE_TH_1 +371 0x03ED //TX_NOISE_TH_2 +372 0x2EE0 //TX_NOISE_TH_3 +373 0x5528 //TX_NOISE_TH_4 +374 0x7FFF //TX_NOISE_TH_5 +375 0x7FFF //TX_NOISE_TH_5_2 +376 0x0000 //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x0FA0 //TX_NOISE_TH_6 +379 0x000A //TX_MINENOISE_TH +380 0x4000 //TX_MORENS_TFMASK_TH +381 0xFFEE //TX_DRC_QUIET_FLOOR +382 0x6000 //TX_RATIODTL_CUT_TH +383 0xFFF3 //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x1000 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x0000 //TX_POST_MASK_SUP_HSNE +392 0x0000 //TX_TAIL_DET_TH +393 0x0000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0800 //TX_SUPHIGH_TH +396 0x00C8 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x0800 //TX_C_POST_FLT_MASK +399 0x0005 //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0001 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x000A //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x7FFF //TX_MIN_G_CTRL_SSNS +409 0x0000 //TX_METAL_RTO_THR +410 0x4848 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x007A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x5000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x01E0 //TX_NOR_OFF_THR +498 0x7C00 //TX_MORE_ON_700HZ_THR +499 0x0000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0xD333 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x7FFF //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0x0000 //TX_DEREVERB_LF_MU +515 0x0000 //TX_DEREVERB_HF_MU +516 0x0000 //TX_DEREVERB_DELAY +517 0x0000 //TX_DEREVERB_COEF_LEN +518 0x0000 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x0000 //TX_GSC_RTOH_TH +523 0x0000 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0014 //TX_FDEQ_SUBNUM +567 0x5858 //TX_FDEQ_GAIN_0 +568 0x5850 //TX_FDEQ_GAIN_1 +569 0x5050 //TX_FDEQ_GAIN_2 +570 0x5048 //TX_FDEQ_GAIN_3 +571 0x3C48 //TX_FDEQ_GAIN_4 +572 0x3C48 //TX_FDEQ_GAIN_5 +573 0x4848 //TX_FDEQ_GAIN_6 +574 0x4842 //TX_FDEQ_GAIN_7 +575 0x3030 //TX_FDEQ_GAIN_8 +576 0x3030 //TX_FDEQ_GAIN_9 +577 0x4848 //TX_FDEQ_GAIN_10 +578 0x4848 //TX_FDEQ_GAIN_11 +579 0x4848 //TX_FDEQ_GAIN_12 +580 0x4848 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0303 //TX_FDEQ_BIN_2 +594 0x0304 //TX_FDEQ_BIN_3 +595 0x0405 //TX_FDEQ_BIN_4 +596 0x0506 //TX_FDEQ_BIN_5 +597 0x0708 //TX_FDEQ_BIN_6 +598 0x090A //TX_FDEQ_BIN_7 +599 0x0B0C //TX_FDEQ_BIN_8 +600 0x0D08 //TX_FDEQ_BIN_9 +601 0x0000 //TX_FDEQ_BIN_10 +602 0x0000 //TX_FDEQ_BIN_11 +603 0x0000 //TX_FDEQ_BIN_12 +604 0x0000 //TX_FDEQ_BIN_13 +605 0x0000 //TX_FDEQ_BIN_14 +606 0x0000 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0014 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x484A //TX_PREEQ_GAIN_MIC0_7 +625 0x4B4E //TX_PREEQ_GAIN_MIC0_8 +626 0x5054 //TX_PREEQ_GAIN_MIC0_9 +627 0x4848 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0202 //TX_PREEQ_BIN_MIC0_0 +642 0x0203 //TX_PREEQ_BIN_MIC0_1 +643 0x0303 //TX_PREEQ_BIN_MIC0_2 +644 0x0304 //TX_PREEQ_BIN_MIC0_3 +645 0x0405 //TX_PREEQ_BIN_MIC0_4 +646 0x0506 //TX_PREEQ_BIN_MIC0_5 +647 0x0708 //TX_PREEQ_BIN_MIC0_6 +648 0x090A //TX_PREEQ_BIN_MIC0_7 +649 0x0B0C //TX_PREEQ_BIN_MIC0_8 +650 0x0D08 //TX_PREEQ_BIN_MIC0_9 +651 0x0000 //TX_PREEQ_BIN_MIC0_10 +652 0x0000 //TX_PREEQ_BIN_MIC0_11 +653 0x0000 //TX_PREEQ_BIN_MIC0_12 +654 0x0000 //TX_PREEQ_BIN_MIC0_13 +655 0x0000 //TX_PREEQ_BIN_MIC0_14 +656 0x0000 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x251A //TX_PREEQ_BIN_MIC1_0 +691 0x0F0F //TX_PREEQ_BIN_MIC1_1 +692 0x0C08 //TX_PREEQ_BIN_MIC1_2 +693 0x0700 //TX_PREEQ_BIN_MIC1_3 +694 0x0000 //TX_PREEQ_BIN_MIC1_4 +695 0x0000 //TX_PREEQ_BIN_MIC1_5 +696 0x0000 //TX_PREEQ_BIN_MIC1_6 +697 0x0000 //TX_PREEQ_BIN_MIC1_7 +698 0x0000 //TX_PREEQ_BIN_MIC1_8 +699 0x0000 //TX_PREEQ_BIN_MIC1_9 +700 0x0000 //TX_PREEQ_BIN_MIC1_10 +701 0x0000 //TX_PREEQ_BIN_MIC1_11 +702 0x0000 //TX_PREEQ_BIN_MIC1_12 +703 0x0000 //TX_PREEQ_BIN_MIC1_13 +704 0x0000 //TX_PREEQ_BIN_MIC1_14 +705 0x0000 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x7800 //TX_PREEQ_BIN_MIC2_0 +740 0x0000 //TX_PREEQ_BIN_MIC2_1 +741 0x0000 //TX_PREEQ_BIN_MIC2_2 +742 0x0000 //TX_PREEQ_BIN_MIC2_3 +743 0x0000 //TX_PREEQ_BIN_MIC2_4 +744 0x0000 //TX_PREEQ_BIN_MIC2_5 +745 0x0000 //TX_PREEQ_BIN_MIC2_6 +746 0x0000 //TX_PREEQ_BIN_MIC2_7 +747 0x0000 //TX_PREEQ_BIN_MIC2_8 +748 0x0000 //TX_PREEQ_BIN_MIC2_9 +749 0x0000 //TX_PREEQ_BIN_MIC2_10 +750 0x0000 //TX_PREEQ_BIN_MIC2_11 +751 0x0000 //TX_PREEQ_BIN_MIC2_12 +752 0x0000 //TX_PREEQ_BIN_MIC2_13 +753 0x0000 //TX_PREEQ_BIN_MIC2_14 +754 0x0000 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x0800 //TX_NND_WEIGHT +765 0x0065 //TX_MIC_CALIBRATION_0 +766 0x0065 //TX_MIC_CALIBRATION_1 +767 0x0065 //TX_MIC_CALIBRATION_2 +768 0x0065 //TX_MIC_CALIBRATION_3 +769 0x0044 //TX_MIC_PWR_BIAS_0 +770 0x0044 //TX_MIC_PWR_BIAS_1 +771 0x0044 //TX_MIC_PWR_BIAS_2 +772 0x0044 //TX_MIC_PWR_BIAS_3 +773 0x0009 //TX_GAIN_LIMIT_0 +774 0x000F //TX_GAIN_LIMIT_1 +775 0x000F //TX_GAIN_LIMIT_2 +776 0x000F //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x4000 //TX_TDDRC_ALPHA_UP_01 +784 0x4000 //TX_TDDRC_ALPHA_UP_02 +785 0x4000 //TX_TDDRC_ALPHA_UP_03 +786 0x4000 //TX_TDDRC_ALPHA_UP_04 +787 0x6000 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x7FFF //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0010 //TX_DEADMIC_SILENCE_TH +817 0x0600 //TX_MIC_DEGRADE_TH +818 0x0078 //TX_DEADMIC_CNT +819 0x0078 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x4848 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0096 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0002 //TX_FILTINDX +854 0x0004 //TX_TDDRC_THRD_0 +855 0x0010 //TX_TDDRC_THRD_1 +856 0x1800 //TX_TDDRC_THRD_2 +857 0x1800 //TX_TDDRC_THRD_3 +858 0x6000 //TX_TDDRC_SLANT_0 +859 0x6000 //TX_TDDRC_SLANT_1 +860 0x4000 //TX_TDDRC_ALPHA_UP_00 +861 0x6000 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x0BE3 //TX_TDDRC_DRC_GAIN +867 0x7FFF //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x0028 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x7FFF //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x0000 //TX_SENDFUNC_REG_MICMUTE +898 0x0000 //TX_SENDFUNC_REG_MICMUTE1 +899 0x0000 //TX_MICMUTE_RATIO_THR +900 0x0000 //TX_MICMUTE_AMP_THR +901 0x0000 //TX_MICMUTE_HPF_IND +902 0x0000 //TX_MICMUTE_LOG_EYR_TH +903 0x0000 //TX_MICMUTE_CVG_TIME +904 0x0000 //TX_MICMUTE_RELEASE_TIME +905 0x0000 //TX_MIC_VOLUME_MIC0MUTE +906 0x0000 //TX_MICMUTE_EPD_OFFSET_0 +907 0x0000 //TX_MICMUTE_FRQ_AEC_L +908 0x0000 //TX_MICMUTE_EAD_THR +909 0x0000 //TX_MICMUTE_LAMBDA_CB_NLE +910 0x0000 //TX_MICMUTE_LAMBDA_RE_EST +911 0x0000 //TX_DTD_THR1_MICMUTE_0 +912 0x0000 //TX_DTD_THR1_MICMUTE_1 +913 0x0000 //TX_DTD_THR1_MICMUTE_2 +914 0x0000 //TX_DTD_THR1_MICMUTE_3 +915 0x0000 //TX_DTD_THR2_MICMUTE_0 +916 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x0000 //TX_MICMUTE_C_POST_FLT +922 0x0000 //TX_MICMUTE_DT_CUT_K +923 0x0000 //TX_MICMUTE_DT_CUT_THR +924 0x0000 //TX_MICMUTE_DT_CUT_K2 +925 0x0000 //TX_MICMUTE_DT_CUT_THR2 +926 0x0000 //TX_MICMUTE_DT2_HOLD_N +927 0x0000 //TX_MICMUTE_RATIODTH_THCUT +928 0x0000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x0000 //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0000 //TX_MICMUTE_C_POST_FLT_MASK +931 0x0000 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0000 //TX_MICMUTE_DT_CUT_K1 +933 0x0000 //TX_MICMUTE_N2_SN_EST +934 0x0000 //TX_MICMUTE_THR_SN_EST_0 +935 0x0000 //TX_MICMUTE_MIN_G_CTRL_0 +936 0x0000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x0000 //TX_MICMUTE_B_POST_FILT_0 +938 0x0000 //TX_MIC1RUB_AMP_THR +939 0x0000 //TX_MIC1MUTE_RATIO_THR +940 0x0000 //TX_MIC1MUTE_AMP_THR +941 0x0000 //TX_MIC1MUTE_CVG_TIME +942 0x0000 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x206C //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0000 //RX_SAMPLINGFREQ_SIG +3 0x0000 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7FFF //RX_A_HP +12 0x0000 //RX_B_PE +13 0x3800 //RX_THR_PITCH_DET_0 +14 0x3000 //RX_THR_PITCH_DET_1 +15 0x2800 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0600 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x0010 //RX_NS_LVL_CTRL +23 0xF800 //RX_THR_SN_EST +24 0x7CCD //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4444 //RX_FDEQ_GAIN_6 +46 0x4040 //RX_FDEQ_GAIN_7 +47 0x4040 //RX_FDEQ_GAIN_8 +48 0x4040 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0000 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x017F //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x2000 //RX_MIN_G_FP +128 0x0080 //RX_MAX_G_FP +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x017F //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4444 //RX_FDEQ_GAIN_6 +46 0x4040 //RX_FDEQ_GAIN_7 +47 0x4040 //RX_FDEQ_GAIN_8 +48 0x4040 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x017F //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4444 //RX_FDEQ_GAIN_6 +46 0x4040 //RX_FDEQ_GAIN_7 +47 0x4040 //RX_FDEQ_GAIN_8 +48 0x4040 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x017F //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4444 //RX_FDEQ_GAIN_6 +46 0x4040 //RX_FDEQ_GAIN_7 +47 0x4040 //RX_FDEQ_GAIN_8 +48 0x4040 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x017F //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4444 //RX_FDEQ_GAIN_6 +46 0x4040 //RX_FDEQ_GAIN_7 +47 0x4040 //RX_FDEQ_GAIN_8 +48 0x4040 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x017F //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4444 //RX_FDEQ_GAIN_6 +46 0x4040 //RX_FDEQ_GAIN_7 +47 0x4040 //RX_FDEQ_GAIN_8 +48 0x4040 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x017F //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4444 //RX_FDEQ_GAIN_6 +46 0x4040 //RX_FDEQ_GAIN_7 +47 0x4040 //RX_FDEQ_GAIN_8 +48 0x4040 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x017F //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4444 //RX_FDEQ_GAIN_6 +46 0x4040 //RX_FDEQ_GAIN_7 +47 0x4040 //RX_FDEQ_GAIN_8 +48 0x4040 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x206C //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0000 //RX_SAMPLINGFREQ_SIG +160 0x0000 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7FFF //RX_A_HP +169 0x0000 //RX_B_PE +170 0x3800 //RX_THR_PITCH_DET_0 +171 0x3000 //RX_THR_PITCH_DET_1 +172 0x2800 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0600 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x0010 //RX_NS_LVL_CTRL +180 0xF800 //RX_THR_SN_EST +181 0x7CCD //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4444 //RX_FDEQ_GAIN_6 +203 0x4040 //RX_FDEQ_GAIN_7 +204 0x4040 //RX_FDEQ_GAIN_8 +205 0x4040 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0000 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x017F //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x2000 //RX_MIN_G_FP +285 0x0080 //RX_MAX_G_FP +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x017F //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4444 //RX_FDEQ_GAIN_6 +203 0x4040 //RX_FDEQ_GAIN_7 +204 0x4040 //RX_FDEQ_GAIN_8 +205 0x4040 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x017F //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4444 //RX_FDEQ_GAIN_6 +203 0x4040 //RX_FDEQ_GAIN_7 +204 0x4040 //RX_FDEQ_GAIN_8 +205 0x4040 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x017F //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4444 //RX_FDEQ_GAIN_6 +203 0x4040 //RX_FDEQ_GAIN_7 +204 0x4040 //RX_FDEQ_GAIN_8 +205 0x4040 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x017F //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4444 //RX_FDEQ_GAIN_6 +203 0x4040 //RX_FDEQ_GAIN_7 +204 0x4040 //RX_FDEQ_GAIN_8 +205 0x4040 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x017F //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4444 //RX_FDEQ_GAIN_6 +203 0x4040 //RX_FDEQ_GAIN_7 +204 0x4040 //RX_FDEQ_GAIN_8 +205 0x4040 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x017F //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4444 //RX_FDEQ_GAIN_6 +203 0x4040 //RX_FDEQ_GAIN_7 +204 0x4040 //RX_FDEQ_GAIN_8 +205 0x4040 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x017F //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4444 //RX_FDEQ_GAIN_6 +203 0x4040 //RX_FDEQ_GAIN_7 +204 0x4040 //RX_FDEQ_GAIN_8 +205 0x4040 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME BLUETOOTH-BT_HAC-VOICE_GENERIC-WB +#PARAM_MODE FULL +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0001 //TX_OPERATION_MODE_0 +1 0x0001 //TX_OPERATION_MODE_1 +2 0x0033 //TX_PATCH_REG +3 0x2F7C //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0003 //TX_NUM_MIC +6 0x0001 //TX_SAMPLINGFREQ_SIG +7 0x0001 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x00A4 //TX_DIST2REF1 +22 0x0017 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x1000 //TX_PGA_0 +28 0x1000 //TX_PGA_1 +29 0x1000 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0001 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0002 //TX_MIC_DATA_SRC0 +42 0x0000 //TX_MIC_DATA_SRC1 +43 0x0001 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3A66 //TX_DIST2REF_11 +73 0x053D //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0800 //TX_MIC_REFBLK_VOLUME +108 0x0C00 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0000 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7B02 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x5000 //TX_THR_PITCH_DET_0 +131 0x4800 //TX_THR_PITCH_DET_1 +132 0x4000 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x0028 //TX_TAIL_LENGTH +147 0x0300 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x6800 //TX_EAD_THR +151 0x1000 //TX_THR_RE_EST +152 0x0200 //TX_MIN_EQ_RE_EST_0 +153 0x0100 //TX_MIN_EQ_RE_EST_1 +154 0x0200 //TX_MIN_EQ_RE_EST_2 +155 0x0200 //TX_MIN_EQ_RE_EST_3 +156 0x0200 //TX_MIN_EQ_RE_EST_4 +157 0x0200 //TX_MIN_EQ_RE_EST_5 +158 0x0200 //TX_MIN_EQ_RE_EST_6 +159 0x1000 //TX_MIN_EQ_RE_EST_7 +160 0x1000 //TX_MIN_EQ_RE_EST_8 +161 0x1000 //TX_MIN_EQ_RE_EST_9 +162 0x1000 //TX_MIN_EQ_RE_EST_10 +163 0x1000 //TX_MIN_EQ_RE_EST_11 +164 0x1000 //TX_MIN_EQ_RE_EST_12 +165 0x4000 //TX_LAMBDA_RE_EST +166 0x4000 //TX_LAMBDA_CB_NLE +167 0x7FFF //TX_C_POST_FLT +168 0x5000 //TX_GAIN_NP +169 0x0180 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x05DC //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x6590 //TX_DTD_THR1_0 +198 0x6590 //TX_DTD_THR1_1 +199 0x6590 //TX_DTD_THR1_2 +200 0x7FF0 //TX_DTD_THR1_3 +201 0x7FF0 //TX_DTD_THR1_4 +202 0x7FF0 //TX_DTD_THR1_5 +203 0x7FF0 //TX_DTD_THR1_6 +204 0x5000 //TX_DTD_THR2_0 +205 0x5000 //TX_DTD_THR2_1 +206 0x5000 //TX_DTD_THR2_2 +207 0x5000 //TX_DTD_THR2_3 +208 0x5000 //TX_DTD_THR2_4 +209 0x5000 //TX_DTD_THR2_5 +210 0x5000 //TX_DTD_THR2_6 +211 0x7FFF //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x07D0 //TX_DT_CUT_K +214 0x0100 //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x023E //TX_ADPT_STRICT_L +222 0x023E //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x2000 //TX_B_POST_FILT_ECHO_L +229 0x7FFF //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x1000 //TX_B_LESSCUT_RTO_ECHO +232 0x0000 //TX_EPD_OFFSET_00 +233 0x0000 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x7FFF //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x0000 //TX_DTD_THR1_7 +238 0x0000 //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xF800 //TX_THR_SN_EST_0 +243 0xFA00 //TX_THR_SN_EST_1 +244 0xFA00 //TX_THR_SN_EST_2 +245 0xFB00 //TX_THR_SN_EST_3 +246 0xFA00 //TX_THR_SN_EST_4 +247 0xFA00 //TX_THR_SN_EST_5 +248 0xF800 //TX_THR_SN_EST_6 +249 0xF800 //TX_THR_SN_EST_7 +250 0x0100 //TX_DELTA_THR_SN_EST_0 +251 0x0100 //TX_DELTA_THR_SN_EST_1 +252 0x0200 //TX_DELTA_THR_SN_EST_2 +253 0x0100 //TX_DELTA_THR_SN_EST_3 +254 0x0100 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0200 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x4000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x4000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x2000 //TX_B_POST_FLT_0 +280 0x1000 //TX_B_POST_FLT_1 +281 0x0010 //TX_NS_LVL_CTRL_0 +282 0x0014 //TX_NS_LVL_CTRL_1 +283 0x0018 //TX_NS_LVL_CTRL_2 +284 0x0016 //TX_NS_LVL_CTRL_3 +285 0x0014 //TX_NS_LVL_CTRL_4 +286 0x0011 //TX_NS_LVL_CTRL_5 +287 0x0014 //TX_NS_LVL_CTRL_6 +288 0x0011 //TX_NS_LVL_CTRL_7 +289 0x000F //TX_MIN_GAIN_S_0 +290 0x0010 //TX_MIN_GAIN_S_1 +291 0x0010 //TX_MIN_GAIN_S_2 +292 0x0010 //TX_MIN_GAIN_S_3 +293 0x0010 //TX_MIN_GAIN_S_4 +294 0x0010 //TX_MIN_GAIN_S_5 +295 0x0010 //TX_MIN_GAIN_S_6 +296 0x000F //TX_MIN_GAIN_S_7 +297 0x6000 //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x4000 //TX_SNRI_SUP_1 +302 0x4000 //TX_SNRI_SUP_2 +303 0x4000 //TX_SNRI_SUP_3 +304 0x4000 //TX_SNRI_SUP_4 +305 0x50C0 //TX_SNRI_SUP_5 +306 0x4000 //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x0018 //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x5000 //TX_A_POST_FILT_S_0 +315 0x4C00 //TX_A_POST_FILT_S_1 +316 0x4000 //TX_A_POST_FILT_S_2 +317 0x6000 //TX_A_POST_FILT_S_3 +318 0x4000 //TX_A_POST_FILT_S_4 +319 0x5000 //TX_A_POST_FILT_S_5 +320 0x6000 //TX_A_POST_FILT_S_6 +321 0x7000 //TX_A_POST_FILT_S_7 +322 0x2000 //TX_B_POST_FILT_0 +323 0x2000 //TX_B_POST_FILT_1 +324 0x2000 //TX_B_POST_FILT_2 +325 0x4000 //TX_B_POST_FILT_3 +326 0x4000 //TX_B_POST_FILT_4 +327 0x1000 //TX_B_POST_FILT_5 +328 0x1000 //TX_B_POST_FILT_6 +329 0x2000 //TX_B_POST_FILT_7 +330 0x4000 //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x6000 //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7C00 //TX_LAMBDA_PFILT +339 0x7C00 //TX_LAMBDA_PFILT_S_0 +340 0x7C00 //TX_LAMBDA_PFILT_S_1 +341 0x7A00 //TX_LAMBDA_PFILT_S_2 +342 0x7C00 //TX_LAMBDA_PFILT_S_3 +343 0x7C00 //TX_LAMBDA_PFILT_S_4 +344 0x7C00 //TX_LAMBDA_PFILT_S_5 +345 0x7C00 //TX_LAMBDA_PFILT_S_6 +346 0x7C00 //TX_LAMBDA_PFILT_S_7 +347 0x0200 //TX_K_PEPPER +348 0x0800 //TX_A_PEPPER +349 0x1EAA //TX_K_PEPPER_HF +350 0x0600 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0200 //TX_DT_BINVAD_TH_0 +354 0x0200 //TX_DT_BINVAD_TH_1 +355 0x0200 //TX_DT_BINVAD_TH_2 +356 0x0200 //TX_DT_BINVAD_TH_3 +357 0x1D4C //TX_DT_BINVAD_ENDF +358 0x0800 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0140 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0064 //TX_NDETCT +367 0x0032 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x017E //TX_NOISE_TH_1 +371 0x0230 //TX_NOISE_TH_2 +372 0x3492 //TX_NOISE_TH_3 +373 0x4E20 //TX_NOISE_TH_4 +374 0x55B8 //TX_NOISE_TH_5 +375 0x49E6 //TX_NOISE_TH_5_2 +376 0x0001 //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x0F0A //TX_NOISE_TH_6 +379 0x0033 //TX_MINENOISE_TH +380 0x4000 //TX_MORENS_TFMASK_TH +381 0xFFEE //TX_DRC_QUIET_FLOOR +382 0x6000 //TX_RATIODTL_CUT_TH +383 0xFFF3 //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x0333 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x0000 //TX_POST_MASK_SUP_HSNE +392 0x0000 //TX_TAIL_DET_TH +393 0x0000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0800 //TX_SUPHIGH_TH +396 0x00C8 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x0800 //TX_C_POST_FLT_MASK +399 0x0005 //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0001 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x0033 //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x7FFF //TX_MIN_G_CTRL_SSNS +409 0x0000 //TX_METAL_RTO_THR +410 0x4848 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x4000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x01E0 //TX_NOR_OFF_THR +498 0x7C00 //TX_MORE_ON_700HZ_THR +499 0x0000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0xD333 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x4000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0x0000 //TX_DEREVERB_LF_MU +515 0x0000 //TX_DEREVERB_HF_MU +516 0x0000 //TX_DEREVERB_DELAY +517 0x0000 //TX_DEREVERB_COEF_LEN +518 0x0000 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x0000 //TX_GSC_RTOH_TH +523 0x0000 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x001C //TX_FDEQ_SUBNUM +567 0x5050 //TX_FDEQ_GAIN_0 +568 0x5048 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4850 //TX_FDEQ_GAIN_5 +573 0x5050 //TX_FDEQ_GAIN_6 +574 0x5048 //TX_FDEQ_GAIN_7 +575 0x4848 //TX_FDEQ_GAIN_8 +576 0x4844 //TX_FDEQ_GAIN_9 +577 0x3C36 //TX_FDEQ_GAIN_10 +578 0x3A3A //TX_FDEQ_GAIN_11 +579 0x4848 //TX_FDEQ_GAIN_12 +580 0x4848 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0303 //TX_FDEQ_BIN_2 +594 0x0304 //TX_FDEQ_BIN_3 +595 0x0405 //TX_FDEQ_BIN_4 +596 0x0506 //TX_FDEQ_BIN_5 +597 0x0708 //TX_FDEQ_BIN_6 +598 0x090A //TX_FDEQ_BIN_7 +599 0x0B0C //TX_FDEQ_BIN_8 +600 0x0D0E //TX_FDEQ_BIN_9 +601 0x0E0F //TX_FDEQ_BIN_10 +602 0x0F10 //TX_FDEQ_BIN_11 +603 0x1011 //TX_FDEQ_BIN_12 +604 0x1104 //TX_FDEQ_BIN_13 +605 0x0000 //TX_FDEQ_BIN_14 +606 0x0000 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x484A //TX_PREEQ_GAIN_MIC0_7 +625 0x4C4E //TX_PREEQ_GAIN_MIC0_8 +626 0x5054 //TX_PREEQ_GAIN_MIC0_9 +627 0x5658 //TX_PREEQ_GAIN_MIC0_10 +628 0x5C5C //TX_PREEQ_GAIN_MIC0_11 +629 0x5E64 //TX_PREEQ_GAIN_MIC0_12 +630 0x6464 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0202 //TX_PREEQ_BIN_MIC0_0 +642 0x0203 //TX_PREEQ_BIN_MIC0_1 +643 0x0303 //TX_PREEQ_BIN_MIC0_2 +644 0x0304 //TX_PREEQ_BIN_MIC0_3 +645 0x0405 //TX_PREEQ_BIN_MIC0_4 +646 0x0506 //TX_PREEQ_BIN_MIC0_5 +647 0x0708 //TX_PREEQ_BIN_MIC0_6 +648 0x090A //TX_PREEQ_BIN_MIC0_7 +649 0x0B0C //TX_PREEQ_BIN_MIC0_8 +650 0x0D0E //TX_PREEQ_BIN_MIC0_9 +651 0x0F10 //TX_PREEQ_BIN_MIC0_10 +652 0x1011 //TX_PREEQ_BIN_MIC0_11 +653 0x1104 //TX_PREEQ_BIN_MIC0_12 +654 0x1010 //TX_PREEQ_BIN_MIC0_13 +655 0x0000 //TX_PREEQ_BIN_MIC0_14 +656 0x0000 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x251A //TX_PREEQ_BIN_MIC1_0 +691 0x0F0F //TX_PREEQ_BIN_MIC1_1 +692 0x0C0C //TX_PREEQ_BIN_MIC1_2 +693 0x0C0F //TX_PREEQ_BIN_MIC1_3 +694 0x0F0F //TX_PREEQ_BIN_MIC1_4 +695 0x0F09 //TX_PREEQ_BIN_MIC1_5 +696 0x0909 //TX_PREEQ_BIN_MIC1_6 +697 0x0908 //TX_PREEQ_BIN_MIC1_7 +698 0x0700 //TX_PREEQ_BIN_MIC1_8 +699 0x0000 //TX_PREEQ_BIN_MIC1_9 +700 0x0000 //TX_PREEQ_BIN_MIC1_10 +701 0x0000 //TX_PREEQ_BIN_MIC1_11 +702 0x0000 //TX_PREEQ_BIN_MIC1_12 +703 0x0000 //TX_PREEQ_BIN_MIC1_13 +704 0x0000 //TX_PREEQ_BIN_MIC1_14 +705 0x0000 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0608 //TX_PREEQ_BIN_MIC2_0 +740 0x0808 //TX_PREEQ_BIN_MIC2_1 +741 0x0808 //TX_PREEQ_BIN_MIC2_2 +742 0x0808 //TX_PREEQ_BIN_MIC2_3 +743 0x0808 //TX_PREEQ_BIN_MIC2_4 +744 0x0808 //TX_PREEQ_BIN_MIC2_5 +745 0x0808 //TX_PREEQ_BIN_MIC2_6 +746 0x0808 //TX_PREEQ_BIN_MIC2_7 +747 0x0808 //TX_PREEQ_BIN_MIC2_8 +748 0x0808 //TX_PREEQ_BIN_MIC2_9 +749 0x0808 //TX_PREEQ_BIN_MIC2_10 +750 0x0808 //TX_PREEQ_BIN_MIC2_11 +751 0x0808 //TX_PREEQ_BIN_MIC2_12 +752 0x0808 //TX_PREEQ_BIN_MIC2_13 +753 0x0808 //TX_PREEQ_BIN_MIC2_14 +754 0x0200 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x0800 //TX_NND_WEIGHT +765 0x0062 //TX_MIC_CALIBRATION_0 +766 0x0062 //TX_MIC_CALIBRATION_1 +767 0x0062 //TX_MIC_CALIBRATION_2 +768 0x0062 //TX_MIC_CALIBRATION_3 +769 0x0046 //TX_MIC_PWR_BIAS_0 +770 0x0046 //TX_MIC_PWR_BIAS_1 +771 0x0046 //TX_MIC_PWR_BIAS_2 +772 0x0046 //TX_MIC_PWR_BIAS_3 +773 0x0009 //TX_GAIN_LIMIT_0 +774 0x000F //TX_GAIN_LIMIT_1 +775 0x000F //TX_GAIN_LIMIT_2 +776 0x000F //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x0800 //TX_TDDRC_ALPHA_UP_01 +784 0x0800 //TX_TDDRC_ALPHA_UP_02 +785 0x0800 //TX_TDDRC_ALPHA_UP_03 +786 0x0800 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x7FFF //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0010 //TX_DEADMIC_SILENCE_TH +817 0x0600 //TX_MIC_DEGRADE_TH +818 0x0078 //TX_DEADMIC_CNT +819 0x0078 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x4848 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0096 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0002 //TX_FILTINDX +854 0x0001 //TX_TDDRC_THRD_0 +855 0x0002 //TX_TDDRC_THRD_1 +856 0x1800 //TX_TDDRC_THRD_2 +857 0x1800 //TX_TDDRC_THRD_3 +858 0x6000 //TX_TDDRC_SLANT_0 +859 0x6000 //TX_TDDRC_SLANT_1 +860 0x0800 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x0BE3 //TX_TDDRC_DRC_GAIN +867 0x7FFF //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x0028 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x1000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x0000 //TX_SENDFUNC_REG_MICMUTE +898 0x0000 //TX_SENDFUNC_REG_MICMUTE1 +899 0x0000 //TX_MICMUTE_RATIO_THR +900 0x0000 //TX_MICMUTE_AMP_THR +901 0x0000 //TX_MICMUTE_HPF_IND +902 0x0000 //TX_MICMUTE_LOG_EYR_TH +903 0x0000 //TX_MICMUTE_CVG_TIME +904 0x0000 //TX_MICMUTE_RELEASE_TIME +905 0x0000 //TX_MIC_VOLUME_MIC0MUTE +906 0x0000 //TX_MICMUTE_EPD_OFFSET_0 +907 0x0000 //TX_MICMUTE_FRQ_AEC_L +908 0x0000 //TX_MICMUTE_EAD_THR +909 0x0000 //TX_MICMUTE_LAMBDA_CB_NLE +910 0x0000 //TX_MICMUTE_LAMBDA_RE_EST +911 0x0000 //TX_DTD_THR1_MICMUTE_0 +912 0x0000 //TX_DTD_THR1_MICMUTE_1 +913 0x0000 //TX_DTD_THR1_MICMUTE_2 +914 0x0000 //TX_DTD_THR1_MICMUTE_3 +915 0x0000 //TX_DTD_THR2_MICMUTE_0 +916 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x0000 //TX_MICMUTE_C_POST_FLT +922 0x0000 //TX_MICMUTE_DT_CUT_K +923 0x0000 //TX_MICMUTE_DT_CUT_THR +924 0x0000 //TX_MICMUTE_DT_CUT_K2 +925 0x0000 //TX_MICMUTE_DT_CUT_THR2 +926 0x0000 //TX_MICMUTE_DT2_HOLD_N +927 0x0000 //TX_MICMUTE_RATIODTH_THCUT +928 0x0000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x0000 //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0000 //TX_MICMUTE_C_POST_FLT_MASK +931 0x0000 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0000 //TX_MICMUTE_DT_CUT_K1 +933 0x0000 //TX_MICMUTE_N2_SN_EST +934 0x0000 //TX_MICMUTE_THR_SN_EST_0 +935 0x0000 //TX_MICMUTE_MIN_G_CTRL_0 +936 0x0000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x0000 //TX_MICMUTE_B_POST_FILT_0 +938 0x0000 //TX_MIC1RUB_AMP_THR +939 0x0000 //TX_MIC1MUTE_RATIO_THR +940 0x0000 //TX_MIC1MUTE_AMP_THR +941 0x0000 //TX_MIC1MUTE_CVG_TIME +942 0x0000 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x206C //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0001 //RX_SAMPLINGFREQ_SIG +3 0x0001 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7FFF //RX_A_HP +12 0x4000 //RX_B_PE +13 0x3800 //RX_THR_PITCH_DET_0 +14 0x3000 //RX_THR_PITCH_DET_1 +15 0x2800 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0600 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x0010 //RX_NS_LVL_CTRL +23 0xF800 //RX_THR_SN_EST +24 0x7CCD //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x3C3C //RX_FDEQ_GAIN_9 +49 0x3C3C //RX_FDEQ_GAIN_10 +50 0x3838 //RX_FDEQ_GAIN_11 +51 0x3838 //RX_FDEQ_GAIN_12 +52 0x3030 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1112 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0000 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7E70 //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x2000 //RX_MIN_G_FP +128 0x0080 //RX_MAX_G_FP +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7E70 //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x3C3C //RX_FDEQ_GAIN_9 +49 0x3C3C //RX_FDEQ_GAIN_10 +50 0x3838 //RX_FDEQ_GAIN_11 +51 0x3838 //RX_FDEQ_GAIN_12 +52 0x3030 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1112 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7E70 //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x3C3C //RX_FDEQ_GAIN_9 +49 0x3C3C //RX_FDEQ_GAIN_10 +50 0x3838 //RX_FDEQ_GAIN_11 +51 0x3838 //RX_FDEQ_GAIN_12 +52 0x3030 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1112 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7E70 //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x3C3C //RX_FDEQ_GAIN_9 +49 0x3C3C //RX_FDEQ_GAIN_10 +50 0x3838 //RX_FDEQ_GAIN_11 +51 0x3838 //RX_FDEQ_GAIN_12 +52 0x3030 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1112 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7E70 //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x3C3C //RX_FDEQ_GAIN_9 +49 0x3C3C //RX_FDEQ_GAIN_10 +50 0x3838 //RX_FDEQ_GAIN_11 +51 0x3838 //RX_FDEQ_GAIN_12 +52 0x3030 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1112 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7E70 //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x3C3C //RX_FDEQ_GAIN_9 +49 0x3C3C //RX_FDEQ_GAIN_10 +50 0x3838 //RX_FDEQ_GAIN_11 +51 0x3838 //RX_FDEQ_GAIN_12 +52 0x3030 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1112 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7E70 //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x3C3C //RX_FDEQ_GAIN_9 +49 0x3C3C //RX_FDEQ_GAIN_10 +50 0x3838 //RX_FDEQ_GAIN_11 +51 0x3838 //RX_FDEQ_GAIN_12 +52 0x3030 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1112 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7E70 //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x3C3C //RX_FDEQ_GAIN_9 +49 0x3C3C //RX_FDEQ_GAIN_10 +50 0x3838 //RX_FDEQ_GAIN_11 +51 0x3838 //RX_FDEQ_GAIN_12 +52 0x3030 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1112 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x206C //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0001 //RX_SAMPLINGFREQ_SIG +160 0x0001 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7FFF //RX_A_HP +169 0x4000 //RX_B_PE +170 0x3800 //RX_THR_PITCH_DET_0 +171 0x3000 //RX_THR_PITCH_DET_1 +172 0x2800 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0600 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x0010 //RX_NS_LVL_CTRL +180 0xF800 //RX_THR_SN_EST +181 0x7CCD //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x3C3C //RX_FDEQ_GAIN_9 +206 0x3C3C //RX_FDEQ_GAIN_10 +207 0x3838 //RX_FDEQ_GAIN_11 +208 0x3838 //RX_FDEQ_GAIN_12 +209 0x3030 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1112 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0000 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7E70 //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x2000 //RX_MIN_G_FP +285 0x0080 //RX_MAX_G_FP +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7E70 //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x3C3C //RX_FDEQ_GAIN_9 +206 0x3C3C //RX_FDEQ_GAIN_10 +207 0x3838 //RX_FDEQ_GAIN_11 +208 0x3838 //RX_FDEQ_GAIN_12 +209 0x3030 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1112 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7E70 //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x3C3C //RX_FDEQ_GAIN_9 +206 0x3C3C //RX_FDEQ_GAIN_10 +207 0x3838 //RX_FDEQ_GAIN_11 +208 0x3838 //RX_FDEQ_GAIN_12 +209 0x3030 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1112 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7E70 //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x3C3C //RX_FDEQ_GAIN_9 +206 0x3C3C //RX_FDEQ_GAIN_10 +207 0x3838 //RX_FDEQ_GAIN_11 +208 0x3838 //RX_FDEQ_GAIN_12 +209 0x3030 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1112 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7E70 //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x3C3C //RX_FDEQ_GAIN_9 +206 0x3C3C //RX_FDEQ_GAIN_10 +207 0x3838 //RX_FDEQ_GAIN_11 +208 0x3838 //RX_FDEQ_GAIN_12 +209 0x3030 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1112 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7E70 //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x3C3C //RX_FDEQ_GAIN_9 +206 0x3C3C //RX_FDEQ_GAIN_10 +207 0x3838 //RX_FDEQ_GAIN_11 +208 0x3838 //RX_FDEQ_GAIN_12 +209 0x3030 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1112 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7E70 //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x3C3C //RX_FDEQ_GAIN_9 +206 0x3C3C //RX_FDEQ_GAIN_10 +207 0x3838 //RX_FDEQ_GAIN_11 +208 0x3838 //RX_FDEQ_GAIN_12 +209 0x3030 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1112 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7E70 //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x3C3C //RX_FDEQ_GAIN_9 +206 0x3C3C //RX_FDEQ_GAIN_10 +207 0x3838 //RX_FDEQ_GAIN_11 +208 0x3838 //RX_FDEQ_GAIN_12 +209 0x3030 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1112 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME BLUETOOTH-BT_HAC-VOICE_GENERIC-SWB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0001 //TX_OPERATION_MODE_0 +1 0x0001 //TX_OPERATION_MODE_1 +2 0x0033 //TX_PATCH_REG +3 0x2F7C //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0003 //TX_NUM_MIC +6 0x0003 //TX_SAMPLINGFREQ_SIG +7 0x0003 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x00A4 //TX_DIST2REF1 +22 0x0017 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x1000 //TX_PGA_0 +28 0x1000 //TX_PGA_1 +29 0x1000 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0001 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0002 //TX_MIC_DATA_SRC0 +42 0x0000 //TX_MIC_DATA_SRC1 +43 0x0001 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3B33 //TX_DIST2REF_11 +73 0x0A70 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0800 //TX_MIC_REFBLK_VOLUME +108 0x0CAE //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0015 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7B02 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x5000 //TX_THR_PITCH_DET_0 +131 0x4800 //TX_THR_PITCH_DET_1 +132 0x4000 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x0028 //TX_TAIL_LENGTH +147 0x0400 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x7600 //TX_EAD_THR +151 0x1000 //TX_THR_RE_EST +152 0x2000 //TX_MIN_EQ_RE_EST_0 +153 0x0600 //TX_MIN_EQ_RE_EST_1 +154 0x3000 //TX_MIN_EQ_RE_EST_2 +155 0x3000 //TX_MIN_EQ_RE_EST_3 +156 0x3000 //TX_MIN_EQ_RE_EST_4 +157 0x3000 //TX_MIN_EQ_RE_EST_5 +158 0x3000 //TX_MIN_EQ_RE_EST_6 +159 0x1000 //TX_MIN_EQ_RE_EST_7 +160 0x7800 //TX_MIN_EQ_RE_EST_8 +161 0x7800 //TX_MIN_EQ_RE_EST_9 +162 0x7800 //TX_MIN_EQ_RE_EST_10 +163 0x7800 //TX_MIN_EQ_RE_EST_11 +164 0x7800 //TX_MIN_EQ_RE_EST_12 +165 0x4000 //TX_LAMBDA_RE_EST +166 0x3000 //TX_LAMBDA_CB_NLE +167 0x7FFF //TX_C_POST_FLT +168 0x4000 //TX_GAIN_NP +169 0x0180 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x05DC //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x7FF0 //TX_DTD_THR1_0 +198 0x7FF0 //TX_DTD_THR1_1 +199 0x7FF0 //TX_DTD_THR1_2 +200 0x7FF0 //TX_DTD_THR1_3 +201 0x7FF0 //TX_DTD_THR1_4 +202 0x7FF0 //TX_DTD_THR1_5 +203 0x7FF0 //TX_DTD_THR1_6 +204 0x7E00 //TX_DTD_THR2_0 +205 0x7E00 //TX_DTD_THR2_1 +206 0x5000 //TX_DTD_THR2_2 +207 0x5000 //TX_DTD_THR2_3 +208 0x5000 //TX_DTD_THR2_4 +209 0x5000 //TX_DTD_THR2_5 +210 0x5000 //TX_DTD_THR2_6 +211 0x7FFF //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x36B0 //TX_DT_CUT_K +214 0x0100 //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x7FFF //TX_DTD_MIC_BLK +221 0x023E //TX_ADPT_STRICT_L +222 0x023E //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1F40 //TX_RATIO_DT_L_TH_HIGH +226 0x6590 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x2000 //TX_B_POST_FILT_ECHO_L +229 0x1000 //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x1000 //TX_B_LESSCUT_RTO_ECHO +232 0x0000 //TX_EPD_OFFSET_00 +233 0x0000 //TX_EPD_OFFST_01 +234 0x2328 //TX_RATIO_DT_L0_TH_HIGH +235 0x7FFF //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x0000 //TX_DTD_THR1_7 +238 0x0000 //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xF800 //TX_THR_SN_EST_0 +243 0xFA00 //TX_THR_SN_EST_1 +244 0xFA00 //TX_THR_SN_EST_2 +245 0xFA00 //TX_THR_SN_EST_3 +246 0xF800 //TX_THR_SN_EST_4 +247 0xFA00 //TX_THR_SN_EST_5 +248 0xF800 //TX_THR_SN_EST_6 +249 0xF800 //TX_THR_SN_EST_7 +250 0x0100 //TX_DELTA_THR_SN_EST_0 +251 0x0100 //TX_DELTA_THR_SN_EST_1 +252 0x0100 //TX_DELTA_THR_SN_EST_2 +253 0x0000 //TX_DELTA_THR_SN_EST_3 +254 0x0100 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0100 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x4000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x4000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x2000 //TX_B_POST_FLT_0 +280 0x1000 //TX_B_POST_FLT_1 +281 0x0010 //TX_NS_LVL_CTRL_0 +282 0x003C //TX_NS_LVL_CTRL_1 +283 0x0024 //TX_NS_LVL_CTRL_2 +284 0x003C //TX_NS_LVL_CTRL_3 +285 0x0014 //TX_NS_LVL_CTRL_4 +286 0x0011 //TX_NS_LVL_CTRL_5 +287 0x003C //TX_NS_LVL_CTRL_6 +288 0x0011 //TX_NS_LVL_CTRL_7 +289 0x000F //TX_MIN_GAIN_S_0 +290 0x0010 //TX_MIN_GAIN_S_1 +291 0x0010 //TX_MIN_GAIN_S_2 +292 0x0010 //TX_MIN_GAIN_S_3 +293 0x0010 //TX_MIN_GAIN_S_4 +294 0x0010 //TX_MIN_GAIN_S_5 +295 0x0010 //TX_MIN_GAIN_S_6 +296 0x000F //TX_MIN_GAIN_S_7 +297 0x6000 //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x1400 //TX_SNRI_SUP_1 +302 0x1400 //TX_SNRI_SUP_2 +303 0x4000 //TX_SNRI_SUP_3 +304 0x4000 //TX_SNRI_SUP_4 +305 0x50C0 //TX_SNRI_SUP_5 +306 0x1400 //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x0018 //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x5000 //TX_A_POST_FILT_S_0 +315 0x4C00 //TX_A_POST_FILT_S_1 +316 0x4000 //TX_A_POST_FILT_S_2 +317 0x6000 //TX_A_POST_FILT_S_3 +318 0x4000 //TX_A_POST_FILT_S_4 +319 0x5000 //TX_A_POST_FILT_S_5 +320 0x7C00 //TX_A_POST_FILT_S_6 +321 0x7000 //TX_A_POST_FILT_S_7 +322 0x2000 //TX_B_POST_FILT_0 +323 0x6000 //TX_B_POST_FILT_1 +324 0x6000 //TX_B_POST_FILT_2 +325 0x6000 //TX_B_POST_FILT_3 +326 0x4000 //TX_B_POST_FILT_4 +327 0x1000 //TX_B_POST_FILT_5 +328 0x1000 //TX_B_POST_FILT_6 +329 0x2000 //TX_B_POST_FILT_7 +330 0x4000 //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x6000 //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7C00 //TX_LAMBDA_PFILT +339 0x7D00 //TX_LAMBDA_PFILT_S_0 +340 0x7D00 //TX_LAMBDA_PFILT_S_1 +341 0x7D00 //TX_LAMBDA_PFILT_S_2 +342 0x7D00 //TX_LAMBDA_PFILT_S_3 +343 0x7D00 //TX_LAMBDA_PFILT_S_4 +344 0x7D00 //TX_LAMBDA_PFILT_S_5 +345 0x7D00 //TX_LAMBDA_PFILT_S_6 +346 0x7D00 //TX_LAMBDA_PFILT_S_7 +347 0x0200 //TX_K_PEPPER +348 0x0400 //TX_A_PEPPER +349 0x1EAA //TX_K_PEPPER_HF +350 0x0600 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0040 //TX_DT_BINVAD_TH_0 +354 0x0040 //TX_DT_BINVAD_TH_1 +355 0x0100 //TX_DT_BINVAD_TH_2 +356 0x0100 //TX_DT_BINVAD_TH_3 +357 0x36B0 //TX_DT_BINVAD_ENDF +358 0x0200 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0140 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0064 //TX_NDETCT +367 0x0050 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x07D0 //TX_NOISE_TH_1 +371 0x01F4 //TX_NOISE_TH_2 +372 0x36B0 //TX_NOISE_TH_3 +373 0x2710 //TX_NOISE_TH_4 +374 0x2CEC //TX_NOISE_TH_5 +375 0x7FFF //TX_NOISE_TH_5_2 +376 0x0000 //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x0DAC //TX_NOISE_TH_6 +379 0x0050 //TX_MINENOISE_TH +380 0x4000 //TX_MORENS_TFMASK_TH +381 0xFFEE //TX_DRC_QUIET_FLOOR +382 0x6000 //TX_RATIODTL_CUT_TH +383 0xFFF3 //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x0333 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x0000 //TX_POST_MASK_SUP_HSNE +392 0x0000 //TX_TAIL_DET_TH +393 0x0000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0800 //TX_SUPHIGH_TH +396 0x00C8 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x0800 //TX_C_POST_FLT_MASK +399 0x0005 //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0001 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x0050 //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x4000 //TX_MIN_G_CTRL_SSNS +409 0x0000 //TX_METAL_RTO_THR +410 0x4848 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x4000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x0230 //TX_NOR_OFF_THR +498 0x0CCD //TX_MORE_ON_700HZ_THR +499 0x0000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x2000 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0x4650 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x4000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0x0000 //TX_DEREVERB_LF_MU +515 0x0000 //TX_DEREVERB_HF_MU +516 0x0000 //TX_DEREVERB_DELAY +517 0x0000 //TX_DEREVERB_COEF_LEN +518 0x0000 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x0000 //TX_GSC_RTOH_TH +523 0x0000 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0020 //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4850 //TX_FDEQ_GAIN_2 +570 0x5050 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x484A //TX_FDEQ_GAIN_5 +573 0x4E5E //TX_FDEQ_GAIN_6 +574 0x5C4C //TX_FDEQ_GAIN_7 +575 0x4C4E //TX_FDEQ_GAIN_8 +576 0x4844 //TX_FDEQ_GAIN_9 +577 0x4448 //TX_FDEQ_GAIN_10 +578 0x4850 //TX_FDEQ_GAIN_11 +579 0x5C6A //TX_FDEQ_GAIN_12 +580 0x5A84 //TX_FDEQ_GAIN_13 +581 0x7880 //TX_FDEQ_GAIN_14 +582 0x7F7F //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0303 //TX_FDEQ_BIN_2 +594 0x0304 //TX_FDEQ_BIN_3 +595 0x0405 //TX_FDEQ_BIN_4 +596 0x0506 //TX_FDEQ_BIN_5 +597 0x0708 //TX_FDEQ_BIN_6 +598 0x090A //TX_FDEQ_BIN_7 +599 0x0B0C //TX_FDEQ_BIN_8 +600 0x0D0E //TX_FDEQ_BIN_9 +601 0x1013 //TX_FDEQ_BIN_10 +602 0x1719 //TX_FDEQ_BIN_11 +603 0x1B1E //TX_FDEQ_BIN_12 +604 0x1E1E //TX_FDEQ_BIN_13 +605 0x1E28 //TX_FDEQ_BIN_14 +606 0x282C //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x484A //TX_PREEQ_GAIN_MIC0_7 +625 0x4C4E //TX_PREEQ_GAIN_MIC0_8 +626 0x5054 //TX_PREEQ_GAIN_MIC0_9 +627 0x5658 //TX_PREEQ_GAIN_MIC0_10 +628 0x5C5C //TX_PREEQ_GAIN_MIC0_11 +629 0x6474 //TX_PREEQ_GAIN_MIC0_12 +630 0x7870 //TX_PREEQ_GAIN_MIC0_13 +631 0x5C48 //TX_PREEQ_GAIN_MIC0_14 +632 0x383C //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0202 //TX_PREEQ_BIN_MIC0_0 +642 0x0203 //TX_PREEQ_BIN_MIC0_1 +643 0x0303 //TX_PREEQ_BIN_MIC0_2 +644 0x0304 //TX_PREEQ_BIN_MIC0_3 +645 0x0405 //TX_PREEQ_BIN_MIC0_4 +646 0x0506 //TX_PREEQ_BIN_MIC0_5 +647 0x0708 //TX_PREEQ_BIN_MIC0_6 +648 0x090A //TX_PREEQ_BIN_MIC0_7 +649 0x0B0C //TX_PREEQ_BIN_MIC0_8 +650 0x0D0E //TX_PREEQ_BIN_MIC0_9 +651 0x1013 //TX_PREEQ_BIN_MIC0_10 +652 0x1719 //TX_PREEQ_BIN_MIC0_11 +653 0x1B1E //TX_PREEQ_BIN_MIC0_12 +654 0x1E1E //TX_PREEQ_BIN_MIC0_13 +655 0x1E28 //TX_PREEQ_BIN_MIC0_14 +656 0x282C //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x251A //TX_PREEQ_BIN_MIC1_0 +691 0x0F0F //TX_PREEQ_BIN_MIC1_1 +692 0x0C0C //TX_PREEQ_BIN_MIC1_2 +693 0x0C0F //TX_PREEQ_BIN_MIC1_3 +694 0x0F0F //TX_PREEQ_BIN_MIC1_4 +695 0x0F09 //TX_PREEQ_BIN_MIC1_5 +696 0x0909 //TX_PREEQ_BIN_MIC1_6 +697 0x0908 //TX_PREEQ_BIN_MIC1_7 +698 0x070F //TX_PREEQ_BIN_MIC1_8 +699 0x1F08 //TX_PREEQ_BIN_MIC1_9 +700 0x0808 //TX_PREEQ_BIN_MIC1_10 +701 0x0920 //TX_PREEQ_BIN_MIC1_11 +702 0x2020 //TX_PREEQ_BIN_MIC1_12 +703 0x2021 //TX_PREEQ_BIN_MIC1_13 +704 0x0000 //TX_PREEQ_BIN_MIC1_14 +705 0x0000 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0608 //TX_PREEQ_BIN_MIC2_0 +740 0x0808 //TX_PREEQ_BIN_MIC2_1 +741 0x0808 //TX_PREEQ_BIN_MIC2_2 +742 0x0808 //TX_PREEQ_BIN_MIC2_3 +743 0x0808 //TX_PREEQ_BIN_MIC2_4 +744 0x0808 //TX_PREEQ_BIN_MIC2_5 +745 0x0808 //TX_PREEQ_BIN_MIC2_6 +746 0x0808 //TX_PREEQ_BIN_MIC2_7 +747 0x0808 //TX_PREEQ_BIN_MIC2_8 +748 0x0808 //TX_PREEQ_BIN_MIC2_9 +749 0x0808 //TX_PREEQ_BIN_MIC2_10 +750 0x0808 //TX_PREEQ_BIN_MIC2_11 +751 0x0808 //TX_PREEQ_BIN_MIC2_12 +752 0x0808 //TX_PREEQ_BIN_MIC2_13 +753 0x0808 //TX_PREEQ_BIN_MIC2_14 +754 0xF200 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x0800 //TX_NND_WEIGHT +765 0x0050 //TX_MIC_CALIBRATION_0 +766 0x0065 //TX_MIC_CALIBRATION_1 +767 0x0050 //TX_MIC_CALIBRATION_2 +768 0x0050 //TX_MIC_CALIBRATION_3 +769 0x0046 //TX_MIC_PWR_BIAS_0 +770 0x0040 //TX_MIC_PWR_BIAS_1 +771 0x0046 //TX_MIC_PWR_BIAS_2 +772 0x0046 //TX_MIC_PWR_BIAS_3 +773 0x0000 //TX_GAIN_LIMIT_0 +774 0x000F //TX_GAIN_LIMIT_1 +775 0x0000 //TX_GAIN_LIMIT_2 +776 0x0000 //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x0800 //TX_TDDRC_ALPHA_UP_01 +784 0x0800 //TX_TDDRC_ALPHA_UP_02 +785 0x0800 //TX_TDDRC_ALPHA_UP_03 +786 0x0800 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x7FFF //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0010 //TX_DEADMIC_SILENCE_TH +817 0x0600 //TX_MIC_DEGRADE_TH +818 0x0078 //TX_DEADMIC_CNT +819 0x0078 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x4848 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0096 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0002 //TX_FILTINDX +854 0x0001 //TX_TDDRC_THRD_0 +855 0x0002 //TX_TDDRC_THRD_1 +856 0x1000 //TX_TDDRC_THRD_2 +857 0x1000 //TX_TDDRC_THRD_3 +858 0x6000 //TX_TDDRC_SLANT_0 +859 0x6000 //TX_TDDRC_SLANT_1 +860 0x0800 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x0E21 //TX_TDDRC_DRC_GAIN +867 0x7FFF //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x00C8 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x4000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x0000 //TX_SENDFUNC_REG_MICMUTE +898 0x0000 //TX_SENDFUNC_REG_MICMUTE1 +899 0x0000 //TX_MICMUTE_RATIO_THR +900 0x0000 //TX_MICMUTE_AMP_THR +901 0x0000 //TX_MICMUTE_HPF_IND +902 0x0000 //TX_MICMUTE_LOG_EYR_TH +903 0x0000 //TX_MICMUTE_CVG_TIME +904 0x0000 //TX_MICMUTE_RELEASE_TIME +905 0x0000 //TX_MIC_VOLUME_MIC0MUTE +906 0x0000 //TX_MICMUTE_EPD_OFFSET_0 +907 0x0000 //TX_MICMUTE_FRQ_AEC_L +908 0x0000 //TX_MICMUTE_EAD_THR +909 0x0000 //TX_MICMUTE_LAMBDA_CB_NLE +910 0x0000 //TX_MICMUTE_LAMBDA_RE_EST +911 0x0000 //TX_DTD_THR1_MICMUTE_0 +912 0x0000 //TX_DTD_THR1_MICMUTE_1 +913 0x0000 //TX_DTD_THR1_MICMUTE_2 +914 0x0000 //TX_DTD_THR1_MICMUTE_3 +915 0x0000 //TX_DTD_THR2_MICMUTE_0 +916 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x0000 //TX_MICMUTE_C_POST_FLT +922 0x0000 //TX_MICMUTE_DT_CUT_K +923 0x0000 //TX_MICMUTE_DT_CUT_THR +924 0x0000 //TX_MICMUTE_DT_CUT_K2 +925 0x0000 //TX_MICMUTE_DT_CUT_THR2 +926 0x0000 //TX_MICMUTE_DT2_HOLD_N +927 0x0000 //TX_MICMUTE_RATIODTH_THCUT +928 0x0000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x0000 //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0000 //TX_MICMUTE_C_POST_FLT_MASK +931 0x0000 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0000 //TX_MICMUTE_DT_CUT_K1 +933 0x0000 //TX_MICMUTE_N2_SN_EST +934 0x0000 //TX_MICMUTE_THR_SN_EST_0 +935 0x0000 //TX_MICMUTE_MIN_G_CTRL_0 +936 0x0000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x0000 //TX_MICMUTE_B_POST_FILT_0 +938 0x0000 //TX_MIC1RUB_AMP_THR +939 0x0000 //TX_MIC1MUTE_RATIO_THR +940 0x0000 //TX_MIC1MUTE_AMP_THR +941 0x0000 //TX_MIC1MUTE_CVG_TIME +942 0x0000 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x2064 //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0003 //RX_SAMPLINGFREQ_SIG +3 0x0003 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7FFF //RX_A_HP +12 0x0000 //RX_B_PE +13 0x1800 //RX_THR_PITCH_DET_0 +14 0x1000 //RX_THR_PITCH_DET_1 +15 0x0800 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0400 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x0003 //RX_NS_LVL_CTRL +23 0x9000 //RX_THR_SN_EST +24 0x7CCD //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0000 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x2000 //RX_MIN_G_FP +128 0x0080 //RX_MAX_G_FP +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x2064 //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0003 //RX_SAMPLINGFREQ_SIG +160 0x0003 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7FFF //RX_A_HP +169 0x0000 //RX_B_PE +170 0x1800 //RX_THR_PITCH_DET_0 +171 0x1000 //RX_THR_PITCH_DET_1 +172 0x0800 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0400 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x0003 //RX_NS_LVL_CTRL +180 0x9000 //RX_THR_SN_EST +181 0x7CCD //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0000 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x2000 //RX_MIN_G_FP +285 0x0080 //RX_MAX_G_FP +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME BLUETOOTH-BT_HAC-VOICE_GENERIC-FB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0001 //TX_OPERATION_MODE_0 +1 0x0001 //TX_OPERATION_MODE_1 +2 0x0033 //TX_PATCH_REG +3 0x4B7C //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0003 //TX_NUM_MIC +6 0x0004 //TX_SAMPLINGFREQ_SIG +7 0x0004 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x00A4 //TX_DIST2REF1 +22 0x0017 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0FF7 //TX_PGA_0 +28 0x0FF7 //TX_PGA_1 +29 0x0FF7 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0001 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0002 //TX_MIC_DATA_SRC0 +42 0x0000 //TX_MIC_DATA_SRC1 +43 0x0001 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3B33 //TX_DIST2REF_11 +73 0x0A70 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0800 //TX_MIC_REFBLK_VOLUME +108 0x0CAE //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0015 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7E56 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x1800 //TX_THR_PITCH_DET_0 +131 0x1000 //TX_THR_PITCH_DET_1 +132 0x0800 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x0028 //TX_TAIL_LENGTH +147 0x0300 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x7A00 //TX_EAD_THR +151 0x1000 //TX_THR_RE_EST +152 0x0800 //TX_MIN_EQ_RE_EST_0 +153 0x2000 //TX_MIN_EQ_RE_EST_1 +154 0x2000 //TX_MIN_EQ_RE_EST_2 +155 0x4000 //TX_MIN_EQ_RE_EST_3 +156 0x4000 //TX_MIN_EQ_RE_EST_4 +157 0x7FFF //TX_MIN_EQ_RE_EST_5 +158 0x7FFF //TX_MIN_EQ_RE_EST_6 +159 0x7FFF //TX_MIN_EQ_RE_EST_7 +160 0x7FFF //TX_MIN_EQ_RE_EST_8 +161 0x7FFF //TX_MIN_EQ_RE_EST_9 +162 0x7FFF //TX_MIN_EQ_RE_EST_10 +163 0x7FFF //TX_MIN_EQ_RE_EST_11 +164 0x7FFF //TX_MIN_EQ_RE_EST_12 +165 0x4000 //TX_LAMBDA_RE_EST +166 0x0CCD //TX_LAMBDA_CB_NLE +167 0x2000 //TX_C_POST_FLT +168 0x7FFF //TX_GAIN_NP +169 0x0180 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x09C4 //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x7D00 //TX_DTD_THR1_0 +198 0x7FF0 //TX_DTD_THR1_1 +199 0x7FF0 //TX_DTD_THR1_2 +200 0x7FF0 //TX_DTD_THR1_3 +201 0x7FF0 //TX_DTD_THR1_4 +202 0x7FF0 //TX_DTD_THR1_5 +203 0x7FF0 //TX_DTD_THR1_6 +204 0x0CCD //TX_DTD_THR2_0 +205 0x0CCD //TX_DTD_THR2_1 +206 0x0CCD //TX_DTD_THR2_2 +207 0x0CCD //TX_DTD_THR2_3 +208 0x0CCD //TX_DTD_THR2_4 +209 0x0CCD //TX_DTD_THR2_5 +210 0x0CCD //TX_DTD_THR2_6 +211 0x7FFF //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x0DAC //TX_DT_CUT_K +214 0x0020 //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x7FFF //TX_DTD_MIC_BLK +221 0x023E //TX_ADPT_STRICT_L +222 0x023E //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x2000 //TX_B_POST_FILT_ECHO_L +229 0x2000 //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x1000 //TX_B_LESSCUT_RTO_ECHO +232 0x0000 //TX_EPD_OFFSET_00 +233 0x0000 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x0000 //TX_DTD_THR1_7 +238 0x0000 //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xF800 //TX_THR_SN_EST_0 +243 0xFA00 //TX_THR_SN_EST_1 +244 0xFA00 //TX_THR_SN_EST_2 +245 0xFB00 //TX_THR_SN_EST_3 +246 0xFA00 //TX_THR_SN_EST_4 +247 0xFA00 //TX_THR_SN_EST_5 +248 0xF800 //TX_THR_SN_EST_6 +249 0xF800 //TX_THR_SN_EST_7 +250 0x0100 //TX_DELTA_THR_SN_EST_0 +251 0x0100 //TX_DELTA_THR_SN_EST_1 +252 0x0200 //TX_DELTA_THR_SN_EST_2 +253 0x0100 //TX_DELTA_THR_SN_EST_3 +254 0x0100 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0200 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x4000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x4000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x2000 //TX_B_POST_FLT_0 +280 0x1000 //TX_B_POST_FLT_1 +281 0x0010 //TX_NS_LVL_CTRL_0 +282 0x0014 //TX_NS_LVL_CTRL_1 +283 0x0018 //TX_NS_LVL_CTRL_2 +284 0x0016 //TX_NS_LVL_CTRL_3 +285 0x0014 //TX_NS_LVL_CTRL_4 +286 0x0011 //TX_NS_LVL_CTRL_5 +287 0x0014 //TX_NS_LVL_CTRL_6 +288 0x0011 //TX_NS_LVL_CTRL_7 +289 0x000F //TX_MIN_GAIN_S_0 +290 0x0010 //TX_MIN_GAIN_S_1 +291 0x0010 //TX_MIN_GAIN_S_2 +292 0x0010 //TX_MIN_GAIN_S_3 +293 0x0010 //TX_MIN_GAIN_S_4 +294 0x0010 //TX_MIN_GAIN_S_5 +295 0x0010 //TX_MIN_GAIN_S_6 +296 0x000F //TX_MIN_GAIN_S_7 +297 0x6000 //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x4000 //TX_SNRI_SUP_1 +302 0x4000 //TX_SNRI_SUP_2 +303 0x4000 //TX_SNRI_SUP_3 +304 0x4000 //TX_SNRI_SUP_4 +305 0x50C0 //TX_SNRI_SUP_5 +306 0x4000 //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x0018 //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x5000 //TX_A_POST_FILT_S_0 +315 0x4C00 //TX_A_POST_FILT_S_1 +316 0x4000 //TX_A_POST_FILT_S_2 +317 0x6000 //TX_A_POST_FILT_S_3 +318 0x4000 //TX_A_POST_FILT_S_4 +319 0x5000 //TX_A_POST_FILT_S_5 +320 0x6000 //TX_A_POST_FILT_S_6 +321 0x7000 //TX_A_POST_FILT_S_7 +322 0x2000 //TX_B_POST_FILT_0 +323 0x2000 //TX_B_POST_FILT_1 +324 0x2000 //TX_B_POST_FILT_2 +325 0x4000 //TX_B_POST_FILT_3 +326 0x4000 //TX_B_POST_FILT_4 +327 0x1000 //TX_B_POST_FILT_5 +328 0x1000 //TX_B_POST_FILT_6 +329 0x2000 //TX_B_POST_FILT_7 +330 0x4000 //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x6000 //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7C00 //TX_LAMBDA_PFILT +339 0x7C00 //TX_LAMBDA_PFILT_S_0 +340 0x7C00 //TX_LAMBDA_PFILT_S_1 +341 0x7A00 //TX_LAMBDA_PFILT_S_2 +342 0x7C00 //TX_LAMBDA_PFILT_S_3 +343 0x7C00 //TX_LAMBDA_PFILT_S_4 +344 0x7C00 //TX_LAMBDA_PFILT_S_5 +345 0x7C00 //TX_LAMBDA_PFILT_S_6 +346 0x7C00 //TX_LAMBDA_PFILT_S_7 +347 0x0000 //TX_K_PEPPER +348 0x0800 //TX_A_PEPPER +349 0x1EAA //TX_K_PEPPER_HF +350 0x0600 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0200 //TX_DT_BINVAD_TH_0 +354 0x0200 //TX_DT_BINVAD_TH_1 +355 0x0200 //TX_DT_BINVAD_TH_2 +356 0x0200 //TX_DT_BINVAD_TH_3 +357 0x1F40 //TX_DT_BINVAD_ENDF +358 0x0100 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0064 //TX_NDETCT +367 0x0050 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x07D0 //TX_NOISE_TH_1 +371 0x0DAC //TX_NOISE_TH_2 +372 0x4E20 //TX_NOISE_TH_3 +373 0x4E20 //TX_NOISE_TH_4 +374 0x59D8 //TX_NOISE_TH_5 +375 0x7FFF //TX_NOISE_TH_5_2 +376 0x0000 //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x2710 //TX_NOISE_TH_6 +379 0x0033 //TX_MINENOISE_TH +380 0x4000 //TX_MORENS_TFMASK_TH +381 0xFFEE //TX_DRC_QUIET_FLOOR +382 0x6000 //TX_RATIODTL_CUT_TH +383 0xFFF3 //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x0333 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x0000 //TX_POST_MASK_SUP_HSNE +392 0x0000 //TX_TAIL_DET_TH +393 0x0000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0800 //TX_SUPHIGH_TH +396 0x00C8 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x0800 //TX_C_POST_FLT_MASK +399 0x0005 //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0002 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x0033 //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x7FFF //TX_MIN_G_CTRL_SSNS +409 0x0000 //TX_METAL_RTO_THR +410 0x4848 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x4000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x0230 //TX_NOR_OFF_THR +498 0x0CCD //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x2000 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0x4650 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x7FFF //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0x0000 //TX_DEREVERB_LF_MU +515 0x0000 //TX_DEREVERB_HF_MU +516 0x0000 //TX_DEREVERB_DELAY +517 0x0000 //TX_DEREVERB_COEF_LEN +518 0x0000 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x0000 //TX_GSC_RTOH_TH +523 0x0000 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0020 //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4848 //TX_FDEQ_GAIN_5 +573 0x4848 //TX_FDEQ_GAIN_6 +574 0x4848 //TX_FDEQ_GAIN_7 +575 0x4848 //TX_FDEQ_GAIN_8 +576 0x4853 //TX_FDEQ_GAIN_9 +577 0x5450 //TX_FDEQ_GAIN_10 +578 0x7465 //TX_FDEQ_GAIN_11 +579 0x807F //TX_FDEQ_GAIN_12 +580 0x82C4 //TX_FDEQ_GAIN_13 +581 0xC4C4 //TX_FDEQ_GAIN_14 +582 0xC4C4 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0304 //TX_FDEQ_BIN_2 +594 0x0405 //TX_FDEQ_BIN_3 +595 0x0607 //TX_FDEQ_BIN_4 +596 0x0809 //TX_FDEQ_BIN_5 +597 0x0A0B //TX_FDEQ_BIN_6 +598 0x0C0D //TX_FDEQ_BIN_7 +599 0x0E0F //TX_FDEQ_BIN_8 +600 0x1011 //TX_FDEQ_BIN_9 +601 0x1214 //TX_FDEQ_BIN_10 +602 0x1618 //TX_FDEQ_BIN_11 +603 0x1C1C //TX_FDEQ_BIN_12 +604 0x2020 //TX_FDEQ_BIN_13 +605 0x2020 //TX_FDEQ_BIN_14 +606 0x2011 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4A4C //TX_PREEQ_GAIN_MIC0_6 +624 0x4E50 //TX_PREEQ_GAIN_MIC0_7 +625 0x5456 //TX_PREEQ_GAIN_MIC0_8 +626 0x585C //TX_PREEQ_GAIN_MIC0_9 +627 0x5C64 //TX_PREEQ_GAIN_MIC0_10 +628 0x7478 //TX_PREEQ_GAIN_MIC0_11 +629 0x705C //TX_PREEQ_GAIN_MIC0_12 +630 0x4838 //TX_PREEQ_GAIN_MIC0_13 +631 0x3C70 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0202 //TX_PREEQ_BIN_MIC0_0 +642 0x0203 //TX_PREEQ_BIN_MIC0_1 +643 0x0303 //TX_PREEQ_BIN_MIC0_2 +644 0x0304 //TX_PREEQ_BIN_MIC0_3 +645 0x0405 //TX_PREEQ_BIN_MIC0_4 +646 0x0506 //TX_PREEQ_BIN_MIC0_5 +647 0x0708 //TX_PREEQ_BIN_MIC0_6 +648 0x0909 //TX_PREEQ_BIN_MIC0_7 +649 0x090B //TX_PREEQ_BIN_MIC0_8 +650 0x0C10 //TX_PREEQ_BIN_MIC0_9 +651 0x1013 //TX_PREEQ_BIN_MIC0_10 +652 0x1414 //TX_PREEQ_BIN_MIC0_11 +653 0x1414 //TX_PREEQ_BIN_MIC0_12 +654 0x1C1E //TX_PREEQ_BIN_MIC0_13 +655 0x1E28 //TX_PREEQ_BIN_MIC0_14 +656 0x462C //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0030 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x1812 //TX_PREEQ_BIN_MIC1_0 +691 0x0A0A //TX_PREEQ_BIN_MIC1_1 +692 0x0808 //TX_PREEQ_BIN_MIC1_2 +693 0x080A //TX_PREEQ_BIN_MIC1_3 +694 0x0B09 //TX_PREEQ_BIN_MIC1_4 +695 0x0A06 //TX_PREEQ_BIN_MIC1_5 +696 0x0606 //TX_PREEQ_BIN_MIC1_6 +697 0x0605 //TX_PREEQ_BIN_MIC1_7 +698 0x050A //TX_PREEQ_BIN_MIC1_8 +699 0x1505 //TX_PREEQ_BIN_MIC1_9 +700 0x0506 //TX_PREEQ_BIN_MIC1_10 +701 0x0615 //TX_PREEQ_BIN_MIC1_11 +702 0x1516 //TX_PREEQ_BIN_MIC1_12 +703 0x2021 //TX_PREEQ_BIN_MIC1_13 +704 0x2021 //TX_PREEQ_BIN_MIC1_14 +705 0x2021 //TX_PREEQ_BIN_MIC1_15 +706 0x0800 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0E10 //TX_PREEQ_BIN_MIC2_0 +740 0x1010 //TX_PREEQ_BIN_MIC2_1 +741 0x1010 //TX_PREEQ_BIN_MIC2_2 +742 0x1010 //TX_PREEQ_BIN_MIC2_3 +743 0x1010 //TX_PREEQ_BIN_MIC2_4 +744 0x1010 //TX_PREEQ_BIN_MIC2_5 +745 0x1010 //TX_PREEQ_BIN_MIC2_6 +746 0x1010 //TX_PREEQ_BIN_MIC2_7 +747 0x1010 //TX_PREEQ_BIN_MIC2_8 +748 0x1010 //TX_PREEQ_BIN_MIC2_9 +749 0x1010 //TX_PREEQ_BIN_MIC2_10 +750 0x1010 //TX_PREEQ_BIN_MIC2_11 +751 0x1010 //TX_PREEQ_BIN_MIC2_12 +752 0x1010 //TX_PREEQ_BIN_MIC2_13 +753 0x1010 //TX_PREEQ_BIN_MIC2_14 +754 0x0200 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x2000 //TX_NND_WEIGHT +765 0x0060 //TX_MIC_CALIBRATION_0 +766 0x0060 //TX_MIC_CALIBRATION_1 +767 0x0070 //TX_MIC_CALIBRATION_2 +768 0x0070 //TX_MIC_CALIBRATION_3 +769 0x0050 //TX_MIC_PWR_BIAS_0 +770 0x0040 //TX_MIC_PWR_BIAS_1 +771 0x0040 //TX_MIC_PWR_BIAS_2 +772 0x0040 //TX_MIC_PWR_BIAS_3 +773 0x0009 //TX_GAIN_LIMIT_0 +774 0x000F //TX_GAIN_LIMIT_1 +775 0x000F //TX_GAIN_LIMIT_2 +776 0x000F //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x0C00 //TX_TDDRC_ALPHA_UP_01 +784 0x0C00 //TX_TDDRC_ALPHA_UP_02 +785 0x0C00 //TX_TDDRC_ALPHA_UP_03 +786 0x0C00 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x7FFF //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0010 //TX_DEADMIC_SILENCE_TH +817 0x0600 //TX_MIC_DEGRADE_TH +818 0x0078 //TX_DEADMIC_CNT +819 0x0078 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x4848 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0096 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0004 //TX_FILTINDX +854 0x0004 //TX_TDDRC_THRD_0 +855 0x0016 //TX_TDDRC_THRD_1 +856 0x1900 //TX_TDDRC_THRD_2 +857 0x1900 //TX_TDDRC_THRD_3 +858 0x3000 //TX_TDDRC_SLANT_0 +859 0x7B00 //TX_TDDRC_SLANT_1 +860 0x0C00 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x0A98 //TX_TDDRC_DRC_GAIN +867 0x7FFF //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x0028 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x1000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x0000 //TX_SENDFUNC_REG_MICMUTE +898 0x0000 //TX_SENDFUNC_REG_MICMUTE1 +899 0x0000 //TX_MICMUTE_RATIO_THR +900 0x0000 //TX_MICMUTE_AMP_THR +901 0x0000 //TX_MICMUTE_HPF_IND +902 0x0000 //TX_MICMUTE_LOG_EYR_TH +903 0x0000 //TX_MICMUTE_CVG_TIME +904 0x0000 //TX_MICMUTE_RELEASE_TIME +905 0x0000 //TX_MIC_VOLUME_MIC0MUTE +906 0x0000 //TX_MICMUTE_EPD_OFFSET_0 +907 0x0000 //TX_MICMUTE_FRQ_AEC_L +908 0x0000 //TX_MICMUTE_EAD_THR +909 0x0000 //TX_MICMUTE_LAMBDA_CB_NLE +910 0x0000 //TX_MICMUTE_LAMBDA_RE_EST +911 0x0000 //TX_DTD_THR1_MICMUTE_0 +912 0x0000 //TX_DTD_THR1_MICMUTE_1 +913 0x0000 //TX_DTD_THR1_MICMUTE_2 +914 0x0000 //TX_DTD_THR1_MICMUTE_3 +915 0x0000 //TX_DTD_THR2_MICMUTE_0 +916 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x0000 //TX_MICMUTE_C_POST_FLT +922 0x0000 //TX_MICMUTE_DT_CUT_K +923 0x0000 //TX_MICMUTE_DT_CUT_THR +924 0x0000 //TX_MICMUTE_DT_CUT_K2 +925 0x0000 //TX_MICMUTE_DT_CUT_THR2 +926 0x0000 //TX_MICMUTE_DT2_HOLD_N +927 0x0000 //TX_MICMUTE_RATIODTH_THCUT +928 0x0000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x0000 //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0000 //TX_MICMUTE_C_POST_FLT_MASK +931 0x0000 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0000 //TX_MICMUTE_DT_CUT_K1 +933 0x0000 //TX_MICMUTE_N2_SN_EST +934 0x0000 //TX_MICMUTE_THR_SN_EST_0 +935 0x0000 //TX_MICMUTE_MIN_G_CTRL_0 +936 0x0000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x0000 //TX_MICMUTE_B_POST_FILT_0 +938 0x0000 //TX_MIC1RUB_AMP_THR +939 0x0000 //TX_MIC1MUTE_RATIO_THR +940 0x0000 //TX_MIC1MUTE_AMP_THR +941 0x0000 //TX_MIC1MUTE_CVG_TIME +942 0x0000 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x0064 //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0004 //RX_SAMPLINGFREQ_SIG +3 0x0004 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7FFF //RX_A_HP +12 0x4000 //RX_B_PE +13 0x7800 //RX_THR_PITCH_DET_0 +14 0x7000 //RX_THR_PITCH_DET_1 +15 0x6000 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0500 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x000A //RX_NS_LVL_CTRL +23 0xF600 //RX_THR_SN_EST +24 0x7000 //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0000 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x2000 //RX_MIN_G_FP +128 0x0080 //RX_MAX_G_FP +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x0064 //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0004 //RX_SAMPLINGFREQ_SIG +160 0x0004 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7FFF //RX_A_HP +169 0x4000 //RX_B_PE +170 0x7800 //RX_THR_PITCH_DET_0 +171 0x7000 //RX_THR_PITCH_DET_1 +172 0x6000 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0500 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x000A //RX_NS_LVL_CTRL +180 0xF600 //RX_THR_SN_EST +181 0x7000 //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0000 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x2000 //RX_MIN_G_FP +285 0x0080 //RX_MAX_G_FP +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME BLUETOOTH-BTNB-VOICE_GENERIC-NB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0008 //TX_OPERATION_MODE_0 +1 0x0008 //TX_OPERATION_MODE_1 +2 0x0033 //TX_PATCH_REG +3 0x0240 //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0001 //TX_NUM_MIC +6 0x0000 //TX_SAMPLINGFREQ_SIG +7 0x0000 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009B //TX_DIST2REF1 +22 0x0000 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0A13 //TX_PGA_0 +28 0x0800 //TX_PGA_1 +29 0x0800 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0000 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0001 //TX_MIC_DATA_SRC1 +43 0x0002 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3E00 //TX_DIST2REF_11 +73 0x0000 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0200 //TX_MIC_REFBLK_VOLUME +108 0x0800 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0000 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7D83 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x6800 //TX_THR_PITCH_DET_0 +131 0x6000 //TX_THR_PITCH_DET_1 +132 0x5800 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x001E //TX_TAIL_LENGTH +147 0x0080 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x7000 //TX_EAD_THR +151 0x0800 //TX_THR_RE_EST +152 0x0800 //TX_MIN_EQ_RE_EST_0 +153 0x0800 //TX_MIN_EQ_RE_EST_1 +154 0x0800 //TX_MIN_EQ_RE_EST_2 +155 0x0800 //TX_MIN_EQ_RE_EST_3 +156 0x0800 //TX_MIN_EQ_RE_EST_4 +157 0x0800 //TX_MIN_EQ_RE_EST_5 +158 0x0800 //TX_MIN_EQ_RE_EST_6 +159 0x0800 //TX_MIN_EQ_RE_EST_7 +160 0x0800 //TX_MIN_EQ_RE_EST_8 +161 0x0800 //TX_MIN_EQ_RE_EST_9 +162 0x0800 //TX_MIN_EQ_RE_EST_10 +163 0x0800 //TX_MIN_EQ_RE_EST_11 +164 0x0800 //TX_MIN_EQ_RE_EST_12 +165 0x4000 //TX_LAMBDA_RE_EST +166 0x2000 //TX_LAMBDA_CB_NLE +167 0x6000 //TX_C_POST_FLT +168 0x7000 //TX_GAIN_NP +169 0x00C8 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x03E8 //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x7800 //TX_DTD_THR1_0 +198 0x7000 //TX_DTD_THR1_1 +199 0x7FFF //TX_DTD_THR1_2 +200 0x7FFF //TX_DTD_THR1_3 +201 0x7FFF //TX_DTD_THR1_4 +202 0x7FFF //TX_DTD_THR1_5 +203 0x7FFF //TX_DTD_THR1_6 +204 0x7FFF //TX_DTD_THR2_0 +205 0x7FFF //TX_DTD_THR2_1 +206 0x7FFF //TX_DTD_THR2_2 +207 0x7FFF //TX_DTD_THR2_3 +208 0x7FFF //TX_DTD_THR2_4 +209 0x7FFF //TX_DTD_THR2_5 +210 0x7FFF //TX_DTD_THR2_6 +211 0x1000 //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x0BB8 //TX_DT_CUT_K +214 0x0CCD //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x0400 //TX_ADPT_STRICT_L +222 0x0200 //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x0800 //TX_B_POST_FILT_ECHO_L +229 0x7FFF //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x7FFF //TX_B_LESSCUT_RTO_ECHO +232 0x0019 //TX_EPD_OFFSET_00 +233 0x0019 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x7FFF //TX_DTD_THR1_7 +238 0x7FFF //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xF400 //TX_THR_SN_EST_0 +243 0xF400 //TX_THR_SN_EST_1 +244 0xF600 //TX_THR_SN_EST_2 +245 0xF400 //TX_THR_SN_EST_3 +246 0xF400 //TX_THR_SN_EST_4 +247 0xF400 //TX_THR_SN_EST_5 +248 0xF400 //TX_THR_SN_EST_6 +249 0xF600 //TX_THR_SN_EST_7 +250 0x0000 //TX_DELTA_THR_SN_EST_0 +251 0x0200 //TX_DELTA_THR_SN_EST_1 +252 0x0200 //TX_DELTA_THR_SN_EST_2 +253 0x0200 //TX_DELTA_THR_SN_EST_3 +254 0x0200 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0000 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x6000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x6000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x1000 //TX_B_POST_FLT_0 +280 0x1000 //TX_B_POST_FLT_1 +281 0x000F //TX_NS_LVL_CTRL_0 +282 0x0011 //TX_NS_LVL_CTRL_1 +283 0x000F //TX_NS_LVL_CTRL_2 +284 0x000F //TX_NS_LVL_CTRL_3 +285 0x000F //TX_NS_LVL_CTRL_4 +286 0x000F //TX_NS_LVL_CTRL_5 +287 0x000F //TX_NS_LVL_CTRL_6 +288 0x0011 //TX_NS_LVL_CTRL_7 +289 0x000C //TX_MIN_GAIN_S_0 +290 0x000F //TX_MIN_GAIN_S_1 +291 0x000C //TX_MIN_GAIN_S_2 +292 0x000C //TX_MIN_GAIN_S_3 +293 0x000C //TX_MIN_GAIN_S_4 +294 0x000C //TX_MIN_GAIN_S_5 +295 0x000C //TX_MIN_GAIN_S_6 +296 0x000F //TX_MIN_GAIN_S_7 +297 0x7FFF //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x7FFF //TX_SNRI_SUP_1 +302 0x7FFF //TX_SNRI_SUP_2 +303 0x7FFF //TX_SNRI_SUP_3 +304 0x7FFF //TX_SNRI_SUP_4 +305 0x7FFF //TX_SNRI_SUP_5 +306 0x7FFF //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x000E //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x4000 //TX_A_POST_FILT_S_0 +315 0x5000 //TX_A_POST_FILT_S_1 +316 0x5000 //TX_A_POST_FILT_S_2 +317 0x5000 //TX_A_POST_FILT_S_3 +318 0x5000 //TX_A_POST_FILT_S_4 +319 0x5000 //TX_A_POST_FILT_S_5 +320 0x4000 //TX_A_POST_FILT_S_6 +321 0x5000 //TX_A_POST_FILT_S_7 +322 0x1000 //TX_B_POST_FILT_0 +323 0x1000 //TX_B_POST_FILT_1 +324 0x1000 //TX_B_POST_FILT_2 +325 0x1000 //TX_B_POST_FILT_3 +326 0x1000 //TX_B_POST_FILT_4 +327 0x1000 //TX_B_POST_FILT_5 +328 0x1000 //TX_B_POST_FILT_6 +329 0x1000 //TX_B_POST_FILT_7 +330 0x7FFF //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x7FFF //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7CCD //TX_LAMBDA_PFILT +339 0x7B00 //TX_LAMBDA_PFILT_S_0 +340 0x7B00 //TX_LAMBDA_PFILT_S_1 +341 0x7B00 //TX_LAMBDA_PFILT_S_2 +342 0x7B00 //TX_LAMBDA_PFILT_S_3 +343 0x7B00 //TX_LAMBDA_PFILT_S_4 +344 0x7B00 //TX_LAMBDA_PFILT_S_5 +345 0x7B00 //TX_LAMBDA_PFILT_S_6 +346 0x7B00 //TX_LAMBDA_PFILT_S_7 +347 0x0200 //TX_K_PEPPER +348 0x0800 //TX_A_PEPPER +349 0x1EAA //TX_K_PEPPER_HF +350 0x0800 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0800 //TX_DT_BINVAD_TH_0 +354 0x0800 //TX_DT_BINVAD_TH_1 +355 0x0800 //TX_DT_BINVAD_TH_2 +356 0x0800 //TX_DT_BINVAD_TH_3 +357 0x1D4C //TX_DT_BINVAD_ENDF +358 0x0000 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0000 //TX_NOISEDET +366 0x0190 //TX_NDETCT +367 0x0050 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x07D0 //TX_NOISE_TH_1 +371 0x00C8 //TX_NOISE_TH_2 +372 0x3A98 //TX_NOISE_TH_3 +373 0x0FA0 //TX_NOISE_TH_4 +374 0x157C //TX_NOISE_TH_5 +375 0x7FFF //TX_NOISE_TH_5_2 +376 0x7FFF //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x044C //TX_NOISE_TH_6 +379 0x0014 //TX_MINENOISE_TH +380 0x4000 //TX_MORENS_TFMASK_TH +381 0xFFEE //TX_DRC_QUIET_FLOOR +382 0x6000 //TX_RATIODTL_CUT_TH +383 0xFFF3 //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x0333 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x0000 //TX_POST_MASK_SUP_HSNE +392 0x0000 //TX_TAIL_DET_TH +393 0x0000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0800 //TX_SUPHIGH_TH +396 0x00C8 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x0800 //TX_C_POST_FLT_MASK +399 0x0005 //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0002 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x0014 //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x7FFF //TX_MIN_G_CTRL_SSNS +409 0x0000 //TX_METAL_RTO_THR +410 0x0000 //TX_NS_FP_K_METAL +411 0x7FFF //TX_NOISEDET_BOOST_TH +412 0x0000 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x4000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x0230 //TX_NOR_OFF_THR +498 0x0CCD //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0xD333 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x6000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0x0000 //TX_DEREVERB_LF_MU +515 0x0000 //TX_DEREVERB_HF_MU +516 0x0000 //TX_DEREVERB_DELAY +517 0x0000 //TX_DEREVERB_COEF_LEN +518 0x0000 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x0000 //TX_GSC_RTOH_TH +523 0x0000 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x001C //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4848 //TX_FDEQ_GAIN_5 +573 0x4242 //TX_FDEQ_GAIN_6 +574 0x423C //TX_FDEQ_GAIN_7 +575 0x3C3C //TX_FDEQ_GAIN_8 +576 0x3434 //TX_FDEQ_GAIN_9 +577 0x4848 //TX_FDEQ_GAIN_10 +578 0x4848 //TX_FDEQ_GAIN_11 +579 0x4848 //TX_FDEQ_GAIN_12 +580 0x4848 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0303 //TX_FDEQ_BIN_2 +594 0x0304 //TX_FDEQ_BIN_3 +595 0x0405 //TX_FDEQ_BIN_4 +596 0x0506 //TX_FDEQ_BIN_5 +597 0x0708 //TX_FDEQ_BIN_6 +598 0x090A //TX_FDEQ_BIN_7 +599 0x0B0C //TX_FDEQ_BIN_8 +600 0x0D0E //TX_FDEQ_BIN_9 +601 0x0E0F //TX_FDEQ_BIN_10 +602 0x0F10 //TX_FDEQ_BIN_11 +603 0x1011 //TX_FDEQ_BIN_12 +604 0x1104 //TX_FDEQ_BIN_13 +605 0x0000 //TX_FDEQ_BIN_14 +606 0x0000 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4848 //TX_PREEQ_GAIN_MIC0_8 +626 0x4848 //TX_PREEQ_GAIN_MIC0_9 +627 0x4848 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0608 //TX_PREEQ_BIN_MIC0_0 +642 0x0808 //TX_PREEQ_BIN_MIC0_1 +643 0x0808 //TX_PREEQ_BIN_MIC0_2 +644 0x0808 //TX_PREEQ_BIN_MIC0_3 +645 0x0808 //TX_PREEQ_BIN_MIC0_4 +646 0x0808 //TX_PREEQ_BIN_MIC0_5 +647 0x0808 //TX_PREEQ_BIN_MIC0_6 +648 0x0808 //TX_PREEQ_BIN_MIC0_7 +649 0x0808 //TX_PREEQ_BIN_MIC0_8 +650 0x0808 //TX_PREEQ_BIN_MIC0_9 +651 0x0808 //TX_PREEQ_BIN_MIC0_10 +652 0x0808 //TX_PREEQ_BIN_MIC0_11 +653 0x0808 //TX_PREEQ_BIN_MIC0_12 +654 0x0808 //TX_PREEQ_BIN_MIC0_13 +655 0x0808 //TX_PREEQ_BIN_MIC0_14 +656 0x0200 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0608 //TX_PREEQ_BIN_MIC1_0 +691 0x0808 //TX_PREEQ_BIN_MIC1_1 +692 0x0808 //TX_PREEQ_BIN_MIC1_2 +693 0x0808 //TX_PREEQ_BIN_MIC1_3 +694 0x0808 //TX_PREEQ_BIN_MIC1_4 +695 0x0808 //TX_PREEQ_BIN_MIC1_5 +696 0x0808 //TX_PREEQ_BIN_MIC1_6 +697 0x0808 //TX_PREEQ_BIN_MIC1_7 +698 0x0808 //TX_PREEQ_BIN_MIC1_8 +699 0x0808 //TX_PREEQ_BIN_MIC1_9 +700 0x0808 //TX_PREEQ_BIN_MIC1_10 +701 0x0808 //TX_PREEQ_BIN_MIC1_11 +702 0x0808 //TX_PREEQ_BIN_MIC1_12 +703 0x0808 //TX_PREEQ_BIN_MIC1_13 +704 0x0808 //TX_PREEQ_BIN_MIC1_14 +705 0x0200 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0608 //TX_PREEQ_BIN_MIC2_0 +740 0x0808 //TX_PREEQ_BIN_MIC2_1 +741 0x0808 //TX_PREEQ_BIN_MIC2_2 +742 0x0808 //TX_PREEQ_BIN_MIC2_3 +743 0x0808 //TX_PREEQ_BIN_MIC2_4 +744 0x0808 //TX_PREEQ_BIN_MIC2_5 +745 0x0808 //TX_PREEQ_BIN_MIC2_6 +746 0x0808 //TX_PREEQ_BIN_MIC2_7 +747 0x0808 //TX_PREEQ_BIN_MIC2_8 +748 0x0808 //TX_PREEQ_BIN_MIC2_9 +749 0x0808 //TX_PREEQ_BIN_MIC2_10 +750 0x0808 //TX_PREEQ_BIN_MIC2_11 +751 0x0808 //TX_PREEQ_BIN_MIC2_12 +752 0x0808 //TX_PREEQ_BIN_MIC2_13 +753 0x0808 //TX_PREEQ_BIN_MIC2_14 +754 0x0200 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x0800 //TX_NND_WEIGHT +765 0x0062 //TX_MIC_CALIBRATION_0 +766 0x0062 //TX_MIC_CALIBRATION_1 +767 0x0062 //TX_MIC_CALIBRATION_2 +768 0x0062 //TX_MIC_CALIBRATION_3 +769 0x0046 //TX_MIC_PWR_BIAS_0 +770 0x0046 //TX_MIC_PWR_BIAS_1 +771 0x0046 //TX_MIC_PWR_BIAS_2 +772 0x0046 //TX_MIC_PWR_BIAS_3 +773 0x000C //TX_GAIN_LIMIT_0 +774 0x000C //TX_GAIN_LIMIT_1 +775 0x000C //TX_GAIN_LIMIT_2 +776 0x000C //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x1000 //TX_TDDRC_ALPHA_UP_01 +784 0x1000 //TX_TDDRC_ALPHA_UP_02 +785 0x1000 //TX_TDDRC_ALPHA_UP_03 +786 0x1000 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x7FFF //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0000 //TX_DEADMIC_SILENCE_TH +817 0x0000 //TX_MIC_DEGRADE_TH +818 0x0000 //TX_DEADMIC_CNT +819 0x0000 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x0000 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0000 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0000 //TX_FILTINDX +854 0x0000 //TX_TDDRC_THRD_0 +855 0x0000 //TX_TDDRC_THRD_1 +856 0x2000 //TX_TDDRC_THRD_2 +857 0x2000 //TX_TDDRC_THRD_3 +858 0x3000 //TX_TDDRC_SLANT_0 +859 0x6E00 //TX_TDDRC_SLANT_1 +860 0x1000 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x07F2 //TX_TDDRC_DRC_GAIN +867 0x7FFF //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x00C8 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x7FFF //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x0000 //TX_SENDFUNC_REG_MICMUTE +898 0x0000 //TX_SENDFUNC_REG_MICMUTE1 +899 0x0000 //TX_MICMUTE_RATIO_THR +900 0x0000 //TX_MICMUTE_AMP_THR +901 0x0000 //TX_MICMUTE_HPF_IND +902 0x0000 //TX_MICMUTE_LOG_EYR_TH +903 0x0000 //TX_MICMUTE_CVG_TIME +904 0x0000 //TX_MICMUTE_RELEASE_TIME +905 0x0000 //TX_MIC_VOLUME_MIC0MUTE +906 0x0000 //TX_MICMUTE_EPD_OFFSET_0 +907 0x0000 //TX_MICMUTE_FRQ_AEC_L +908 0x0000 //TX_MICMUTE_EAD_THR +909 0x0000 //TX_MICMUTE_LAMBDA_CB_NLE +910 0x0000 //TX_MICMUTE_LAMBDA_RE_EST +911 0x0000 //TX_DTD_THR1_MICMUTE_0 +912 0x0000 //TX_DTD_THR1_MICMUTE_1 +913 0x0000 //TX_DTD_THR1_MICMUTE_2 +914 0x0000 //TX_DTD_THR1_MICMUTE_3 +915 0x0000 //TX_DTD_THR2_MICMUTE_0 +916 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x0000 //TX_MICMUTE_C_POST_FLT +922 0x0000 //TX_MICMUTE_DT_CUT_K +923 0x0000 //TX_MICMUTE_DT_CUT_THR +924 0x0000 //TX_MICMUTE_DT_CUT_K2 +925 0x0000 //TX_MICMUTE_DT_CUT_THR2 +926 0x0000 //TX_MICMUTE_DT2_HOLD_N +927 0x0000 //TX_MICMUTE_RATIODTH_THCUT +928 0x0000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x0000 //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0000 //TX_MICMUTE_C_POST_FLT_MASK +931 0x0000 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0000 //TX_MICMUTE_DT_CUT_K1 +933 0x0000 //TX_MICMUTE_N2_SN_EST +934 0x0000 //TX_MICMUTE_THR_SN_EST_0 +935 0x0000 //TX_MICMUTE_MIN_G_CTRL_0 +936 0x0000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x0000 //TX_MICMUTE_B_POST_FILT_0 +938 0x0000 //TX_MIC1RUB_AMP_THR +939 0x0000 //TX_MIC1MUTE_RATIO_THR +940 0x0000 //TX_MIC1MUTE_AMP_THR +941 0x0000 //TX_MIC1MUTE_CVG_TIME +942 0x0000 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x206C //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0000 //RX_SAMPLINGFREQ_SIG +3 0x0000 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7FFF //RX_A_HP +12 0x0000 //RX_B_PE +13 0x3800 //RX_THR_PITCH_DET_0 +14 0x3000 //RX_THR_PITCH_DET_1 +15 0x2800 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0600 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x0010 //RX_NS_LVL_CTRL +23 0xF800 //RX_THR_SN_EST +24 0x7CCD //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4444 //RX_FDEQ_GAIN_6 +46 0x4040 //RX_FDEQ_GAIN_7 +47 0x4040 //RX_FDEQ_GAIN_8 +48 0x4040 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0000 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x017F //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x2000 //RX_MIN_G_FP +128 0x0080 //RX_MAX_G_FP +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x017F //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4444 //RX_FDEQ_GAIN_6 +46 0x4040 //RX_FDEQ_GAIN_7 +47 0x4040 //RX_FDEQ_GAIN_8 +48 0x4040 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x017F //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4444 //RX_FDEQ_GAIN_6 +46 0x4040 //RX_FDEQ_GAIN_7 +47 0x4040 //RX_FDEQ_GAIN_8 +48 0x4040 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x017F //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4444 //RX_FDEQ_GAIN_6 +46 0x4040 //RX_FDEQ_GAIN_7 +47 0x4040 //RX_FDEQ_GAIN_8 +48 0x4040 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x017F //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4444 //RX_FDEQ_GAIN_6 +46 0x4040 //RX_FDEQ_GAIN_7 +47 0x4040 //RX_FDEQ_GAIN_8 +48 0x4040 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x017F //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4444 //RX_FDEQ_GAIN_6 +46 0x4040 //RX_FDEQ_GAIN_7 +47 0x4040 //RX_FDEQ_GAIN_8 +48 0x4040 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x017F //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4444 //RX_FDEQ_GAIN_6 +46 0x4040 //RX_FDEQ_GAIN_7 +47 0x4040 //RX_FDEQ_GAIN_8 +48 0x4040 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x017F //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4444 //RX_FDEQ_GAIN_6 +46 0x4040 //RX_FDEQ_GAIN_7 +47 0x4040 //RX_FDEQ_GAIN_8 +48 0x4040 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x206C //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0000 //RX_SAMPLINGFREQ_SIG +160 0x0000 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7FFF //RX_A_HP +169 0x0000 //RX_B_PE +170 0x3800 //RX_THR_PITCH_DET_0 +171 0x3000 //RX_THR_PITCH_DET_1 +172 0x2800 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0600 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x0010 //RX_NS_LVL_CTRL +180 0xF800 //RX_THR_SN_EST +181 0x7CCD //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4444 //RX_FDEQ_GAIN_6 +203 0x4040 //RX_FDEQ_GAIN_7 +204 0x4040 //RX_FDEQ_GAIN_8 +205 0x4040 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0000 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x017F //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x2000 //RX_MIN_G_FP +285 0x0080 //RX_MAX_G_FP +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x017F //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4444 //RX_FDEQ_GAIN_6 +203 0x4040 //RX_FDEQ_GAIN_7 +204 0x4040 //RX_FDEQ_GAIN_8 +205 0x4040 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x017F //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4444 //RX_FDEQ_GAIN_6 +203 0x4040 //RX_FDEQ_GAIN_7 +204 0x4040 //RX_FDEQ_GAIN_8 +205 0x4040 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x017F //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4444 //RX_FDEQ_GAIN_6 +203 0x4040 //RX_FDEQ_GAIN_7 +204 0x4040 //RX_FDEQ_GAIN_8 +205 0x4040 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x017F //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4444 //RX_FDEQ_GAIN_6 +203 0x4040 //RX_FDEQ_GAIN_7 +204 0x4040 //RX_FDEQ_GAIN_8 +205 0x4040 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x017F //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4444 //RX_FDEQ_GAIN_6 +203 0x4040 //RX_FDEQ_GAIN_7 +204 0x4040 //RX_FDEQ_GAIN_8 +205 0x4040 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x017F //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4444 //RX_FDEQ_GAIN_6 +203 0x4040 //RX_FDEQ_GAIN_7 +204 0x4040 //RX_FDEQ_GAIN_8 +205 0x4040 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x017F //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4444 //RX_FDEQ_GAIN_6 +203 0x4040 //RX_FDEQ_GAIN_7 +204 0x4040 //RX_FDEQ_GAIN_8 +205 0x4040 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME BLUETOOTH-BTNB-VOICE_GENERIC-WB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0008 //TX_OPERATION_MODE_0 +1 0x0008 //TX_OPERATION_MODE_1 +2 0x0033 //TX_PATCH_REG +3 0x0240 //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0001 //TX_NUM_MIC +6 0x0001 //TX_SAMPLINGFREQ_SIG +7 0x0001 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009B //TX_DIST2REF1 +22 0x0000 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0915 //TX_PGA_0 +28 0x0800 //TX_PGA_1 +29 0x0800 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0000 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0001 //TX_MIC_DATA_SRC1 +43 0x0002 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3E00 //TX_DIST2REF_11 +73 0x0000 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0200 //TX_MIC_REFBLK_VOLUME +108 0x0800 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0000 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7D83 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x6800 //TX_THR_PITCH_DET_0 +131 0x6000 //TX_THR_PITCH_DET_1 +132 0x5800 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x001E //TX_TAIL_LENGTH +147 0x0080 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x7000 //TX_EAD_THR +151 0x0800 //TX_THR_RE_EST +152 0x0800 //TX_MIN_EQ_RE_EST_0 +153 0x0800 //TX_MIN_EQ_RE_EST_1 +154 0x0800 //TX_MIN_EQ_RE_EST_2 +155 0x0800 //TX_MIN_EQ_RE_EST_3 +156 0x0800 //TX_MIN_EQ_RE_EST_4 +157 0x0800 //TX_MIN_EQ_RE_EST_5 +158 0x0800 //TX_MIN_EQ_RE_EST_6 +159 0x0800 //TX_MIN_EQ_RE_EST_7 +160 0x0800 //TX_MIN_EQ_RE_EST_8 +161 0x0800 //TX_MIN_EQ_RE_EST_9 +162 0x0800 //TX_MIN_EQ_RE_EST_10 +163 0x0800 //TX_MIN_EQ_RE_EST_11 +164 0x0800 //TX_MIN_EQ_RE_EST_12 +165 0x4000 //TX_LAMBDA_RE_EST +166 0x2000 //TX_LAMBDA_CB_NLE +167 0x6000 //TX_C_POST_FLT +168 0x7000 //TX_GAIN_NP +169 0x00C8 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x03E8 //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x7800 //TX_DTD_THR1_0 +198 0x7000 //TX_DTD_THR1_1 +199 0x7FFF //TX_DTD_THR1_2 +200 0x7FFF //TX_DTD_THR1_3 +201 0x7FFF //TX_DTD_THR1_4 +202 0x7FFF //TX_DTD_THR1_5 +203 0x7FFF //TX_DTD_THR1_6 +204 0x7FFF //TX_DTD_THR2_0 +205 0x7FFF //TX_DTD_THR2_1 +206 0x7FFF //TX_DTD_THR2_2 +207 0x7FFF //TX_DTD_THR2_3 +208 0x7FFF //TX_DTD_THR2_4 +209 0x7FFF //TX_DTD_THR2_5 +210 0x7FFF //TX_DTD_THR2_6 +211 0x1000 //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x0BB8 //TX_DT_CUT_K +214 0x0CCD //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x0400 //TX_ADPT_STRICT_L +222 0x0200 //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x0800 //TX_B_POST_FILT_ECHO_L +229 0x7FFF //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x7FFF //TX_B_LESSCUT_RTO_ECHO +232 0x0019 //TX_EPD_OFFSET_00 +233 0x0019 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x7FFF //TX_DTD_THR1_7 +238 0x7FFF //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xF400 //TX_THR_SN_EST_0 +243 0xF400 //TX_THR_SN_EST_1 +244 0xF600 //TX_THR_SN_EST_2 +245 0xF400 //TX_THR_SN_EST_3 +246 0xF400 //TX_THR_SN_EST_4 +247 0xF400 //TX_THR_SN_EST_5 +248 0xF400 //TX_THR_SN_EST_6 +249 0xF600 //TX_THR_SN_EST_7 +250 0x0000 //TX_DELTA_THR_SN_EST_0 +251 0x0200 //TX_DELTA_THR_SN_EST_1 +252 0x0200 //TX_DELTA_THR_SN_EST_2 +253 0x0200 //TX_DELTA_THR_SN_EST_3 +254 0x0200 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0000 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x6000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x6000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x1000 //TX_B_POST_FLT_0 +280 0x1000 //TX_B_POST_FLT_1 +281 0x000F //TX_NS_LVL_CTRL_0 +282 0x0011 //TX_NS_LVL_CTRL_1 +283 0x000F //TX_NS_LVL_CTRL_2 +284 0x000F //TX_NS_LVL_CTRL_3 +285 0x000F //TX_NS_LVL_CTRL_4 +286 0x000F //TX_NS_LVL_CTRL_5 +287 0x000F //TX_NS_LVL_CTRL_6 +288 0x0011 //TX_NS_LVL_CTRL_7 +289 0x000C //TX_MIN_GAIN_S_0 +290 0x000F //TX_MIN_GAIN_S_1 +291 0x000C //TX_MIN_GAIN_S_2 +292 0x000C //TX_MIN_GAIN_S_3 +293 0x000C //TX_MIN_GAIN_S_4 +294 0x000C //TX_MIN_GAIN_S_5 +295 0x000C //TX_MIN_GAIN_S_6 +296 0x000F //TX_MIN_GAIN_S_7 +297 0x7FFF //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x7FFF //TX_SNRI_SUP_1 +302 0x7FFF //TX_SNRI_SUP_2 +303 0x7FFF //TX_SNRI_SUP_3 +304 0x7FFF //TX_SNRI_SUP_4 +305 0x7FFF //TX_SNRI_SUP_5 +306 0x7FFF //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x000E //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x4000 //TX_A_POST_FILT_S_0 +315 0x5000 //TX_A_POST_FILT_S_1 +316 0x5000 //TX_A_POST_FILT_S_2 +317 0x5000 //TX_A_POST_FILT_S_3 +318 0x5000 //TX_A_POST_FILT_S_4 +319 0x5000 //TX_A_POST_FILT_S_5 +320 0x4000 //TX_A_POST_FILT_S_6 +321 0x5000 //TX_A_POST_FILT_S_7 +322 0x1000 //TX_B_POST_FILT_0 +323 0x1000 //TX_B_POST_FILT_1 +324 0x1000 //TX_B_POST_FILT_2 +325 0x1000 //TX_B_POST_FILT_3 +326 0x1000 //TX_B_POST_FILT_4 +327 0x1000 //TX_B_POST_FILT_5 +328 0x1000 //TX_B_POST_FILT_6 +329 0x1000 //TX_B_POST_FILT_7 +330 0x7FFF //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x7FFF //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7CCD //TX_LAMBDA_PFILT +339 0x7B00 //TX_LAMBDA_PFILT_S_0 +340 0x7B00 //TX_LAMBDA_PFILT_S_1 +341 0x7B00 //TX_LAMBDA_PFILT_S_2 +342 0x7B00 //TX_LAMBDA_PFILT_S_3 +343 0x7B00 //TX_LAMBDA_PFILT_S_4 +344 0x7B00 //TX_LAMBDA_PFILT_S_5 +345 0x7B00 //TX_LAMBDA_PFILT_S_6 +346 0x7B00 //TX_LAMBDA_PFILT_S_7 +347 0x0200 //TX_K_PEPPER +348 0x0800 //TX_A_PEPPER +349 0x1EAA //TX_K_PEPPER_HF +350 0x0800 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0800 //TX_DT_BINVAD_TH_0 +354 0x0800 //TX_DT_BINVAD_TH_1 +355 0x0800 //TX_DT_BINVAD_TH_2 +356 0x0800 //TX_DT_BINVAD_TH_3 +357 0x1D4C //TX_DT_BINVAD_ENDF +358 0x0000 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0000 //TX_NOISEDET +366 0x0190 //TX_NDETCT +367 0x0050 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x07D0 //TX_NOISE_TH_1 +371 0x00C8 //TX_NOISE_TH_2 +372 0x3A98 //TX_NOISE_TH_3 +373 0x0FA0 //TX_NOISE_TH_4 +374 0x157C //TX_NOISE_TH_5 +375 0x7FFF //TX_NOISE_TH_5_2 +376 0x7FFF //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x044C //TX_NOISE_TH_6 +379 0x0014 //TX_MINENOISE_TH +380 0x4000 //TX_MORENS_TFMASK_TH +381 0xFFEE //TX_DRC_QUIET_FLOOR +382 0x6000 //TX_RATIODTL_CUT_TH +383 0xFFF3 //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x0333 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x0000 //TX_POST_MASK_SUP_HSNE +392 0x0000 //TX_TAIL_DET_TH +393 0x0000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0800 //TX_SUPHIGH_TH +396 0x00C8 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x0800 //TX_C_POST_FLT_MASK +399 0x0005 //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0002 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x0014 //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x7FFF //TX_MIN_G_CTRL_SSNS +409 0x0000 //TX_METAL_RTO_THR +410 0x0000 //TX_NS_FP_K_METAL +411 0x7FFF //TX_NOISEDET_BOOST_TH +412 0x0000 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x4000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x0230 //TX_NOR_OFF_THR +498 0x0CCD //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0xD333 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x6000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0x0000 //TX_DEREVERB_LF_MU +515 0x0000 //TX_DEREVERB_HF_MU +516 0x0000 //TX_DEREVERB_DELAY +517 0x0000 //TX_DEREVERB_COEF_LEN +518 0x0000 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x0000 //TX_GSC_RTOH_TH +523 0x0000 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x001C //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4848 //TX_FDEQ_GAIN_5 +573 0x4848 //TX_FDEQ_GAIN_6 +574 0x4444 //TX_FDEQ_GAIN_7 +575 0x4444 //TX_FDEQ_GAIN_8 +576 0x3C3C //TX_FDEQ_GAIN_9 +577 0x3C3C //TX_FDEQ_GAIN_10 +578 0x3C3C //TX_FDEQ_GAIN_11 +579 0x3C30 //TX_FDEQ_GAIN_12 +580 0x3030 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0303 //TX_FDEQ_BIN_2 +594 0x0304 //TX_FDEQ_BIN_3 +595 0x0405 //TX_FDEQ_BIN_4 +596 0x0506 //TX_FDEQ_BIN_5 +597 0x0708 //TX_FDEQ_BIN_6 +598 0x090A //TX_FDEQ_BIN_7 +599 0x0B0C //TX_FDEQ_BIN_8 +600 0x0D0E //TX_FDEQ_BIN_9 +601 0x0E0F //TX_FDEQ_BIN_10 +602 0x0F10 //TX_FDEQ_BIN_11 +603 0x1011 //TX_FDEQ_BIN_12 +604 0x1112 //TX_FDEQ_BIN_13 +605 0x0000 //TX_FDEQ_BIN_14 +606 0x0000 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4848 //TX_PREEQ_GAIN_MIC0_8 +626 0x4848 //TX_PREEQ_GAIN_MIC0_9 +627 0x4848 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0608 //TX_PREEQ_BIN_MIC0_0 +642 0x0808 //TX_PREEQ_BIN_MIC0_1 +643 0x0808 //TX_PREEQ_BIN_MIC0_2 +644 0x0808 //TX_PREEQ_BIN_MIC0_3 +645 0x0808 //TX_PREEQ_BIN_MIC0_4 +646 0x0808 //TX_PREEQ_BIN_MIC0_5 +647 0x0808 //TX_PREEQ_BIN_MIC0_6 +648 0x0808 //TX_PREEQ_BIN_MIC0_7 +649 0x0808 //TX_PREEQ_BIN_MIC0_8 +650 0x0808 //TX_PREEQ_BIN_MIC0_9 +651 0x0808 //TX_PREEQ_BIN_MIC0_10 +652 0x0808 //TX_PREEQ_BIN_MIC0_11 +653 0x0808 //TX_PREEQ_BIN_MIC0_12 +654 0x0808 //TX_PREEQ_BIN_MIC0_13 +655 0x0808 //TX_PREEQ_BIN_MIC0_14 +656 0x0200 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0608 //TX_PREEQ_BIN_MIC1_0 +691 0x0808 //TX_PREEQ_BIN_MIC1_1 +692 0x0808 //TX_PREEQ_BIN_MIC1_2 +693 0x0808 //TX_PREEQ_BIN_MIC1_3 +694 0x0808 //TX_PREEQ_BIN_MIC1_4 +695 0x0808 //TX_PREEQ_BIN_MIC1_5 +696 0x0808 //TX_PREEQ_BIN_MIC1_6 +697 0x0808 //TX_PREEQ_BIN_MIC1_7 +698 0x0808 //TX_PREEQ_BIN_MIC1_8 +699 0x0808 //TX_PREEQ_BIN_MIC1_9 +700 0x0808 //TX_PREEQ_BIN_MIC1_10 +701 0x0808 //TX_PREEQ_BIN_MIC1_11 +702 0x0808 //TX_PREEQ_BIN_MIC1_12 +703 0x0808 //TX_PREEQ_BIN_MIC1_13 +704 0x0808 //TX_PREEQ_BIN_MIC1_14 +705 0x0200 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0608 //TX_PREEQ_BIN_MIC2_0 +740 0x0808 //TX_PREEQ_BIN_MIC2_1 +741 0x0808 //TX_PREEQ_BIN_MIC2_2 +742 0x0808 //TX_PREEQ_BIN_MIC2_3 +743 0x0808 //TX_PREEQ_BIN_MIC2_4 +744 0x0808 //TX_PREEQ_BIN_MIC2_5 +745 0x0808 //TX_PREEQ_BIN_MIC2_6 +746 0x0808 //TX_PREEQ_BIN_MIC2_7 +747 0x0808 //TX_PREEQ_BIN_MIC2_8 +748 0x0808 //TX_PREEQ_BIN_MIC2_9 +749 0x0808 //TX_PREEQ_BIN_MIC2_10 +750 0x0808 //TX_PREEQ_BIN_MIC2_11 +751 0x0808 //TX_PREEQ_BIN_MIC2_12 +752 0x0808 //TX_PREEQ_BIN_MIC2_13 +753 0x0808 //TX_PREEQ_BIN_MIC2_14 +754 0x0200 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x0800 //TX_NND_WEIGHT +765 0x0062 //TX_MIC_CALIBRATION_0 +766 0x0062 //TX_MIC_CALIBRATION_1 +767 0x0062 //TX_MIC_CALIBRATION_2 +768 0x0062 //TX_MIC_CALIBRATION_3 +769 0x0046 //TX_MIC_PWR_BIAS_0 +770 0x0046 //TX_MIC_PWR_BIAS_1 +771 0x0046 //TX_MIC_PWR_BIAS_2 +772 0x0046 //TX_MIC_PWR_BIAS_3 +773 0x000C //TX_GAIN_LIMIT_0 +774 0x000C //TX_GAIN_LIMIT_1 +775 0x000C //TX_GAIN_LIMIT_2 +776 0x000C //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x1000 //TX_TDDRC_ALPHA_UP_01 +784 0x1000 //TX_TDDRC_ALPHA_UP_02 +785 0x1000 //TX_TDDRC_ALPHA_UP_03 +786 0x1000 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x7FFF //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0000 //TX_DEADMIC_SILENCE_TH +817 0x0000 //TX_MIC_DEGRADE_TH +818 0x0000 //TX_DEADMIC_CNT +819 0x0000 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x0000 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0000 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0000 //TX_FILTINDX +854 0x0000 //TX_TDDRC_THRD_0 +855 0x0000 //TX_TDDRC_THRD_1 +856 0x2000 //TX_TDDRC_THRD_2 +857 0x2000 //TX_TDDRC_THRD_3 +858 0x3000 //TX_TDDRC_SLANT_0 +859 0x6E00 //TX_TDDRC_SLANT_1 +860 0x1000 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x07F2 //TX_TDDRC_DRC_GAIN +867 0x7FFF //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x00C8 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x7FFF //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x0000 //TX_SENDFUNC_REG_MICMUTE +898 0x0000 //TX_SENDFUNC_REG_MICMUTE1 +899 0x0000 //TX_MICMUTE_RATIO_THR +900 0x0000 //TX_MICMUTE_AMP_THR +901 0x0000 //TX_MICMUTE_HPF_IND +902 0x0000 //TX_MICMUTE_LOG_EYR_TH +903 0x0000 //TX_MICMUTE_CVG_TIME +904 0x0000 //TX_MICMUTE_RELEASE_TIME +905 0x0000 //TX_MIC_VOLUME_MIC0MUTE +906 0x0000 //TX_MICMUTE_EPD_OFFSET_0 +907 0x0000 //TX_MICMUTE_FRQ_AEC_L +908 0x0000 //TX_MICMUTE_EAD_THR +909 0x0000 //TX_MICMUTE_LAMBDA_CB_NLE +910 0x0000 //TX_MICMUTE_LAMBDA_RE_EST +911 0x0000 //TX_DTD_THR1_MICMUTE_0 +912 0x0000 //TX_DTD_THR1_MICMUTE_1 +913 0x0000 //TX_DTD_THR1_MICMUTE_2 +914 0x0000 //TX_DTD_THR1_MICMUTE_3 +915 0x0000 //TX_DTD_THR2_MICMUTE_0 +916 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x0000 //TX_MICMUTE_C_POST_FLT +922 0x0000 //TX_MICMUTE_DT_CUT_K +923 0x0000 //TX_MICMUTE_DT_CUT_THR +924 0x0000 //TX_MICMUTE_DT_CUT_K2 +925 0x0000 //TX_MICMUTE_DT_CUT_THR2 +926 0x0000 //TX_MICMUTE_DT2_HOLD_N +927 0x0000 //TX_MICMUTE_RATIODTH_THCUT +928 0x0000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x0000 //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0000 //TX_MICMUTE_C_POST_FLT_MASK +931 0x0000 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0000 //TX_MICMUTE_DT_CUT_K1 +933 0x0000 //TX_MICMUTE_N2_SN_EST +934 0x0000 //TX_MICMUTE_THR_SN_EST_0 +935 0x0000 //TX_MICMUTE_MIN_G_CTRL_0 +936 0x0000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x0000 //TX_MICMUTE_B_POST_FILT_0 +938 0x0000 //TX_MIC1RUB_AMP_THR +939 0x0000 //TX_MIC1MUTE_RATIO_THR +940 0x0000 //TX_MIC1MUTE_AMP_THR +941 0x0000 //TX_MIC1MUTE_CVG_TIME +942 0x0000 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x206C //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0001 //RX_SAMPLINGFREQ_SIG +3 0x0001 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7FFF //RX_A_HP +12 0x4000 //RX_B_PE +13 0x3800 //RX_THR_PITCH_DET_0 +14 0x3000 //RX_THR_PITCH_DET_1 +15 0x2800 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0600 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x0010 //RX_NS_LVL_CTRL +23 0xF800 //RX_THR_SN_EST +24 0x7CCD //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x3C3C //RX_FDEQ_GAIN_9 +49 0x3C3C //RX_FDEQ_GAIN_10 +50 0x3838 //RX_FDEQ_GAIN_11 +51 0x3838 //RX_FDEQ_GAIN_12 +52 0x3030 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1112 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0000 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7E70 //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x2000 //RX_MIN_G_FP +128 0x0080 //RX_MAX_G_FP +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7E70 //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x3C3C //RX_FDEQ_GAIN_9 +49 0x3C3C //RX_FDEQ_GAIN_10 +50 0x3838 //RX_FDEQ_GAIN_11 +51 0x3838 //RX_FDEQ_GAIN_12 +52 0x3030 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1112 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7E70 //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x3C3C //RX_FDEQ_GAIN_9 +49 0x3C3C //RX_FDEQ_GAIN_10 +50 0x3838 //RX_FDEQ_GAIN_11 +51 0x3838 //RX_FDEQ_GAIN_12 +52 0x3030 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1112 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7E70 //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x3C3C //RX_FDEQ_GAIN_9 +49 0x3C3C //RX_FDEQ_GAIN_10 +50 0x3838 //RX_FDEQ_GAIN_11 +51 0x3838 //RX_FDEQ_GAIN_12 +52 0x3030 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1112 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7E70 //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x3C3C //RX_FDEQ_GAIN_9 +49 0x3C3C //RX_FDEQ_GAIN_10 +50 0x3838 //RX_FDEQ_GAIN_11 +51 0x3838 //RX_FDEQ_GAIN_12 +52 0x3030 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1112 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7E70 //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x3C3C //RX_FDEQ_GAIN_9 +49 0x3C3C //RX_FDEQ_GAIN_10 +50 0x3838 //RX_FDEQ_GAIN_11 +51 0x3838 //RX_FDEQ_GAIN_12 +52 0x3030 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1112 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7E70 //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x3C3C //RX_FDEQ_GAIN_9 +49 0x3C3C //RX_FDEQ_GAIN_10 +50 0x3838 //RX_FDEQ_GAIN_11 +51 0x3838 //RX_FDEQ_GAIN_12 +52 0x3030 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1112 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7E70 //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x3C3C //RX_FDEQ_GAIN_9 +49 0x3C3C //RX_FDEQ_GAIN_10 +50 0x3838 //RX_FDEQ_GAIN_11 +51 0x3838 //RX_FDEQ_GAIN_12 +52 0x3030 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1112 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x206C //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0001 //RX_SAMPLINGFREQ_SIG +160 0x0001 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7FFF //RX_A_HP +169 0x4000 //RX_B_PE +170 0x3800 //RX_THR_PITCH_DET_0 +171 0x3000 //RX_THR_PITCH_DET_1 +172 0x2800 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0600 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x0010 //RX_NS_LVL_CTRL +180 0xF800 //RX_THR_SN_EST +181 0x7CCD //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x3C3C //RX_FDEQ_GAIN_9 +206 0x3C3C //RX_FDEQ_GAIN_10 +207 0x3838 //RX_FDEQ_GAIN_11 +208 0x3838 //RX_FDEQ_GAIN_12 +209 0x3030 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1112 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0000 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7E70 //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x2000 //RX_MIN_G_FP +285 0x0080 //RX_MAX_G_FP +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7E70 //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x3C3C //RX_FDEQ_GAIN_9 +206 0x3C3C //RX_FDEQ_GAIN_10 +207 0x3838 //RX_FDEQ_GAIN_11 +208 0x3838 //RX_FDEQ_GAIN_12 +209 0x3030 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1112 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7E70 //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x3C3C //RX_FDEQ_GAIN_9 +206 0x3C3C //RX_FDEQ_GAIN_10 +207 0x3838 //RX_FDEQ_GAIN_11 +208 0x3838 //RX_FDEQ_GAIN_12 +209 0x3030 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1112 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7E70 //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x3C3C //RX_FDEQ_GAIN_9 +206 0x3C3C //RX_FDEQ_GAIN_10 +207 0x3838 //RX_FDEQ_GAIN_11 +208 0x3838 //RX_FDEQ_GAIN_12 +209 0x3030 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1112 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7E70 //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x3C3C //RX_FDEQ_GAIN_9 +206 0x3C3C //RX_FDEQ_GAIN_10 +207 0x3838 //RX_FDEQ_GAIN_11 +208 0x3838 //RX_FDEQ_GAIN_12 +209 0x3030 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1112 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7E70 //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x3C3C //RX_FDEQ_GAIN_9 +206 0x3C3C //RX_FDEQ_GAIN_10 +207 0x3838 //RX_FDEQ_GAIN_11 +208 0x3838 //RX_FDEQ_GAIN_12 +209 0x3030 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1112 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7E70 //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x3C3C //RX_FDEQ_GAIN_9 +206 0x3C3C //RX_FDEQ_GAIN_10 +207 0x3838 //RX_FDEQ_GAIN_11 +208 0x3838 //RX_FDEQ_GAIN_12 +209 0x3030 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1112 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7E70 //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x3C3C //RX_FDEQ_GAIN_9 +206 0x3C3C //RX_FDEQ_GAIN_10 +207 0x3838 //RX_FDEQ_GAIN_11 +208 0x3838 //RX_FDEQ_GAIN_12 +209 0x3030 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1112 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME BLUETOOTH-BTNB-VOICE_GENERIC-SWB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0001 //TX_OPERATION_MODE_0 +1 0x0001 //TX_OPERATION_MODE_1 +2 0x0033 //TX_PATCH_REG +3 0x0200 //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0001 //TX_NUM_MIC +6 0x0003 //TX_SAMPLINGFREQ_SIG +7 0x0003 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009B //TX_DIST2REF1 +22 0x0000 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0915 //TX_PGA_0 +28 0x0800 //TX_PGA_1 +29 0x0800 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0000 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0001 //TX_MIC_DATA_SRC1 +43 0x0002 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3E00 //TX_DIST2REF_11 +73 0x0000 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0200 //TX_MIC_REFBLK_VOLUME +108 0x0800 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0000 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7EFF //TX_A_HP +129 0x4000 //TX_B_PE +130 0x1800 //TX_THR_PITCH_DET_0 +131 0x1000 //TX_THR_PITCH_DET_1 +132 0x0800 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x001E //TX_TAIL_LENGTH +147 0x0080 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x7000 //TX_EAD_THR +151 0x0800 //TX_THR_RE_EST +152 0x0800 //TX_MIN_EQ_RE_EST_0 +153 0x0800 //TX_MIN_EQ_RE_EST_1 +154 0x0800 //TX_MIN_EQ_RE_EST_2 +155 0x0800 //TX_MIN_EQ_RE_EST_3 +156 0x0800 //TX_MIN_EQ_RE_EST_4 +157 0x0800 //TX_MIN_EQ_RE_EST_5 +158 0x0800 //TX_MIN_EQ_RE_EST_6 +159 0x0800 //TX_MIN_EQ_RE_EST_7 +160 0x0800 //TX_MIN_EQ_RE_EST_8 +161 0x0800 //TX_MIN_EQ_RE_EST_9 +162 0x0800 //TX_MIN_EQ_RE_EST_10 +163 0x0800 //TX_MIN_EQ_RE_EST_11 +164 0x0800 //TX_MIN_EQ_RE_EST_12 +165 0x4000 //TX_LAMBDA_RE_EST +166 0x2000 //TX_LAMBDA_CB_NLE +167 0x6000 //TX_C_POST_FLT +168 0x7000 //TX_GAIN_NP +169 0x00C8 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x03E8 //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x7800 //TX_DTD_THR1_0 +198 0x7000 //TX_DTD_THR1_1 +199 0x7FFF //TX_DTD_THR1_2 +200 0x7FFF //TX_DTD_THR1_3 +201 0x7FFF //TX_DTD_THR1_4 +202 0x7FFF //TX_DTD_THR1_5 +203 0x7FFF //TX_DTD_THR1_6 +204 0x7FFF //TX_DTD_THR2_0 +205 0x7FFF //TX_DTD_THR2_1 +206 0x7FFF //TX_DTD_THR2_2 +207 0x7FFF //TX_DTD_THR2_3 +208 0x7FFF //TX_DTD_THR2_4 +209 0x7FFF //TX_DTD_THR2_5 +210 0x7FFF //TX_DTD_THR2_6 +211 0x1000 //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x0BB8 //TX_DT_CUT_K +214 0x0CCD //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x0400 //TX_ADPT_STRICT_L +222 0x0200 //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x0800 //TX_B_POST_FILT_ECHO_L +229 0x7FFF //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x7FFF //TX_B_LESSCUT_RTO_ECHO +232 0x00F0 //TX_EPD_OFFSET_00 +233 0x00F0 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x7FFF //TX_DTD_THR1_7 +238 0x7FFF //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xF400 //TX_THR_SN_EST_0 +243 0xF400 //TX_THR_SN_EST_1 +244 0xF600 //TX_THR_SN_EST_2 +245 0xF400 //TX_THR_SN_EST_3 +246 0xF400 //TX_THR_SN_EST_4 +247 0xF400 //TX_THR_SN_EST_5 +248 0xF400 //TX_THR_SN_EST_6 +249 0xF600 //TX_THR_SN_EST_7 +250 0x0000 //TX_DELTA_THR_SN_EST_0 +251 0x0200 //TX_DELTA_THR_SN_EST_1 +252 0x0200 //TX_DELTA_THR_SN_EST_2 +253 0x0200 //TX_DELTA_THR_SN_EST_3 +254 0x0200 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0000 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x6000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x6000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x1000 //TX_B_POST_FLT_0 +280 0x1000 //TX_B_POST_FLT_1 +281 0x000B //TX_NS_LVL_CTRL_0 +282 0x0011 //TX_NS_LVL_CTRL_1 +283 0x000F //TX_NS_LVL_CTRL_2 +284 0x000F //TX_NS_LVL_CTRL_3 +285 0x000F //TX_NS_LVL_CTRL_4 +286 0x000F //TX_NS_LVL_CTRL_5 +287 0x000F //TX_NS_LVL_CTRL_6 +288 0x0011 //TX_NS_LVL_CTRL_7 +289 0x000C //TX_MIN_GAIN_S_0 +290 0x000F //TX_MIN_GAIN_S_1 +291 0x000C //TX_MIN_GAIN_S_2 +292 0x000C //TX_MIN_GAIN_S_3 +293 0x000C //TX_MIN_GAIN_S_4 +294 0x000C //TX_MIN_GAIN_S_5 +295 0x000C //TX_MIN_GAIN_S_6 +296 0x000F //TX_MIN_GAIN_S_7 +297 0x7FFF //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x7FFF //TX_SNRI_SUP_1 +302 0x7FFF //TX_SNRI_SUP_2 +303 0x7FFF //TX_SNRI_SUP_3 +304 0x7FFF //TX_SNRI_SUP_4 +305 0x7FFF //TX_SNRI_SUP_5 +306 0x7FFF //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x000E //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x2000 //TX_A_POST_FILT_S_0 +315 0x5000 //TX_A_POST_FILT_S_1 +316 0x5000 //TX_A_POST_FILT_S_2 +317 0x5000 //TX_A_POST_FILT_S_3 +318 0x5000 //TX_A_POST_FILT_S_4 +319 0x5000 //TX_A_POST_FILT_S_5 +320 0x4000 //TX_A_POST_FILT_S_6 +321 0x5000 //TX_A_POST_FILT_S_7 +322 0x1000 //TX_B_POST_FILT_0 +323 0x1000 //TX_B_POST_FILT_1 +324 0x1000 //TX_B_POST_FILT_2 +325 0x1000 //TX_B_POST_FILT_3 +326 0x1000 //TX_B_POST_FILT_4 +327 0x1000 //TX_B_POST_FILT_5 +328 0x1000 //TX_B_POST_FILT_6 +329 0x1000 //TX_B_POST_FILT_7 +330 0x7FFF //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x7FFF //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7900 //TX_LAMBDA_PFILT +339 0x7B00 //TX_LAMBDA_PFILT_S_0 +340 0x7B00 //TX_LAMBDA_PFILT_S_1 +341 0x7B00 //TX_LAMBDA_PFILT_S_2 +342 0x7B00 //TX_LAMBDA_PFILT_S_3 +343 0x7B00 //TX_LAMBDA_PFILT_S_4 +344 0x7B00 //TX_LAMBDA_PFILT_S_5 +345 0x7B00 //TX_LAMBDA_PFILT_S_6 +346 0x7B00 //TX_LAMBDA_PFILT_S_7 +347 0x0000 //TX_K_PEPPER +348 0x0800 //TX_A_PEPPER +349 0x1EAA //TX_K_PEPPER_HF +350 0x0800 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0800 //TX_DT_BINVAD_TH_0 +354 0x0800 //TX_DT_BINVAD_TH_1 +355 0x0800 //TX_DT_BINVAD_TH_2 +356 0x0800 //TX_DT_BINVAD_TH_3 +357 0x1D4C //TX_DT_BINVAD_ENDF +358 0x0000 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0000 //TX_NOISEDET +366 0x0190 //TX_NDETCT +367 0x0050 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x07D0 //TX_NOISE_TH_1 +371 0x00C8 //TX_NOISE_TH_2 +372 0x3A98 //TX_NOISE_TH_3 +373 0x0FA0 //TX_NOISE_TH_4 +374 0x157C //TX_NOISE_TH_5 +375 0x7FFF //TX_NOISE_TH_5_2 +376 0x7FFF //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x044C //TX_NOISE_TH_6 +379 0x0014 //TX_MINENOISE_TH +380 0x4000 //TX_MORENS_TFMASK_TH +381 0xFFEE //TX_DRC_QUIET_FLOOR +382 0x6000 //TX_RATIODTL_CUT_TH +383 0xFFF3 //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x0333 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x0000 //TX_POST_MASK_SUP_HSNE +392 0x0000 //TX_TAIL_DET_TH +393 0x0000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0800 //TX_SUPHIGH_TH +396 0x00C8 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x0800 //TX_C_POST_FLT_MASK +399 0x0005 //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0002 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x0014 //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x2900 //TX_MIN_G_CTRL_SSNS +409 0x0800 //TX_METAL_RTO_THR +410 0x4848 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x4000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x01E0 //TX_NOR_OFF_THR +498 0x7C00 //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0xD333 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x6000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0x0000 //TX_DEREVERB_LF_MU +515 0x0000 //TX_DEREVERB_HF_MU +516 0x0000 //TX_DEREVERB_DELAY +517 0x0000 //TX_DEREVERB_COEF_LEN +518 0x0000 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x0000 //TX_GSC_RTOH_TH +523 0x0000 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0020 //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4848 //TX_FDEQ_GAIN_5 +573 0x4848 //TX_FDEQ_GAIN_6 +574 0x4848 //TX_FDEQ_GAIN_7 +575 0x4848 //TX_FDEQ_GAIN_8 +576 0x4848 //TX_FDEQ_GAIN_9 +577 0x4848 //TX_FDEQ_GAIN_10 +578 0x4848 //TX_FDEQ_GAIN_11 +579 0x4848 //TX_FDEQ_GAIN_12 +580 0x4848 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0303 //TX_FDEQ_BIN_2 +594 0x0304 //TX_FDEQ_BIN_3 +595 0x0405 //TX_FDEQ_BIN_4 +596 0x0506 //TX_FDEQ_BIN_5 +597 0x0708 //TX_FDEQ_BIN_6 +598 0x090A //TX_FDEQ_BIN_7 +599 0x0B0C //TX_FDEQ_BIN_8 +600 0x0D0E //TX_FDEQ_BIN_9 +601 0x1013 //TX_FDEQ_BIN_10 +602 0x1719 //TX_FDEQ_BIN_11 +603 0x1B1E //TX_FDEQ_BIN_12 +604 0x1E1E //TX_FDEQ_BIN_13 +605 0x1E28 //TX_FDEQ_BIN_14 +606 0x282C //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4868 //TX_PREEQ_GAIN_MIC0_8 +626 0x6860 //TX_PREEQ_GAIN_MIC0_9 +627 0x6048 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0E10 //TX_PREEQ_BIN_MIC0_0 +642 0x1010 //TX_PREEQ_BIN_MIC0_1 +643 0x1010 //TX_PREEQ_BIN_MIC0_2 +644 0x1010 //TX_PREEQ_BIN_MIC0_3 +645 0x1010 //TX_PREEQ_BIN_MIC0_4 +646 0x1010 //TX_PREEQ_BIN_MIC0_5 +647 0x1010 //TX_PREEQ_BIN_MIC0_6 +648 0x1010 //TX_PREEQ_BIN_MIC0_7 +649 0x1010 //TX_PREEQ_BIN_MIC0_8 +650 0x1010 //TX_PREEQ_BIN_MIC0_9 +651 0x1010 //TX_PREEQ_BIN_MIC0_10 +652 0x1010 //TX_PREEQ_BIN_MIC0_11 +653 0x1010 //TX_PREEQ_BIN_MIC0_12 +654 0x1010 //TX_PREEQ_BIN_MIC0_13 +655 0x1010 //TX_PREEQ_BIN_MIC0_14 +656 0x0200 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0E10 //TX_PREEQ_BIN_MIC1_0 +691 0x1010 //TX_PREEQ_BIN_MIC1_1 +692 0x1010 //TX_PREEQ_BIN_MIC1_2 +693 0x1010 //TX_PREEQ_BIN_MIC1_3 +694 0x1010 //TX_PREEQ_BIN_MIC1_4 +695 0x1010 //TX_PREEQ_BIN_MIC1_5 +696 0x1010 //TX_PREEQ_BIN_MIC1_6 +697 0x1010 //TX_PREEQ_BIN_MIC1_7 +698 0x1010 //TX_PREEQ_BIN_MIC1_8 +699 0x1010 //TX_PREEQ_BIN_MIC1_9 +700 0x1010 //TX_PREEQ_BIN_MIC1_10 +701 0x1010 //TX_PREEQ_BIN_MIC1_11 +702 0x1010 //TX_PREEQ_BIN_MIC1_12 +703 0x1010 //TX_PREEQ_BIN_MIC1_13 +704 0x1010 //TX_PREEQ_BIN_MIC1_14 +705 0x0200 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0E10 //TX_PREEQ_BIN_MIC2_0 +740 0x1010 //TX_PREEQ_BIN_MIC2_1 +741 0x1010 //TX_PREEQ_BIN_MIC2_2 +742 0x1010 //TX_PREEQ_BIN_MIC2_3 +743 0x1010 //TX_PREEQ_BIN_MIC2_4 +744 0x1010 //TX_PREEQ_BIN_MIC2_5 +745 0x1010 //TX_PREEQ_BIN_MIC2_6 +746 0x1010 //TX_PREEQ_BIN_MIC2_7 +747 0x1010 //TX_PREEQ_BIN_MIC2_8 +748 0x1010 //TX_PREEQ_BIN_MIC2_9 +749 0x1010 //TX_PREEQ_BIN_MIC2_10 +750 0x1010 //TX_PREEQ_BIN_MIC2_11 +751 0x1010 //TX_PREEQ_BIN_MIC2_12 +752 0x1010 //TX_PREEQ_BIN_MIC2_13 +753 0x1010 //TX_PREEQ_BIN_MIC2_14 +754 0x0200 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x0800 //TX_NND_WEIGHT +765 0x0062 //TX_MIC_CALIBRATION_0 +766 0x0062 //TX_MIC_CALIBRATION_1 +767 0x0062 //TX_MIC_CALIBRATION_2 +768 0x0062 //TX_MIC_CALIBRATION_3 +769 0x0046 //TX_MIC_PWR_BIAS_0 +770 0x0046 //TX_MIC_PWR_BIAS_1 +771 0x0046 //TX_MIC_PWR_BIAS_2 +772 0x0046 //TX_MIC_PWR_BIAS_3 +773 0x000C //TX_GAIN_LIMIT_0 +774 0x000C //TX_GAIN_LIMIT_1 +775 0x000C //TX_GAIN_LIMIT_2 +776 0x000C //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x3000 //TX_TDDRC_ALPHA_UP_01 +784 0x3000 //TX_TDDRC_ALPHA_UP_02 +785 0x3000 //TX_TDDRC_ALPHA_UP_03 +786 0x3000 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x78D6 //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0000 //TX_DEADMIC_SILENCE_TH +817 0x0000 //TX_MIC_DEGRADE_TH +818 0x0000 //TX_DEADMIC_CNT +819 0x0000 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x4848 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0000 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0000 //TX_FILTINDX +854 0x0000 //TX_TDDRC_THRD_0 +855 0x0000 //TX_TDDRC_THRD_1 +856 0x2000 //TX_TDDRC_THRD_2 +857 0x2000 //TX_TDDRC_THRD_3 +858 0x3000 //TX_TDDRC_SLANT_0 +859 0x6E00 //TX_TDDRC_SLANT_1 +860 0x3000 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x0970 //TX_TDDRC_DRC_GAIN +867 0x78D6 //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x0028 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x1000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x0000 //TX_SENDFUNC_REG_MICMUTE +898 0x0000 //TX_SENDFUNC_REG_MICMUTE1 +899 0x0000 //TX_MICMUTE_RATIO_THR +900 0x0000 //TX_MICMUTE_AMP_THR +901 0x0000 //TX_MICMUTE_HPF_IND +902 0x0000 //TX_MICMUTE_LOG_EYR_TH +903 0x0000 //TX_MICMUTE_CVG_TIME +904 0x0000 //TX_MICMUTE_RELEASE_TIME +905 0x0000 //TX_MIC_VOLUME_MIC0MUTE +906 0x0000 //TX_MICMUTE_EPD_OFFSET_0 +907 0x0000 //TX_MICMUTE_FRQ_AEC_L +908 0x0000 //TX_MICMUTE_EAD_THR +909 0x0000 //TX_MICMUTE_LAMBDA_CB_NLE +910 0x0000 //TX_MICMUTE_LAMBDA_RE_EST +911 0x0000 //TX_DTD_THR1_MICMUTE_0 +912 0x0000 //TX_DTD_THR1_MICMUTE_1 +913 0x0000 //TX_DTD_THR1_MICMUTE_2 +914 0x0000 //TX_DTD_THR1_MICMUTE_3 +915 0x0000 //TX_DTD_THR2_MICMUTE_0 +916 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x0000 //TX_MICMUTE_C_POST_FLT +922 0x0000 //TX_MICMUTE_DT_CUT_K +923 0x0000 //TX_MICMUTE_DT_CUT_THR +924 0x0000 //TX_MICMUTE_DT_CUT_K2 +925 0x0000 //TX_MICMUTE_DT_CUT_THR2 +926 0x0000 //TX_MICMUTE_DT2_HOLD_N +927 0x0000 //TX_MICMUTE_RATIODTH_THCUT +928 0x0000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x0000 //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0000 //TX_MICMUTE_C_POST_FLT_MASK +931 0x0000 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0000 //TX_MICMUTE_DT_CUT_K1 +933 0x0000 //TX_MICMUTE_N2_SN_EST +934 0x0000 //TX_MICMUTE_THR_SN_EST_0 +935 0x0000 //TX_MICMUTE_MIN_G_CTRL_0 +936 0x0000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x0000 //TX_MICMUTE_B_POST_FILT_0 +938 0x0000 //TX_MIC1RUB_AMP_THR +939 0x0000 //TX_MIC1MUTE_RATIO_THR +940 0x0000 //TX_MIC1MUTE_AMP_THR +941 0x0000 //TX_MIC1MUTE_CVG_TIME +942 0x0000 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x2064 //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0003 //RX_SAMPLINGFREQ_SIG +3 0x0003 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7FFF //RX_A_HP +12 0x0000 //RX_B_PE +13 0x1800 //RX_THR_PITCH_DET_0 +14 0x1000 //RX_THR_PITCH_DET_1 +15 0x0800 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0400 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x0003 //RX_NS_LVL_CTRL +23 0x9000 //RX_THR_SN_EST +24 0x7CCD //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0000 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x2000 //RX_MIN_G_FP +128 0x0080 //RX_MAX_G_FP +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x2064 //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0003 //RX_SAMPLINGFREQ_SIG +160 0x0003 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7FFF //RX_A_HP +169 0x0000 //RX_B_PE +170 0x1800 //RX_THR_PITCH_DET_0 +171 0x1000 //RX_THR_PITCH_DET_1 +172 0x0800 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0400 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x0003 //RX_NS_LVL_CTRL +180 0x9000 //RX_THR_SN_EST +181 0x7CCD //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0000 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x2000 //RX_MIN_G_FP +285 0x0080 //RX_MAX_G_FP +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME BLUETOOTH-BTNB-VOICE_GENERIC-FB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0009 //TX_OPERATION_MODE_0 +1 0x0009 //TX_OPERATION_MODE_1 +2 0x0020 //TX_PATCH_REG +3 0x0200 //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0001 //TX_NUM_MIC +6 0x0004 //TX_SAMPLINGFREQ_SIG +7 0x0004 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009B //TX_DIST2REF1 +22 0x0000 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0915 //TX_PGA_0 +28 0x0800 //TX_PGA_1 +29 0x0000 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0000 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0001 //TX_MIC_DATA_SRC1 +43 0x0002 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3E00 //TX_DIST2REF_11 +73 0x0000 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0200 //TX_MIC_REFBLK_VOLUME +108 0x0800 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0000 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7E56 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x6800 //TX_THR_PITCH_DET_0 +131 0x6000 //TX_THR_PITCH_DET_1 +132 0x5800 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x001E //TX_TAIL_LENGTH +147 0x0200 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x6000 //TX_EAD_THR +151 0x0400 //TX_THR_RE_EST +152 0x3000 //TX_MIN_EQ_RE_EST_0 +153 0x3000 //TX_MIN_EQ_RE_EST_1 +154 0x4000 //TX_MIN_EQ_RE_EST_2 +155 0x0800 //TX_MIN_EQ_RE_EST_3 +156 0x0800 //TX_MIN_EQ_RE_EST_4 +157 0x0800 //TX_MIN_EQ_RE_EST_5 +158 0x6000 //TX_MIN_EQ_RE_EST_6 +159 0x6000 //TX_MIN_EQ_RE_EST_7 +160 0x6000 //TX_MIN_EQ_RE_EST_8 +161 0x6000 //TX_MIN_EQ_RE_EST_9 +162 0x4000 //TX_MIN_EQ_RE_EST_10 +163 0x4000 //TX_MIN_EQ_RE_EST_11 +164 0x4000 //TX_MIN_EQ_RE_EST_12 +165 0x3000 //TX_LAMBDA_RE_EST +166 0x4000 //TX_LAMBDA_CB_NLE +167 0x3000 //TX_C_POST_FLT +168 0x4500 //TX_GAIN_NP +169 0x00C8 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x03E8 //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x5000 //TX_DTD_THR1_0 +198 0x7000 //TX_DTD_THR1_1 +199 0x7F00 //TX_DTD_THR1_2 +200 0x7FFF //TX_DTD_THR1_3 +201 0x7FFF //TX_DTD_THR1_4 +202 0x7FFF //TX_DTD_THR1_5 +203 0x7FFF //TX_DTD_THR1_6 +204 0x0800 //TX_DTD_THR2_0 +205 0x0800 //TX_DTD_THR2_1 +206 0x0800 //TX_DTD_THR2_2 +207 0x0800 //TX_DTD_THR2_3 +208 0x0800 //TX_DTD_THR2_4 +209 0x0100 //TX_DTD_THR2_5 +210 0x0100 //TX_DTD_THR2_6 +211 0x7FFF //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x03E8 //TX_DT_CUT_K +214 0x0CCD //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x0400 //TX_ADPT_STRICT_L +222 0x0200 //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x0800 //TX_B_POST_FILT_ECHO_L +229 0x7FFF //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x7FFF //TX_B_LESSCUT_RTO_ECHO +232 0x00C0 //TX_EPD_OFFSET_00 +233 0x00C0 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x7FFF //TX_DTD_THR1_7 +238 0x7FFF //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xF700 //TX_THR_SN_EST_0 +243 0xFB00 //TX_THR_SN_EST_1 +244 0xFA00 //TX_THR_SN_EST_2 +245 0xF700 //TX_THR_SN_EST_3 +246 0xFA00 //TX_THR_SN_EST_4 +247 0xF600 //TX_THR_SN_EST_5 +248 0xF600 //TX_THR_SN_EST_6 +249 0xF600 //TX_THR_SN_EST_7 +250 0x0200 //TX_DELTA_THR_SN_EST_0 +251 0x0400 //TX_DELTA_THR_SN_EST_1 +252 0x0300 //TX_DELTA_THR_SN_EST_2 +253 0x0600 //TX_DELTA_THR_SN_EST_3 +254 0x0200 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0200 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x4000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x4000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x2000 //TX_B_POST_FLT_0 +280 0x2000 //TX_B_POST_FLT_1 +281 0x0012 //TX_NS_LVL_CTRL_0 +282 0x0016 //TX_NS_LVL_CTRL_1 +283 0x0016 //TX_NS_LVL_CTRL_2 +284 0x0019 //TX_NS_LVL_CTRL_3 +285 0x0010 //TX_NS_LVL_CTRL_4 +286 0x0010 //TX_NS_LVL_CTRL_5 +287 0x0019 //TX_NS_LVL_CTRL_6 +288 0x0010 //TX_NS_LVL_CTRL_7 +289 0x000C //TX_MIN_GAIN_S_0 +290 0x000C //TX_MIN_GAIN_S_1 +291 0x000C //TX_MIN_GAIN_S_2 +292 0x000F //TX_MIN_GAIN_S_3 +293 0x000C //TX_MIN_GAIN_S_4 +294 0x000C //TX_MIN_GAIN_S_5 +295 0x0011 //TX_MIN_GAIN_S_6 +296 0x000C //TX_MIN_GAIN_S_7 +297 0x7FFF //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7000 //TX_SNRI_SUP_0 +301 0x7000 //TX_SNRI_SUP_1 +302 0x7000 //TX_SNRI_SUP_2 +303 0x6000 //TX_SNRI_SUP_3 +304 0x7FFF //TX_SNRI_SUP_4 +305 0x7FFF //TX_SNRI_SUP_5 +306 0x6000 //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x0016 //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x6000 //TX_A_POST_FILT_S_0 +315 0x6000 //TX_A_POST_FILT_S_1 +316 0x6000 //TX_A_POST_FILT_S_2 +317 0x6000 //TX_A_POST_FILT_S_3 +318 0x6000 //TX_A_POST_FILT_S_4 +319 0x6000 //TX_A_POST_FILT_S_5 +320 0x6000 //TX_A_POST_FILT_S_6 +321 0x6000 //TX_A_POST_FILT_S_7 +322 0x2000 //TX_B_POST_FILT_0 +323 0x4000 //TX_B_POST_FILT_1 +324 0x2000 //TX_B_POST_FILT_2 +325 0x2000 //TX_B_POST_FILT_3 +326 0x2000 //TX_B_POST_FILT_4 +327 0x2000 //TX_B_POST_FILT_5 +328 0x2000 //TX_B_POST_FILT_6 +329 0x2000 //TX_B_POST_FILT_7 +330 0x7FFF //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x7FFF //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7CCD //TX_LAMBDA_PFILT +339 0x7CCD //TX_LAMBDA_PFILT_S_0 +340 0x7CCD //TX_LAMBDA_PFILT_S_1 +341 0x7CCD //TX_LAMBDA_PFILT_S_2 +342 0x7CCD //TX_LAMBDA_PFILT_S_3 +343 0x7CCD //TX_LAMBDA_PFILT_S_4 +344 0x7CCD //TX_LAMBDA_PFILT_S_5 +345 0x7CCD //TX_LAMBDA_PFILT_S_6 +346 0x7CCD //TX_LAMBDA_PFILT_S_7 +347 0x0200 //TX_K_PEPPER +348 0x0500 //TX_A_PEPPER +349 0x1600 //TX_K_PEPPER_HF +350 0x0400 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0800 //TX_DT_BINVAD_TH_0 +354 0x0800 //TX_DT_BINVAD_TH_1 +355 0x0800 //TX_DT_BINVAD_TH_2 +356 0x0800 //TX_DT_BINVAD_TH_3 +357 0x1D4C //TX_DT_BINVAD_ENDF +358 0x0000 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0190 //TX_NDETCT +367 0x0020 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x02A6 //TX_NOISE_TH_1 +371 0x04B0 //TX_NOISE_TH_2 +372 0x3194 //TX_NOISE_TH_3 +373 0x0960 //TX_NOISE_TH_4 +374 0x5555 //TX_NOISE_TH_5 +375 0x3FF4 //TX_NOISE_TH_5_2 +376 0x0001 //TX_NOISE_TH_5_3 +377 0x0000 //TX_NOISE_TH_5_4 +378 0x02BC //TX_NOISE_TH_6 +379 0x0020 //TX_MINENOISE_TH +380 0x4000 //TX_MORENS_TFMASK_TH +381 0xFFEE //TX_DRC_QUIET_FLOOR +382 0x6000 //TX_RATIODTL_CUT_TH +383 0xFFF3 //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x0333 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x0000 //TX_POST_MASK_SUP_HSNE +392 0x0000 //TX_TAIL_DET_TH +393 0x0000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0800 //TX_SUPHIGH_TH +396 0x00C8 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x0800 //TX_C_POST_FLT_MASK +399 0x0005 //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0002 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x0020 //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x2900 //TX_MIN_G_CTRL_SSNS +409 0x0800 //TX_METAL_RTO_THR +410 0x4848 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x4000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x01E0 //TX_NOR_OFF_THR +498 0x7C00 //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0xD333 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x6000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0x0000 //TX_DEREVERB_LF_MU +515 0x0000 //TX_DEREVERB_HF_MU +516 0x0000 //TX_DEREVERB_DELAY +517 0x0000 //TX_DEREVERB_COEF_LEN +518 0x0000 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x0000 //TX_GSC_RTOH_TH +523 0x0000 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0020 //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4848 //TX_FDEQ_GAIN_5 +573 0x4848 //TX_FDEQ_GAIN_6 +574 0x4848 //TX_FDEQ_GAIN_7 +575 0x4848 //TX_FDEQ_GAIN_8 +576 0x4848 //TX_FDEQ_GAIN_9 +577 0x4848 //TX_FDEQ_GAIN_10 +578 0x4848 //TX_FDEQ_GAIN_11 +579 0x4848 //TX_FDEQ_GAIN_12 +580 0x4848 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0304 //TX_FDEQ_BIN_2 +594 0x0405 //TX_FDEQ_BIN_3 +595 0x0607 //TX_FDEQ_BIN_4 +596 0x0809 //TX_FDEQ_BIN_5 +597 0x0A0B //TX_FDEQ_BIN_6 +598 0x0C0D //TX_FDEQ_BIN_7 +599 0x0E0F //TX_FDEQ_BIN_8 +600 0x1011 //TX_FDEQ_BIN_9 +601 0x1214 //TX_FDEQ_BIN_10 +602 0x1618 //TX_FDEQ_BIN_11 +603 0x1C1C //TX_FDEQ_BIN_12 +604 0x2020 //TX_FDEQ_BIN_13 +605 0x2020 //TX_FDEQ_BIN_14 +606 0x2011 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4848 //TX_PREEQ_GAIN_MIC0_8 +626 0x4848 //TX_PREEQ_GAIN_MIC0_9 +627 0x4848 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0E10 //TX_PREEQ_BIN_MIC0_0 +642 0x1010 //TX_PREEQ_BIN_MIC0_1 +643 0x1010 //TX_PREEQ_BIN_MIC0_2 +644 0x1010 //TX_PREEQ_BIN_MIC0_3 +645 0x1010 //TX_PREEQ_BIN_MIC0_4 +646 0x1010 //TX_PREEQ_BIN_MIC0_5 +647 0x1010 //TX_PREEQ_BIN_MIC0_6 +648 0x1010 //TX_PREEQ_BIN_MIC0_7 +649 0x1010 //TX_PREEQ_BIN_MIC0_8 +650 0x1010 //TX_PREEQ_BIN_MIC0_9 +651 0x1010 //TX_PREEQ_BIN_MIC0_10 +652 0x1010 //TX_PREEQ_BIN_MIC0_11 +653 0x1010 //TX_PREEQ_BIN_MIC0_12 +654 0x1010 //TX_PREEQ_BIN_MIC0_13 +655 0x1010 //TX_PREEQ_BIN_MIC0_14 +656 0x0200 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0E10 //TX_PREEQ_BIN_MIC1_0 +691 0x1010 //TX_PREEQ_BIN_MIC1_1 +692 0x1010 //TX_PREEQ_BIN_MIC1_2 +693 0x1010 //TX_PREEQ_BIN_MIC1_3 +694 0x1010 //TX_PREEQ_BIN_MIC1_4 +695 0x1010 //TX_PREEQ_BIN_MIC1_5 +696 0x1010 //TX_PREEQ_BIN_MIC1_6 +697 0x1010 //TX_PREEQ_BIN_MIC1_7 +698 0x1010 //TX_PREEQ_BIN_MIC1_8 +699 0x1010 //TX_PREEQ_BIN_MIC1_9 +700 0x1010 //TX_PREEQ_BIN_MIC1_10 +701 0x1010 //TX_PREEQ_BIN_MIC1_11 +702 0x1010 //TX_PREEQ_BIN_MIC1_12 +703 0x1010 //TX_PREEQ_BIN_MIC1_13 +704 0x1010 //TX_PREEQ_BIN_MIC1_14 +705 0x0200 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0E10 //TX_PREEQ_BIN_MIC2_0 +740 0x1010 //TX_PREEQ_BIN_MIC2_1 +741 0x1010 //TX_PREEQ_BIN_MIC2_2 +742 0x1010 //TX_PREEQ_BIN_MIC2_3 +743 0x1010 //TX_PREEQ_BIN_MIC2_4 +744 0x1010 //TX_PREEQ_BIN_MIC2_5 +745 0x1010 //TX_PREEQ_BIN_MIC2_6 +746 0x1010 //TX_PREEQ_BIN_MIC2_7 +747 0x1010 //TX_PREEQ_BIN_MIC2_8 +748 0x1010 //TX_PREEQ_BIN_MIC2_9 +749 0x1010 //TX_PREEQ_BIN_MIC2_10 +750 0x1010 //TX_PREEQ_BIN_MIC2_11 +751 0x1010 //TX_PREEQ_BIN_MIC2_12 +752 0x1010 //TX_PREEQ_BIN_MIC2_13 +753 0x1010 //TX_PREEQ_BIN_MIC2_14 +754 0x0200 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x2000 //TX_NND_WEIGHT +765 0x0060 //TX_MIC_CALIBRATION_0 +766 0x0060 //TX_MIC_CALIBRATION_1 +767 0x0070 //TX_MIC_CALIBRATION_2 +768 0x0070 //TX_MIC_CALIBRATION_3 +769 0x0050 //TX_MIC_PWR_BIAS_0 +770 0x0040 //TX_MIC_PWR_BIAS_1 +771 0x0040 //TX_MIC_PWR_BIAS_2 +772 0x0040 //TX_MIC_PWR_BIAS_3 +773 0x0009 //TX_GAIN_LIMIT_0 +774 0x000F //TX_GAIN_LIMIT_1 +775 0x000F //TX_GAIN_LIMIT_2 +776 0x000F //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x0C00 //TX_TDDRC_ALPHA_UP_01 +784 0x0C00 //TX_TDDRC_ALPHA_UP_02 +785 0x0C00 //TX_TDDRC_ALPHA_UP_03 +786 0x0C00 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x7FFF //TX_TDDRC_TD_DRC_LIMIT +792 0x2000 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0000 //TX_DEADMIC_SILENCE_TH +817 0x0000 //TX_MIC_DEGRADE_TH +818 0x0000 //TX_DEADMIC_CNT +819 0x0000 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x4848 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0000 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0000 //TX_FILTINDX +854 0x0001 //TX_TDDRC_THRD_0 +855 0x0001 //TX_TDDRC_THRD_1 +856 0x1900 //TX_TDDRC_THRD_2 +857 0x1900 //TX_TDDRC_THRD_3 +858 0x3000 //TX_TDDRC_SLANT_0 +859 0x7B00 //TX_TDDRC_SLANT_1 +860 0x0C00 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x0200 //TX_TDDRC_DRC_GAIN +867 0x7FFF //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x0028 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x7000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x0000 //TX_SENDFUNC_REG_MICMUTE +898 0x0000 //TX_SENDFUNC_REG_MICMUTE1 +899 0x0000 //TX_MICMUTE_RATIO_THR +900 0x0000 //TX_MICMUTE_AMP_THR +901 0x0000 //TX_MICMUTE_HPF_IND +902 0x0000 //TX_MICMUTE_LOG_EYR_TH +903 0x0000 //TX_MICMUTE_CVG_TIME +904 0x0000 //TX_MICMUTE_RELEASE_TIME +905 0x0000 //TX_MIC_VOLUME_MIC0MUTE +906 0x0000 //TX_MICMUTE_EPD_OFFSET_0 +907 0x0000 //TX_MICMUTE_FRQ_AEC_L +908 0x0000 //TX_MICMUTE_EAD_THR +909 0x0000 //TX_MICMUTE_LAMBDA_CB_NLE +910 0x0000 //TX_MICMUTE_LAMBDA_RE_EST +911 0x0000 //TX_DTD_THR1_MICMUTE_0 +912 0x0000 //TX_DTD_THR1_MICMUTE_1 +913 0x0000 //TX_DTD_THR1_MICMUTE_2 +914 0x0000 //TX_DTD_THR1_MICMUTE_3 +915 0x0000 //TX_DTD_THR2_MICMUTE_0 +916 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x0000 //TX_MICMUTE_C_POST_FLT +922 0x0000 //TX_MICMUTE_DT_CUT_K +923 0x0000 //TX_MICMUTE_DT_CUT_THR +924 0x0000 //TX_MICMUTE_DT_CUT_K2 +925 0x0000 //TX_MICMUTE_DT_CUT_THR2 +926 0x0000 //TX_MICMUTE_DT2_HOLD_N +927 0x0000 //TX_MICMUTE_RATIODTH_THCUT +928 0x0000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x0000 //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0000 //TX_MICMUTE_C_POST_FLT_MASK +931 0x0000 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0000 //TX_MICMUTE_DT_CUT_K1 +933 0x0000 //TX_MICMUTE_N2_SN_EST +934 0x0000 //TX_MICMUTE_THR_SN_EST_0 +935 0x0000 //TX_MICMUTE_MIN_G_CTRL_0 +936 0x0000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x0000 //TX_MICMUTE_B_POST_FILT_0 +938 0x0000 //TX_MIC1RUB_AMP_THR +939 0x0000 //TX_MIC1MUTE_RATIO_THR +940 0x0000 //TX_MIC1MUTE_AMP_THR +941 0x0000 //TX_MIC1MUTE_CVG_TIME +942 0x0000 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x2064 //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0004 //RX_SAMPLINGFREQ_SIG +3 0x0004 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7FFF //RX_A_HP +12 0x4000 //RX_B_PE +13 0x7800 //RX_THR_PITCH_DET_0 +14 0x7000 //RX_THR_PITCH_DET_1 +15 0x6000 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0500 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x000A //RX_NS_LVL_CTRL +23 0xF600 //RX_THR_SN_EST +24 0x7000 //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0000 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x2000 //RX_MIN_G_FP +128 0x0080 //RX_MAX_G_FP +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x0064 //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0004 //RX_SAMPLINGFREQ_SIG +160 0x0004 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7FFF //RX_A_HP +169 0x4000 //RX_B_PE +170 0x7800 //RX_THR_PITCH_DET_0 +171 0x7000 //RX_THR_PITCH_DET_1 +172 0x6000 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0500 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x000A //RX_NS_LVL_CTRL +180 0xF600 //RX_THR_SN_EST +181 0x7000 //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0000 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x2000 //RX_MIN_G_FP +285 0x0080 //RX_MAX_G_FP +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME BLUETOOTH-BTNB_NREC-VOICE_GENERIC-NB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0008 //TX_OPERATION_MODE_0 +1 0x0008 //TX_OPERATION_MODE_1 +2 0x0033 //TX_PATCH_REG +3 0x2A68 //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0001 //TX_NUM_MIC +6 0x0000 //TX_SAMPLINGFREQ_SIG +7 0x0000 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009B //TX_DIST2REF1 +22 0x0000 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0A13 //TX_PGA_0 +28 0x0800 //TX_PGA_1 +29 0x0800 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0000 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0001 //TX_MIC_DATA_SRC1 +43 0x0002 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3E00 //TX_DIST2REF_11 +73 0x0000 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0200 //TX_MIC_REFBLK_VOLUME +108 0x0800 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0000 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7D83 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x6800 //TX_THR_PITCH_DET_0 +131 0x6000 //TX_THR_PITCH_DET_1 +132 0x5800 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x001E //TX_TAIL_LENGTH +147 0x0080 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x7000 //TX_EAD_THR +151 0x0800 //TX_THR_RE_EST +152 0x0800 //TX_MIN_EQ_RE_EST_0 +153 0x0800 //TX_MIN_EQ_RE_EST_1 +154 0x0800 //TX_MIN_EQ_RE_EST_2 +155 0x0800 //TX_MIN_EQ_RE_EST_3 +156 0x0800 //TX_MIN_EQ_RE_EST_4 +157 0x0800 //TX_MIN_EQ_RE_EST_5 +158 0x0800 //TX_MIN_EQ_RE_EST_6 +159 0x0800 //TX_MIN_EQ_RE_EST_7 +160 0x0800 //TX_MIN_EQ_RE_EST_8 +161 0x0800 //TX_MIN_EQ_RE_EST_9 +162 0x0800 //TX_MIN_EQ_RE_EST_10 +163 0x0800 //TX_MIN_EQ_RE_EST_11 +164 0x0800 //TX_MIN_EQ_RE_EST_12 +165 0x4000 //TX_LAMBDA_RE_EST +166 0x2000 //TX_LAMBDA_CB_NLE +167 0x6000 //TX_C_POST_FLT +168 0x7000 //TX_GAIN_NP +169 0x00C8 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x03E8 //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x7800 //TX_DTD_THR1_0 +198 0x7000 //TX_DTD_THR1_1 +199 0x7FFF //TX_DTD_THR1_2 +200 0x7FFF //TX_DTD_THR1_3 +201 0x7FFF //TX_DTD_THR1_4 +202 0x7FFF //TX_DTD_THR1_5 +203 0x7FFF //TX_DTD_THR1_6 +204 0x7FFF //TX_DTD_THR2_0 +205 0x7FFF //TX_DTD_THR2_1 +206 0x7FFF //TX_DTD_THR2_2 +207 0x7FFF //TX_DTD_THR2_3 +208 0x7FFF //TX_DTD_THR2_4 +209 0x7FFF //TX_DTD_THR2_5 +210 0x7FFF //TX_DTD_THR2_6 +211 0x1000 //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x0BB8 //TX_DT_CUT_K +214 0x0CCD //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x0400 //TX_ADPT_STRICT_L +222 0x0200 //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x0800 //TX_B_POST_FILT_ECHO_L +229 0x7FFF //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x7FFF //TX_B_LESSCUT_RTO_ECHO +232 0x0019 //TX_EPD_OFFSET_00 +233 0x0019 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x7FFF //TX_DTD_THR1_7 +238 0x7FFF //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xF400 //TX_THR_SN_EST_0 +243 0xF400 //TX_THR_SN_EST_1 +244 0xF600 //TX_THR_SN_EST_2 +245 0xF400 //TX_THR_SN_EST_3 +246 0xF400 //TX_THR_SN_EST_4 +247 0xF400 //TX_THR_SN_EST_5 +248 0xF400 //TX_THR_SN_EST_6 +249 0xF600 //TX_THR_SN_EST_7 +250 0x0000 //TX_DELTA_THR_SN_EST_0 +251 0x0200 //TX_DELTA_THR_SN_EST_1 +252 0x0200 //TX_DELTA_THR_SN_EST_2 +253 0x0200 //TX_DELTA_THR_SN_EST_3 +254 0x0200 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0000 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x6000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x6000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x1000 //TX_B_POST_FLT_0 +280 0x1000 //TX_B_POST_FLT_1 +281 0x000F //TX_NS_LVL_CTRL_0 +282 0x0011 //TX_NS_LVL_CTRL_1 +283 0x000F //TX_NS_LVL_CTRL_2 +284 0x000F //TX_NS_LVL_CTRL_3 +285 0x000F //TX_NS_LVL_CTRL_4 +286 0x000F //TX_NS_LVL_CTRL_5 +287 0x000F //TX_NS_LVL_CTRL_6 +288 0x0011 //TX_NS_LVL_CTRL_7 +289 0x000C //TX_MIN_GAIN_S_0 +290 0x000F //TX_MIN_GAIN_S_1 +291 0x000C //TX_MIN_GAIN_S_2 +292 0x000C //TX_MIN_GAIN_S_3 +293 0x000C //TX_MIN_GAIN_S_4 +294 0x000C //TX_MIN_GAIN_S_5 +295 0x000C //TX_MIN_GAIN_S_6 +296 0x000F //TX_MIN_GAIN_S_7 +297 0x7FFF //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x7FFF //TX_SNRI_SUP_1 +302 0x7FFF //TX_SNRI_SUP_2 +303 0x7FFF //TX_SNRI_SUP_3 +304 0x7FFF //TX_SNRI_SUP_4 +305 0x7FFF //TX_SNRI_SUP_5 +306 0x7FFF //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x000E //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x4000 //TX_A_POST_FILT_S_0 +315 0x5000 //TX_A_POST_FILT_S_1 +316 0x5000 //TX_A_POST_FILT_S_2 +317 0x5000 //TX_A_POST_FILT_S_3 +318 0x5000 //TX_A_POST_FILT_S_4 +319 0x5000 //TX_A_POST_FILT_S_5 +320 0x4000 //TX_A_POST_FILT_S_6 +321 0x5000 //TX_A_POST_FILT_S_7 +322 0x1000 //TX_B_POST_FILT_0 +323 0x1000 //TX_B_POST_FILT_1 +324 0x1000 //TX_B_POST_FILT_2 +325 0x1000 //TX_B_POST_FILT_3 +326 0x1000 //TX_B_POST_FILT_4 +327 0x1000 //TX_B_POST_FILT_5 +328 0x1000 //TX_B_POST_FILT_6 +329 0x1000 //TX_B_POST_FILT_7 +330 0x7FFF //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x7FFF //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7CCD //TX_LAMBDA_PFILT +339 0x7B00 //TX_LAMBDA_PFILT_S_0 +340 0x7B00 //TX_LAMBDA_PFILT_S_1 +341 0x7B00 //TX_LAMBDA_PFILT_S_2 +342 0x7B00 //TX_LAMBDA_PFILT_S_3 +343 0x7B00 //TX_LAMBDA_PFILT_S_4 +344 0x7B00 //TX_LAMBDA_PFILT_S_5 +345 0x7B00 //TX_LAMBDA_PFILT_S_6 +346 0x7B00 //TX_LAMBDA_PFILT_S_7 +347 0x0200 //TX_K_PEPPER +348 0x0800 //TX_A_PEPPER +349 0x1EAA //TX_K_PEPPER_HF +350 0x0800 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0800 //TX_DT_BINVAD_TH_0 +354 0x0800 //TX_DT_BINVAD_TH_1 +355 0x0800 //TX_DT_BINVAD_TH_2 +356 0x0800 //TX_DT_BINVAD_TH_3 +357 0x1D4C //TX_DT_BINVAD_ENDF +358 0x0000 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0190 //TX_NDETCT +367 0x0050 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x07D0 //TX_NOISE_TH_1 +371 0x00C8 //TX_NOISE_TH_2 +372 0x3A98 //TX_NOISE_TH_3 +373 0x0FA0 //TX_NOISE_TH_4 +374 0x157C //TX_NOISE_TH_5 +375 0x7FFF //TX_NOISE_TH_5_2 +376 0x7FFF //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x044C //TX_NOISE_TH_6 +379 0x0014 //TX_MINENOISE_TH +380 0x4000 //TX_MORENS_TFMASK_TH +381 0xFFEE //TX_DRC_QUIET_FLOOR +382 0x6000 //TX_RATIODTL_CUT_TH +383 0xFFF3 //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x0333 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x0000 //TX_POST_MASK_SUP_HSNE +392 0x0000 //TX_TAIL_DET_TH +393 0x0000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0800 //TX_SUPHIGH_TH +396 0x00C8 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x0800 //TX_C_POST_FLT_MASK +399 0x0005 //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0002 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x0014 //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x7FFF //TX_MIN_G_CTRL_SSNS +409 0x0000 //TX_METAL_RTO_THR +410 0x0000 //TX_NS_FP_K_METAL +411 0x7FFF //TX_NOISEDET_BOOST_TH +412 0x0000 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x4000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x0230 //TX_NOR_OFF_THR +498 0x0CCD //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0xD333 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x6000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0x0000 //TX_DEREVERB_LF_MU +515 0x0000 //TX_DEREVERB_HF_MU +516 0x0000 //TX_DEREVERB_DELAY +517 0x0000 //TX_DEREVERB_COEF_LEN +518 0x0000 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x0000 //TX_GSC_RTOH_TH +523 0x0000 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x001C //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4848 //TX_FDEQ_GAIN_5 +573 0x4242 //TX_FDEQ_GAIN_6 +574 0x423C //TX_FDEQ_GAIN_7 +575 0x3C3C //TX_FDEQ_GAIN_8 +576 0x3434 //TX_FDEQ_GAIN_9 +577 0x4848 //TX_FDEQ_GAIN_10 +578 0x4848 //TX_FDEQ_GAIN_11 +579 0x4848 //TX_FDEQ_GAIN_12 +580 0x4848 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0303 //TX_FDEQ_BIN_2 +594 0x0304 //TX_FDEQ_BIN_3 +595 0x0405 //TX_FDEQ_BIN_4 +596 0x0506 //TX_FDEQ_BIN_5 +597 0x0708 //TX_FDEQ_BIN_6 +598 0x090A //TX_FDEQ_BIN_7 +599 0x0B0C //TX_FDEQ_BIN_8 +600 0x0D0E //TX_FDEQ_BIN_9 +601 0x0E0F //TX_FDEQ_BIN_10 +602 0x0F10 //TX_FDEQ_BIN_11 +603 0x1011 //TX_FDEQ_BIN_12 +604 0x1104 //TX_FDEQ_BIN_13 +605 0x0000 //TX_FDEQ_BIN_14 +606 0x0000 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4848 //TX_PREEQ_GAIN_MIC0_8 +626 0x4848 //TX_PREEQ_GAIN_MIC0_9 +627 0x4848 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0608 //TX_PREEQ_BIN_MIC0_0 +642 0x0808 //TX_PREEQ_BIN_MIC0_1 +643 0x0808 //TX_PREEQ_BIN_MIC0_2 +644 0x0808 //TX_PREEQ_BIN_MIC0_3 +645 0x0808 //TX_PREEQ_BIN_MIC0_4 +646 0x0808 //TX_PREEQ_BIN_MIC0_5 +647 0x0808 //TX_PREEQ_BIN_MIC0_6 +648 0x0808 //TX_PREEQ_BIN_MIC0_7 +649 0x0808 //TX_PREEQ_BIN_MIC0_8 +650 0x0808 //TX_PREEQ_BIN_MIC0_9 +651 0x0808 //TX_PREEQ_BIN_MIC0_10 +652 0x0808 //TX_PREEQ_BIN_MIC0_11 +653 0x0808 //TX_PREEQ_BIN_MIC0_12 +654 0x0808 //TX_PREEQ_BIN_MIC0_13 +655 0x0808 //TX_PREEQ_BIN_MIC0_14 +656 0x0200 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0608 //TX_PREEQ_BIN_MIC1_0 +691 0x0808 //TX_PREEQ_BIN_MIC1_1 +692 0x0808 //TX_PREEQ_BIN_MIC1_2 +693 0x0808 //TX_PREEQ_BIN_MIC1_3 +694 0x0808 //TX_PREEQ_BIN_MIC1_4 +695 0x0808 //TX_PREEQ_BIN_MIC1_5 +696 0x0808 //TX_PREEQ_BIN_MIC1_6 +697 0x0808 //TX_PREEQ_BIN_MIC1_7 +698 0x0808 //TX_PREEQ_BIN_MIC1_8 +699 0x0808 //TX_PREEQ_BIN_MIC1_9 +700 0x0808 //TX_PREEQ_BIN_MIC1_10 +701 0x0808 //TX_PREEQ_BIN_MIC1_11 +702 0x0808 //TX_PREEQ_BIN_MIC1_12 +703 0x0808 //TX_PREEQ_BIN_MIC1_13 +704 0x0808 //TX_PREEQ_BIN_MIC1_14 +705 0x0200 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0608 //TX_PREEQ_BIN_MIC2_0 +740 0x0808 //TX_PREEQ_BIN_MIC2_1 +741 0x0808 //TX_PREEQ_BIN_MIC2_2 +742 0x0808 //TX_PREEQ_BIN_MIC2_3 +743 0x0808 //TX_PREEQ_BIN_MIC2_4 +744 0x0808 //TX_PREEQ_BIN_MIC2_5 +745 0x0808 //TX_PREEQ_BIN_MIC2_6 +746 0x0808 //TX_PREEQ_BIN_MIC2_7 +747 0x0808 //TX_PREEQ_BIN_MIC2_8 +748 0x0808 //TX_PREEQ_BIN_MIC2_9 +749 0x0808 //TX_PREEQ_BIN_MIC2_10 +750 0x0808 //TX_PREEQ_BIN_MIC2_11 +751 0x0808 //TX_PREEQ_BIN_MIC2_12 +752 0x0808 //TX_PREEQ_BIN_MIC2_13 +753 0x0808 //TX_PREEQ_BIN_MIC2_14 +754 0x0200 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x0800 //TX_NND_WEIGHT +765 0x0062 //TX_MIC_CALIBRATION_0 +766 0x0062 //TX_MIC_CALIBRATION_1 +767 0x0062 //TX_MIC_CALIBRATION_2 +768 0x0062 //TX_MIC_CALIBRATION_3 +769 0x0046 //TX_MIC_PWR_BIAS_0 +770 0x0046 //TX_MIC_PWR_BIAS_1 +771 0x0046 //TX_MIC_PWR_BIAS_2 +772 0x0046 //TX_MIC_PWR_BIAS_3 +773 0x000C //TX_GAIN_LIMIT_0 +774 0x000C //TX_GAIN_LIMIT_1 +775 0x000C //TX_GAIN_LIMIT_2 +776 0x000C //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x1000 //TX_TDDRC_ALPHA_UP_01 +784 0x1000 //TX_TDDRC_ALPHA_UP_02 +785 0x1000 //TX_TDDRC_ALPHA_UP_03 +786 0x1000 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x7FFF //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0000 //TX_DEADMIC_SILENCE_TH +817 0x0000 //TX_MIC_DEGRADE_TH +818 0x0000 //TX_DEADMIC_CNT +819 0x0000 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x0000 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0000 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0000 //TX_FILTINDX +854 0x0000 //TX_TDDRC_THRD_0 +855 0x0000 //TX_TDDRC_THRD_1 +856 0x2000 //TX_TDDRC_THRD_2 +857 0x2000 //TX_TDDRC_THRD_3 +858 0x3000 //TX_TDDRC_SLANT_0 +859 0x6E00 //TX_TDDRC_SLANT_1 +860 0x1000 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x07F2 //TX_TDDRC_DRC_GAIN +867 0x7FFF //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x00C8 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x7FFF //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x0000 //TX_SENDFUNC_REG_MICMUTE +898 0x0000 //TX_SENDFUNC_REG_MICMUTE1 +899 0x0000 //TX_MICMUTE_RATIO_THR +900 0x0000 //TX_MICMUTE_AMP_THR +901 0x0000 //TX_MICMUTE_HPF_IND +902 0x0000 //TX_MICMUTE_LOG_EYR_TH +903 0x0000 //TX_MICMUTE_CVG_TIME +904 0x0000 //TX_MICMUTE_RELEASE_TIME +905 0x0000 //TX_MIC_VOLUME_MIC0MUTE +906 0x0000 //TX_MICMUTE_EPD_OFFSET_0 +907 0x0000 //TX_MICMUTE_FRQ_AEC_L +908 0x0000 //TX_MICMUTE_EAD_THR +909 0x0000 //TX_MICMUTE_LAMBDA_CB_NLE +910 0x0000 //TX_MICMUTE_LAMBDA_RE_EST +911 0x0000 //TX_DTD_THR1_MICMUTE_0 +912 0x0000 //TX_DTD_THR1_MICMUTE_1 +913 0x0000 //TX_DTD_THR1_MICMUTE_2 +914 0x0000 //TX_DTD_THR1_MICMUTE_3 +915 0x0000 //TX_DTD_THR2_MICMUTE_0 +916 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x0000 //TX_MICMUTE_C_POST_FLT +922 0x0000 //TX_MICMUTE_DT_CUT_K +923 0x0000 //TX_MICMUTE_DT_CUT_THR +924 0x0000 //TX_MICMUTE_DT_CUT_K2 +925 0x0000 //TX_MICMUTE_DT_CUT_THR2 +926 0x0000 //TX_MICMUTE_DT2_HOLD_N +927 0x0000 //TX_MICMUTE_RATIODTH_THCUT +928 0x0000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x0000 //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0000 //TX_MICMUTE_C_POST_FLT_MASK +931 0x0000 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0000 //TX_MICMUTE_DT_CUT_K1 +933 0x0000 //TX_MICMUTE_N2_SN_EST +934 0x0000 //TX_MICMUTE_THR_SN_EST_0 +935 0x0000 //TX_MICMUTE_MIN_G_CTRL_0 +936 0x0000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x0000 //TX_MICMUTE_B_POST_FILT_0 +938 0x0000 //TX_MIC1RUB_AMP_THR +939 0x0000 //TX_MIC1MUTE_RATIO_THR +940 0x0000 //TX_MIC1MUTE_AMP_THR +941 0x0000 //TX_MIC1MUTE_CVG_TIME +942 0x0000 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x206C //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0000 //RX_SAMPLINGFREQ_SIG +3 0x0000 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7FFF //RX_A_HP +12 0x0000 //RX_B_PE +13 0x3800 //RX_THR_PITCH_DET_0 +14 0x3000 //RX_THR_PITCH_DET_1 +15 0x2800 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0600 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x0010 //RX_NS_LVL_CTRL +23 0xF800 //RX_THR_SN_EST +24 0x7CCD //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4444 //RX_FDEQ_GAIN_6 +46 0x4040 //RX_FDEQ_GAIN_7 +47 0x4040 //RX_FDEQ_GAIN_8 +48 0x4040 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0000 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x017F //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x2000 //RX_MIN_G_FP +128 0x0080 //RX_MAX_G_FP +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x017F //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4444 //RX_FDEQ_GAIN_6 +46 0x4040 //RX_FDEQ_GAIN_7 +47 0x4040 //RX_FDEQ_GAIN_8 +48 0x4040 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x017F //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4444 //RX_FDEQ_GAIN_6 +46 0x4040 //RX_FDEQ_GAIN_7 +47 0x4040 //RX_FDEQ_GAIN_8 +48 0x4040 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x017F //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4444 //RX_FDEQ_GAIN_6 +46 0x4040 //RX_FDEQ_GAIN_7 +47 0x4040 //RX_FDEQ_GAIN_8 +48 0x4040 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x017F //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4444 //RX_FDEQ_GAIN_6 +46 0x4040 //RX_FDEQ_GAIN_7 +47 0x4040 //RX_FDEQ_GAIN_8 +48 0x4040 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x017F //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4444 //RX_FDEQ_GAIN_6 +46 0x4040 //RX_FDEQ_GAIN_7 +47 0x4040 //RX_FDEQ_GAIN_8 +48 0x4040 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x017F //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4444 //RX_FDEQ_GAIN_6 +46 0x4040 //RX_FDEQ_GAIN_7 +47 0x4040 //RX_FDEQ_GAIN_8 +48 0x4040 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x017F //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4444 //RX_FDEQ_GAIN_6 +46 0x4040 //RX_FDEQ_GAIN_7 +47 0x4040 //RX_FDEQ_GAIN_8 +48 0x4040 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x206C //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0000 //RX_SAMPLINGFREQ_SIG +160 0x0000 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7FFF //RX_A_HP +169 0x0000 //RX_B_PE +170 0x3800 //RX_THR_PITCH_DET_0 +171 0x3000 //RX_THR_PITCH_DET_1 +172 0x2800 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0600 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x0010 //RX_NS_LVL_CTRL +180 0xF800 //RX_THR_SN_EST +181 0x7CCD //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4444 //RX_FDEQ_GAIN_6 +203 0x4040 //RX_FDEQ_GAIN_7 +204 0x4040 //RX_FDEQ_GAIN_8 +205 0x4040 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0000 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x017F //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x2000 //RX_MIN_G_FP +285 0x0080 //RX_MAX_G_FP +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x017F //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4444 //RX_FDEQ_GAIN_6 +203 0x4040 //RX_FDEQ_GAIN_7 +204 0x4040 //RX_FDEQ_GAIN_8 +205 0x4040 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x017F //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4444 //RX_FDEQ_GAIN_6 +203 0x4040 //RX_FDEQ_GAIN_7 +204 0x4040 //RX_FDEQ_GAIN_8 +205 0x4040 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x017F //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4444 //RX_FDEQ_GAIN_6 +203 0x4040 //RX_FDEQ_GAIN_7 +204 0x4040 //RX_FDEQ_GAIN_8 +205 0x4040 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x017F //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4444 //RX_FDEQ_GAIN_6 +203 0x4040 //RX_FDEQ_GAIN_7 +204 0x4040 //RX_FDEQ_GAIN_8 +205 0x4040 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x017F //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4444 //RX_FDEQ_GAIN_6 +203 0x4040 //RX_FDEQ_GAIN_7 +204 0x4040 //RX_FDEQ_GAIN_8 +205 0x4040 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x017F //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4444 //RX_FDEQ_GAIN_6 +203 0x4040 //RX_FDEQ_GAIN_7 +204 0x4040 //RX_FDEQ_GAIN_8 +205 0x4040 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x017F //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4444 //RX_FDEQ_GAIN_6 +203 0x4040 //RX_FDEQ_GAIN_7 +204 0x4040 //RX_FDEQ_GAIN_8 +205 0x4040 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME BLUETOOTH-BTNB_NREC-VOICE_GENERIC-WB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0008 //TX_OPERATION_MODE_0 +1 0x0008 //TX_OPERATION_MODE_1 +2 0x0033 //TX_PATCH_REG +3 0x2A68 //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0001 //TX_NUM_MIC +6 0x0001 //TX_SAMPLINGFREQ_SIG +7 0x0001 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009B //TX_DIST2REF1 +22 0x0000 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0915 //TX_PGA_0 +28 0x0800 //TX_PGA_1 +29 0x0800 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0000 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0001 //TX_MIC_DATA_SRC1 +43 0x0002 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3E00 //TX_DIST2REF_11 +73 0x0000 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0200 //TX_MIC_REFBLK_VOLUME +108 0x0800 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0000 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7D83 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x6800 //TX_THR_PITCH_DET_0 +131 0x6000 //TX_THR_PITCH_DET_1 +132 0x5800 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x001E //TX_TAIL_LENGTH +147 0x0080 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x7000 //TX_EAD_THR +151 0x0800 //TX_THR_RE_EST +152 0x0800 //TX_MIN_EQ_RE_EST_0 +153 0x0800 //TX_MIN_EQ_RE_EST_1 +154 0x0800 //TX_MIN_EQ_RE_EST_2 +155 0x0800 //TX_MIN_EQ_RE_EST_3 +156 0x0800 //TX_MIN_EQ_RE_EST_4 +157 0x0800 //TX_MIN_EQ_RE_EST_5 +158 0x0800 //TX_MIN_EQ_RE_EST_6 +159 0x0800 //TX_MIN_EQ_RE_EST_7 +160 0x0800 //TX_MIN_EQ_RE_EST_8 +161 0x0800 //TX_MIN_EQ_RE_EST_9 +162 0x0800 //TX_MIN_EQ_RE_EST_10 +163 0x0800 //TX_MIN_EQ_RE_EST_11 +164 0x0800 //TX_MIN_EQ_RE_EST_12 +165 0x4000 //TX_LAMBDA_RE_EST +166 0x2000 //TX_LAMBDA_CB_NLE +167 0x6000 //TX_C_POST_FLT +168 0x7000 //TX_GAIN_NP +169 0x00C8 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x03E8 //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x7800 //TX_DTD_THR1_0 +198 0x7000 //TX_DTD_THR1_1 +199 0x7FFF //TX_DTD_THR1_2 +200 0x7FFF //TX_DTD_THR1_3 +201 0x7FFF //TX_DTD_THR1_4 +202 0x7FFF //TX_DTD_THR1_5 +203 0x7FFF //TX_DTD_THR1_6 +204 0x7FFF //TX_DTD_THR2_0 +205 0x7FFF //TX_DTD_THR2_1 +206 0x7FFF //TX_DTD_THR2_2 +207 0x7FFF //TX_DTD_THR2_3 +208 0x7FFF //TX_DTD_THR2_4 +209 0x7FFF //TX_DTD_THR2_5 +210 0x7FFF //TX_DTD_THR2_6 +211 0x1000 //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x0BB8 //TX_DT_CUT_K +214 0x0CCD //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x0400 //TX_ADPT_STRICT_L +222 0x0200 //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x0800 //TX_B_POST_FILT_ECHO_L +229 0x7FFF //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x7FFF //TX_B_LESSCUT_RTO_ECHO +232 0x0019 //TX_EPD_OFFSET_00 +233 0x0019 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x7FFF //TX_DTD_THR1_7 +238 0x7FFF //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xF400 //TX_THR_SN_EST_0 +243 0xF400 //TX_THR_SN_EST_1 +244 0xF600 //TX_THR_SN_EST_2 +245 0xF400 //TX_THR_SN_EST_3 +246 0xF400 //TX_THR_SN_EST_4 +247 0xF400 //TX_THR_SN_EST_5 +248 0xF400 //TX_THR_SN_EST_6 +249 0xF600 //TX_THR_SN_EST_7 +250 0x0000 //TX_DELTA_THR_SN_EST_0 +251 0x0200 //TX_DELTA_THR_SN_EST_1 +252 0x0200 //TX_DELTA_THR_SN_EST_2 +253 0x0200 //TX_DELTA_THR_SN_EST_3 +254 0x0200 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0000 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x6000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x6000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x1000 //TX_B_POST_FLT_0 +280 0x1000 //TX_B_POST_FLT_1 +281 0x000F //TX_NS_LVL_CTRL_0 +282 0x0011 //TX_NS_LVL_CTRL_1 +283 0x000F //TX_NS_LVL_CTRL_2 +284 0x000F //TX_NS_LVL_CTRL_3 +285 0x000F //TX_NS_LVL_CTRL_4 +286 0x000F //TX_NS_LVL_CTRL_5 +287 0x000F //TX_NS_LVL_CTRL_6 +288 0x0011 //TX_NS_LVL_CTRL_7 +289 0x000C //TX_MIN_GAIN_S_0 +290 0x000F //TX_MIN_GAIN_S_1 +291 0x000C //TX_MIN_GAIN_S_2 +292 0x000C //TX_MIN_GAIN_S_3 +293 0x000C //TX_MIN_GAIN_S_4 +294 0x000C //TX_MIN_GAIN_S_5 +295 0x000C //TX_MIN_GAIN_S_6 +296 0x000F //TX_MIN_GAIN_S_7 +297 0x7FFF //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x7FFF //TX_SNRI_SUP_1 +302 0x7FFF //TX_SNRI_SUP_2 +303 0x7FFF //TX_SNRI_SUP_3 +304 0x7FFF //TX_SNRI_SUP_4 +305 0x7FFF //TX_SNRI_SUP_5 +306 0x7FFF //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x000E //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x4000 //TX_A_POST_FILT_S_0 +315 0x5000 //TX_A_POST_FILT_S_1 +316 0x5000 //TX_A_POST_FILT_S_2 +317 0x5000 //TX_A_POST_FILT_S_3 +318 0x5000 //TX_A_POST_FILT_S_4 +319 0x5000 //TX_A_POST_FILT_S_5 +320 0x4000 //TX_A_POST_FILT_S_6 +321 0x5000 //TX_A_POST_FILT_S_7 +322 0x1000 //TX_B_POST_FILT_0 +323 0x1000 //TX_B_POST_FILT_1 +324 0x1000 //TX_B_POST_FILT_2 +325 0x1000 //TX_B_POST_FILT_3 +326 0x1000 //TX_B_POST_FILT_4 +327 0x1000 //TX_B_POST_FILT_5 +328 0x1000 //TX_B_POST_FILT_6 +329 0x1000 //TX_B_POST_FILT_7 +330 0x7FFF //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x7FFF //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7CCD //TX_LAMBDA_PFILT +339 0x7B00 //TX_LAMBDA_PFILT_S_0 +340 0x7B00 //TX_LAMBDA_PFILT_S_1 +341 0x7B00 //TX_LAMBDA_PFILT_S_2 +342 0x7B00 //TX_LAMBDA_PFILT_S_3 +343 0x7B00 //TX_LAMBDA_PFILT_S_4 +344 0x7B00 //TX_LAMBDA_PFILT_S_5 +345 0x7B00 //TX_LAMBDA_PFILT_S_6 +346 0x7B00 //TX_LAMBDA_PFILT_S_7 +347 0x0200 //TX_K_PEPPER +348 0x0800 //TX_A_PEPPER +349 0x1EAA //TX_K_PEPPER_HF +350 0x0800 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0800 //TX_DT_BINVAD_TH_0 +354 0x0800 //TX_DT_BINVAD_TH_1 +355 0x0800 //TX_DT_BINVAD_TH_2 +356 0x0800 //TX_DT_BINVAD_TH_3 +357 0x1D4C //TX_DT_BINVAD_ENDF +358 0x0000 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0190 //TX_NDETCT +367 0x0050 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x07D0 //TX_NOISE_TH_1 +371 0x00C8 //TX_NOISE_TH_2 +372 0x3A98 //TX_NOISE_TH_3 +373 0x0FA0 //TX_NOISE_TH_4 +374 0x157C //TX_NOISE_TH_5 +375 0x7FFF //TX_NOISE_TH_5_2 +376 0x7FFF //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x044C //TX_NOISE_TH_6 +379 0x0014 //TX_MINENOISE_TH +380 0x4000 //TX_MORENS_TFMASK_TH +381 0xFFEE //TX_DRC_QUIET_FLOOR +382 0x6000 //TX_RATIODTL_CUT_TH +383 0xFFF3 //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x0333 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x0000 //TX_POST_MASK_SUP_HSNE +392 0x0000 //TX_TAIL_DET_TH +393 0x0000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0800 //TX_SUPHIGH_TH +396 0x00C8 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x0800 //TX_C_POST_FLT_MASK +399 0x0005 //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0002 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x0014 //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x7FFF //TX_MIN_G_CTRL_SSNS +409 0x0000 //TX_METAL_RTO_THR +410 0x0000 //TX_NS_FP_K_METAL +411 0x7FFF //TX_NOISEDET_BOOST_TH +412 0x0000 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x4000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x0230 //TX_NOR_OFF_THR +498 0x0CCD //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0xD333 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x6000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0x0000 //TX_DEREVERB_LF_MU +515 0x0000 //TX_DEREVERB_HF_MU +516 0x0000 //TX_DEREVERB_DELAY +517 0x0000 //TX_DEREVERB_COEF_LEN +518 0x0000 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x0000 //TX_GSC_RTOH_TH +523 0x0000 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x001C //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4848 //TX_FDEQ_GAIN_5 +573 0x4848 //TX_FDEQ_GAIN_6 +574 0x4444 //TX_FDEQ_GAIN_7 +575 0x4444 //TX_FDEQ_GAIN_8 +576 0x3C3C //TX_FDEQ_GAIN_9 +577 0x3C3C //TX_FDEQ_GAIN_10 +578 0x3C3C //TX_FDEQ_GAIN_11 +579 0x3C30 //TX_FDEQ_GAIN_12 +580 0x3030 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0303 //TX_FDEQ_BIN_2 +594 0x0304 //TX_FDEQ_BIN_3 +595 0x0405 //TX_FDEQ_BIN_4 +596 0x0506 //TX_FDEQ_BIN_5 +597 0x0708 //TX_FDEQ_BIN_6 +598 0x090A //TX_FDEQ_BIN_7 +599 0x0B0C //TX_FDEQ_BIN_8 +600 0x0D0E //TX_FDEQ_BIN_9 +601 0x0E0F //TX_FDEQ_BIN_10 +602 0x0F10 //TX_FDEQ_BIN_11 +603 0x1011 //TX_FDEQ_BIN_12 +604 0x1112 //TX_FDEQ_BIN_13 +605 0x0000 //TX_FDEQ_BIN_14 +606 0x0000 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4848 //TX_PREEQ_GAIN_MIC0_8 +626 0x4848 //TX_PREEQ_GAIN_MIC0_9 +627 0x4848 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0608 //TX_PREEQ_BIN_MIC0_0 +642 0x0808 //TX_PREEQ_BIN_MIC0_1 +643 0x0808 //TX_PREEQ_BIN_MIC0_2 +644 0x0808 //TX_PREEQ_BIN_MIC0_3 +645 0x0808 //TX_PREEQ_BIN_MIC0_4 +646 0x0808 //TX_PREEQ_BIN_MIC0_5 +647 0x0808 //TX_PREEQ_BIN_MIC0_6 +648 0x0808 //TX_PREEQ_BIN_MIC0_7 +649 0x0808 //TX_PREEQ_BIN_MIC0_8 +650 0x0808 //TX_PREEQ_BIN_MIC0_9 +651 0x0808 //TX_PREEQ_BIN_MIC0_10 +652 0x0808 //TX_PREEQ_BIN_MIC0_11 +653 0x0808 //TX_PREEQ_BIN_MIC0_12 +654 0x0808 //TX_PREEQ_BIN_MIC0_13 +655 0x0808 //TX_PREEQ_BIN_MIC0_14 +656 0x0200 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0608 //TX_PREEQ_BIN_MIC1_0 +691 0x0808 //TX_PREEQ_BIN_MIC1_1 +692 0x0808 //TX_PREEQ_BIN_MIC1_2 +693 0x0808 //TX_PREEQ_BIN_MIC1_3 +694 0x0808 //TX_PREEQ_BIN_MIC1_4 +695 0x0808 //TX_PREEQ_BIN_MIC1_5 +696 0x0808 //TX_PREEQ_BIN_MIC1_6 +697 0x0808 //TX_PREEQ_BIN_MIC1_7 +698 0x0808 //TX_PREEQ_BIN_MIC1_8 +699 0x0808 //TX_PREEQ_BIN_MIC1_9 +700 0x0808 //TX_PREEQ_BIN_MIC1_10 +701 0x0808 //TX_PREEQ_BIN_MIC1_11 +702 0x0808 //TX_PREEQ_BIN_MIC1_12 +703 0x0808 //TX_PREEQ_BIN_MIC1_13 +704 0x0808 //TX_PREEQ_BIN_MIC1_14 +705 0x0200 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0608 //TX_PREEQ_BIN_MIC2_0 +740 0x0808 //TX_PREEQ_BIN_MIC2_1 +741 0x0808 //TX_PREEQ_BIN_MIC2_2 +742 0x0808 //TX_PREEQ_BIN_MIC2_3 +743 0x0808 //TX_PREEQ_BIN_MIC2_4 +744 0x0808 //TX_PREEQ_BIN_MIC2_5 +745 0x0808 //TX_PREEQ_BIN_MIC2_6 +746 0x0808 //TX_PREEQ_BIN_MIC2_7 +747 0x0808 //TX_PREEQ_BIN_MIC2_8 +748 0x0808 //TX_PREEQ_BIN_MIC2_9 +749 0x0808 //TX_PREEQ_BIN_MIC2_10 +750 0x0808 //TX_PREEQ_BIN_MIC2_11 +751 0x0808 //TX_PREEQ_BIN_MIC2_12 +752 0x0808 //TX_PREEQ_BIN_MIC2_13 +753 0x0808 //TX_PREEQ_BIN_MIC2_14 +754 0x0200 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x0800 //TX_NND_WEIGHT +765 0x0062 //TX_MIC_CALIBRATION_0 +766 0x0062 //TX_MIC_CALIBRATION_1 +767 0x0062 //TX_MIC_CALIBRATION_2 +768 0x0062 //TX_MIC_CALIBRATION_3 +769 0x0046 //TX_MIC_PWR_BIAS_0 +770 0x0046 //TX_MIC_PWR_BIAS_1 +771 0x0046 //TX_MIC_PWR_BIAS_2 +772 0x0046 //TX_MIC_PWR_BIAS_3 +773 0x000C //TX_GAIN_LIMIT_0 +774 0x000C //TX_GAIN_LIMIT_1 +775 0x000C //TX_GAIN_LIMIT_2 +776 0x000C //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x1000 //TX_TDDRC_ALPHA_UP_01 +784 0x1000 //TX_TDDRC_ALPHA_UP_02 +785 0x1000 //TX_TDDRC_ALPHA_UP_03 +786 0x1000 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x7FFF //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0000 //TX_DEADMIC_SILENCE_TH +817 0x0000 //TX_MIC_DEGRADE_TH +818 0x0000 //TX_DEADMIC_CNT +819 0x0000 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x0000 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0000 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0000 //TX_FILTINDX +854 0x0000 //TX_TDDRC_THRD_0 +855 0x0000 //TX_TDDRC_THRD_1 +856 0x2000 //TX_TDDRC_THRD_2 +857 0x2000 //TX_TDDRC_THRD_3 +858 0x3000 //TX_TDDRC_SLANT_0 +859 0x6E00 //TX_TDDRC_SLANT_1 +860 0x1000 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x07F2 //TX_TDDRC_DRC_GAIN +867 0x7FFF //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x00C8 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x7FFF //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x0000 //TX_SENDFUNC_REG_MICMUTE +898 0x0000 //TX_SENDFUNC_REG_MICMUTE1 +899 0x0000 //TX_MICMUTE_RATIO_THR +900 0x0000 //TX_MICMUTE_AMP_THR +901 0x0000 //TX_MICMUTE_HPF_IND +902 0x0000 //TX_MICMUTE_LOG_EYR_TH +903 0x0000 //TX_MICMUTE_CVG_TIME +904 0x0000 //TX_MICMUTE_RELEASE_TIME +905 0x0000 //TX_MIC_VOLUME_MIC0MUTE +906 0x0000 //TX_MICMUTE_EPD_OFFSET_0 +907 0x0000 //TX_MICMUTE_FRQ_AEC_L +908 0x0000 //TX_MICMUTE_EAD_THR +909 0x0000 //TX_MICMUTE_LAMBDA_CB_NLE +910 0x0000 //TX_MICMUTE_LAMBDA_RE_EST +911 0x0000 //TX_DTD_THR1_MICMUTE_0 +912 0x0000 //TX_DTD_THR1_MICMUTE_1 +913 0x0000 //TX_DTD_THR1_MICMUTE_2 +914 0x0000 //TX_DTD_THR1_MICMUTE_3 +915 0x0000 //TX_DTD_THR2_MICMUTE_0 +916 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x0000 //TX_MICMUTE_C_POST_FLT +922 0x0000 //TX_MICMUTE_DT_CUT_K +923 0x0000 //TX_MICMUTE_DT_CUT_THR +924 0x0000 //TX_MICMUTE_DT_CUT_K2 +925 0x0000 //TX_MICMUTE_DT_CUT_THR2 +926 0x0000 //TX_MICMUTE_DT2_HOLD_N +927 0x0000 //TX_MICMUTE_RATIODTH_THCUT +928 0x0000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x0000 //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0000 //TX_MICMUTE_C_POST_FLT_MASK +931 0x0000 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0000 //TX_MICMUTE_DT_CUT_K1 +933 0x0000 //TX_MICMUTE_N2_SN_EST +934 0x0000 //TX_MICMUTE_THR_SN_EST_0 +935 0x0000 //TX_MICMUTE_MIN_G_CTRL_0 +936 0x0000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x0000 //TX_MICMUTE_B_POST_FILT_0 +938 0x0000 //TX_MIC1RUB_AMP_THR +939 0x0000 //TX_MIC1MUTE_RATIO_THR +940 0x0000 //TX_MIC1MUTE_AMP_THR +941 0x0000 //TX_MIC1MUTE_CVG_TIME +942 0x0000 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x206C //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0001 //RX_SAMPLINGFREQ_SIG +3 0x0001 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7FFF //RX_A_HP +12 0x4000 //RX_B_PE +13 0x3800 //RX_THR_PITCH_DET_0 +14 0x3000 //RX_THR_PITCH_DET_1 +15 0x2800 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0600 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x0010 //RX_NS_LVL_CTRL +23 0xF800 //RX_THR_SN_EST +24 0x7CCD //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x3C3C //RX_FDEQ_GAIN_9 +49 0x3C3C //RX_FDEQ_GAIN_10 +50 0x3838 //RX_FDEQ_GAIN_11 +51 0x3838 //RX_FDEQ_GAIN_12 +52 0x3030 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1112 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0000 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7E70 //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x2000 //RX_MIN_G_FP +128 0x0080 //RX_MAX_G_FP +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7E70 //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x3C3C //RX_FDEQ_GAIN_9 +49 0x3C3C //RX_FDEQ_GAIN_10 +50 0x3838 //RX_FDEQ_GAIN_11 +51 0x3838 //RX_FDEQ_GAIN_12 +52 0x3030 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1112 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7E70 //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x3C3C //RX_FDEQ_GAIN_9 +49 0x3C3C //RX_FDEQ_GAIN_10 +50 0x3838 //RX_FDEQ_GAIN_11 +51 0x3838 //RX_FDEQ_GAIN_12 +52 0x3030 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1112 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7E70 //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x3C3C //RX_FDEQ_GAIN_9 +49 0x3C3C //RX_FDEQ_GAIN_10 +50 0x3838 //RX_FDEQ_GAIN_11 +51 0x3838 //RX_FDEQ_GAIN_12 +52 0x3030 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1112 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7E70 //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x3C3C //RX_FDEQ_GAIN_9 +49 0x3C3C //RX_FDEQ_GAIN_10 +50 0x3838 //RX_FDEQ_GAIN_11 +51 0x3838 //RX_FDEQ_GAIN_12 +52 0x3030 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1112 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7E70 //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x3C3C //RX_FDEQ_GAIN_9 +49 0x3C3C //RX_FDEQ_GAIN_10 +50 0x3838 //RX_FDEQ_GAIN_11 +51 0x3838 //RX_FDEQ_GAIN_12 +52 0x3030 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1112 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7E70 //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x3C3C //RX_FDEQ_GAIN_9 +49 0x3C3C //RX_FDEQ_GAIN_10 +50 0x3838 //RX_FDEQ_GAIN_11 +51 0x3838 //RX_FDEQ_GAIN_12 +52 0x3030 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1112 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7E70 //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x3C3C //RX_FDEQ_GAIN_9 +49 0x3C3C //RX_FDEQ_GAIN_10 +50 0x3838 //RX_FDEQ_GAIN_11 +51 0x3838 //RX_FDEQ_GAIN_12 +52 0x3030 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1112 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x206C //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0001 //RX_SAMPLINGFREQ_SIG +160 0x0001 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7FFF //RX_A_HP +169 0x4000 //RX_B_PE +170 0x3800 //RX_THR_PITCH_DET_0 +171 0x3000 //RX_THR_PITCH_DET_1 +172 0x2800 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0600 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x0010 //RX_NS_LVL_CTRL +180 0xF800 //RX_THR_SN_EST +181 0x7CCD //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x3C3C //RX_FDEQ_GAIN_9 +206 0x3C3C //RX_FDEQ_GAIN_10 +207 0x3838 //RX_FDEQ_GAIN_11 +208 0x3838 //RX_FDEQ_GAIN_12 +209 0x3030 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1112 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0000 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7E70 //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x2000 //RX_MIN_G_FP +285 0x0080 //RX_MAX_G_FP +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7E70 //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x3C3C //RX_FDEQ_GAIN_9 +206 0x3C3C //RX_FDEQ_GAIN_10 +207 0x3838 //RX_FDEQ_GAIN_11 +208 0x3838 //RX_FDEQ_GAIN_12 +209 0x3030 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1112 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7E70 //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x3C3C //RX_FDEQ_GAIN_9 +206 0x3C3C //RX_FDEQ_GAIN_10 +207 0x3838 //RX_FDEQ_GAIN_11 +208 0x3838 //RX_FDEQ_GAIN_12 +209 0x3030 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1112 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7E70 //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x3C3C //RX_FDEQ_GAIN_9 +206 0x3C3C //RX_FDEQ_GAIN_10 +207 0x3838 //RX_FDEQ_GAIN_11 +208 0x3838 //RX_FDEQ_GAIN_12 +209 0x3030 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1112 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7E70 //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x3C3C //RX_FDEQ_GAIN_9 +206 0x3C3C //RX_FDEQ_GAIN_10 +207 0x3838 //RX_FDEQ_GAIN_11 +208 0x3838 //RX_FDEQ_GAIN_12 +209 0x3030 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1112 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7E70 //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x3C3C //RX_FDEQ_GAIN_9 +206 0x3C3C //RX_FDEQ_GAIN_10 +207 0x3838 //RX_FDEQ_GAIN_11 +208 0x3838 //RX_FDEQ_GAIN_12 +209 0x3030 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1112 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7E70 //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x3C3C //RX_FDEQ_GAIN_9 +206 0x3C3C //RX_FDEQ_GAIN_10 +207 0x3838 //RX_FDEQ_GAIN_11 +208 0x3838 //RX_FDEQ_GAIN_12 +209 0x3030 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1112 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7E70 //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x3C3C //RX_FDEQ_GAIN_9 +206 0x3C3C //RX_FDEQ_GAIN_10 +207 0x3838 //RX_FDEQ_GAIN_11 +208 0x3838 //RX_FDEQ_GAIN_12 +209 0x3030 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1112 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME BLUETOOTH-BTNB_NREC-VOICE_GENERIC-SWB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0001 //TX_OPERATION_MODE_0 +1 0x0001 //TX_OPERATION_MODE_1 +2 0x0033 //TX_PATCH_REG +3 0x2A28 //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0001 //TX_NUM_MIC +6 0x0003 //TX_SAMPLINGFREQ_SIG +7 0x0003 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009B //TX_DIST2REF1 +22 0x0000 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0915 //TX_PGA_0 +28 0x0800 //TX_PGA_1 +29 0x0800 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0000 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0001 //TX_MIC_DATA_SRC1 +43 0x0002 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3E00 //TX_DIST2REF_11 +73 0x0000 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0200 //TX_MIC_REFBLK_VOLUME +108 0x0800 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0000 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7EFF //TX_A_HP +129 0x4000 //TX_B_PE +130 0x1800 //TX_THR_PITCH_DET_0 +131 0x1000 //TX_THR_PITCH_DET_1 +132 0x0800 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x001E //TX_TAIL_LENGTH +147 0x0080 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x7000 //TX_EAD_THR +151 0x0800 //TX_THR_RE_EST +152 0x0800 //TX_MIN_EQ_RE_EST_0 +153 0x0800 //TX_MIN_EQ_RE_EST_1 +154 0x0800 //TX_MIN_EQ_RE_EST_2 +155 0x0800 //TX_MIN_EQ_RE_EST_3 +156 0x0800 //TX_MIN_EQ_RE_EST_4 +157 0x0800 //TX_MIN_EQ_RE_EST_5 +158 0x0800 //TX_MIN_EQ_RE_EST_6 +159 0x0800 //TX_MIN_EQ_RE_EST_7 +160 0x0800 //TX_MIN_EQ_RE_EST_8 +161 0x0800 //TX_MIN_EQ_RE_EST_9 +162 0x0800 //TX_MIN_EQ_RE_EST_10 +163 0x0800 //TX_MIN_EQ_RE_EST_11 +164 0x0800 //TX_MIN_EQ_RE_EST_12 +165 0x4000 //TX_LAMBDA_RE_EST +166 0x2000 //TX_LAMBDA_CB_NLE +167 0x6000 //TX_C_POST_FLT +168 0x7000 //TX_GAIN_NP +169 0x00C8 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x03E8 //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x7800 //TX_DTD_THR1_0 +198 0x7000 //TX_DTD_THR1_1 +199 0x7FFF //TX_DTD_THR1_2 +200 0x7FFF //TX_DTD_THR1_3 +201 0x7FFF //TX_DTD_THR1_4 +202 0x7FFF //TX_DTD_THR1_5 +203 0x7FFF //TX_DTD_THR1_6 +204 0x7FFF //TX_DTD_THR2_0 +205 0x7FFF //TX_DTD_THR2_1 +206 0x7FFF //TX_DTD_THR2_2 +207 0x7FFF //TX_DTD_THR2_3 +208 0x7FFF //TX_DTD_THR2_4 +209 0x7FFF //TX_DTD_THR2_5 +210 0x7FFF //TX_DTD_THR2_6 +211 0x1000 //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x0BB8 //TX_DT_CUT_K +214 0x0CCD //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x0400 //TX_ADPT_STRICT_L +222 0x0200 //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x0800 //TX_B_POST_FILT_ECHO_L +229 0x7FFF //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x7FFF //TX_B_LESSCUT_RTO_ECHO +232 0x00F0 //TX_EPD_OFFSET_00 +233 0x00F0 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x7FFF //TX_DTD_THR1_7 +238 0x7FFF //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xF400 //TX_THR_SN_EST_0 +243 0xF400 //TX_THR_SN_EST_1 +244 0xF600 //TX_THR_SN_EST_2 +245 0xF400 //TX_THR_SN_EST_3 +246 0xF400 //TX_THR_SN_EST_4 +247 0xF400 //TX_THR_SN_EST_5 +248 0xF400 //TX_THR_SN_EST_6 +249 0xF600 //TX_THR_SN_EST_7 +250 0x0000 //TX_DELTA_THR_SN_EST_0 +251 0x0200 //TX_DELTA_THR_SN_EST_1 +252 0x0200 //TX_DELTA_THR_SN_EST_2 +253 0x0200 //TX_DELTA_THR_SN_EST_3 +254 0x0200 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0000 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x6000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x6000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x1000 //TX_B_POST_FLT_0 +280 0x1000 //TX_B_POST_FLT_1 +281 0x000B //TX_NS_LVL_CTRL_0 +282 0x0011 //TX_NS_LVL_CTRL_1 +283 0x000F //TX_NS_LVL_CTRL_2 +284 0x000F //TX_NS_LVL_CTRL_3 +285 0x000F //TX_NS_LVL_CTRL_4 +286 0x000F //TX_NS_LVL_CTRL_5 +287 0x000F //TX_NS_LVL_CTRL_6 +288 0x0011 //TX_NS_LVL_CTRL_7 +289 0x000C //TX_MIN_GAIN_S_0 +290 0x000F //TX_MIN_GAIN_S_1 +291 0x000C //TX_MIN_GAIN_S_2 +292 0x000C //TX_MIN_GAIN_S_3 +293 0x000C //TX_MIN_GAIN_S_4 +294 0x000C //TX_MIN_GAIN_S_5 +295 0x000C //TX_MIN_GAIN_S_6 +296 0x000F //TX_MIN_GAIN_S_7 +297 0x7FFF //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x7FFF //TX_SNRI_SUP_1 +302 0x7FFF //TX_SNRI_SUP_2 +303 0x7FFF //TX_SNRI_SUP_3 +304 0x7FFF //TX_SNRI_SUP_4 +305 0x7FFF //TX_SNRI_SUP_5 +306 0x7FFF //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x000E //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x2000 //TX_A_POST_FILT_S_0 +315 0x5000 //TX_A_POST_FILT_S_1 +316 0x5000 //TX_A_POST_FILT_S_2 +317 0x5000 //TX_A_POST_FILT_S_3 +318 0x5000 //TX_A_POST_FILT_S_4 +319 0x5000 //TX_A_POST_FILT_S_5 +320 0x4000 //TX_A_POST_FILT_S_6 +321 0x5000 //TX_A_POST_FILT_S_7 +322 0x1000 //TX_B_POST_FILT_0 +323 0x1000 //TX_B_POST_FILT_1 +324 0x1000 //TX_B_POST_FILT_2 +325 0x1000 //TX_B_POST_FILT_3 +326 0x1000 //TX_B_POST_FILT_4 +327 0x1000 //TX_B_POST_FILT_5 +328 0x1000 //TX_B_POST_FILT_6 +329 0x1000 //TX_B_POST_FILT_7 +330 0x7FFF //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x7FFF //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7900 //TX_LAMBDA_PFILT +339 0x7B00 //TX_LAMBDA_PFILT_S_0 +340 0x7B00 //TX_LAMBDA_PFILT_S_1 +341 0x7B00 //TX_LAMBDA_PFILT_S_2 +342 0x7B00 //TX_LAMBDA_PFILT_S_3 +343 0x7B00 //TX_LAMBDA_PFILT_S_4 +344 0x7B00 //TX_LAMBDA_PFILT_S_5 +345 0x7B00 //TX_LAMBDA_PFILT_S_6 +346 0x7B00 //TX_LAMBDA_PFILT_S_7 +347 0x0000 //TX_K_PEPPER +348 0x0800 //TX_A_PEPPER +349 0x1EAA //TX_K_PEPPER_HF +350 0x0800 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0800 //TX_DT_BINVAD_TH_0 +354 0x0800 //TX_DT_BINVAD_TH_1 +355 0x0800 //TX_DT_BINVAD_TH_2 +356 0x0800 //TX_DT_BINVAD_TH_3 +357 0x1D4C //TX_DT_BINVAD_ENDF +358 0x0000 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0190 //TX_NDETCT +367 0x0050 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x07D0 //TX_NOISE_TH_1 +371 0x00C8 //TX_NOISE_TH_2 +372 0x3A98 //TX_NOISE_TH_3 +373 0x0FA0 //TX_NOISE_TH_4 +374 0x157C //TX_NOISE_TH_5 +375 0x7FFF //TX_NOISE_TH_5_2 +376 0x7FFF //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x044C //TX_NOISE_TH_6 +379 0x0014 //TX_MINENOISE_TH +380 0x4000 //TX_MORENS_TFMASK_TH +381 0xFFEE //TX_DRC_QUIET_FLOOR +382 0x6000 //TX_RATIODTL_CUT_TH +383 0xFFF3 //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x0333 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x0000 //TX_POST_MASK_SUP_HSNE +392 0x0000 //TX_TAIL_DET_TH +393 0x0000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0800 //TX_SUPHIGH_TH +396 0x00C8 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x0800 //TX_C_POST_FLT_MASK +399 0x0005 //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0002 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x0014 //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x2900 //TX_MIN_G_CTRL_SSNS +409 0x0800 //TX_METAL_RTO_THR +410 0x4848 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x4000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x01E0 //TX_NOR_OFF_THR +498 0x7C00 //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0xD333 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x6000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0x0000 //TX_DEREVERB_LF_MU +515 0x0000 //TX_DEREVERB_HF_MU +516 0x0000 //TX_DEREVERB_DELAY +517 0x0000 //TX_DEREVERB_COEF_LEN +518 0x0000 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x0000 //TX_GSC_RTOH_TH +523 0x0000 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0020 //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4848 //TX_FDEQ_GAIN_5 +573 0x4848 //TX_FDEQ_GAIN_6 +574 0x4848 //TX_FDEQ_GAIN_7 +575 0x4848 //TX_FDEQ_GAIN_8 +576 0x4848 //TX_FDEQ_GAIN_9 +577 0x4848 //TX_FDEQ_GAIN_10 +578 0x4848 //TX_FDEQ_GAIN_11 +579 0x4848 //TX_FDEQ_GAIN_12 +580 0x4848 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0303 //TX_FDEQ_BIN_2 +594 0x0304 //TX_FDEQ_BIN_3 +595 0x0405 //TX_FDEQ_BIN_4 +596 0x0506 //TX_FDEQ_BIN_5 +597 0x0708 //TX_FDEQ_BIN_6 +598 0x090A //TX_FDEQ_BIN_7 +599 0x0B0C //TX_FDEQ_BIN_8 +600 0x0D0E //TX_FDEQ_BIN_9 +601 0x1013 //TX_FDEQ_BIN_10 +602 0x1719 //TX_FDEQ_BIN_11 +603 0x1B1E //TX_FDEQ_BIN_12 +604 0x1E1E //TX_FDEQ_BIN_13 +605 0x1E28 //TX_FDEQ_BIN_14 +606 0x282C //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4868 //TX_PREEQ_GAIN_MIC0_8 +626 0x6860 //TX_PREEQ_GAIN_MIC0_9 +627 0x6048 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0E10 //TX_PREEQ_BIN_MIC0_0 +642 0x1010 //TX_PREEQ_BIN_MIC0_1 +643 0x1010 //TX_PREEQ_BIN_MIC0_2 +644 0x1010 //TX_PREEQ_BIN_MIC0_3 +645 0x1010 //TX_PREEQ_BIN_MIC0_4 +646 0x1010 //TX_PREEQ_BIN_MIC0_5 +647 0x1010 //TX_PREEQ_BIN_MIC0_6 +648 0x1010 //TX_PREEQ_BIN_MIC0_7 +649 0x1010 //TX_PREEQ_BIN_MIC0_8 +650 0x1010 //TX_PREEQ_BIN_MIC0_9 +651 0x1010 //TX_PREEQ_BIN_MIC0_10 +652 0x1010 //TX_PREEQ_BIN_MIC0_11 +653 0x1010 //TX_PREEQ_BIN_MIC0_12 +654 0x1010 //TX_PREEQ_BIN_MIC0_13 +655 0x1010 //TX_PREEQ_BIN_MIC0_14 +656 0x0200 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0E10 //TX_PREEQ_BIN_MIC1_0 +691 0x1010 //TX_PREEQ_BIN_MIC1_1 +692 0x1010 //TX_PREEQ_BIN_MIC1_2 +693 0x1010 //TX_PREEQ_BIN_MIC1_3 +694 0x1010 //TX_PREEQ_BIN_MIC1_4 +695 0x1010 //TX_PREEQ_BIN_MIC1_5 +696 0x1010 //TX_PREEQ_BIN_MIC1_6 +697 0x1010 //TX_PREEQ_BIN_MIC1_7 +698 0x1010 //TX_PREEQ_BIN_MIC1_8 +699 0x1010 //TX_PREEQ_BIN_MIC1_9 +700 0x1010 //TX_PREEQ_BIN_MIC1_10 +701 0x1010 //TX_PREEQ_BIN_MIC1_11 +702 0x1010 //TX_PREEQ_BIN_MIC1_12 +703 0x1010 //TX_PREEQ_BIN_MIC1_13 +704 0x1010 //TX_PREEQ_BIN_MIC1_14 +705 0x0200 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0E10 //TX_PREEQ_BIN_MIC2_0 +740 0x1010 //TX_PREEQ_BIN_MIC2_1 +741 0x1010 //TX_PREEQ_BIN_MIC2_2 +742 0x1010 //TX_PREEQ_BIN_MIC2_3 +743 0x1010 //TX_PREEQ_BIN_MIC2_4 +744 0x1010 //TX_PREEQ_BIN_MIC2_5 +745 0x1010 //TX_PREEQ_BIN_MIC2_6 +746 0x1010 //TX_PREEQ_BIN_MIC2_7 +747 0x1010 //TX_PREEQ_BIN_MIC2_8 +748 0x1010 //TX_PREEQ_BIN_MIC2_9 +749 0x1010 //TX_PREEQ_BIN_MIC2_10 +750 0x1010 //TX_PREEQ_BIN_MIC2_11 +751 0x1010 //TX_PREEQ_BIN_MIC2_12 +752 0x1010 //TX_PREEQ_BIN_MIC2_13 +753 0x1010 //TX_PREEQ_BIN_MIC2_14 +754 0x0200 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x0800 //TX_NND_WEIGHT +765 0x0062 //TX_MIC_CALIBRATION_0 +766 0x0062 //TX_MIC_CALIBRATION_1 +767 0x0062 //TX_MIC_CALIBRATION_2 +768 0x0062 //TX_MIC_CALIBRATION_3 +769 0x0046 //TX_MIC_PWR_BIAS_0 +770 0x0046 //TX_MIC_PWR_BIAS_1 +771 0x0046 //TX_MIC_PWR_BIAS_2 +772 0x0046 //TX_MIC_PWR_BIAS_3 +773 0x000C //TX_GAIN_LIMIT_0 +774 0x000C //TX_GAIN_LIMIT_1 +775 0x000C //TX_GAIN_LIMIT_2 +776 0x000C //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x3000 //TX_TDDRC_ALPHA_UP_01 +784 0x3000 //TX_TDDRC_ALPHA_UP_02 +785 0x3000 //TX_TDDRC_ALPHA_UP_03 +786 0x3000 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x78D6 //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0000 //TX_DEADMIC_SILENCE_TH +817 0x0000 //TX_MIC_DEGRADE_TH +818 0x0000 //TX_DEADMIC_CNT +819 0x0000 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x4848 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0000 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0000 //TX_FILTINDX +854 0x0000 //TX_TDDRC_THRD_0 +855 0x0000 //TX_TDDRC_THRD_1 +856 0x2000 //TX_TDDRC_THRD_2 +857 0x2000 //TX_TDDRC_THRD_3 +858 0x3000 //TX_TDDRC_SLANT_0 +859 0x6E00 //TX_TDDRC_SLANT_1 +860 0x3000 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x0970 //TX_TDDRC_DRC_GAIN +867 0x78D6 //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x0028 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x1000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x0000 //TX_SENDFUNC_REG_MICMUTE +898 0x0000 //TX_SENDFUNC_REG_MICMUTE1 +899 0x0000 //TX_MICMUTE_RATIO_THR +900 0x0000 //TX_MICMUTE_AMP_THR +901 0x0000 //TX_MICMUTE_HPF_IND +902 0x0000 //TX_MICMUTE_LOG_EYR_TH +903 0x0000 //TX_MICMUTE_CVG_TIME +904 0x0000 //TX_MICMUTE_RELEASE_TIME +905 0x0000 //TX_MIC_VOLUME_MIC0MUTE +906 0x0000 //TX_MICMUTE_EPD_OFFSET_0 +907 0x0000 //TX_MICMUTE_FRQ_AEC_L +908 0x0000 //TX_MICMUTE_EAD_THR +909 0x0000 //TX_MICMUTE_LAMBDA_CB_NLE +910 0x0000 //TX_MICMUTE_LAMBDA_RE_EST +911 0x0000 //TX_DTD_THR1_MICMUTE_0 +912 0x0000 //TX_DTD_THR1_MICMUTE_1 +913 0x0000 //TX_DTD_THR1_MICMUTE_2 +914 0x0000 //TX_DTD_THR1_MICMUTE_3 +915 0x0000 //TX_DTD_THR2_MICMUTE_0 +916 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x0000 //TX_MICMUTE_C_POST_FLT +922 0x0000 //TX_MICMUTE_DT_CUT_K +923 0x0000 //TX_MICMUTE_DT_CUT_THR +924 0x0000 //TX_MICMUTE_DT_CUT_K2 +925 0x0000 //TX_MICMUTE_DT_CUT_THR2 +926 0x0000 //TX_MICMUTE_DT2_HOLD_N +927 0x0000 //TX_MICMUTE_RATIODTH_THCUT +928 0x0000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x0000 //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0000 //TX_MICMUTE_C_POST_FLT_MASK +931 0x0000 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0000 //TX_MICMUTE_DT_CUT_K1 +933 0x0000 //TX_MICMUTE_N2_SN_EST +934 0x0000 //TX_MICMUTE_THR_SN_EST_0 +935 0x0000 //TX_MICMUTE_MIN_G_CTRL_0 +936 0x0000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x0000 //TX_MICMUTE_B_POST_FILT_0 +938 0x0000 //TX_MIC1RUB_AMP_THR +939 0x0000 //TX_MIC1MUTE_RATIO_THR +940 0x0000 //TX_MIC1MUTE_AMP_THR +941 0x0000 //TX_MIC1MUTE_CVG_TIME +942 0x0000 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x2064 //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0003 //RX_SAMPLINGFREQ_SIG +3 0x0003 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7FFF //RX_A_HP +12 0x0000 //RX_B_PE +13 0x1800 //RX_THR_PITCH_DET_0 +14 0x1000 //RX_THR_PITCH_DET_1 +15 0x0800 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0400 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x0003 //RX_NS_LVL_CTRL +23 0x9000 //RX_THR_SN_EST +24 0x7CCD //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0000 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x2000 //RX_MIN_G_FP +128 0x0080 //RX_MAX_G_FP +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x2064 //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0003 //RX_SAMPLINGFREQ_SIG +160 0x0003 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7FFF //RX_A_HP +169 0x0000 //RX_B_PE +170 0x1800 //RX_THR_PITCH_DET_0 +171 0x1000 //RX_THR_PITCH_DET_1 +172 0x0800 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0400 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x0003 //RX_NS_LVL_CTRL +180 0x9000 //RX_THR_SN_EST +181 0x7CCD //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0000 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x2000 //RX_MIN_G_FP +285 0x0080 //RX_MAX_G_FP +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME BLUETOOTH-BTNB_NREC-VOICE_GENERIC-FB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0009 //TX_OPERATION_MODE_0 +1 0x0009 //TX_OPERATION_MODE_1 +2 0x0020 //TX_PATCH_REG +3 0x286A //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0001 //TX_NUM_MIC +6 0x0004 //TX_SAMPLINGFREQ_SIG +7 0x0004 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009B //TX_DIST2REF1 +22 0x0000 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0915 //TX_PGA_0 +28 0x0800 //TX_PGA_1 +29 0x0000 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0000 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0001 //TX_MIC_DATA_SRC1 +43 0x0002 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3E00 //TX_DIST2REF_11 +73 0x0000 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0200 //TX_MIC_REFBLK_VOLUME +108 0x0800 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0000 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7E56 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x6800 //TX_THR_PITCH_DET_0 +131 0x6000 //TX_THR_PITCH_DET_1 +132 0x5800 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x001E //TX_TAIL_LENGTH +147 0x0200 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x6000 //TX_EAD_THR +151 0x0400 //TX_THR_RE_EST +152 0x3000 //TX_MIN_EQ_RE_EST_0 +153 0x3000 //TX_MIN_EQ_RE_EST_1 +154 0x4000 //TX_MIN_EQ_RE_EST_2 +155 0x0800 //TX_MIN_EQ_RE_EST_3 +156 0x0800 //TX_MIN_EQ_RE_EST_4 +157 0x0800 //TX_MIN_EQ_RE_EST_5 +158 0x6000 //TX_MIN_EQ_RE_EST_6 +159 0x6000 //TX_MIN_EQ_RE_EST_7 +160 0x6000 //TX_MIN_EQ_RE_EST_8 +161 0x6000 //TX_MIN_EQ_RE_EST_9 +162 0x4000 //TX_MIN_EQ_RE_EST_10 +163 0x4000 //TX_MIN_EQ_RE_EST_11 +164 0x4000 //TX_MIN_EQ_RE_EST_12 +165 0x3000 //TX_LAMBDA_RE_EST +166 0x4000 //TX_LAMBDA_CB_NLE +167 0x3000 //TX_C_POST_FLT +168 0x4500 //TX_GAIN_NP +169 0x00C8 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x03E8 //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x5000 //TX_DTD_THR1_0 +198 0x7000 //TX_DTD_THR1_1 +199 0x7F00 //TX_DTD_THR1_2 +200 0x7FFF //TX_DTD_THR1_3 +201 0x7FFF //TX_DTD_THR1_4 +202 0x7FFF //TX_DTD_THR1_5 +203 0x7FFF //TX_DTD_THR1_6 +204 0x0800 //TX_DTD_THR2_0 +205 0x0800 //TX_DTD_THR2_1 +206 0x0800 //TX_DTD_THR2_2 +207 0x0800 //TX_DTD_THR2_3 +208 0x0800 //TX_DTD_THR2_4 +209 0x0100 //TX_DTD_THR2_5 +210 0x0100 //TX_DTD_THR2_6 +211 0x7FFF //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x03E8 //TX_DT_CUT_K +214 0x0CCD //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x0400 //TX_ADPT_STRICT_L +222 0x0200 //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x0800 //TX_B_POST_FILT_ECHO_L +229 0x7FFF //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x7FFF //TX_B_LESSCUT_RTO_ECHO +232 0x00C0 //TX_EPD_OFFSET_00 +233 0x00C0 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x7FFF //TX_DTD_THR1_7 +238 0x7FFF //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xF700 //TX_THR_SN_EST_0 +243 0xFB00 //TX_THR_SN_EST_1 +244 0xFA00 //TX_THR_SN_EST_2 +245 0xF700 //TX_THR_SN_EST_3 +246 0xFA00 //TX_THR_SN_EST_4 +247 0xF600 //TX_THR_SN_EST_5 +248 0xF600 //TX_THR_SN_EST_6 +249 0xF600 //TX_THR_SN_EST_7 +250 0x0200 //TX_DELTA_THR_SN_EST_0 +251 0x0400 //TX_DELTA_THR_SN_EST_1 +252 0x0300 //TX_DELTA_THR_SN_EST_2 +253 0x0600 //TX_DELTA_THR_SN_EST_3 +254 0x0200 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0200 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x4000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x4000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x2000 //TX_B_POST_FLT_0 +280 0x2000 //TX_B_POST_FLT_1 +281 0x0012 //TX_NS_LVL_CTRL_0 +282 0x0016 //TX_NS_LVL_CTRL_1 +283 0x0016 //TX_NS_LVL_CTRL_2 +284 0x0019 //TX_NS_LVL_CTRL_3 +285 0x0010 //TX_NS_LVL_CTRL_4 +286 0x0010 //TX_NS_LVL_CTRL_5 +287 0x0019 //TX_NS_LVL_CTRL_6 +288 0x0010 //TX_NS_LVL_CTRL_7 +289 0x000C //TX_MIN_GAIN_S_0 +290 0x000C //TX_MIN_GAIN_S_1 +291 0x000C //TX_MIN_GAIN_S_2 +292 0x000F //TX_MIN_GAIN_S_3 +293 0x000C //TX_MIN_GAIN_S_4 +294 0x000C //TX_MIN_GAIN_S_5 +295 0x0011 //TX_MIN_GAIN_S_6 +296 0x000C //TX_MIN_GAIN_S_7 +297 0x7FFF //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7000 //TX_SNRI_SUP_0 +301 0x7000 //TX_SNRI_SUP_1 +302 0x7000 //TX_SNRI_SUP_2 +303 0x6000 //TX_SNRI_SUP_3 +304 0x7FFF //TX_SNRI_SUP_4 +305 0x7FFF //TX_SNRI_SUP_5 +306 0x6000 //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x0016 //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x6000 //TX_A_POST_FILT_S_0 +315 0x6000 //TX_A_POST_FILT_S_1 +316 0x6000 //TX_A_POST_FILT_S_2 +317 0x6000 //TX_A_POST_FILT_S_3 +318 0x6000 //TX_A_POST_FILT_S_4 +319 0x6000 //TX_A_POST_FILT_S_5 +320 0x6000 //TX_A_POST_FILT_S_6 +321 0x6000 //TX_A_POST_FILT_S_7 +322 0x2000 //TX_B_POST_FILT_0 +323 0x4000 //TX_B_POST_FILT_1 +324 0x2000 //TX_B_POST_FILT_2 +325 0x2000 //TX_B_POST_FILT_3 +326 0x2000 //TX_B_POST_FILT_4 +327 0x2000 //TX_B_POST_FILT_5 +328 0x2000 //TX_B_POST_FILT_6 +329 0x2000 //TX_B_POST_FILT_7 +330 0x7FFF //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x7FFF //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7CCD //TX_LAMBDA_PFILT +339 0x7CCD //TX_LAMBDA_PFILT_S_0 +340 0x7CCD //TX_LAMBDA_PFILT_S_1 +341 0x7CCD //TX_LAMBDA_PFILT_S_2 +342 0x7CCD //TX_LAMBDA_PFILT_S_3 +343 0x7CCD //TX_LAMBDA_PFILT_S_4 +344 0x7CCD //TX_LAMBDA_PFILT_S_5 +345 0x7CCD //TX_LAMBDA_PFILT_S_6 +346 0x7CCD //TX_LAMBDA_PFILT_S_7 +347 0x0200 //TX_K_PEPPER +348 0x0500 //TX_A_PEPPER +349 0x1600 //TX_K_PEPPER_HF +350 0x0400 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0800 //TX_DT_BINVAD_TH_0 +354 0x0800 //TX_DT_BINVAD_TH_1 +355 0x0800 //TX_DT_BINVAD_TH_2 +356 0x0800 //TX_DT_BINVAD_TH_3 +357 0x1D4C //TX_DT_BINVAD_ENDF +358 0x0000 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0190 //TX_NDETCT +367 0x0020 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x02A6 //TX_NOISE_TH_1 +371 0x04B0 //TX_NOISE_TH_2 +372 0x3194 //TX_NOISE_TH_3 +373 0x0960 //TX_NOISE_TH_4 +374 0x5555 //TX_NOISE_TH_5 +375 0x3FF4 //TX_NOISE_TH_5_2 +376 0x0001 //TX_NOISE_TH_5_3 +377 0x0000 //TX_NOISE_TH_5_4 +378 0x02BC //TX_NOISE_TH_6 +379 0x0020 //TX_MINENOISE_TH +380 0x4000 //TX_MORENS_TFMASK_TH +381 0xFFEE //TX_DRC_QUIET_FLOOR +382 0x6000 //TX_RATIODTL_CUT_TH +383 0xFFF3 //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x0333 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x0000 //TX_POST_MASK_SUP_HSNE +392 0x0000 //TX_TAIL_DET_TH +393 0x0000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0800 //TX_SUPHIGH_TH +396 0x00C8 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x0800 //TX_C_POST_FLT_MASK +399 0x0005 //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0002 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x0020 //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x2900 //TX_MIN_G_CTRL_SSNS +409 0x0800 //TX_METAL_RTO_THR +410 0x4848 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x4000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x01E0 //TX_NOR_OFF_THR +498 0x7C00 //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0xD333 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x6000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0x0000 //TX_DEREVERB_LF_MU +515 0x0000 //TX_DEREVERB_HF_MU +516 0x0000 //TX_DEREVERB_DELAY +517 0x0000 //TX_DEREVERB_COEF_LEN +518 0x0000 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x0000 //TX_GSC_RTOH_TH +523 0x0000 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0020 //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4848 //TX_FDEQ_GAIN_5 +573 0x4848 //TX_FDEQ_GAIN_6 +574 0x4848 //TX_FDEQ_GAIN_7 +575 0x4848 //TX_FDEQ_GAIN_8 +576 0x4848 //TX_FDEQ_GAIN_9 +577 0x4848 //TX_FDEQ_GAIN_10 +578 0x4848 //TX_FDEQ_GAIN_11 +579 0x4848 //TX_FDEQ_GAIN_12 +580 0x4848 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0304 //TX_FDEQ_BIN_2 +594 0x0405 //TX_FDEQ_BIN_3 +595 0x0607 //TX_FDEQ_BIN_4 +596 0x0809 //TX_FDEQ_BIN_5 +597 0x0A0B //TX_FDEQ_BIN_6 +598 0x0C0D //TX_FDEQ_BIN_7 +599 0x0E0F //TX_FDEQ_BIN_8 +600 0x1011 //TX_FDEQ_BIN_9 +601 0x1214 //TX_FDEQ_BIN_10 +602 0x1618 //TX_FDEQ_BIN_11 +603 0x1C1C //TX_FDEQ_BIN_12 +604 0x2020 //TX_FDEQ_BIN_13 +605 0x2020 //TX_FDEQ_BIN_14 +606 0x2011 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4848 //TX_PREEQ_GAIN_MIC0_8 +626 0x4848 //TX_PREEQ_GAIN_MIC0_9 +627 0x4848 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0E10 //TX_PREEQ_BIN_MIC0_0 +642 0x1010 //TX_PREEQ_BIN_MIC0_1 +643 0x1010 //TX_PREEQ_BIN_MIC0_2 +644 0x1010 //TX_PREEQ_BIN_MIC0_3 +645 0x1010 //TX_PREEQ_BIN_MIC0_4 +646 0x1010 //TX_PREEQ_BIN_MIC0_5 +647 0x1010 //TX_PREEQ_BIN_MIC0_6 +648 0x1010 //TX_PREEQ_BIN_MIC0_7 +649 0x1010 //TX_PREEQ_BIN_MIC0_8 +650 0x1010 //TX_PREEQ_BIN_MIC0_9 +651 0x1010 //TX_PREEQ_BIN_MIC0_10 +652 0x1010 //TX_PREEQ_BIN_MIC0_11 +653 0x1010 //TX_PREEQ_BIN_MIC0_12 +654 0x1010 //TX_PREEQ_BIN_MIC0_13 +655 0x1010 //TX_PREEQ_BIN_MIC0_14 +656 0x0200 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0E10 //TX_PREEQ_BIN_MIC1_0 +691 0x1010 //TX_PREEQ_BIN_MIC1_1 +692 0x1010 //TX_PREEQ_BIN_MIC1_2 +693 0x1010 //TX_PREEQ_BIN_MIC1_3 +694 0x1010 //TX_PREEQ_BIN_MIC1_4 +695 0x1010 //TX_PREEQ_BIN_MIC1_5 +696 0x1010 //TX_PREEQ_BIN_MIC1_6 +697 0x1010 //TX_PREEQ_BIN_MIC1_7 +698 0x1010 //TX_PREEQ_BIN_MIC1_8 +699 0x1010 //TX_PREEQ_BIN_MIC1_9 +700 0x1010 //TX_PREEQ_BIN_MIC1_10 +701 0x1010 //TX_PREEQ_BIN_MIC1_11 +702 0x1010 //TX_PREEQ_BIN_MIC1_12 +703 0x1010 //TX_PREEQ_BIN_MIC1_13 +704 0x1010 //TX_PREEQ_BIN_MIC1_14 +705 0x0200 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0E10 //TX_PREEQ_BIN_MIC2_0 +740 0x1010 //TX_PREEQ_BIN_MIC2_1 +741 0x1010 //TX_PREEQ_BIN_MIC2_2 +742 0x1010 //TX_PREEQ_BIN_MIC2_3 +743 0x1010 //TX_PREEQ_BIN_MIC2_4 +744 0x1010 //TX_PREEQ_BIN_MIC2_5 +745 0x1010 //TX_PREEQ_BIN_MIC2_6 +746 0x1010 //TX_PREEQ_BIN_MIC2_7 +747 0x1010 //TX_PREEQ_BIN_MIC2_8 +748 0x1010 //TX_PREEQ_BIN_MIC2_9 +749 0x1010 //TX_PREEQ_BIN_MIC2_10 +750 0x1010 //TX_PREEQ_BIN_MIC2_11 +751 0x1010 //TX_PREEQ_BIN_MIC2_12 +752 0x1010 //TX_PREEQ_BIN_MIC2_13 +753 0x1010 //TX_PREEQ_BIN_MIC2_14 +754 0x0200 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x2000 //TX_NND_WEIGHT +765 0x0060 //TX_MIC_CALIBRATION_0 +766 0x0060 //TX_MIC_CALIBRATION_1 +767 0x0070 //TX_MIC_CALIBRATION_2 +768 0x0070 //TX_MIC_CALIBRATION_3 +769 0x0050 //TX_MIC_PWR_BIAS_0 +770 0x0040 //TX_MIC_PWR_BIAS_1 +771 0x0040 //TX_MIC_PWR_BIAS_2 +772 0x0040 //TX_MIC_PWR_BIAS_3 +773 0x0009 //TX_GAIN_LIMIT_0 +774 0x000F //TX_GAIN_LIMIT_1 +775 0x000F //TX_GAIN_LIMIT_2 +776 0x000F //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x0C00 //TX_TDDRC_ALPHA_UP_01 +784 0x0C00 //TX_TDDRC_ALPHA_UP_02 +785 0x0C00 //TX_TDDRC_ALPHA_UP_03 +786 0x0C00 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x7FFF //TX_TDDRC_TD_DRC_LIMIT +792 0x2000 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0000 //TX_DEADMIC_SILENCE_TH +817 0x0000 //TX_MIC_DEGRADE_TH +818 0x0000 //TX_DEADMIC_CNT +819 0x0000 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x4848 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0000 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0002 //TX_FILTINDX +854 0x0001 //TX_TDDRC_THRD_0 +855 0x0001 //TX_TDDRC_THRD_1 +856 0x1900 //TX_TDDRC_THRD_2 +857 0x1900 //TX_TDDRC_THRD_3 +858 0x3000 //TX_TDDRC_SLANT_0 +859 0x7B00 //TX_TDDRC_SLANT_1 +860 0x0C00 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x0200 //TX_TDDRC_DRC_GAIN +867 0x7FFF //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x0028 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x7000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x0000 //TX_SENDFUNC_REG_MICMUTE +898 0x0000 //TX_SENDFUNC_REG_MICMUTE1 +899 0x0000 //TX_MICMUTE_RATIO_THR +900 0x0000 //TX_MICMUTE_AMP_THR +901 0x0000 //TX_MICMUTE_HPF_IND +902 0x0000 //TX_MICMUTE_LOG_EYR_TH +903 0x0000 //TX_MICMUTE_CVG_TIME +904 0x0000 //TX_MICMUTE_RELEASE_TIME +905 0x0000 //TX_MIC_VOLUME_MIC0MUTE +906 0x0000 //TX_MICMUTE_EPD_OFFSET_0 +907 0x0000 //TX_MICMUTE_FRQ_AEC_L +908 0x0000 //TX_MICMUTE_EAD_THR +909 0x0000 //TX_MICMUTE_LAMBDA_CB_NLE +910 0x0000 //TX_MICMUTE_LAMBDA_RE_EST +911 0x0000 //TX_DTD_THR1_MICMUTE_0 +912 0x0000 //TX_DTD_THR1_MICMUTE_1 +913 0x0000 //TX_DTD_THR1_MICMUTE_2 +914 0x0000 //TX_DTD_THR1_MICMUTE_3 +915 0x0000 //TX_DTD_THR2_MICMUTE_0 +916 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x0000 //TX_MICMUTE_C_POST_FLT +922 0x0000 //TX_MICMUTE_DT_CUT_K +923 0x0000 //TX_MICMUTE_DT_CUT_THR +924 0x0000 //TX_MICMUTE_DT_CUT_K2 +925 0x0000 //TX_MICMUTE_DT_CUT_THR2 +926 0x0000 //TX_MICMUTE_DT2_HOLD_N +927 0x0000 //TX_MICMUTE_RATIODTH_THCUT +928 0x0000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x0000 //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0000 //TX_MICMUTE_C_POST_FLT_MASK +931 0x0000 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0000 //TX_MICMUTE_DT_CUT_K1 +933 0x0000 //TX_MICMUTE_N2_SN_EST +934 0x0000 //TX_MICMUTE_THR_SN_EST_0 +935 0x0000 //TX_MICMUTE_MIN_G_CTRL_0 +936 0x0000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x0000 //TX_MICMUTE_B_POST_FILT_0 +938 0x0000 //TX_MIC1RUB_AMP_THR +939 0x0000 //TX_MIC1MUTE_RATIO_THR +940 0x0000 //TX_MIC1MUTE_AMP_THR +941 0x0000 //TX_MIC1MUTE_CVG_TIME +942 0x0000 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x2064 //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0004 //RX_SAMPLINGFREQ_SIG +3 0x0004 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7FFF //RX_A_HP +12 0x4000 //RX_B_PE +13 0x7800 //RX_THR_PITCH_DET_0 +14 0x7000 //RX_THR_PITCH_DET_1 +15 0x6000 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0500 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x000A //RX_NS_LVL_CTRL +23 0xF600 //RX_THR_SN_EST +24 0x7000 //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0000 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x2000 //RX_MIN_G_FP +128 0x0080 //RX_MAX_G_FP +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x0064 //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0004 //RX_SAMPLINGFREQ_SIG +160 0x0004 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7FFF //RX_A_HP +169 0x4000 //RX_B_PE +170 0x7800 //RX_THR_PITCH_DET_0 +171 0x7000 //RX_THR_PITCH_DET_1 +172 0x6000 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0500 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x000A //RX_NS_LVL_CTRL +180 0xF600 //RX_THR_SN_EST +181 0x7000 //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0000 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x2000 //RX_MIN_G_FP +285 0x0080 //RX_MAX_G_FP +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME BLUETOOTH-BTWB-VOICE_GENERIC-NB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0008 //TX_OPERATION_MODE_0 +1 0x0008 //TX_OPERATION_MODE_1 +2 0x0033 //TX_PATCH_REG +3 0x0240 //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0001 //TX_NUM_MIC +6 0x0000 //TX_SAMPLINGFREQ_SIG +7 0x0000 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009B //TX_DIST2REF1 +22 0x0000 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0A13 //TX_PGA_0 +28 0x0800 //TX_PGA_1 +29 0x0800 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0000 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0001 //TX_MIC_DATA_SRC1 +43 0x0002 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3E00 //TX_DIST2REF_11 +73 0x0000 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0200 //TX_MIC_REFBLK_VOLUME +108 0x0800 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0000 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7D83 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x6800 //TX_THR_PITCH_DET_0 +131 0x6000 //TX_THR_PITCH_DET_1 +132 0x5800 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x001E //TX_TAIL_LENGTH +147 0x0080 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x7000 //TX_EAD_THR +151 0x0800 //TX_THR_RE_EST +152 0x0800 //TX_MIN_EQ_RE_EST_0 +153 0x0800 //TX_MIN_EQ_RE_EST_1 +154 0x0800 //TX_MIN_EQ_RE_EST_2 +155 0x0800 //TX_MIN_EQ_RE_EST_3 +156 0x0800 //TX_MIN_EQ_RE_EST_4 +157 0x0800 //TX_MIN_EQ_RE_EST_5 +158 0x0800 //TX_MIN_EQ_RE_EST_6 +159 0x0800 //TX_MIN_EQ_RE_EST_7 +160 0x0800 //TX_MIN_EQ_RE_EST_8 +161 0x0800 //TX_MIN_EQ_RE_EST_9 +162 0x0800 //TX_MIN_EQ_RE_EST_10 +163 0x0800 //TX_MIN_EQ_RE_EST_11 +164 0x0800 //TX_MIN_EQ_RE_EST_12 +165 0x4000 //TX_LAMBDA_RE_EST +166 0x2000 //TX_LAMBDA_CB_NLE +167 0x6000 //TX_C_POST_FLT +168 0x7000 //TX_GAIN_NP +169 0x00C8 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x03E8 //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x7800 //TX_DTD_THR1_0 +198 0x7000 //TX_DTD_THR1_1 +199 0x7FFF //TX_DTD_THR1_2 +200 0x7FFF //TX_DTD_THR1_3 +201 0x7FFF //TX_DTD_THR1_4 +202 0x7FFF //TX_DTD_THR1_5 +203 0x7FFF //TX_DTD_THR1_6 +204 0x7FFF //TX_DTD_THR2_0 +205 0x7FFF //TX_DTD_THR2_1 +206 0x7FFF //TX_DTD_THR2_2 +207 0x7FFF //TX_DTD_THR2_3 +208 0x7FFF //TX_DTD_THR2_4 +209 0x7FFF //TX_DTD_THR2_5 +210 0x7FFF //TX_DTD_THR2_6 +211 0x1000 //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x0BB8 //TX_DT_CUT_K +214 0x0CCD //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x0400 //TX_ADPT_STRICT_L +222 0x0200 //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x0800 //TX_B_POST_FILT_ECHO_L +229 0x7FFF //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x7FFF //TX_B_LESSCUT_RTO_ECHO +232 0x0019 //TX_EPD_OFFSET_00 +233 0x0019 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x7FFF //TX_DTD_THR1_7 +238 0x7FFF //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xF400 //TX_THR_SN_EST_0 +243 0xF400 //TX_THR_SN_EST_1 +244 0xF600 //TX_THR_SN_EST_2 +245 0xF400 //TX_THR_SN_EST_3 +246 0xF400 //TX_THR_SN_EST_4 +247 0xF400 //TX_THR_SN_EST_5 +248 0xF400 //TX_THR_SN_EST_6 +249 0xF600 //TX_THR_SN_EST_7 +250 0x0000 //TX_DELTA_THR_SN_EST_0 +251 0x0200 //TX_DELTA_THR_SN_EST_1 +252 0x0200 //TX_DELTA_THR_SN_EST_2 +253 0x0200 //TX_DELTA_THR_SN_EST_3 +254 0x0200 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0000 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x6000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x6000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x1000 //TX_B_POST_FLT_0 +280 0x1000 //TX_B_POST_FLT_1 +281 0x000F //TX_NS_LVL_CTRL_0 +282 0x0011 //TX_NS_LVL_CTRL_1 +283 0x000F //TX_NS_LVL_CTRL_2 +284 0x000F //TX_NS_LVL_CTRL_3 +285 0x000F //TX_NS_LVL_CTRL_4 +286 0x000F //TX_NS_LVL_CTRL_5 +287 0x000F //TX_NS_LVL_CTRL_6 +288 0x0011 //TX_NS_LVL_CTRL_7 +289 0x000C //TX_MIN_GAIN_S_0 +290 0x000F //TX_MIN_GAIN_S_1 +291 0x000C //TX_MIN_GAIN_S_2 +292 0x000C //TX_MIN_GAIN_S_3 +293 0x000C //TX_MIN_GAIN_S_4 +294 0x000C //TX_MIN_GAIN_S_5 +295 0x000C //TX_MIN_GAIN_S_6 +296 0x000F //TX_MIN_GAIN_S_7 +297 0x7FFF //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x7FFF //TX_SNRI_SUP_1 +302 0x7FFF //TX_SNRI_SUP_2 +303 0x7FFF //TX_SNRI_SUP_3 +304 0x7FFF //TX_SNRI_SUP_4 +305 0x7FFF //TX_SNRI_SUP_5 +306 0x7FFF //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x000E //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x4000 //TX_A_POST_FILT_S_0 +315 0x5000 //TX_A_POST_FILT_S_1 +316 0x5000 //TX_A_POST_FILT_S_2 +317 0x5000 //TX_A_POST_FILT_S_3 +318 0x5000 //TX_A_POST_FILT_S_4 +319 0x5000 //TX_A_POST_FILT_S_5 +320 0x4000 //TX_A_POST_FILT_S_6 +321 0x5000 //TX_A_POST_FILT_S_7 +322 0x1000 //TX_B_POST_FILT_0 +323 0x1000 //TX_B_POST_FILT_1 +324 0x1000 //TX_B_POST_FILT_2 +325 0x1000 //TX_B_POST_FILT_3 +326 0x1000 //TX_B_POST_FILT_4 +327 0x1000 //TX_B_POST_FILT_5 +328 0x1000 //TX_B_POST_FILT_6 +329 0x1000 //TX_B_POST_FILT_7 +330 0x7FFF //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x7FFF //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7CCD //TX_LAMBDA_PFILT +339 0x7B00 //TX_LAMBDA_PFILT_S_0 +340 0x7B00 //TX_LAMBDA_PFILT_S_1 +341 0x7B00 //TX_LAMBDA_PFILT_S_2 +342 0x7B00 //TX_LAMBDA_PFILT_S_3 +343 0x7B00 //TX_LAMBDA_PFILT_S_4 +344 0x7B00 //TX_LAMBDA_PFILT_S_5 +345 0x7B00 //TX_LAMBDA_PFILT_S_6 +346 0x7B00 //TX_LAMBDA_PFILT_S_7 +347 0x0200 //TX_K_PEPPER +348 0x0800 //TX_A_PEPPER +349 0x1EAA //TX_K_PEPPER_HF +350 0x0800 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0800 //TX_DT_BINVAD_TH_0 +354 0x0800 //TX_DT_BINVAD_TH_1 +355 0x0800 //TX_DT_BINVAD_TH_2 +356 0x0800 //TX_DT_BINVAD_TH_3 +357 0x1D4C //TX_DT_BINVAD_ENDF +358 0x0000 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0000 //TX_NOISEDET +366 0x0190 //TX_NDETCT +367 0x0050 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x07D0 //TX_NOISE_TH_1 +371 0x00C8 //TX_NOISE_TH_2 +372 0x3A98 //TX_NOISE_TH_3 +373 0x0FA0 //TX_NOISE_TH_4 +374 0x157C //TX_NOISE_TH_5 +375 0x7FFF //TX_NOISE_TH_5_2 +376 0x7FFF //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x044C //TX_NOISE_TH_6 +379 0x0014 //TX_MINENOISE_TH +380 0x4000 //TX_MORENS_TFMASK_TH +381 0xFFEE //TX_DRC_QUIET_FLOOR +382 0x6000 //TX_RATIODTL_CUT_TH +383 0xFFF3 //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x0333 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x0000 //TX_POST_MASK_SUP_HSNE +392 0x0000 //TX_TAIL_DET_TH +393 0x0000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0800 //TX_SUPHIGH_TH +396 0x00C8 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x0800 //TX_C_POST_FLT_MASK +399 0x0005 //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0002 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x0014 //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x7FFF //TX_MIN_G_CTRL_SSNS +409 0x0000 //TX_METAL_RTO_THR +410 0x0000 //TX_NS_FP_K_METAL +411 0x7FFF //TX_NOISEDET_BOOST_TH +412 0x0000 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x4000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x0230 //TX_NOR_OFF_THR +498 0x0CCD //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0xD333 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x6000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0x0000 //TX_DEREVERB_LF_MU +515 0x0000 //TX_DEREVERB_HF_MU +516 0x0000 //TX_DEREVERB_DELAY +517 0x0000 //TX_DEREVERB_COEF_LEN +518 0x0000 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x0000 //TX_GSC_RTOH_TH +523 0x0000 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x001C //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4848 //TX_FDEQ_GAIN_5 +573 0x4242 //TX_FDEQ_GAIN_6 +574 0x423C //TX_FDEQ_GAIN_7 +575 0x3C3C //TX_FDEQ_GAIN_8 +576 0x3434 //TX_FDEQ_GAIN_9 +577 0x4848 //TX_FDEQ_GAIN_10 +578 0x4848 //TX_FDEQ_GAIN_11 +579 0x4848 //TX_FDEQ_GAIN_12 +580 0x4848 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0303 //TX_FDEQ_BIN_2 +594 0x0304 //TX_FDEQ_BIN_3 +595 0x0405 //TX_FDEQ_BIN_4 +596 0x0506 //TX_FDEQ_BIN_5 +597 0x0708 //TX_FDEQ_BIN_6 +598 0x090A //TX_FDEQ_BIN_7 +599 0x0B0C //TX_FDEQ_BIN_8 +600 0x0D0E //TX_FDEQ_BIN_9 +601 0x0E0F //TX_FDEQ_BIN_10 +602 0x0F10 //TX_FDEQ_BIN_11 +603 0x1011 //TX_FDEQ_BIN_12 +604 0x1104 //TX_FDEQ_BIN_13 +605 0x0000 //TX_FDEQ_BIN_14 +606 0x0000 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4848 //TX_PREEQ_GAIN_MIC0_8 +626 0x4848 //TX_PREEQ_GAIN_MIC0_9 +627 0x4848 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0608 //TX_PREEQ_BIN_MIC0_0 +642 0x0808 //TX_PREEQ_BIN_MIC0_1 +643 0x0808 //TX_PREEQ_BIN_MIC0_2 +644 0x0808 //TX_PREEQ_BIN_MIC0_3 +645 0x0808 //TX_PREEQ_BIN_MIC0_4 +646 0x0808 //TX_PREEQ_BIN_MIC0_5 +647 0x0808 //TX_PREEQ_BIN_MIC0_6 +648 0x0808 //TX_PREEQ_BIN_MIC0_7 +649 0x0808 //TX_PREEQ_BIN_MIC0_8 +650 0x0808 //TX_PREEQ_BIN_MIC0_9 +651 0x0808 //TX_PREEQ_BIN_MIC0_10 +652 0x0808 //TX_PREEQ_BIN_MIC0_11 +653 0x0808 //TX_PREEQ_BIN_MIC0_12 +654 0x0808 //TX_PREEQ_BIN_MIC0_13 +655 0x0808 //TX_PREEQ_BIN_MIC0_14 +656 0x0200 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0608 //TX_PREEQ_BIN_MIC1_0 +691 0x0808 //TX_PREEQ_BIN_MIC1_1 +692 0x0808 //TX_PREEQ_BIN_MIC1_2 +693 0x0808 //TX_PREEQ_BIN_MIC1_3 +694 0x0808 //TX_PREEQ_BIN_MIC1_4 +695 0x0808 //TX_PREEQ_BIN_MIC1_5 +696 0x0808 //TX_PREEQ_BIN_MIC1_6 +697 0x0808 //TX_PREEQ_BIN_MIC1_7 +698 0x0808 //TX_PREEQ_BIN_MIC1_8 +699 0x0808 //TX_PREEQ_BIN_MIC1_9 +700 0x0808 //TX_PREEQ_BIN_MIC1_10 +701 0x0808 //TX_PREEQ_BIN_MIC1_11 +702 0x0808 //TX_PREEQ_BIN_MIC1_12 +703 0x0808 //TX_PREEQ_BIN_MIC1_13 +704 0x0808 //TX_PREEQ_BIN_MIC1_14 +705 0x0200 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0608 //TX_PREEQ_BIN_MIC2_0 +740 0x0808 //TX_PREEQ_BIN_MIC2_1 +741 0x0808 //TX_PREEQ_BIN_MIC2_2 +742 0x0808 //TX_PREEQ_BIN_MIC2_3 +743 0x0808 //TX_PREEQ_BIN_MIC2_4 +744 0x0808 //TX_PREEQ_BIN_MIC2_5 +745 0x0808 //TX_PREEQ_BIN_MIC2_6 +746 0x0808 //TX_PREEQ_BIN_MIC2_7 +747 0x0808 //TX_PREEQ_BIN_MIC2_8 +748 0x0808 //TX_PREEQ_BIN_MIC2_9 +749 0x0808 //TX_PREEQ_BIN_MIC2_10 +750 0x0808 //TX_PREEQ_BIN_MIC2_11 +751 0x0808 //TX_PREEQ_BIN_MIC2_12 +752 0x0808 //TX_PREEQ_BIN_MIC2_13 +753 0x0808 //TX_PREEQ_BIN_MIC2_14 +754 0x0200 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x0800 //TX_NND_WEIGHT +765 0x0062 //TX_MIC_CALIBRATION_0 +766 0x0062 //TX_MIC_CALIBRATION_1 +767 0x0062 //TX_MIC_CALIBRATION_2 +768 0x0062 //TX_MIC_CALIBRATION_3 +769 0x0046 //TX_MIC_PWR_BIAS_0 +770 0x0046 //TX_MIC_PWR_BIAS_1 +771 0x0046 //TX_MIC_PWR_BIAS_2 +772 0x0046 //TX_MIC_PWR_BIAS_3 +773 0x000C //TX_GAIN_LIMIT_0 +774 0x000C //TX_GAIN_LIMIT_1 +775 0x000C //TX_GAIN_LIMIT_2 +776 0x000C //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x1000 //TX_TDDRC_ALPHA_UP_01 +784 0x1000 //TX_TDDRC_ALPHA_UP_02 +785 0x1000 //TX_TDDRC_ALPHA_UP_03 +786 0x1000 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x7FFF //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0000 //TX_DEADMIC_SILENCE_TH +817 0x0000 //TX_MIC_DEGRADE_TH +818 0x0000 //TX_DEADMIC_CNT +819 0x0000 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x0000 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0000 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0000 //TX_FILTINDX +854 0x0000 //TX_TDDRC_THRD_0 +855 0x0000 //TX_TDDRC_THRD_1 +856 0x2000 //TX_TDDRC_THRD_2 +857 0x2000 //TX_TDDRC_THRD_3 +858 0x3000 //TX_TDDRC_SLANT_0 +859 0x6E00 //TX_TDDRC_SLANT_1 +860 0x1000 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x07F2 //TX_TDDRC_DRC_GAIN +867 0x7FFF //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x00C8 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x7FFF //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x0000 //TX_SENDFUNC_REG_MICMUTE +898 0x0000 //TX_SENDFUNC_REG_MICMUTE1 +899 0x0000 //TX_MICMUTE_RATIO_THR +900 0x0000 //TX_MICMUTE_AMP_THR +901 0x0000 //TX_MICMUTE_HPF_IND +902 0x0000 //TX_MICMUTE_LOG_EYR_TH +903 0x0000 //TX_MICMUTE_CVG_TIME +904 0x0000 //TX_MICMUTE_RELEASE_TIME +905 0x0000 //TX_MIC_VOLUME_MIC0MUTE +906 0x0000 //TX_MICMUTE_EPD_OFFSET_0 +907 0x0000 //TX_MICMUTE_FRQ_AEC_L +908 0x0000 //TX_MICMUTE_EAD_THR +909 0x0000 //TX_MICMUTE_LAMBDA_CB_NLE +910 0x0000 //TX_MICMUTE_LAMBDA_RE_EST +911 0x0000 //TX_DTD_THR1_MICMUTE_0 +912 0x0000 //TX_DTD_THR1_MICMUTE_1 +913 0x0000 //TX_DTD_THR1_MICMUTE_2 +914 0x0000 //TX_DTD_THR1_MICMUTE_3 +915 0x0000 //TX_DTD_THR2_MICMUTE_0 +916 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x0000 //TX_MICMUTE_C_POST_FLT +922 0x0000 //TX_MICMUTE_DT_CUT_K +923 0x0000 //TX_MICMUTE_DT_CUT_THR +924 0x0000 //TX_MICMUTE_DT_CUT_K2 +925 0x0000 //TX_MICMUTE_DT_CUT_THR2 +926 0x0000 //TX_MICMUTE_DT2_HOLD_N +927 0x0000 //TX_MICMUTE_RATIODTH_THCUT +928 0x0000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x0000 //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0000 //TX_MICMUTE_C_POST_FLT_MASK +931 0x0000 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0000 //TX_MICMUTE_DT_CUT_K1 +933 0x0000 //TX_MICMUTE_N2_SN_EST +934 0x0000 //TX_MICMUTE_THR_SN_EST_0 +935 0x0000 //TX_MICMUTE_MIN_G_CTRL_0 +936 0x0000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x0000 //TX_MICMUTE_B_POST_FILT_0 +938 0x0000 //TX_MIC1RUB_AMP_THR +939 0x0000 //TX_MIC1MUTE_RATIO_THR +940 0x0000 //TX_MIC1MUTE_AMP_THR +941 0x0000 //TX_MIC1MUTE_CVG_TIME +942 0x0000 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x206C //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0000 //RX_SAMPLINGFREQ_SIG +3 0x0000 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7FFF //RX_A_HP +12 0x0000 //RX_B_PE +13 0x3800 //RX_THR_PITCH_DET_0 +14 0x3000 //RX_THR_PITCH_DET_1 +15 0x2800 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0600 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x0010 //RX_NS_LVL_CTRL +23 0xF800 //RX_THR_SN_EST +24 0x7CCD //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4444 //RX_FDEQ_GAIN_6 +46 0x4040 //RX_FDEQ_GAIN_7 +47 0x4040 //RX_FDEQ_GAIN_8 +48 0x4040 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0000 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x017F //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x2000 //RX_MIN_G_FP +128 0x0080 //RX_MAX_G_FP +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x017F //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4444 //RX_FDEQ_GAIN_6 +46 0x4040 //RX_FDEQ_GAIN_7 +47 0x4040 //RX_FDEQ_GAIN_8 +48 0x4040 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x017F //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4444 //RX_FDEQ_GAIN_6 +46 0x4040 //RX_FDEQ_GAIN_7 +47 0x4040 //RX_FDEQ_GAIN_8 +48 0x4040 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x017F //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4444 //RX_FDEQ_GAIN_6 +46 0x4040 //RX_FDEQ_GAIN_7 +47 0x4040 //RX_FDEQ_GAIN_8 +48 0x4040 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x017F //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4444 //RX_FDEQ_GAIN_6 +46 0x4040 //RX_FDEQ_GAIN_7 +47 0x4040 //RX_FDEQ_GAIN_8 +48 0x4040 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x017F //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4444 //RX_FDEQ_GAIN_6 +46 0x4040 //RX_FDEQ_GAIN_7 +47 0x4040 //RX_FDEQ_GAIN_8 +48 0x4040 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x017F //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4444 //RX_FDEQ_GAIN_6 +46 0x4040 //RX_FDEQ_GAIN_7 +47 0x4040 //RX_FDEQ_GAIN_8 +48 0x4040 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x017F //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4444 //RX_FDEQ_GAIN_6 +46 0x4040 //RX_FDEQ_GAIN_7 +47 0x4040 //RX_FDEQ_GAIN_8 +48 0x4040 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x206C //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0000 //RX_SAMPLINGFREQ_SIG +160 0x0000 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7FFF //RX_A_HP +169 0x0000 //RX_B_PE +170 0x3800 //RX_THR_PITCH_DET_0 +171 0x3000 //RX_THR_PITCH_DET_1 +172 0x2800 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0600 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x0010 //RX_NS_LVL_CTRL +180 0xF800 //RX_THR_SN_EST +181 0x7CCD //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4444 //RX_FDEQ_GAIN_6 +203 0x4040 //RX_FDEQ_GAIN_7 +204 0x4040 //RX_FDEQ_GAIN_8 +205 0x4040 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0000 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x017F //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x2000 //RX_MIN_G_FP +285 0x0080 //RX_MAX_G_FP +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x017F //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4444 //RX_FDEQ_GAIN_6 +203 0x4040 //RX_FDEQ_GAIN_7 +204 0x4040 //RX_FDEQ_GAIN_8 +205 0x4040 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x017F //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4444 //RX_FDEQ_GAIN_6 +203 0x4040 //RX_FDEQ_GAIN_7 +204 0x4040 //RX_FDEQ_GAIN_8 +205 0x4040 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x017F //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4444 //RX_FDEQ_GAIN_6 +203 0x4040 //RX_FDEQ_GAIN_7 +204 0x4040 //RX_FDEQ_GAIN_8 +205 0x4040 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x017F //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4444 //RX_FDEQ_GAIN_6 +203 0x4040 //RX_FDEQ_GAIN_7 +204 0x4040 //RX_FDEQ_GAIN_8 +205 0x4040 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x017F //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4444 //RX_FDEQ_GAIN_6 +203 0x4040 //RX_FDEQ_GAIN_7 +204 0x4040 //RX_FDEQ_GAIN_8 +205 0x4040 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x017F //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4444 //RX_FDEQ_GAIN_6 +203 0x4040 //RX_FDEQ_GAIN_7 +204 0x4040 //RX_FDEQ_GAIN_8 +205 0x4040 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x017F //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4444 //RX_FDEQ_GAIN_6 +203 0x4040 //RX_FDEQ_GAIN_7 +204 0x4040 //RX_FDEQ_GAIN_8 +205 0x4040 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME BLUETOOTH-BTWB-VOICE_GENERIC-WB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0008 //TX_OPERATION_MODE_0 +1 0x0008 //TX_OPERATION_MODE_1 +2 0x0033 //TX_PATCH_REG +3 0x0240 //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0001 //TX_NUM_MIC +6 0x0001 //TX_SAMPLINGFREQ_SIG +7 0x0001 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009B //TX_DIST2REF1 +22 0x0000 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0915 //TX_PGA_0 +28 0x0800 //TX_PGA_1 +29 0x0800 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0000 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0001 //TX_MIC_DATA_SRC1 +43 0x0002 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3E00 //TX_DIST2REF_11 +73 0x0000 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0200 //TX_MIC_REFBLK_VOLUME +108 0x0800 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0000 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7D83 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x6800 //TX_THR_PITCH_DET_0 +131 0x6000 //TX_THR_PITCH_DET_1 +132 0x5800 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x001E //TX_TAIL_LENGTH +147 0x0080 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x7000 //TX_EAD_THR +151 0x0800 //TX_THR_RE_EST +152 0x0800 //TX_MIN_EQ_RE_EST_0 +153 0x0800 //TX_MIN_EQ_RE_EST_1 +154 0x0800 //TX_MIN_EQ_RE_EST_2 +155 0x0800 //TX_MIN_EQ_RE_EST_3 +156 0x0800 //TX_MIN_EQ_RE_EST_4 +157 0x0800 //TX_MIN_EQ_RE_EST_5 +158 0x0800 //TX_MIN_EQ_RE_EST_6 +159 0x0800 //TX_MIN_EQ_RE_EST_7 +160 0x0800 //TX_MIN_EQ_RE_EST_8 +161 0x0800 //TX_MIN_EQ_RE_EST_9 +162 0x0800 //TX_MIN_EQ_RE_EST_10 +163 0x0800 //TX_MIN_EQ_RE_EST_11 +164 0x0800 //TX_MIN_EQ_RE_EST_12 +165 0x4000 //TX_LAMBDA_RE_EST +166 0x2000 //TX_LAMBDA_CB_NLE +167 0x6000 //TX_C_POST_FLT +168 0x7000 //TX_GAIN_NP +169 0x00C8 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x03E8 //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x7800 //TX_DTD_THR1_0 +198 0x7000 //TX_DTD_THR1_1 +199 0x7FFF //TX_DTD_THR1_2 +200 0x7FFF //TX_DTD_THR1_3 +201 0x7FFF //TX_DTD_THR1_4 +202 0x7FFF //TX_DTD_THR1_5 +203 0x7FFF //TX_DTD_THR1_6 +204 0x7FFF //TX_DTD_THR2_0 +205 0x7FFF //TX_DTD_THR2_1 +206 0x7FFF //TX_DTD_THR2_2 +207 0x7FFF //TX_DTD_THR2_3 +208 0x7FFF //TX_DTD_THR2_4 +209 0x7FFF //TX_DTD_THR2_5 +210 0x7FFF //TX_DTD_THR2_6 +211 0x1000 //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x0BB8 //TX_DT_CUT_K +214 0x0CCD //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x0400 //TX_ADPT_STRICT_L +222 0x0200 //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x0800 //TX_B_POST_FILT_ECHO_L +229 0x7FFF //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x7FFF //TX_B_LESSCUT_RTO_ECHO +232 0x0019 //TX_EPD_OFFSET_00 +233 0x0019 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x7FFF //TX_DTD_THR1_7 +238 0x7FFF //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xF400 //TX_THR_SN_EST_0 +243 0xF400 //TX_THR_SN_EST_1 +244 0xF600 //TX_THR_SN_EST_2 +245 0xF400 //TX_THR_SN_EST_3 +246 0xF400 //TX_THR_SN_EST_4 +247 0xF400 //TX_THR_SN_EST_5 +248 0xF400 //TX_THR_SN_EST_6 +249 0xF600 //TX_THR_SN_EST_7 +250 0x0000 //TX_DELTA_THR_SN_EST_0 +251 0x0200 //TX_DELTA_THR_SN_EST_1 +252 0x0200 //TX_DELTA_THR_SN_EST_2 +253 0x0200 //TX_DELTA_THR_SN_EST_3 +254 0x0200 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0000 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x6000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x6000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x1000 //TX_B_POST_FLT_0 +280 0x1000 //TX_B_POST_FLT_1 +281 0x000F //TX_NS_LVL_CTRL_0 +282 0x0011 //TX_NS_LVL_CTRL_1 +283 0x000F //TX_NS_LVL_CTRL_2 +284 0x000F //TX_NS_LVL_CTRL_3 +285 0x000F //TX_NS_LVL_CTRL_4 +286 0x000F //TX_NS_LVL_CTRL_5 +287 0x000F //TX_NS_LVL_CTRL_6 +288 0x0011 //TX_NS_LVL_CTRL_7 +289 0x000C //TX_MIN_GAIN_S_0 +290 0x000F //TX_MIN_GAIN_S_1 +291 0x000C //TX_MIN_GAIN_S_2 +292 0x000C //TX_MIN_GAIN_S_3 +293 0x000C //TX_MIN_GAIN_S_4 +294 0x000C //TX_MIN_GAIN_S_5 +295 0x000C //TX_MIN_GAIN_S_6 +296 0x000F //TX_MIN_GAIN_S_7 +297 0x7FFF //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x7FFF //TX_SNRI_SUP_1 +302 0x7FFF //TX_SNRI_SUP_2 +303 0x7FFF //TX_SNRI_SUP_3 +304 0x7FFF //TX_SNRI_SUP_4 +305 0x7FFF //TX_SNRI_SUP_5 +306 0x7FFF //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x000E //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x4000 //TX_A_POST_FILT_S_0 +315 0x5000 //TX_A_POST_FILT_S_1 +316 0x5000 //TX_A_POST_FILT_S_2 +317 0x5000 //TX_A_POST_FILT_S_3 +318 0x5000 //TX_A_POST_FILT_S_4 +319 0x5000 //TX_A_POST_FILT_S_5 +320 0x4000 //TX_A_POST_FILT_S_6 +321 0x5000 //TX_A_POST_FILT_S_7 +322 0x1000 //TX_B_POST_FILT_0 +323 0x1000 //TX_B_POST_FILT_1 +324 0x1000 //TX_B_POST_FILT_2 +325 0x1000 //TX_B_POST_FILT_3 +326 0x1000 //TX_B_POST_FILT_4 +327 0x1000 //TX_B_POST_FILT_5 +328 0x1000 //TX_B_POST_FILT_6 +329 0x1000 //TX_B_POST_FILT_7 +330 0x7FFF //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x7FFF //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7CCD //TX_LAMBDA_PFILT +339 0x7B00 //TX_LAMBDA_PFILT_S_0 +340 0x7B00 //TX_LAMBDA_PFILT_S_1 +341 0x7B00 //TX_LAMBDA_PFILT_S_2 +342 0x7B00 //TX_LAMBDA_PFILT_S_3 +343 0x7B00 //TX_LAMBDA_PFILT_S_4 +344 0x7B00 //TX_LAMBDA_PFILT_S_5 +345 0x7B00 //TX_LAMBDA_PFILT_S_6 +346 0x7B00 //TX_LAMBDA_PFILT_S_7 +347 0x0200 //TX_K_PEPPER +348 0x0800 //TX_A_PEPPER +349 0x1EAA //TX_K_PEPPER_HF +350 0x0800 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0800 //TX_DT_BINVAD_TH_0 +354 0x0800 //TX_DT_BINVAD_TH_1 +355 0x0800 //TX_DT_BINVAD_TH_2 +356 0x0800 //TX_DT_BINVAD_TH_3 +357 0x1D4C //TX_DT_BINVAD_ENDF +358 0x0000 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0000 //TX_NOISEDET +366 0x0190 //TX_NDETCT +367 0x0050 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x07D0 //TX_NOISE_TH_1 +371 0x00C8 //TX_NOISE_TH_2 +372 0x3A98 //TX_NOISE_TH_3 +373 0x0FA0 //TX_NOISE_TH_4 +374 0x157C //TX_NOISE_TH_5 +375 0x7FFF //TX_NOISE_TH_5_2 +376 0x7FFF //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x044C //TX_NOISE_TH_6 +379 0x0014 //TX_MINENOISE_TH +380 0x4000 //TX_MORENS_TFMASK_TH +381 0xFFEE //TX_DRC_QUIET_FLOOR +382 0x6000 //TX_RATIODTL_CUT_TH +383 0xFFF3 //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x0333 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x0000 //TX_POST_MASK_SUP_HSNE +392 0x0000 //TX_TAIL_DET_TH +393 0x0000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0800 //TX_SUPHIGH_TH +396 0x00C8 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x0800 //TX_C_POST_FLT_MASK +399 0x0005 //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0002 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x0014 //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x7FFF //TX_MIN_G_CTRL_SSNS +409 0x0000 //TX_METAL_RTO_THR +410 0x0000 //TX_NS_FP_K_METAL +411 0x7FFF //TX_NOISEDET_BOOST_TH +412 0x0000 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x4000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x0230 //TX_NOR_OFF_THR +498 0x0CCD //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0xD333 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x6000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0x0000 //TX_DEREVERB_LF_MU +515 0x0000 //TX_DEREVERB_HF_MU +516 0x0000 //TX_DEREVERB_DELAY +517 0x0000 //TX_DEREVERB_COEF_LEN +518 0x0000 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x0000 //TX_GSC_RTOH_TH +523 0x0000 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x001C //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4848 //TX_FDEQ_GAIN_5 +573 0x4848 //TX_FDEQ_GAIN_6 +574 0x4444 //TX_FDEQ_GAIN_7 +575 0x4444 //TX_FDEQ_GAIN_8 +576 0x3C3C //TX_FDEQ_GAIN_9 +577 0x3C3C //TX_FDEQ_GAIN_10 +578 0x3C3C //TX_FDEQ_GAIN_11 +579 0x3C30 //TX_FDEQ_GAIN_12 +580 0x3030 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0303 //TX_FDEQ_BIN_2 +594 0x0304 //TX_FDEQ_BIN_3 +595 0x0405 //TX_FDEQ_BIN_4 +596 0x0506 //TX_FDEQ_BIN_5 +597 0x0708 //TX_FDEQ_BIN_6 +598 0x090A //TX_FDEQ_BIN_7 +599 0x0B0C //TX_FDEQ_BIN_8 +600 0x0D0E //TX_FDEQ_BIN_9 +601 0x0E0F //TX_FDEQ_BIN_10 +602 0x0F10 //TX_FDEQ_BIN_11 +603 0x1011 //TX_FDEQ_BIN_12 +604 0x1112 //TX_FDEQ_BIN_13 +605 0x0000 //TX_FDEQ_BIN_14 +606 0x0000 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4848 //TX_PREEQ_GAIN_MIC0_8 +626 0x4848 //TX_PREEQ_GAIN_MIC0_9 +627 0x4848 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0608 //TX_PREEQ_BIN_MIC0_0 +642 0x0808 //TX_PREEQ_BIN_MIC0_1 +643 0x0808 //TX_PREEQ_BIN_MIC0_2 +644 0x0808 //TX_PREEQ_BIN_MIC0_3 +645 0x0808 //TX_PREEQ_BIN_MIC0_4 +646 0x0808 //TX_PREEQ_BIN_MIC0_5 +647 0x0808 //TX_PREEQ_BIN_MIC0_6 +648 0x0808 //TX_PREEQ_BIN_MIC0_7 +649 0x0808 //TX_PREEQ_BIN_MIC0_8 +650 0x0808 //TX_PREEQ_BIN_MIC0_9 +651 0x0808 //TX_PREEQ_BIN_MIC0_10 +652 0x0808 //TX_PREEQ_BIN_MIC0_11 +653 0x0808 //TX_PREEQ_BIN_MIC0_12 +654 0x0808 //TX_PREEQ_BIN_MIC0_13 +655 0x0808 //TX_PREEQ_BIN_MIC0_14 +656 0x0200 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0608 //TX_PREEQ_BIN_MIC1_0 +691 0x0808 //TX_PREEQ_BIN_MIC1_1 +692 0x0808 //TX_PREEQ_BIN_MIC1_2 +693 0x0808 //TX_PREEQ_BIN_MIC1_3 +694 0x0808 //TX_PREEQ_BIN_MIC1_4 +695 0x0808 //TX_PREEQ_BIN_MIC1_5 +696 0x0808 //TX_PREEQ_BIN_MIC1_6 +697 0x0808 //TX_PREEQ_BIN_MIC1_7 +698 0x0808 //TX_PREEQ_BIN_MIC1_8 +699 0x0808 //TX_PREEQ_BIN_MIC1_9 +700 0x0808 //TX_PREEQ_BIN_MIC1_10 +701 0x0808 //TX_PREEQ_BIN_MIC1_11 +702 0x0808 //TX_PREEQ_BIN_MIC1_12 +703 0x0808 //TX_PREEQ_BIN_MIC1_13 +704 0x0808 //TX_PREEQ_BIN_MIC1_14 +705 0x0200 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0608 //TX_PREEQ_BIN_MIC2_0 +740 0x0808 //TX_PREEQ_BIN_MIC2_1 +741 0x0808 //TX_PREEQ_BIN_MIC2_2 +742 0x0808 //TX_PREEQ_BIN_MIC2_3 +743 0x0808 //TX_PREEQ_BIN_MIC2_4 +744 0x0808 //TX_PREEQ_BIN_MIC2_5 +745 0x0808 //TX_PREEQ_BIN_MIC2_6 +746 0x0808 //TX_PREEQ_BIN_MIC2_7 +747 0x0808 //TX_PREEQ_BIN_MIC2_8 +748 0x0808 //TX_PREEQ_BIN_MIC2_9 +749 0x0808 //TX_PREEQ_BIN_MIC2_10 +750 0x0808 //TX_PREEQ_BIN_MIC2_11 +751 0x0808 //TX_PREEQ_BIN_MIC2_12 +752 0x0808 //TX_PREEQ_BIN_MIC2_13 +753 0x0808 //TX_PREEQ_BIN_MIC2_14 +754 0x0200 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x0800 //TX_NND_WEIGHT +765 0x0062 //TX_MIC_CALIBRATION_0 +766 0x0062 //TX_MIC_CALIBRATION_1 +767 0x0062 //TX_MIC_CALIBRATION_2 +768 0x0062 //TX_MIC_CALIBRATION_3 +769 0x0046 //TX_MIC_PWR_BIAS_0 +770 0x0046 //TX_MIC_PWR_BIAS_1 +771 0x0046 //TX_MIC_PWR_BIAS_2 +772 0x0046 //TX_MIC_PWR_BIAS_3 +773 0x000C //TX_GAIN_LIMIT_0 +774 0x000C //TX_GAIN_LIMIT_1 +775 0x000C //TX_GAIN_LIMIT_2 +776 0x000C //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x1000 //TX_TDDRC_ALPHA_UP_01 +784 0x1000 //TX_TDDRC_ALPHA_UP_02 +785 0x1000 //TX_TDDRC_ALPHA_UP_03 +786 0x1000 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x7FFF //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0000 //TX_DEADMIC_SILENCE_TH +817 0x0000 //TX_MIC_DEGRADE_TH +818 0x0000 //TX_DEADMIC_CNT +819 0x0000 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x0000 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0000 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0000 //TX_FILTINDX +854 0x0000 //TX_TDDRC_THRD_0 +855 0x0000 //TX_TDDRC_THRD_1 +856 0x2000 //TX_TDDRC_THRD_2 +857 0x2000 //TX_TDDRC_THRD_3 +858 0x3000 //TX_TDDRC_SLANT_0 +859 0x6E00 //TX_TDDRC_SLANT_1 +860 0x1000 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x07F2 //TX_TDDRC_DRC_GAIN +867 0x7FFF //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x00C8 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x7FFF //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x0000 //TX_SENDFUNC_REG_MICMUTE +898 0x0000 //TX_SENDFUNC_REG_MICMUTE1 +899 0x0000 //TX_MICMUTE_RATIO_THR +900 0x0000 //TX_MICMUTE_AMP_THR +901 0x0000 //TX_MICMUTE_HPF_IND +902 0x0000 //TX_MICMUTE_LOG_EYR_TH +903 0x0000 //TX_MICMUTE_CVG_TIME +904 0x0000 //TX_MICMUTE_RELEASE_TIME +905 0x0000 //TX_MIC_VOLUME_MIC0MUTE +906 0x0000 //TX_MICMUTE_EPD_OFFSET_0 +907 0x0000 //TX_MICMUTE_FRQ_AEC_L +908 0x0000 //TX_MICMUTE_EAD_THR +909 0x0000 //TX_MICMUTE_LAMBDA_CB_NLE +910 0x0000 //TX_MICMUTE_LAMBDA_RE_EST +911 0x0000 //TX_DTD_THR1_MICMUTE_0 +912 0x0000 //TX_DTD_THR1_MICMUTE_1 +913 0x0000 //TX_DTD_THR1_MICMUTE_2 +914 0x0000 //TX_DTD_THR1_MICMUTE_3 +915 0x0000 //TX_DTD_THR2_MICMUTE_0 +916 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x0000 //TX_MICMUTE_C_POST_FLT +922 0x0000 //TX_MICMUTE_DT_CUT_K +923 0x0000 //TX_MICMUTE_DT_CUT_THR +924 0x0000 //TX_MICMUTE_DT_CUT_K2 +925 0x0000 //TX_MICMUTE_DT_CUT_THR2 +926 0x0000 //TX_MICMUTE_DT2_HOLD_N +927 0x0000 //TX_MICMUTE_RATIODTH_THCUT +928 0x0000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x0000 //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0000 //TX_MICMUTE_C_POST_FLT_MASK +931 0x0000 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0000 //TX_MICMUTE_DT_CUT_K1 +933 0x0000 //TX_MICMUTE_N2_SN_EST +934 0x0000 //TX_MICMUTE_THR_SN_EST_0 +935 0x0000 //TX_MICMUTE_MIN_G_CTRL_0 +936 0x0000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x0000 //TX_MICMUTE_B_POST_FILT_0 +938 0x0000 //TX_MIC1RUB_AMP_THR +939 0x0000 //TX_MIC1MUTE_RATIO_THR +940 0x0000 //TX_MIC1MUTE_AMP_THR +941 0x0000 //TX_MIC1MUTE_CVG_TIME +942 0x0000 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x206C //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0001 //RX_SAMPLINGFREQ_SIG +3 0x0001 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7FFF //RX_A_HP +12 0x4000 //RX_B_PE +13 0x3800 //RX_THR_PITCH_DET_0 +14 0x3000 //RX_THR_PITCH_DET_1 +15 0x2800 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0600 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x0010 //RX_NS_LVL_CTRL +23 0xF800 //RX_THR_SN_EST +24 0x7CCD //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x3C3C //RX_FDEQ_GAIN_9 +49 0x3C3C //RX_FDEQ_GAIN_10 +50 0x3838 //RX_FDEQ_GAIN_11 +51 0x3838 //RX_FDEQ_GAIN_12 +52 0x3030 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1112 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0000 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7E70 //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x2000 //RX_MIN_G_FP +128 0x0080 //RX_MAX_G_FP +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7E70 //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x3C3C //RX_FDEQ_GAIN_9 +49 0x3C3C //RX_FDEQ_GAIN_10 +50 0x3838 //RX_FDEQ_GAIN_11 +51 0x3838 //RX_FDEQ_GAIN_12 +52 0x3030 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1112 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7E70 //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x3C3C //RX_FDEQ_GAIN_9 +49 0x3C3C //RX_FDEQ_GAIN_10 +50 0x3838 //RX_FDEQ_GAIN_11 +51 0x3838 //RX_FDEQ_GAIN_12 +52 0x3030 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1112 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7E70 //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x3C3C //RX_FDEQ_GAIN_9 +49 0x3C3C //RX_FDEQ_GAIN_10 +50 0x3838 //RX_FDEQ_GAIN_11 +51 0x3838 //RX_FDEQ_GAIN_12 +52 0x3030 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1112 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7E70 //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x3C3C //RX_FDEQ_GAIN_9 +49 0x3C3C //RX_FDEQ_GAIN_10 +50 0x3838 //RX_FDEQ_GAIN_11 +51 0x3838 //RX_FDEQ_GAIN_12 +52 0x3030 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1112 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7E70 //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x3C3C //RX_FDEQ_GAIN_9 +49 0x3C3C //RX_FDEQ_GAIN_10 +50 0x3838 //RX_FDEQ_GAIN_11 +51 0x3838 //RX_FDEQ_GAIN_12 +52 0x3030 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1112 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7E70 //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x3C3C //RX_FDEQ_GAIN_9 +49 0x3C3C //RX_FDEQ_GAIN_10 +50 0x3838 //RX_FDEQ_GAIN_11 +51 0x3838 //RX_FDEQ_GAIN_12 +52 0x3030 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1112 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7E70 //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x3C3C //RX_FDEQ_GAIN_9 +49 0x3C3C //RX_FDEQ_GAIN_10 +50 0x3838 //RX_FDEQ_GAIN_11 +51 0x3838 //RX_FDEQ_GAIN_12 +52 0x3030 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1112 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x206C //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0001 //RX_SAMPLINGFREQ_SIG +160 0x0001 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7FFF //RX_A_HP +169 0x4000 //RX_B_PE +170 0x3800 //RX_THR_PITCH_DET_0 +171 0x3000 //RX_THR_PITCH_DET_1 +172 0x2800 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0600 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x0010 //RX_NS_LVL_CTRL +180 0xF800 //RX_THR_SN_EST +181 0x7CCD //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x3C3C //RX_FDEQ_GAIN_9 +206 0x3C3C //RX_FDEQ_GAIN_10 +207 0x3838 //RX_FDEQ_GAIN_11 +208 0x3838 //RX_FDEQ_GAIN_12 +209 0x3030 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1112 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0000 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7E70 //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x2000 //RX_MIN_G_FP +285 0x0080 //RX_MAX_G_FP +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7E70 //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x3C3C //RX_FDEQ_GAIN_9 +206 0x3C3C //RX_FDEQ_GAIN_10 +207 0x3838 //RX_FDEQ_GAIN_11 +208 0x3838 //RX_FDEQ_GAIN_12 +209 0x3030 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1112 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7E70 //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x3C3C //RX_FDEQ_GAIN_9 +206 0x3C3C //RX_FDEQ_GAIN_10 +207 0x3838 //RX_FDEQ_GAIN_11 +208 0x3838 //RX_FDEQ_GAIN_12 +209 0x3030 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1112 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7E70 //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x3C3C //RX_FDEQ_GAIN_9 +206 0x3C3C //RX_FDEQ_GAIN_10 +207 0x3838 //RX_FDEQ_GAIN_11 +208 0x3838 //RX_FDEQ_GAIN_12 +209 0x3030 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1112 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7E70 //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x3C3C //RX_FDEQ_GAIN_9 +206 0x3C3C //RX_FDEQ_GAIN_10 +207 0x3838 //RX_FDEQ_GAIN_11 +208 0x3838 //RX_FDEQ_GAIN_12 +209 0x3030 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1112 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7E70 //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x3C3C //RX_FDEQ_GAIN_9 +206 0x3C3C //RX_FDEQ_GAIN_10 +207 0x3838 //RX_FDEQ_GAIN_11 +208 0x3838 //RX_FDEQ_GAIN_12 +209 0x3030 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1112 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7E70 //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x3C3C //RX_FDEQ_GAIN_9 +206 0x3C3C //RX_FDEQ_GAIN_10 +207 0x3838 //RX_FDEQ_GAIN_11 +208 0x3838 //RX_FDEQ_GAIN_12 +209 0x3030 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1112 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7E70 //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x3C3C //RX_FDEQ_GAIN_9 +206 0x3C3C //RX_FDEQ_GAIN_10 +207 0x3838 //RX_FDEQ_GAIN_11 +208 0x3838 //RX_FDEQ_GAIN_12 +209 0x3030 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1112 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME BLUETOOTH-BTWB-VOICE_GENERIC-SWB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0001 //TX_OPERATION_MODE_0 +1 0x0001 //TX_OPERATION_MODE_1 +2 0x0033 //TX_PATCH_REG +3 0x0200 //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0001 //TX_NUM_MIC +6 0x0003 //TX_SAMPLINGFREQ_SIG +7 0x0003 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009B //TX_DIST2REF1 +22 0x0000 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0915 //TX_PGA_0 +28 0x0800 //TX_PGA_1 +29 0x0800 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0000 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0001 //TX_MIC_DATA_SRC1 +43 0x0002 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3E00 //TX_DIST2REF_11 +73 0x0000 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0200 //TX_MIC_REFBLK_VOLUME +108 0x0800 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0000 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7EFF //TX_A_HP +129 0x4000 //TX_B_PE +130 0x1800 //TX_THR_PITCH_DET_0 +131 0x1000 //TX_THR_PITCH_DET_1 +132 0x0800 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x001E //TX_TAIL_LENGTH +147 0x0080 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x7000 //TX_EAD_THR +151 0x0800 //TX_THR_RE_EST +152 0x0800 //TX_MIN_EQ_RE_EST_0 +153 0x0800 //TX_MIN_EQ_RE_EST_1 +154 0x0800 //TX_MIN_EQ_RE_EST_2 +155 0x0800 //TX_MIN_EQ_RE_EST_3 +156 0x0800 //TX_MIN_EQ_RE_EST_4 +157 0x0800 //TX_MIN_EQ_RE_EST_5 +158 0x0800 //TX_MIN_EQ_RE_EST_6 +159 0x0800 //TX_MIN_EQ_RE_EST_7 +160 0x0800 //TX_MIN_EQ_RE_EST_8 +161 0x0800 //TX_MIN_EQ_RE_EST_9 +162 0x0800 //TX_MIN_EQ_RE_EST_10 +163 0x0800 //TX_MIN_EQ_RE_EST_11 +164 0x0800 //TX_MIN_EQ_RE_EST_12 +165 0x4000 //TX_LAMBDA_RE_EST +166 0x2000 //TX_LAMBDA_CB_NLE +167 0x6000 //TX_C_POST_FLT +168 0x7000 //TX_GAIN_NP +169 0x00C8 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x03E8 //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x7800 //TX_DTD_THR1_0 +198 0x7000 //TX_DTD_THR1_1 +199 0x7FFF //TX_DTD_THR1_2 +200 0x7FFF //TX_DTD_THR1_3 +201 0x7FFF //TX_DTD_THR1_4 +202 0x7FFF //TX_DTD_THR1_5 +203 0x7FFF //TX_DTD_THR1_6 +204 0x7FFF //TX_DTD_THR2_0 +205 0x7FFF //TX_DTD_THR2_1 +206 0x7FFF //TX_DTD_THR2_2 +207 0x7FFF //TX_DTD_THR2_3 +208 0x7FFF //TX_DTD_THR2_4 +209 0x7FFF //TX_DTD_THR2_5 +210 0x7FFF //TX_DTD_THR2_6 +211 0x1000 //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x0BB8 //TX_DT_CUT_K +214 0x0CCD //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x0400 //TX_ADPT_STRICT_L +222 0x0200 //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x0800 //TX_B_POST_FILT_ECHO_L +229 0x7FFF //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x7FFF //TX_B_LESSCUT_RTO_ECHO +232 0x00F0 //TX_EPD_OFFSET_00 +233 0x00F0 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x7FFF //TX_DTD_THR1_7 +238 0x7FFF //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xF400 //TX_THR_SN_EST_0 +243 0xF400 //TX_THR_SN_EST_1 +244 0xF600 //TX_THR_SN_EST_2 +245 0xF400 //TX_THR_SN_EST_3 +246 0xF400 //TX_THR_SN_EST_4 +247 0xF400 //TX_THR_SN_EST_5 +248 0xF400 //TX_THR_SN_EST_6 +249 0xF600 //TX_THR_SN_EST_7 +250 0x0000 //TX_DELTA_THR_SN_EST_0 +251 0x0200 //TX_DELTA_THR_SN_EST_1 +252 0x0200 //TX_DELTA_THR_SN_EST_2 +253 0x0200 //TX_DELTA_THR_SN_EST_3 +254 0x0200 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0000 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x6000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x6000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x1000 //TX_B_POST_FLT_0 +280 0x1000 //TX_B_POST_FLT_1 +281 0x000B //TX_NS_LVL_CTRL_0 +282 0x0011 //TX_NS_LVL_CTRL_1 +283 0x000F //TX_NS_LVL_CTRL_2 +284 0x000F //TX_NS_LVL_CTRL_3 +285 0x000F //TX_NS_LVL_CTRL_4 +286 0x000F //TX_NS_LVL_CTRL_5 +287 0x000F //TX_NS_LVL_CTRL_6 +288 0x0011 //TX_NS_LVL_CTRL_7 +289 0x000C //TX_MIN_GAIN_S_0 +290 0x000F //TX_MIN_GAIN_S_1 +291 0x000C //TX_MIN_GAIN_S_2 +292 0x000C //TX_MIN_GAIN_S_3 +293 0x000C //TX_MIN_GAIN_S_4 +294 0x000C //TX_MIN_GAIN_S_5 +295 0x000C //TX_MIN_GAIN_S_6 +296 0x000F //TX_MIN_GAIN_S_7 +297 0x7FFF //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x7FFF //TX_SNRI_SUP_1 +302 0x7FFF //TX_SNRI_SUP_2 +303 0x7FFF //TX_SNRI_SUP_3 +304 0x7FFF //TX_SNRI_SUP_4 +305 0x7FFF //TX_SNRI_SUP_5 +306 0x7FFF //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x000E //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x2000 //TX_A_POST_FILT_S_0 +315 0x5000 //TX_A_POST_FILT_S_1 +316 0x5000 //TX_A_POST_FILT_S_2 +317 0x5000 //TX_A_POST_FILT_S_3 +318 0x5000 //TX_A_POST_FILT_S_4 +319 0x5000 //TX_A_POST_FILT_S_5 +320 0x4000 //TX_A_POST_FILT_S_6 +321 0x5000 //TX_A_POST_FILT_S_7 +322 0x1000 //TX_B_POST_FILT_0 +323 0x1000 //TX_B_POST_FILT_1 +324 0x1000 //TX_B_POST_FILT_2 +325 0x1000 //TX_B_POST_FILT_3 +326 0x1000 //TX_B_POST_FILT_4 +327 0x1000 //TX_B_POST_FILT_5 +328 0x1000 //TX_B_POST_FILT_6 +329 0x1000 //TX_B_POST_FILT_7 +330 0x7FFF //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x7FFF //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7900 //TX_LAMBDA_PFILT +339 0x7B00 //TX_LAMBDA_PFILT_S_0 +340 0x7B00 //TX_LAMBDA_PFILT_S_1 +341 0x7B00 //TX_LAMBDA_PFILT_S_2 +342 0x7B00 //TX_LAMBDA_PFILT_S_3 +343 0x7B00 //TX_LAMBDA_PFILT_S_4 +344 0x7B00 //TX_LAMBDA_PFILT_S_5 +345 0x7B00 //TX_LAMBDA_PFILT_S_6 +346 0x7B00 //TX_LAMBDA_PFILT_S_7 +347 0x0000 //TX_K_PEPPER +348 0x0800 //TX_A_PEPPER +349 0x1EAA //TX_K_PEPPER_HF +350 0x0800 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0800 //TX_DT_BINVAD_TH_0 +354 0x0800 //TX_DT_BINVAD_TH_1 +355 0x0800 //TX_DT_BINVAD_TH_2 +356 0x0800 //TX_DT_BINVAD_TH_3 +357 0x1D4C //TX_DT_BINVAD_ENDF +358 0x0000 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0000 //TX_NOISEDET +366 0x0190 //TX_NDETCT +367 0x0050 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x07D0 //TX_NOISE_TH_1 +371 0x00C8 //TX_NOISE_TH_2 +372 0x3A98 //TX_NOISE_TH_3 +373 0x0FA0 //TX_NOISE_TH_4 +374 0x157C //TX_NOISE_TH_5 +375 0x7FFF //TX_NOISE_TH_5_2 +376 0x7FFF //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x044C //TX_NOISE_TH_6 +379 0x0014 //TX_MINENOISE_TH +380 0x4000 //TX_MORENS_TFMASK_TH +381 0xFFEE //TX_DRC_QUIET_FLOOR +382 0x6000 //TX_RATIODTL_CUT_TH +383 0xFFF3 //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x0333 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x0000 //TX_POST_MASK_SUP_HSNE +392 0x0000 //TX_TAIL_DET_TH +393 0x0000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0800 //TX_SUPHIGH_TH +396 0x00C8 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x0800 //TX_C_POST_FLT_MASK +399 0x0005 //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0002 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x0014 //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x2900 //TX_MIN_G_CTRL_SSNS +409 0x0800 //TX_METAL_RTO_THR +410 0x4848 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x4000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x01E0 //TX_NOR_OFF_THR +498 0x7C00 //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0xD333 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x6000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0x0000 //TX_DEREVERB_LF_MU +515 0x0000 //TX_DEREVERB_HF_MU +516 0x0000 //TX_DEREVERB_DELAY +517 0x0000 //TX_DEREVERB_COEF_LEN +518 0x0000 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x0000 //TX_GSC_RTOH_TH +523 0x0000 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0020 //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4848 //TX_FDEQ_GAIN_5 +573 0x4848 //TX_FDEQ_GAIN_6 +574 0x4848 //TX_FDEQ_GAIN_7 +575 0x4848 //TX_FDEQ_GAIN_8 +576 0x4848 //TX_FDEQ_GAIN_9 +577 0x4848 //TX_FDEQ_GAIN_10 +578 0x4848 //TX_FDEQ_GAIN_11 +579 0x4848 //TX_FDEQ_GAIN_12 +580 0x4848 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0303 //TX_FDEQ_BIN_2 +594 0x0304 //TX_FDEQ_BIN_3 +595 0x0405 //TX_FDEQ_BIN_4 +596 0x0506 //TX_FDEQ_BIN_5 +597 0x0708 //TX_FDEQ_BIN_6 +598 0x090A //TX_FDEQ_BIN_7 +599 0x0B0C //TX_FDEQ_BIN_8 +600 0x0D0E //TX_FDEQ_BIN_9 +601 0x1013 //TX_FDEQ_BIN_10 +602 0x1719 //TX_FDEQ_BIN_11 +603 0x1B1E //TX_FDEQ_BIN_12 +604 0x1E1E //TX_FDEQ_BIN_13 +605 0x1E28 //TX_FDEQ_BIN_14 +606 0x282C //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4868 //TX_PREEQ_GAIN_MIC0_8 +626 0x6860 //TX_PREEQ_GAIN_MIC0_9 +627 0x6048 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0E10 //TX_PREEQ_BIN_MIC0_0 +642 0x1010 //TX_PREEQ_BIN_MIC0_1 +643 0x1010 //TX_PREEQ_BIN_MIC0_2 +644 0x1010 //TX_PREEQ_BIN_MIC0_3 +645 0x1010 //TX_PREEQ_BIN_MIC0_4 +646 0x1010 //TX_PREEQ_BIN_MIC0_5 +647 0x1010 //TX_PREEQ_BIN_MIC0_6 +648 0x1010 //TX_PREEQ_BIN_MIC0_7 +649 0x1010 //TX_PREEQ_BIN_MIC0_8 +650 0x1010 //TX_PREEQ_BIN_MIC0_9 +651 0x1010 //TX_PREEQ_BIN_MIC0_10 +652 0x1010 //TX_PREEQ_BIN_MIC0_11 +653 0x1010 //TX_PREEQ_BIN_MIC0_12 +654 0x1010 //TX_PREEQ_BIN_MIC0_13 +655 0x1010 //TX_PREEQ_BIN_MIC0_14 +656 0x0200 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0E10 //TX_PREEQ_BIN_MIC1_0 +691 0x1010 //TX_PREEQ_BIN_MIC1_1 +692 0x1010 //TX_PREEQ_BIN_MIC1_2 +693 0x1010 //TX_PREEQ_BIN_MIC1_3 +694 0x1010 //TX_PREEQ_BIN_MIC1_4 +695 0x1010 //TX_PREEQ_BIN_MIC1_5 +696 0x1010 //TX_PREEQ_BIN_MIC1_6 +697 0x1010 //TX_PREEQ_BIN_MIC1_7 +698 0x1010 //TX_PREEQ_BIN_MIC1_8 +699 0x1010 //TX_PREEQ_BIN_MIC1_9 +700 0x1010 //TX_PREEQ_BIN_MIC1_10 +701 0x1010 //TX_PREEQ_BIN_MIC1_11 +702 0x1010 //TX_PREEQ_BIN_MIC1_12 +703 0x1010 //TX_PREEQ_BIN_MIC1_13 +704 0x1010 //TX_PREEQ_BIN_MIC1_14 +705 0x0200 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0E10 //TX_PREEQ_BIN_MIC2_0 +740 0x1010 //TX_PREEQ_BIN_MIC2_1 +741 0x1010 //TX_PREEQ_BIN_MIC2_2 +742 0x1010 //TX_PREEQ_BIN_MIC2_3 +743 0x1010 //TX_PREEQ_BIN_MIC2_4 +744 0x1010 //TX_PREEQ_BIN_MIC2_5 +745 0x1010 //TX_PREEQ_BIN_MIC2_6 +746 0x1010 //TX_PREEQ_BIN_MIC2_7 +747 0x1010 //TX_PREEQ_BIN_MIC2_8 +748 0x1010 //TX_PREEQ_BIN_MIC2_9 +749 0x1010 //TX_PREEQ_BIN_MIC2_10 +750 0x1010 //TX_PREEQ_BIN_MIC2_11 +751 0x1010 //TX_PREEQ_BIN_MIC2_12 +752 0x1010 //TX_PREEQ_BIN_MIC2_13 +753 0x1010 //TX_PREEQ_BIN_MIC2_14 +754 0x0200 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x0800 //TX_NND_WEIGHT +765 0x0062 //TX_MIC_CALIBRATION_0 +766 0x0062 //TX_MIC_CALIBRATION_1 +767 0x0062 //TX_MIC_CALIBRATION_2 +768 0x0062 //TX_MIC_CALIBRATION_3 +769 0x0046 //TX_MIC_PWR_BIAS_0 +770 0x0046 //TX_MIC_PWR_BIAS_1 +771 0x0046 //TX_MIC_PWR_BIAS_2 +772 0x0046 //TX_MIC_PWR_BIAS_3 +773 0x000C //TX_GAIN_LIMIT_0 +774 0x000C //TX_GAIN_LIMIT_1 +775 0x000C //TX_GAIN_LIMIT_2 +776 0x000C //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x3000 //TX_TDDRC_ALPHA_UP_01 +784 0x3000 //TX_TDDRC_ALPHA_UP_02 +785 0x3000 //TX_TDDRC_ALPHA_UP_03 +786 0x3000 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x78D6 //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0000 //TX_DEADMIC_SILENCE_TH +817 0x0000 //TX_MIC_DEGRADE_TH +818 0x0000 //TX_DEADMIC_CNT +819 0x0000 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x4848 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0000 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0000 //TX_FILTINDX +854 0x0000 //TX_TDDRC_THRD_0 +855 0x0000 //TX_TDDRC_THRD_1 +856 0x2000 //TX_TDDRC_THRD_2 +857 0x2000 //TX_TDDRC_THRD_3 +858 0x3000 //TX_TDDRC_SLANT_0 +859 0x6E00 //TX_TDDRC_SLANT_1 +860 0x3000 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x0970 //TX_TDDRC_DRC_GAIN +867 0x78D6 //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x0028 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x1000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x0000 //TX_SENDFUNC_REG_MICMUTE +898 0x0000 //TX_SENDFUNC_REG_MICMUTE1 +899 0x0000 //TX_MICMUTE_RATIO_THR +900 0x0000 //TX_MICMUTE_AMP_THR +901 0x0000 //TX_MICMUTE_HPF_IND +902 0x0000 //TX_MICMUTE_LOG_EYR_TH +903 0x0000 //TX_MICMUTE_CVG_TIME +904 0x0000 //TX_MICMUTE_RELEASE_TIME +905 0x0000 //TX_MIC_VOLUME_MIC0MUTE +906 0x0000 //TX_MICMUTE_EPD_OFFSET_0 +907 0x0000 //TX_MICMUTE_FRQ_AEC_L +908 0x0000 //TX_MICMUTE_EAD_THR +909 0x0000 //TX_MICMUTE_LAMBDA_CB_NLE +910 0x0000 //TX_MICMUTE_LAMBDA_RE_EST +911 0x0000 //TX_DTD_THR1_MICMUTE_0 +912 0x0000 //TX_DTD_THR1_MICMUTE_1 +913 0x0000 //TX_DTD_THR1_MICMUTE_2 +914 0x0000 //TX_DTD_THR1_MICMUTE_3 +915 0x0000 //TX_DTD_THR2_MICMUTE_0 +916 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x0000 //TX_MICMUTE_C_POST_FLT +922 0x0000 //TX_MICMUTE_DT_CUT_K +923 0x0000 //TX_MICMUTE_DT_CUT_THR +924 0x0000 //TX_MICMUTE_DT_CUT_K2 +925 0x0000 //TX_MICMUTE_DT_CUT_THR2 +926 0x0000 //TX_MICMUTE_DT2_HOLD_N +927 0x0000 //TX_MICMUTE_RATIODTH_THCUT +928 0x0000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x0000 //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0000 //TX_MICMUTE_C_POST_FLT_MASK +931 0x0000 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0000 //TX_MICMUTE_DT_CUT_K1 +933 0x0000 //TX_MICMUTE_N2_SN_EST +934 0x0000 //TX_MICMUTE_THR_SN_EST_0 +935 0x0000 //TX_MICMUTE_MIN_G_CTRL_0 +936 0x0000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x0000 //TX_MICMUTE_B_POST_FILT_0 +938 0x0000 //TX_MIC1RUB_AMP_THR +939 0x0000 //TX_MIC1MUTE_RATIO_THR +940 0x0000 //TX_MIC1MUTE_AMP_THR +941 0x0000 //TX_MIC1MUTE_CVG_TIME +942 0x0000 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x2064 //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0003 //RX_SAMPLINGFREQ_SIG +3 0x0003 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7FFF //RX_A_HP +12 0x0000 //RX_B_PE +13 0x1800 //RX_THR_PITCH_DET_0 +14 0x1000 //RX_THR_PITCH_DET_1 +15 0x0800 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0400 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x0003 //RX_NS_LVL_CTRL +23 0x9000 //RX_THR_SN_EST +24 0x7CCD //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0000 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x2000 //RX_MIN_G_FP +128 0x0080 //RX_MAX_G_FP +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x2064 //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0003 //RX_SAMPLINGFREQ_SIG +160 0x0003 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7FFF //RX_A_HP +169 0x0000 //RX_B_PE +170 0x1800 //RX_THR_PITCH_DET_0 +171 0x1000 //RX_THR_PITCH_DET_1 +172 0x0800 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0400 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x0003 //RX_NS_LVL_CTRL +180 0x9000 //RX_THR_SN_EST +181 0x7CCD //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0000 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x2000 //RX_MIN_G_FP +285 0x0080 //RX_MAX_G_FP +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME BLUETOOTH-BTWB-VOICE_GENERIC-FB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0009 //TX_OPERATION_MODE_0 +1 0x0009 //TX_OPERATION_MODE_1 +2 0x0020 //TX_PATCH_REG +3 0x0200 //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0001 //TX_NUM_MIC +6 0x0004 //TX_SAMPLINGFREQ_SIG +7 0x0004 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009B //TX_DIST2REF1 +22 0x0000 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0915 //TX_PGA_0 +28 0x0800 //TX_PGA_1 +29 0x0000 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0000 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0001 //TX_MIC_DATA_SRC1 +43 0x0002 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3E00 //TX_DIST2REF_11 +73 0x0000 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0200 //TX_MIC_REFBLK_VOLUME +108 0x0800 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0000 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7E56 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x6800 //TX_THR_PITCH_DET_0 +131 0x6000 //TX_THR_PITCH_DET_1 +132 0x5800 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x001E //TX_TAIL_LENGTH +147 0x0200 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x6000 //TX_EAD_THR +151 0x0400 //TX_THR_RE_EST +152 0x3000 //TX_MIN_EQ_RE_EST_0 +153 0x3000 //TX_MIN_EQ_RE_EST_1 +154 0x4000 //TX_MIN_EQ_RE_EST_2 +155 0x0800 //TX_MIN_EQ_RE_EST_3 +156 0x0800 //TX_MIN_EQ_RE_EST_4 +157 0x0800 //TX_MIN_EQ_RE_EST_5 +158 0x6000 //TX_MIN_EQ_RE_EST_6 +159 0x6000 //TX_MIN_EQ_RE_EST_7 +160 0x6000 //TX_MIN_EQ_RE_EST_8 +161 0x6000 //TX_MIN_EQ_RE_EST_9 +162 0x4000 //TX_MIN_EQ_RE_EST_10 +163 0x4000 //TX_MIN_EQ_RE_EST_11 +164 0x4000 //TX_MIN_EQ_RE_EST_12 +165 0x3000 //TX_LAMBDA_RE_EST +166 0x4000 //TX_LAMBDA_CB_NLE +167 0x3000 //TX_C_POST_FLT +168 0x4500 //TX_GAIN_NP +169 0x00C8 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x03E8 //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x5000 //TX_DTD_THR1_0 +198 0x7000 //TX_DTD_THR1_1 +199 0x7F00 //TX_DTD_THR1_2 +200 0x7FFF //TX_DTD_THR1_3 +201 0x7FFF //TX_DTD_THR1_4 +202 0x7FFF //TX_DTD_THR1_5 +203 0x7FFF //TX_DTD_THR1_6 +204 0x0800 //TX_DTD_THR2_0 +205 0x0800 //TX_DTD_THR2_1 +206 0x0800 //TX_DTD_THR2_2 +207 0x0800 //TX_DTD_THR2_3 +208 0x0800 //TX_DTD_THR2_4 +209 0x0100 //TX_DTD_THR2_5 +210 0x0100 //TX_DTD_THR2_6 +211 0x7FFF //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x03E8 //TX_DT_CUT_K +214 0x0CCD //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x0400 //TX_ADPT_STRICT_L +222 0x0200 //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x0800 //TX_B_POST_FILT_ECHO_L +229 0x7FFF //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x7FFF //TX_B_LESSCUT_RTO_ECHO +232 0x00C0 //TX_EPD_OFFSET_00 +233 0x00C0 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x7FFF //TX_DTD_THR1_7 +238 0x7FFF //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xF700 //TX_THR_SN_EST_0 +243 0xFB00 //TX_THR_SN_EST_1 +244 0xFA00 //TX_THR_SN_EST_2 +245 0xF700 //TX_THR_SN_EST_3 +246 0xFA00 //TX_THR_SN_EST_4 +247 0xF600 //TX_THR_SN_EST_5 +248 0xF600 //TX_THR_SN_EST_6 +249 0xF600 //TX_THR_SN_EST_7 +250 0x0200 //TX_DELTA_THR_SN_EST_0 +251 0x0400 //TX_DELTA_THR_SN_EST_1 +252 0x0300 //TX_DELTA_THR_SN_EST_2 +253 0x0600 //TX_DELTA_THR_SN_EST_3 +254 0x0200 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0200 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x4000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x4000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x2000 //TX_B_POST_FLT_0 +280 0x2000 //TX_B_POST_FLT_1 +281 0x0012 //TX_NS_LVL_CTRL_0 +282 0x0016 //TX_NS_LVL_CTRL_1 +283 0x0016 //TX_NS_LVL_CTRL_2 +284 0x0019 //TX_NS_LVL_CTRL_3 +285 0x0010 //TX_NS_LVL_CTRL_4 +286 0x0010 //TX_NS_LVL_CTRL_5 +287 0x0019 //TX_NS_LVL_CTRL_6 +288 0x0010 //TX_NS_LVL_CTRL_7 +289 0x000C //TX_MIN_GAIN_S_0 +290 0x000C //TX_MIN_GAIN_S_1 +291 0x000C //TX_MIN_GAIN_S_2 +292 0x000F //TX_MIN_GAIN_S_3 +293 0x000C //TX_MIN_GAIN_S_4 +294 0x000C //TX_MIN_GAIN_S_5 +295 0x0011 //TX_MIN_GAIN_S_6 +296 0x000C //TX_MIN_GAIN_S_7 +297 0x7FFF //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7000 //TX_SNRI_SUP_0 +301 0x7000 //TX_SNRI_SUP_1 +302 0x7000 //TX_SNRI_SUP_2 +303 0x6000 //TX_SNRI_SUP_3 +304 0x7FFF //TX_SNRI_SUP_4 +305 0x7FFF //TX_SNRI_SUP_5 +306 0x6000 //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x0016 //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x6000 //TX_A_POST_FILT_S_0 +315 0x6000 //TX_A_POST_FILT_S_1 +316 0x6000 //TX_A_POST_FILT_S_2 +317 0x6000 //TX_A_POST_FILT_S_3 +318 0x6000 //TX_A_POST_FILT_S_4 +319 0x6000 //TX_A_POST_FILT_S_5 +320 0x6000 //TX_A_POST_FILT_S_6 +321 0x6000 //TX_A_POST_FILT_S_7 +322 0x2000 //TX_B_POST_FILT_0 +323 0x4000 //TX_B_POST_FILT_1 +324 0x2000 //TX_B_POST_FILT_2 +325 0x2000 //TX_B_POST_FILT_3 +326 0x2000 //TX_B_POST_FILT_4 +327 0x2000 //TX_B_POST_FILT_5 +328 0x2000 //TX_B_POST_FILT_6 +329 0x2000 //TX_B_POST_FILT_7 +330 0x7FFF //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x7FFF //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7CCD //TX_LAMBDA_PFILT +339 0x7CCD //TX_LAMBDA_PFILT_S_0 +340 0x7CCD //TX_LAMBDA_PFILT_S_1 +341 0x7CCD //TX_LAMBDA_PFILT_S_2 +342 0x7CCD //TX_LAMBDA_PFILT_S_3 +343 0x7CCD //TX_LAMBDA_PFILT_S_4 +344 0x7CCD //TX_LAMBDA_PFILT_S_5 +345 0x7CCD //TX_LAMBDA_PFILT_S_6 +346 0x7CCD //TX_LAMBDA_PFILT_S_7 +347 0x0200 //TX_K_PEPPER +348 0x0500 //TX_A_PEPPER +349 0x1600 //TX_K_PEPPER_HF +350 0x0400 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0800 //TX_DT_BINVAD_TH_0 +354 0x0800 //TX_DT_BINVAD_TH_1 +355 0x0800 //TX_DT_BINVAD_TH_2 +356 0x0800 //TX_DT_BINVAD_TH_3 +357 0x1D4C //TX_DT_BINVAD_ENDF +358 0x0000 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0190 //TX_NDETCT +367 0x0020 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x02A6 //TX_NOISE_TH_1 +371 0x04B0 //TX_NOISE_TH_2 +372 0x3194 //TX_NOISE_TH_3 +373 0x0960 //TX_NOISE_TH_4 +374 0x5555 //TX_NOISE_TH_5 +375 0x3FF4 //TX_NOISE_TH_5_2 +376 0x0001 //TX_NOISE_TH_5_3 +377 0x0000 //TX_NOISE_TH_5_4 +378 0x02BC //TX_NOISE_TH_6 +379 0x0020 //TX_MINENOISE_TH +380 0x4000 //TX_MORENS_TFMASK_TH +381 0xFFEE //TX_DRC_QUIET_FLOOR +382 0x6000 //TX_RATIODTL_CUT_TH +383 0xFFF3 //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x0333 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x0000 //TX_POST_MASK_SUP_HSNE +392 0x0000 //TX_TAIL_DET_TH +393 0x0000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0800 //TX_SUPHIGH_TH +396 0x00C8 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x0800 //TX_C_POST_FLT_MASK +399 0x0005 //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0002 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x0020 //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x2900 //TX_MIN_G_CTRL_SSNS +409 0x0800 //TX_METAL_RTO_THR +410 0x4848 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x4000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x01E0 //TX_NOR_OFF_THR +498 0x7C00 //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0xD333 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x6000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0x0000 //TX_DEREVERB_LF_MU +515 0x0000 //TX_DEREVERB_HF_MU +516 0x0000 //TX_DEREVERB_DELAY +517 0x0000 //TX_DEREVERB_COEF_LEN +518 0x0000 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x0000 //TX_GSC_RTOH_TH +523 0x0000 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0020 //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4848 //TX_FDEQ_GAIN_5 +573 0x4848 //TX_FDEQ_GAIN_6 +574 0x4848 //TX_FDEQ_GAIN_7 +575 0x4848 //TX_FDEQ_GAIN_8 +576 0x4848 //TX_FDEQ_GAIN_9 +577 0x4848 //TX_FDEQ_GAIN_10 +578 0x4848 //TX_FDEQ_GAIN_11 +579 0x4848 //TX_FDEQ_GAIN_12 +580 0x4848 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0304 //TX_FDEQ_BIN_2 +594 0x0405 //TX_FDEQ_BIN_3 +595 0x0607 //TX_FDEQ_BIN_4 +596 0x0809 //TX_FDEQ_BIN_5 +597 0x0A0B //TX_FDEQ_BIN_6 +598 0x0C0D //TX_FDEQ_BIN_7 +599 0x0E0F //TX_FDEQ_BIN_8 +600 0x1011 //TX_FDEQ_BIN_9 +601 0x1214 //TX_FDEQ_BIN_10 +602 0x1618 //TX_FDEQ_BIN_11 +603 0x1C1C //TX_FDEQ_BIN_12 +604 0x2020 //TX_FDEQ_BIN_13 +605 0x2020 //TX_FDEQ_BIN_14 +606 0x2011 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4848 //TX_PREEQ_GAIN_MIC0_8 +626 0x4848 //TX_PREEQ_GAIN_MIC0_9 +627 0x4848 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0E10 //TX_PREEQ_BIN_MIC0_0 +642 0x1010 //TX_PREEQ_BIN_MIC0_1 +643 0x1010 //TX_PREEQ_BIN_MIC0_2 +644 0x1010 //TX_PREEQ_BIN_MIC0_3 +645 0x1010 //TX_PREEQ_BIN_MIC0_4 +646 0x1010 //TX_PREEQ_BIN_MIC0_5 +647 0x1010 //TX_PREEQ_BIN_MIC0_6 +648 0x1010 //TX_PREEQ_BIN_MIC0_7 +649 0x1010 //TX_PREEQ_BIN_MIC0_8 +650 0x1010 //TX_PREEQ_BIN_MIC0_9 +651 0x1010 //TX_PREEQ_BIN_MIC0_10 +652 0x1010 //TX_PREEQ_BIN_MIC0_11 +653 0x1010 //TX_PREEQ_BIN_MIC0_12 +654 0x1010 //TX_PREEQ_BIN_MIC0_13 +655 0x1010 //TX_PREEQ_BIN_MIC0_14 +656 0x0200 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0E10 //TX_PREEQ_BIN_MIC1_0 +691 0x1010 //TX_PREEQ_BIN_MIC1_1 +692 0x1010 //TX_PREEQ_BIN_MIC1_2 +693 0x1010 //TX_PREEQ_BIN_MIC1_3 +694 0x1010 //TX_PREEQ_BIN_MIC1_4 +695 0x1010 //TX_PREEQ_BIN_MIC1_5 +696 0x1010 //TX_PREEQ_BIN_MIC1_6 +697 0x1010 //TX_PREEQ_BIN_MIC1_7 +698 0x1010 //TX_PREEQ_BIN_MIC1_8 +699 0x1010 //TX_PREEQ_BIN_MIC1_9 +700 0x1010 //TX_PREEQ_BIN_MIC1_10 +701 0x1010 //TX_PREEQ_BIN_MIC1_11 +702 0x1010 //TX_PREEQ_BIN_MIC1_12 +703 0x1010 //TX_PREEQ_BIN_MIC1_13 +704 0x1010 //TX_PREEQ_BIN_MIC1_14 +705 0x0200 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0E10 //TX_PREEQ_BIN_MIC2_0 +740 0x1010 //TX_PREEQ_BIN_MIC2_1 +741 0x1010 //TX_PREEQ_BIN_MIC2_2 +742 0x1010 //TX_PREEQ_BIN_MIC2_3 +743 0x1010 //TX_PREEQ_BIN_MIC2_4 +744 0x1010 //TX_PREEQ_BIN_MIC2_5 +745 0x1010 //TX_PREEQ_BIN_MIC2_6 +746 0x1010 //TX_PREEQ_BIN_MIC2_7 +747 0x1010 //TX_PREEQ_BIN_MIC2_8 +748 0x1010 //TX_PREEQ_BIN_MIC2_9 +749 0x1010 //TX_PREEQ_BIN_MIC2_10 +750 0x1010 //TX_PREEQ_BIN_MIC2_11 +751 0x1010 //TX_PREEQ_BIN_MIC2_12 +752 0x1010 //TX_PREEQ_BIN_MIC2_13 +753 0x1010 //TX_PREEQ_BIN_MIC2_14 +754 0x0200 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x2000 //TX_NND_WEIGHT +765 0x0060 //TX_MIC_CALIBRATION_0 +766 0x0060 //TX_MIC_CALIBRATION_1 +767 0x0070 //TX_MIC_CALIBRATION_2 +768 0x0070 //TX_MIC_CALIBRATION_3 +769 0x0050 //TX_MIC_PWR_BIAS_0 +770 0x0040 //TX_MIC_PWR_BIAS_1 +771 0x0040 //TX_MIC_PWR_BIAS_2 +772 0x0040 //TX_MIC_PWR_BIAS_3 +773 0x0009 //TX_GAIN_LIMIT_0 +774 0x000F //TX_GAIN_LIMIT_1 +775 0x000F //TX_GAIN_LIMIT_2 +776 0x000F //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x0C00 //TX_TDDRC_ALPHA_UP_01 +784 0x0C00 //TX_TDDRC_ALPHA_UP_02 +785 0x0C00 //TX_TDDRC_ALPHA_UP_03 +786 0x0C00 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x7FFF //TX_TDDRC_TD_DRC_LIMIT +792 0x2000 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0000 //TX_DEADMIC_SILENCE_TH +817 0x0000 //TX_MIC_DEGRADE_TH +818 0x0000 //TX_DEADMIC_CNT +819 0x0000 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x4848 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0000 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0000 //TX_FILTINDX +854 0x0001 //TX_TDDRC_THRD_0 +855 0x0001 //TX_TDDRC_THRD_1 +856 0x1900 //TX_TDDRC_THRD_2 +857 0x1900 //TX_TDDRC_THRD_3 +858 0x3000 //TX_TDDRC_SLANT_0 +859 0x7B00 //TX_TDDRC_SLANT_1 +860 0x0C00 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x0200 //TX_TDDRC_DRC_GAIN +867 0x7FFF //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x0028 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x7000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x0000 //TX_SENDFUNC_REG_MICMUTE +898 0x0000 //TX_SENDFUNC_REG_MICMUTE1 +899 0x0000 //TX_MICMUTE_RATIO_THR +900 0x0000 //TX_MICMUTE_AMP_THR +901 0x0000 //TX_MICMUTE_HPF_IND +902 0x0000 //TX_MICMUTE_LOG_EYR_TH +903 0x0000 //TX_MICMUTE_CVG_TIME +904 0x0000 //TX_MICMUTE_RELEASE_TIME +905 0x0000 //TX_MIC_VOLUME_MIC0MUTE +906 0x0000 //TX_MICMUTE_EPD_OFFSET_0 +907 0x0000 //TX_MICMUTE_FRQ_AEC_L +908 0x0000 //TX_MICMUTE_EAD_THR +909 0x0000 //TX_MICMUTE_LAMBDA_CB_NLE +910 0x0000 //TX_MICMUTE_LAMBDA_RE_EST +911 0x0000 //TX_DTD_THR1_MICMUTE_0 +912 0x0000 //TX_DTD_THR1_MICMUTE_1 +913 0x0000 //TX_DTD_THR1_MICMUTE_2 +914 0x0000 //TX_DTD_THR1_MICMUTE_3 +915 0x0000 //TX_DTD_THR2_MICMUTE_0 +916 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x0000 //TX_MICMUTE_C_POST_FLT +922 0x0000 //TX_MICMUTE_DT_CUT_K +923 0x0000 //TX_MICMUTE_DT_CUT_THR +924 0x0000 //TX_MICMUTE_DT_CUT_K2 +925 0x0000 //TX_MICMUTE_DT_CUT_THR2 +926 0x0000 //TX_MICMUTE_DT2_HOLD_N +927 0x0000 //TX_MICMUTE_RATIODTH_THCUT +928 0x0000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x0000 //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0000 //TX_MICMUTE_C_POST_FLT_MASK +931 0x0000 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0000 //TX_MICMUTE_DT_CUT_K1 +933 0x0000 //TX_MICMUTE_N2_SN_EST +934 0x0000 //TX_MICMUTE_THR_SN_EST_0 +935 0x0000 //TX_MICMUTE_MIN_G_CTRL_0 +936 0x0000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x0000 //TX_MICMUTE_B_POST_FILT_0 +938 0x0000 //TX_MIC1RUB_AMP_THR +939 0x0000 //TX_MIC1MUTE_RATIO_THR +940 0x0000 //TX_MIC1MUTE_AMP_THR +941 0x0000 //TX_MIC1MUTE_CVG_TIME +942 0x0000 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x2064 //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0004 //RX_SAMPLINGFREQ_SIG +3 0x0004 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7FFF //RX_A_HP +12 0x4000 //RX_B_PE +13 0x7800 //RX_THR_PITCH_DET_0 +14 0x7000 //RX_THR_PITCH_DET_1 +15 0x6000 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0500 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x000A //RX_NS_LVL_CTRL +23 0xF600 //RX_THR_SN_EST +24 0x7000 //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0000 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x2000 //RX_MIN_G_FP +128 0x0080 //RX_MAX_G_FP +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x0064 //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0004 //RX_SAMPLINGFREQ_SIG +160 0x0004 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7FFF //RX_A_HP +169 0x4000 //RX_B_PE +170 0x7800 //RX_THR_PITCH_DET_0 +171 0x7000 //RX_THR_PITCH_DET_1 +172 0x6000 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0500 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x000A //RX_NS_LVL_CTRL +180 0xF600 //RX_THR_SN_EST +181 0x7000 //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0000 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x2000 //RX_MIN_G_FP +285 0x0080 //RX_MAX_G_FP +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME BLUETOOTH-BTWB_NREC-VOICE_GENERIC-NB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0008 //TX_OPERATION_MODE_0 +1 0x0008 //TX_OPERATION_MODE_1 +2 0x0033 //TX_PATCH_REG +3 0x2A68 //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0001 //TX_NUM_MIC +6 0x0000 //TX_SAMPLINGFREQ_SIG +7 0x0000 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009B //TX_DIST2REF1 +22 0x0000 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0A13 //TX_PGA_0 +28 0x0800 //TX_PGA_1 +29 0x0800 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0000 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0001 //TX_MIC_DATA_SRC1 +43 0x0002 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3E00 //TX_DIST2REF_11 +73 0x0000 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0200 //TX_MIC_REFBLK_VOLUME +108 0x0800 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0000 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7D83 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x6800 //TX_THR_PITCH_DET_0 +131 0x6000 //TX_THR_PITCH_DET_1 +132 0x5800 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x001E //TX_TAIL_LENGTH +147 0x0080 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x7000 //TX_EAD_THR +151 0x0800 //TX_THR_RE_EST +152 0x0800 //TX_MIN_EQ_RE_EST_0 +153 0x0800 //TX_MIN_EQ_RE_EST_1 +154 0x0800 //TX_MIN_EQ_RE_EST_2 +155 0x0800 //TX_MIN_EQ_RE_EST_3 +156 0x0800 //TX_MIN_EQ_RE_EST_4 +157 0x0800 //TX_MIN_EQ_RE_EST_5 +158 0x0800 //TX_MIN_EQ_RE_EST_6 +159 0x0800 //TX_MIN_EQ_RE_EST_7 +160 0x0800 //TX_MIN_EQ_RE_EST_8 +161 0x0800 //TX_MIN_EQ_RE_EST_9 +162 0x0800 //TX_MIN_EQ_RE_EST_10 +163 0x0800 //TX_MIN_EQ_RE_EST_11 +164 0x0800 //TX_MIN_EQ_RE_EST_12 +165 0x4000 //TX_LAMBDA_RE_EST +166 0x2000 //TX_LAMBDA_CB_NLE +167 0x6000 //TX_C_POST_FLT +168 0x7000 //TX_GAIN_NP +169 0x00C8 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x03E8 //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x7800 //TX_DTD_THR1_0 +198 0x7000 //TX_DTD_THR1_1 +199 0x7FFF //TX_DTD_THR1_2 +200 0x7FFF //TX_DTD_THR1_3 +201 0x7FFF //TX_DTD_THR1_4 +202 0x7FFF //TX_DTD_THR1_5 +203 0x7FFF //TX_DTD_THR1_6 +204 0x7FFF //TX_DTD_THR2_0 +205 0x7FFF //TX_DTD_THR2_1 +206 0x7FFF //TX_DTD_THR2_2 +207 0x7FFF //TX_DTD_THR2_3 +208 0x7FFF //TX_DTD_THR2_4 +209 0x7FFF //TX_DTD_THR2_5 +210 0x7FFF //TX_DTD_THR2_6 +211 0x1000 //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x0BB8 //TX_DT_CUT_K +214 0x0CCD //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x0400 //TX_ADPT_STRICT_L +222 0x0200 //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x0800 //TX_B_POST_FILT_ECHO_L +229 0x7FFF //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x7FFF //TX_B_LESSCUT_RTO_ECHO +232 0x0019 //TX_EPD_OFFSET_00 +233 0x0019 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x7FFF //TX_DTD_THR1_7 +238 0x7FFF //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xF400 //TX_THR_SN_EST_0 +243 0xF400 //TX_THR_SN_EST_1 +244 0xF600 //TX_THR_SN_EST_2 +245 0xF400 //TX_THR_SN_EST_3 +246 0xF400 //TX_THR_SN_EST_4 +247 0xF400 //TX_THR_SN_EST_5 +248 0xF400 //TX_THR_SN_EST_6 +249 0xF600 //TX_THR_SN_EST_7 +250 0x0000 //TX_DELTA_THR_SN_EST_0 +251 0x0200 //TX_DELTA_THR_SN_EST_1 +252 0x0200 //TX_DELTA_THR_SN_EST_2 +253 0x0200 //TX_DELTA_THR_SN_EST_3 +254 0x0200 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0000 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x6000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x6000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x1000 //TX_B_POST_FLT_0 +280 0x1000 //TX_B_POST_FLT_1 +281 0x000F //TX_NS_LVL_CTRL_0 +282 0x0011 //TX_NS_LVL_CTRL_1 +283 0x000F //TX_NS_LVL_CTRL_2 +284 0x000F //TX_NS_LVL_CTRL_3 +285 0x000F //TX_NS_LVL_CTRL_4 +286 0x000F //TX_NS_LVL_CTRL_5 +287 0x000F //TX_NS_LVL_CTRL_6 +288 0x0011 //TX_NS_LVL_CTRL_7 +289 0x000C //TX_MIN_GAIN_S_0 +290 0x000F //TX_MIN_GAIN_S_1 +291 0x000C //TX_MIN_GAIN_S_2 +292 0x000C //TX_MIN_GAIN_S_3 +293 0x000C //TX_MIN_GAIN_S_4 +294 0x000C //TX_MIN_GAIN_S_5 +295 0x000C //TX_MIN_GAIN_S_6 +296 0x000F //TX_MIN_GAIN_S_7 +297 0x7FFF //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x7FFF //TX_SNRI_SUP_1 +302 0x7FFF //TX_SNRI_SUP_2 +303 0x7FFF //TX_SNRI_SUP_3 +304 0x7FFF //TX_SNRI_SUP_4 +305 0x7FFF //TX_SNRI_SUP_5 +306 0x7FFF //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x000E //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x4000 //TX_A_POST_FILT_S_0 +315 0x5000 //TX_A_POST_FILT_S_1 +316 0x5000 //TX_A_POST_FILT_S_2 +317 0x5000 //TX_A_POST_FILT_S_3 +318 0x5000 //TX_A_POST_FILT_S_4 +319 0x5000 //TX_A_POST_FILT_S_5 +320 0x4000 //TX_A_POST_FILT_S_6 +321 0x5000 //TX_A_POST_FILT_S_7 +322 0x1000 //TX_B_POST_FILT_0 +323 0x1000 //TX_B_POST_FILT_1 +324 0x1000 //TX_B_POST_FILT_2 +325 0x1000 //TX_B_POST_FILT_3 +326 0x1000 //TX_B_POST_FILT_4 +327 0x1000 //TX_B_POST_FILT_5 +328 0x1000 //TX_B_POST_FILT_6 +329 0x1000 //TX_B_POST_FILT_7 +330 0x7FFF //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x7FFF //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7CCD //TX_LAMBDA_PFILT +339 0x7B00 //TX_LAMBDA_PFILT_S_0 +340 0x7B00 //TX_LAMBDA_PFILT_S_1 +341 0x7B00 //TX_LAMBDA_PFILT_S_2 +342 0x7B00 //TX_LAMBDA_PFILT_S_3 +343 0x7B00 //TX_LAMBDA_PFILT_S_4 +344 0x7B00 //TX_LAMBDA_PFILT_S_5 +345 0x7B00 //TX_LAMBDA_PFILT_S_6 +346 0x7B00 //TX_LAMBDA_PFILT_S_7 +347 0x0200 //TX_K_PEPPER +348 0x0800 //TX_A_PEPPER +349 0x1EAA //TX_K_PEPPER_HF +350 0x0800 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0800 //TX_DT_BINVAD_TH_0 +354 0x0800 //TX_DT_BINVAD_TH_1 +355 0x0800 //TX_DT_BINVAD_TH_2 +356 0x0800 //TX_DT_BINVAD_TH_3 +357 0x1D4C //TX_DT_BINVAD_ENDF +358 0x0000 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0190 //TX_NDETCT +367 0x0050 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x07D0 //TX_NOISE_TH_1 +371 0x00C8 //TX_NOISE_TH_2 +372 0x3A98 //TX_NOISE_TH_3 +373 0x0FA0 //TX_NOISE_TH_4 +374 0x157C //TX_NOISE_TH_5 +375 0x7FFF //TX_NOISE_TH_5_2 +376 0x7FFF //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x044C //TX_NOISE_TH_6 +379 0x0014 //TX_MINENOISE_TH +380 0x4000 //TX_MORENS_TFMASK_TH +381 0xFFEE //TX_DRC_QUIET_FLOOR +382 0x6000 //TX_RATIODTL_CUT_TH +383 0xFFF3 //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x0333 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x0000 //TX_POST_MASK_SUP_HSNE +392 0x0000 //TX_TAIL_DET_TH +393 0x0000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0800 //TX_SUPHIGH_TH +396 0x00C8 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x0800 //TX_C_POST_FLT_MASK +399 0x0005 //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0002 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x0014 //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x7FFF //TX_MIN_G_CTRL_SSNS +409 0x0000 //TX_METAL_RTO_THR +410 0x0000 //TX_NS_FP_K_METAL +411 0x7FFF //TX_NOISEDET_BOOST_TH +412 0x0000 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x4000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x0230 //TX_NOR_OFF_THR +498 0x0CCD //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0xD333 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x6000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0x0000 //TX_DEREVERB_LF_MU +515 0x0000 //TX_DEREVERB_HF_MU +516 0x0000 //TX_DEREVERB_DELAY +517 0x0000 //TX_DEREVERB_COEF_LEN +518 0x0000 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x0000 //TX_GSC_RTOH_TH +523 0x0000 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x001C //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4848 //TX_FDEQ_GAIN_5 +573 0x4242 //TX_FDEQ_GAIN_6 +574 0x423C //TX_FDEQ_GAIN_7 +575 0x3C3C //TX_FDEQ_GAIN_8 +576 0x3434 //TX_FDEQ_GAIN_9 +577 0x4848 //TX_FDEQ_GAIN_10 +578 0x4848 //TX_FDEQ_GAIN_11 +579 0x4848 //TX_FDEQ_GAIN_12 +580 0x4848 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0303 //TX_FDEQ_BIN_2 +594 0x0304 //TX_FDEQ_BIN_3 +595 0x0405 //TX_FDEQ_BIN_4 +596 0x0506 //TX_FDEQ_BIN_5 +597 0x0708 //TX_FDEQ_BIN_6 +598 0x090A //TX_FDEQ_BIN_7 +599 0x0B0C //TX_FDEQ_BIN_8 +600 0x0D0E //TX_FDEQ_BIN_9 +601 0x0E0F //TX_FDEQ_BIN_10 +602 0x0F10 //TX_FDEQ_BIN_11 +603 0x1011 //TX_FDEQ_BIN_12 +604 0x1104 //TX_FDEQ_BIN_13 +605 0x0000 //TX_FDEQ_BIN_14 +606 0x0000 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4848 //TX_PREEQ_GAIN_MIC0_8 +626 0x4848 //TX_PREEQ_GAIN_MIC0_9 +627 0x4848 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0608 //TX_PREEQ_BIN_MIC0_0 +642 0x0808 //TX_PREEQ_BIN_MIC0_1 +643 0x0808 //TX_PREEQ_BIN_MIC0_2 +644 0x0808 //TX_PREEQ_BIN_MIC0_3 +645 0x0808 //TX_PREEQ_BIN_MIC0_4 +646 0x0808 //TX_PREEQ_BIN_MIC0_5 +647 0x0808 //TX_PREEQ_BIN_MIC0_6 +648 0x0808 //TX_PREEQ_BIN_MIC0_7 +649 0x0808 //TX_PREEQ_BIN_MIC0_8 +650 0x0808 //TX_PREEQ_BIN_MIC0_9 +651 0x0808 //TX_PREEQ_BIN_MIC0_10 +652 0x0808 //TX_PREEQ_BIN_MIC0_11 +653 0x0808 //TX_PREEQ_BIN_MIC0_12 +654 0x0808 //TX_PREEQ_BIN_MIC0_13 +655 0x0808 //TX_PREEQ_BIN_MIC0_14 +656 0x0200 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0608 //TX_PREEQ_BIN_MIC1_0 +691 0x0808 //TX_PREEQ_BIN_MIC1_1 +692 0x0808 //TX_PREEQ_BIN_MIC1_2 +693 0x0808 //TX_PREEQ_BIN_MIC1_3 +694 0x0808 //TX_PREEQ_BIN_MIC1_4 +695 0x0808 //TX_PREEQ_BIN_MIC1_5 +696 0x0808 //TX_PREEQ_BIN_MIC1_6 +697 0x0808 //TX_PREEQ_BIN_MIC1_7 +698 0x0808 //TX_PREEQ_BIN_MIC1_8 +699 0x0808 //TX_PREEQ_BIN_MIC1_9 +700 0x0808 //TX_PREEQ_BIN_MIC1_10 +701 0x0808 //TX_PREEQ_BIN_MIC1_11 +702 0x0808 //TX_PREEQ_BIN_MIC1_12 +703 0x0808 //TX_PREEQ_BIN_MIC1_13 +704 0x0808 //TX_PREEQ_BIN_MIC1_14 +705 0x0200 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0608 //TX_PREEQ_BIN_MIC2_0 +740 0x0808 //TX_PREEQ_BIN_MIC2_1 +741 0x0808 //TX_PREEQ_BIN_MIC2_2 +742 0x0808 //TX_PREEQ_BIN_MIC2_3 +743 0x0808 //TX_PREEQ_BIN_MIC2_4 +744 0x0808 //TX_PREEQ_BIN_MIC2_5 +745 0x0808 //TX_PREEQ_BIN_MIC2_6 +746 0x0808 //TX_PREEQ_BIN_MIC2_7 +747 0x0808 //TX_PREEQ_BIN_MIC2_8 +748 0x0808 //TX_PREEQ_BIN_MIC2_9 +749 0x0808 //TX_PREEQ_BIN_MIC2_10 +750 0x0808 //TX_PREEQ_BIN_MIC2_11 +751 0x0808 //TX_PREEQ_BIN_MIC2_12 +752 0x0808 //TX_PREEQ_BIN_MIC2_13 +753 0x0808 //TX_PREEQ_BIN_MIC2_14 +754 0x0200 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x0800 //TX_NND_WEIGHT +765 0x0062 //TX_MIC_CALIBRATION_0 +766 0x0062 //TX_MIC_CALIBRATION_1 +767 0x0062 //TX_MIC_CALIBRATION_2 +768 0x0062 //TX_MIC_CALIBRATION_3 +769 0x0046 //TX_MIC_PWR_BIAS_0 +770 0x0046 //TX_MIC_PWR_BIAS_1 +771 0x0046 //TX_MIC_PWR_BIAS_2 +772 0x0046 //TX_MIC_PWR_BIAS_3 +773 0x000C //TX_GAIN_LIMIT_0 +774 0x000C //TX_GAIN_LIMIT_1 +775 0x000C //TX_GAIN_LIMIT_2 +776 0x000C //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x1000 //TX_TDDRC_ALPHA_UP_01 +784 0x1000 //TX_TDDRC_ALPHA_UP_02 +785 0x1000 //TX_TDDRC_ALPHA_UP_03 +786 0x1000 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x7FFF //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0000 //TX_DEADMIC_SILENCE_TH +817 0x0000 //TX_MIC_DEGRADE_TH +818 0x0000 //TX_DEADMIC_CNT +819 0x0000 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x0000 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0000 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0000 //TX_FILTINDX +854 0x0000 //TX_TDDRC_THRD_0 +855 0x0000 //TX_TDDRC_THRD_1 +856 0x2000 //TX_TDDRC_THRD_2 +857 0x2000 //TX_TDDRC_THRD_3 +858 0x3000 //TX_TDDRC_SLANT_0 +859 0x6E00 //TX_TDDRC_SLANT_1 +860 0x1000 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x07F2 //TX_TDDRC_DRC_GAIN +867 0x7FFF //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x00C8 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x7FFF //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x0000 //TX_SENDFUNC_REG_MICMUTE +898 0x0000 //TX_SENDFUNC_REG_MICMUTE1 +899 0x0000 //TX_MICMUTE_RATIO_THR +900 0x0000 //TX_MICMUTE_AMP_THR +901 0x0000 //TX_MICMUTE_HPF_IND +902 0x0000 //TX_MICMUTE_LOG_EYR_TH +903 0x0000 //TX_MICMUTE_CVG_TIME +904 0x0000 //TX_MICMUTE_RELEASE_TIME +905 0x0000 //TX_MIC_VOLUME_MIC0MUTE +906 0x0000 //TX_MICMUTE_EPD_OFFSET_0 +907 0x0000 //TX_MICMUTE_FRQ_AEC_L +908 0x0000 //TX_MICMUTE_EAD_THR +909 0x0000 //TX_MICMUTE_LAMBDA_CB_NLE +910 0x0000 //TX_MICMUTE_LAMBDA_RE_EST +911 0x0000 //TX_DTD_THR1_MICMUTE_0 +912 0x0000 //TX_DTD_THR1_MICMUTE_1 +913 0x0000 //TX_DTD_THR1_MICMUTE_2 +914 0x0000 //TX_DTD_THR1_MICMUTE_3 +915 0x0000 //TX_DTD_THR2_MICMUTE_0 +916 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x0000 //TX_MICMUTE_C_POST_FLT +922 0x0000 //TX_MICMUTE_DT_CUT_K +923 0x0000 //TX_MICMUTE_DT_CUT_THR +924 0x0000 //TX_MICMUTE_DT_CUT_K2 +925 0x0000 //TX_MICMUTE_DT_CUT_THR2 +926 0x0000 //TX_MICMUTE_DT2_HOLD_N +927 0x0000 //TX_MICMUTE_RATIODTH_THCUT +928 0x0000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x0000 //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0000 //TX_MICMUTE_C_POST_FLT_MASK +931 0x0000 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0000 //TX_MICMUTE_DT_CUT_K1 +933 0x0000 //TX_MICMUTE_N2_SN_EST +934 0x0000 //TX_MICMUTE_THR_SN_EST_0 +935 0x0000 //TX_MICMUTE_MIN_G_CTRL_0 +936 0x0000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x0000 //TX_MICMUTE_B_POST_FILT_0 +938 0x0000 //TX_MIC1RUB_AMP_THR +939 0x0000 //TX_MIC1MUTE_RATIO_THR +940 0x0000 //TX_MIC1MUTE_AMP_THR +941 0x0000 //TX_MIC1MUTE_CVG_TIME +942 0x0000 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x206C //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0000 //RX_SAMPLINGFREQ_SIG +3 0x0000 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7FFF //RX_A_HP +12 0x0000 //RX_B_PE +13 0x3800 //RX_THR_PITCH_DET_0 +14 0x3000 //RX_THR_PITCH_DET_1 +15 0x2800 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0600 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x0010 //RX_NS_LVL_CTRL +23 0xF800 //RX_THR_SN_EST +24 0x7CCD //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4444 //RX_FDEQ_GAIN_6 +46 0x4040 //RX_FDEQ_GAIN_7 +47 0x4040 //RX_FDEQ_GAIN_8 +48 0x4040 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0000 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x017F //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x2000 //RX_MIN_G_FP +128 0x0080 //RX_MAX_G_FP +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x017F //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4444 //RX_FDEQ_GAIN_6 +46 0x4040 //RX_FDEQ_GAIN_7 +47 0x4040 //RX_FDEQ_GAIN_8 +48 0x4040 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x017F //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4444 //RX_FDEQ_GAIN_6 +46 0x4040 //RX_FDEQ_GAIN_7 +47 0x4040 //RX_FDEQ_GAIN_8 +48 0x4040 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x017F //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4444 //RX_FDEQ_GAIN_6 +46 0x4040 //RX_FDEQ_GAIN_7 +47 0x4040 //RX_FDEQ_GAIN_8 +48 0x4040 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x017F //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4444 //RX_FDEQ_GAIN_6 +46 0x4040 //RX_FDEQ_GAIN_7 +47 0x4040 //RX_FDEQ_GAIN_8 +48 0x4040 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x017F //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4444 //RX_FDEQ_GAIN_6 +46 0x4040 //RX_FDEQ_GAIN_7 +47 0x4040 //RX_FDEQ_GAIN_8 +48 0x4040 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x017F //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4444 //RX_FDEQ_GAIN_6 +46 0x4040 //RX_FDEQ_GAIN_7 +47 0x4040 //RX_FDEQ_GAIN_8 +48 0x4040 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x017F //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4444 //RX_FDEQ_GAIN_6 +46 0x4040 //RX_FDEQ_GAIN_7 +47 0x4040 //RX_FDEQ_GAIN_8 +48 0x4040 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x206C //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0000 //RX_SAMPLINGFREQ_SIG +160 0x0000 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7FFF //RX_A_HP +169 0x0000 //RX_B_PE +170 0x3800 //RX_THR_PITCH_DET_0 +171 0x3000 //RX_THR_PITCH_DET_1 +172 0x2800 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0600 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x0010 //RX_NS_LVL_CTRL +180 0xF800 //RX_THR_SN_EST +181 0x7CCD //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4444 //RX_FDEQ_GAIN_6 +203 0x4040 //RX_FDEQ_GAIN_7 +204 0x4040 //RX_FDEQ_GAIN_8 +205 0x4040 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0000 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x017F //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x2000 //RX_MIN_G_FP +285 0x0080 //RX_MAX_G_FP +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x017F //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4444 //RX_FDEQ_GAIN_6 +203 0x4040 //RX_FDEQ_GAIN_7 +204 0x4040 //RX_FDEQ_GAIN_8 +205 0x4040 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x017F //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4444 //RX_FDEQ_GAIN_6 +203 0x4040 //RX_FDEQ_GAIN_7 +204 0x4040 //RX_FDEQ_GAIN_8 +205 0x4040 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x017F //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4444 //RX_FDEQ_GAIN_6 +203 0x4040 //RX_FDEQ_GAIN_7 +204 0x4040 //RX_FDEQ_GAIN_8 +205 0x4040 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x017F //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4444 //RX_FDEQ_GAIN_6 +203 0x4040 //RX_FDEQ_GAIN_7 +204 0x4040 //RX_FDEQ_GAIN_8 +205 0x4040 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x017F //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4444 //RX_FDEQ_GAIN_6 +203 0x4040 //RX_FDEQ_GAIN_7 +204 0x4040 //RX_FDEQ_GAIN_8 +205 0x4040 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x017F //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4444 //RX_FDEQ_GAIN_6 +203 0x4040 //RX_FDEQ_GAIN_7 +204 0x4040 //RX_FDEQ_GAIN_8 +205 0x4040 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x017F //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4444 //RX_FDEQ_GAIN_6 +203 0x4040 //RX_FDEQ_GAIN_7 +204 0x4040 //RX_FDEQ_GAIN_8 +205 0x4040 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME BLUETOOTH-BTWB_NREC-VOICE_GENERIC-WB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0008 //TX_OPERATION_MODE_0 +1 0x0008 //TX_OPERATION_MODE_1 +2 0x0033 //TX_PATCH_REG +3 0x2A68 //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0001 //TX_NUM_MIC +6 0x0001 //TX_SAMPLINGFREQ_SIG +7 0x0001 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009B //TX_DIST2REF1 +22 0x0000 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0915 //TX_PGA_0 +28 0x0800 //TX_PGA_1 +29 0x0800 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0000 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0001 //TX_MIC_DATA_SRC1 +43 0x0002 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3E00 //TX_DIST2REF_11 +73 0x0000 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0200 //TX_MIC_REFBLK_VOLUME +108 0x0800 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0000 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7D83 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x6800 //TX_THR_PITCH_DET_0 +131 0x6000 //TX_THR_PITCH_DET_1 +132 0x5800 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x001E //TX_TAIL_LENGTH +147 0x0080 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x7000 //TX_EAD_THR +151 0x0800 //TX_THR_RE_EST +152 0x0800 //TX_MIN_EQ_RE_EST_0 +153 0x0800 //TX_MIN_EQ_RE_EST_1 +154 0x0800 //TX_MIN_EQ_RE_EST_2 +155 0x0800 //TX_MIN_EQ_RE_EST_3 +156 0x0800 //TX_MIN_EQ_RE_EST_4 +157 0x0800 //TX_MIN_EQ_RE_EST_5 +158 0x0800 //TX_MIN_EQ_RE_EST_6 +159 0x0800 //TX_MIN_EQ_RE_EST_7 +160 0x0800 //TX_MIN_EQ_RE_EST_8 +161 0x0800 //TX_MIN_EQ_RE_EST_9 +162 0x0800 //TX_MIN_EQ_RE_EST_10 +163 0x0800 //TX_MIN_EQ_RE_EST_11 +164 0x0800 //TX_MIN_EQ_RE_EST_12 +165 0x4000 //TX_LAMBDA_RE_EST +166 0x2000 //TX_LAMBDA_CB_NLE +167 0x6000 //TX_C_POST_FLT +168 0x7000 //TX_GAIN_NP +169 0x00C8 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x03E8 //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x7800 //TX_DTD_THR1_0 +198 0x7000 //TX_DTD_THR1_1 +199 0x7FFF //TX_DTD_THR1_2 +200 0x7FFF //TX_DTD_THR1_3 +201 0x7FFF //TX_DTD_THR1_4 +202 0x7FFF //TX_DTD_THR1_5 +203 0x7FFF //TX_DTD_THR1_6 +204 0x7FFF //TX_DTD_THR2_0 +205 0x7FFF //TX_DTD_THR2_1 +206 0x7FFF //TX_DTD_THR2_2 +207 0x7FFF //TX_DTD_THR2_3 +208 0x7FFF //TX_DTD_THR2_4 +209 0x7FFF //TX_DTD_THR2_5 +210 0x7FFF //TX_DTD_THR2_6 +211 0x1000 //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x0BB8 //TX_DT_CUT_K +214 0x0CCD //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x0400 //TX_ADPT_STRICT_L +222 0x0200 //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x0800 //TX_B_POST_FILT_ECHO_L +229 0x7FFF //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x7FFF //TX_B_LESSCUT_RTO_ECHO +232 0x0019 //TX_EPD_OFFSET_00 +233 0x0019 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x7FFF //TX_DTD_THR1_7 +238 0x7FFF //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xF400 //TX_THR_SN_EST_0 +243 0xF400 //TX_THR_SN_EST_1 +244 0xF600 //TX_THR_SN_EST_2 +245 0xF400 //TX_THR_SN_EST_3 +246 0xF400 //TX_THR_SN_EST_4 +247 0xF400 //TX_THR_SN_EST_5 +248 0xF400 //TX_THR_SN_EST_6 +249 0xF600 //TX_THR_SN_EST_7 +250 0x0000 //TX_DELTA_THR_SN_EST_0 +251 0x0200 //TX_DELTA_THR_SN_EST_1 +252 0x0200 //TX_DELTA_THR_SN_EST_2 +253 0x0200 //TX_DELTA_THR_SN_EST_3 +254 0x0200 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0000 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x6000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x6000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x1000 //TX_B_POST_FLT_0 +280 0x1000 //TX_B_POST_FLT_1 +281 0x000F //TX_NS_LVL_CTRL_0 +282 0x0011 //TX_NS_LVL_CTRL_1 +283 0x000F //TX_NS_LVL_CTRL_2 +284 0x000F //TX_NS_LVL_CTRL_3 +285 0x000F //TX_NS_LVL_CTRL_4 +286 0x000F //TX_NS_LVL_CTRL_5 +287 0x000F //TX_NS_LVL_CTRL_6 +288 0x0011 //TX_NS_LVL_CTRL_7 +289 0x000C //TX_MIN_GAIN_S_0 +290 0x000F //TX_MIN_GAIN_S_1 +291 0x000C //TX_MIN_GAIN_S_2 +292 0x000C //TX_MIN_GAIN_S_3 +293 0x000C //TX_MIN_GAIN_S_4 +294 0x000C //TX_MIN_GAIN_S_5 +295 0x000C //TX_MIN_GAIN_S_6 +296 0x000F //TX_MIN_GAIN_S_7 +297 0x7FFF //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x7FFF //TX_SNRI_SUP_1 +302 0x7FFF //TX_SNRI_SUP_2 +303 0x7FFF //TX_SNRI_SUP_3 +304 0x7FFF //TX_SNRI_SUP_4 +305 0x7FFF //TX_SNRI_SUP_5 +306 0x7FFF //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x000E //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x4000 //TX_A_POST_FILT_S_0 +315 0x5000 //TX_A_POST_FILT_S_1 +316 0x5000 //TX_A_POST_FILT_S_2 +317 0x5000 //TX_A_POST_FILT_S_3 +318 0x5000 //TX_A_POST_FILT_S_4 +319 0x5000 //TX_A_POST_FILT_S_5 +320 0x4000 //TX_A_POST_FILT_S_6 +321 0x5000 //TX_A_POST_FILT_S_7 +322 0x1000 //TX_B_POST_FILT_0 +323 0x1000 //TX_B_POST_FILT_1 +324 0x1000 //TX_B_POST_FILT_2 +325 0x1000 //TX_B_POST_FILT_3 +326 0x1000 //TX_B_POST_FILT_4 +327 0x1000 //TX_B_POST_FILT_5 +328 0x1000 //TX_B_POST_FILT_6 +329 0x1000 //TX_B_POST_FILT_7 +330 0x7FFF //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x7FFF //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7CCD //TX_LAMBDA_PFILT +339 0x7B00 //TX_LAMBDA_PFILT_S_0 +340 0x7B00 //TX_LAMBDA_PFILT_S_1 +341 0x7B00 //TX_LAMBDA_PFILT_S_2 +342 0x7B00 //TX_LAMBDA_PFILT_S_3 +343 0x7B00 //TX_LAMBDA_PFILT_S_4 +344 0x7B00 //TX_LAMBDA_PFILT_S_5 +345 0x7B00 //TX_LAMBDA_PFILT_S_6 +346 0x7B00 //TX_LAMBDA_PFILT_S_7 +347 0x0200 //TX_K_PEPPER +348 0x0800 //TX_A_PEPPER +349 0x1EAA //TX_K_PEPPER_HF +350 0x0800 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0800 //TX_DT_BINVAD_TH_0 +354 0x0800 //TX_DT_BINVAD_TH_1 +355 0x0800 //TX_DT_BINVAD_TH_2 +356 0x0800 //TX_DT_BINVAD_TH_3 +357 0x1D4C //TX_DT_BINVAD_ENDF +358 0x0000 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0190 //TX_NDETCT +367 0x0050 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x07D0 //TX_NOISE_TH_1 +371 0x00C8 //TX_NOISE_TH_2 +372 0x3A98 //TX_NOISE_TH_3 +373 0x0FA0 //TX_NOISE_TH_4 +374 0x157C //TX_NOISE_TH_5 +375 0x7FFF //TX_NOISE_TH_5_2 +376 0x7FFF //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x044C //TX_NOISE_TH_6 +379 0x0014 //TX_MINENOISE_TH +380 0x4000 //TX_MORENS_TFMASK_TH +381 0xFFEE //TX_DRC_QUIET_FLOOR +382 0x6000 //TX_RATIODTL_CUT_TH +383 0xFFF3 //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x0333 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x0000 //TX_POST_MASK_SUP_HSNE +392 0x0000 //TX_TAIL_DET_TH +393 0x0000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0800 //TX_SUPHIGH_TH +396 0x00C8 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x0800 //TX_C_POST_FLT_MASK +399 0x0005 //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0002 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x0014 //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x7FFF //TX_MIN_G_CTRL_SSNS +409 0x0000 //TX_METAL_RTO_THR +410 0x0000 //TX_NS_FP_K_METAL +411 0x7FFF //TX_NOISEDET_BOOST_TH +412 0x0000 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x4000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x0230 //TX_NOR_OFF_THR +498 0x0CCD //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0xD333 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x6000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0x0000 //TX_DEREVERB_LF_MU +515 0x0000 //TX_DEREVERB_HF_MU +516 0x0000 //TX_DEREVERB_DELAY +517 0x0000 //TX_DEREVERB_COEF_LEN +518 0x0000 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x0000 //TX_GSC_RTOH_TH +523 0x0000 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x001C //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4848 //TX_FDEQ_GAIN_5 +573 0x4848 //TX_FDEQ_GAIN_6 +574 0x4444 //TX_FDEQ_GAIN_7 +575 0x4444 //TX_FDEQ_GAIN_8 +576 0x3C3C //TX_FDEQ_GAIN_9 +577 0x3C3C //TX_FDEQ_GAIN_10 +578 0x3C3C //TX_FDEQ_GAIN_11 +579 0x3C30 //TX_FDEQ_GAIN_12 +580 0x3030 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0303 //TX_FDEQ_BIN_2 +594 0x0304 //TX_FDEQ_BIN_3 +595 0x0405 //TX_FDEQ_BIN_4 +596 0x0506 //TX_FDEQ_BIN_5 +597 0x0708 //TX_FDEQ_BIN_6 +598 0x090A //TX_FDEQ_BIN_7 +599 0x0B0C //TX_FDEQ_BIN_8 +600 0x0D0E //TX_FDEQ_BIN_9 +601 0x0E0F //TX_FDEQ_BIN_10 +602 0x0F10 //TX_FDEQ_BIN_11 +603 0x1011 //TX_FDEQ_BIN_12 +604 0x1112 //TX_FDEQ_BIN_13 +605 0x0000 //TX_FDEQ_BIN_14 +606 0x0000 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4848 //TX_PREEQ_GAIN_MIC0_8 +626 0x4848 //TX_PREEQ_GAIN_MIC0_9 +627 0x4848 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0608 //TX_PREEQ_BIN_MIC0_0 +642 0x0808 //TX_PREEQ_BIN_MIC0_1 +643 0x0808 //TX_PREEQ_BIN_MIC0_2 +644 0x0808 //TX_PREEQ_BIN_MIC0_3 +645 0x0808 //TX_PREEQ_BIN_MIC0_4 +646 0x0808 //TX_PREEQ_BIN_MIC0_5 +647 0x0808 //TX_PREEQ_BIN_MIC0_6 +648 0x0808 //TX_PREEQ_BIN_MIC0_7 +649 0x0808 //TX_PREEQ_BIN_MIC0_8 +650 0x0808 //TX_PREEQ_BIN_MIC0_9 +651 0x0808 //TX_PREEQ_BIN_MIC0_10 +652 0x0808 //TX_PREEQ_BIN_MIC0_11 +653 0x0808 //TX_PREEQ_BIN_MIC0_12 +654 0x0808 //TX_PREEQ_BIN_MIC0_13 +655 0x0808 //TX_PREEQ_BIN_MIC0_14 +656 0x0200 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0608 //TX_PREEQ_BIN_MIC1_0 +691 0x0808 //TX_PREEQ_BIN_MIC1_1 +692 0x0808 //TX_PREEQ_BIN_MIC1_2 +693 0x0808 //TX_PREEQ_BIN_MIC1_3 +694 0x0808 //TX_PREEQ_BIN_MIC1_4 +695 0x0808 //TX_PREEQ_BIN_MIC1_5 +696 0x0808 //TX_PREEQ_BIN_MIC1_6 +697 0x0808 //TX_PREEQ_BIN_MIC1_7 +698 0x0808 //TX_PREEQ_BIN_MIC1_8 +699 0x0808 //TX_PREEQ_BIN_MIC1_9 +700 0x0808 //TX_PREEQ_BIN_MIC1_10 +701 0x0808 //TX_PREEQ_BIN_MIC1_11 +702 0x0808 //TX_PREEQ_BIN_MIC1_12 +703 0x0808 //TX_PREEQ_BIN_MIC1_13 +704 0x0808 //TX_PREEQ_BIN_MIC1_14 +705 0x0200 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0608 //TX_PREEQ_BIN_MIC2_0 +740 0x0808 //TX_PREEQ_BIN_MIC2_1 +741 0x0808 //TX_PREEQ_BIN_MIC2_2 +742 0x0808 //TX_PREEQ_BIN_MIC2_3 +743 0x0808 //TX_PREEQ_BIN_MIC2_4 +744 0x0808 //TX_PREEQ_BIN_MIC2_5 +745 0x0808 //TX_PREEQ_BIN_MIC2_6 +746 0x0808 //TX_PREEQ_BIN_MIC2_7 +747 0x0808 //TX_PREEQ_BIN_MIC2_8 +748 0x0808 //TX_PREEQ_BIN_MIC2_9 +749 0x0808 //TX_PREEQ_BIN_MIC2_10 +750 0x0808 //TX_PREEQ_BIN_MIC2_11 +751 0x0808 //TX_PREEQ_BIN_MIC2_12 +752 0x0808 //TX_PREEQ_BIN_MIC2_13 +753 0x0808 //TX_PREEQ_BIN_MIC2_14 +754 0x0200 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x0800 //TX_NND_WEIGHT +765 0x0062 //TX_MIC_CALIBRATION_0 +766 0x0062 //TX_MIC_CALIBRATION_1 +767 0x0062 //TX_MIC_CALIBRATION_2 +768 0x0062 //TX_MIC_CALIBRATION_3 +769 0x0046 //TX_MIC_PWR_BIAS_0 +770 0x0046 //TX_MIC_PWR_BIAS_1 +771 0x0046 //TX_MIC_PWR_BIAS_2 +772 0x0046 //TX_MIC_PWR_BIAS_3 +773 0x000C //TX_GAIN_LIMIT_0 +774 0x000C //TX_GAIN_LIMIT_1 +775 0x000C //TX_GAIN_LIMIT_2 +776 0x000C //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x1000 //TX_TDDRC_ALPHA_UP_01 +784 0x1000 //TX_TDDRC_ALPHA_UP_02 +785 0x1000 //TX_TDDRC_ALPHA_UP_03 +786 0x1000 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x7FFF //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0000 //TX_DEADMIC_SILENCE_TH +817 0x0000 //TX_MIC_DEGRADE_TH +818 0x0000 //TX_DEADMIC_CNT +819 0x0000 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x0000 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0000 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0000 //TX_FILTINDX +854 0x0000 //TX_TDDRC_THRD_0 +855 0x0000 //TX_TDDRC_THRD_1 +856 0x2000 //TX_TDDRC_THRD_2 +857 0x2000 //TX_TDDRC_THRD_3 +858 0x3000 //TX_TDDRC_SLANT_0 +859 0x6E00 //TX_TDDRC_SLANT_1 +860 0x1000 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x07F2 //TX_TDDRC_DRC_GAIN +867 0x7FFF //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x00C8 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x7FFF //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x0000 //TX_SENDFUNC_REG_MICMUTE +898 0x0000 //TX_SENDFUNC_REG_MICMUTE1 +899 0x0000 //TX_MICMUTE_RATIO_THR +900 0x0000 //TX_MICMUTE_AMP_THR +901 0x0000 //TX_MICMUTE_HPF_IND +902 0x0000 //TX_MICMUTE_LOG_EYR_TH +903 0x0000 //TX_MICMUTE_CVG_TIME +904 0x0000 //TX_MICMUTE_RELEASE_TIME +905 0x0000 //TX_MIC_VOLUME_MIC0MUTE +906 0x0000 //TX_MICMUTE_EPD_OFFSET_0 +907 0x0000 //TX_MICMUTE_FRQ_AEC_L +908 0x0000 //TX_MICMUTE_EAD_THR +909 0x0000 //TX_MICMUTE_LAMBDA_CB_NLE +910 0x0000 //TX_MICMUTE_LAMBDA_RE_EST +911 0x0000 //TX_DTD_THR1_MICMUTE_0 +912 0x0000 //TX_DTD_THR1_MICMUTE_1 +913 0x0000 //TX_DTD_THR1_MICMUTE_2 +914 0x0000 //TX_DTD_THR1_MICMUTE_3 +915 0x0000 //TX_DTD_THR2_MICMUTE_0 +916 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x0000 //TX_MICMUTE_C_POST_FLT +922 0x0000 //TX_MICMUTE_DT_CUT_K +923 0x0000 //TX_MICMUTE_DT_CUT_THR +924 0x0000 //TX_MICMUTE_DT_CUT_K2 +925 0x0000 //TX_MICMUTE_DT_CUT_THR2 +926 0x0000 //TX_MICMUTE_DT2_HOLD_N +927 0x0000 //TX_MICMUTE_RATIODTH_THCUT +928 0x0000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x0000 //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0000 //TX_MICMUTE_C_POST_FLT_MASK +931 0x0000 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0000 //TX_MICMUTE_DT_CUT_K1 +933 0x0000 //TX_MICMUTE_N2_SN_EST +934 0x0000 //TX_MICMUTE_THR_SN_EST_0 +935 0x0000 //TX_MICMUTE_MIN_G_CTRL_0 +936 0x0000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x0000 //TX_MICMUTE_B_POST_FILT_0 +938 0x0000 //TX_MIC1RUB_AMP_THR +939 0x0000 //TX_MIC1MUTE_RATIO_THR +940 0x0000 //TX_MIC1MUTE_AMP_THR +941 0x0000 //TX_MIC1MUTE_CVG_TIME +942 0x0000 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x206C //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0001 //RX_SAMPLINGFREQ_SIG +3 0x0001 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7FFF //RX_A_HP +12 0x4000 //RX_B_PE +13 0x3800 //RX_THR_PITCH_DET_0 +14 0x3000 //RX_THR_PITCH_DET_1 +15 0x2800 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0600 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x0010 //RX_NS_LVL_CTRL +23 0xF800 //RX_THR_SN_EST +24 0x7CCD //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x3C3C //RX_FDEQ_GAIN_9 +49 0x3C3C //RX_FDEQ_GAIN_10 +50 0x3838 //RX_FDEQ_GAIN_11 +51 0x3838 //RX_FDEQ_GAIN_12 +52 0x3030 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1112 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0000 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7E70 //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x2000 //RX_MIN_G_FP +128 0x0080 //RX_MAX_G_FP +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7E70 //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x3C3C //RX_FDEQ_GAIN_9 +49 0x3C3C //RX_FDEQ_GAIN_10 +50 0x3838 //RX_FDEQ_GAIN_11 +51 0x3838 //RX_FDEQ_GAIN_12 +52 0x3030 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1112 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7E70 //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x3C3C //RX_FDEQ_GAIN_9 +49 0x3C3C //RX_FDEQ_GAIN_10 +50 0x3838 //RX_FDEQ_GAIN_11 +51 0x3838 //RX_FDEQ_GAIN_12 +52 0x3030 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1112 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7E70 //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x3C3C //RX_FDEQ_GAIN_9 +49 0x3C3C //RX_FDEQ_GAIN_10 +50 0x3838 //RX_FDEQ_GAIN_11 +51 0x3838 //RX_FDEQ_GAIN_12 +52 0x3030 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1112 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7E70 //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x3C3C //RX_FDEQ_GAIN_9 +49 0x3C3C //RX_FDEQ_GAIN_10 +50 0x3838 //RX_FDEQ_GAIN_11 +51 0x3838 //RX_FDEQ_GAIN_12 +52 0x3030 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1112 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7E70 //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x3C3C //RX_FDEQ_GAIN_9 +49 0x3C3C //RX_FDEQ_GAIN_10 +50 0x3838 //RX_FDEQ_GAIN_11 +51 0x3838 //RX_FDEQ_GAIN_12 +52 0x3030 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1112 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7E70 //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x3C3C //RX_FDEQ_GAIN_9 +49 0x3C3C //RX_FDEQ_GAIN_10 +50 0x3838 //RX_FDEQ_GAIN_11 +51 0x3838 //RX_FDEQ_GAIN_12 +52 0x3030 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1112 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7E70 //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x3C3C //RX_FDEQ_GAIN_9 +49 0x3C3C //RX_FDEQ_GAIN_10 +50 0x3838 //RX_FDEQ_GAIN_11 +51 0x3838 //RX_FDEQ_GAIN_12 +52 0x3030 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1112 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x206C //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0001 //RX_SAMPLINGFREQ_SIG +160 0x0001 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7FFF //RX_A_HP +169 0x4000 //RX_B_PE +170 0x3800 //RX_THR_PITCH_DET_0 +171 0x3000 //RX_THR_PITCH_DET_1 +172 0x2800 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0600 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x0010 //RX_NS_LVL_CTRL +180 0xF800 //RX_THR_SN_EST +181 0x7CCD //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x3C3C //RX_FDEQ_GAIN_9 +206 0x3C3C //RX_FDEQ_GAIN_10 +207 0x3838 //RX_FDEQ_GAIN_11 +208 0x3838 //RX_FDEQ_GAIN_12 +209 0x3030 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1112 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0000 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7E70 //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x2000 //RX_MIN_G_FP +285 0x0080 //RX_MAX_G_FP +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7E70 //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x3C3C //RX_FDEQ_GAIN_9 +206 0x3C3C //RX_FDEQ_GAIN_10 +207 0x3838 //RX_FDEQ_GAIN_11 +208 0x3838 //RX_FDEQ_GAIN_12 +209 0x3030 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1112 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7E70 //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x3C3C //RX_FDEQ_GAIN_9 +206 0x3C3C //RX_FDEQ_GAIN_10 +207 0x3838 //RX_FDEQ_GAIN_11 +208 0x3838 //RX_FDEQ_GAIN_12 +209 0x3030 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1112 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7E70 //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x3C3C //RX_FDEQ_GAIN_9 +206 0x3C3C //RX_FDEQ_GAIN_10 +207 0x3838 //RX_FDEQ_GAIN_11 +208 0x3838 //RX_FDEQ_GAIN_12 +209 0x3030 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1112 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7E70 //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x3C3C //RX_FDEQ_GAIN_9 +206 0x3C3C //RX_FDEQ_GAIN_10 +207 0x3838 //RX_FDEQ_GAIN_11 +208 0x3838 //RX_FDEQ_GAIN_12 +209 0x3030 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1112 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7E70 //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x3C3C //RX_FDEQ_GAIN_9 +206 0x3C3C //RX_FDEQ_GAIN_10 +207 0x3838 //RX_FDEQ_GAIN_11 +208 0x3838 //RX_FDEQ_GAIN_12 +209 0x3030 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1112 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7E70 //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x3C3C //RX_FDEQ_GAIN_9 +206 0x3C3C //RX_FDEQ_GAIN_10 +207 0x3838 //RX_FDEQ_GAIN_11 +208 0x3838 //RX_FDEQ_GAIN_12 +209 0x3030 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1112 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7E70 //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x3C3C //RX_FDEQ_GAIN_9 +206 0x3C3C //RX_FDEQ_GAIN_10 +207 0x3838 //RX_FDEQ_GAIN_11 +208 0x3838 //RX_FDEQ_GAIN_12 +209 0x3030 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1112 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME BLUETOOTH-BTWB_NREC-VOICE_GENERIC-SWB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0001 //TX_OPERATION_MODE_0 +1 0x0001 //TX_OPERATION_MODE_1 +2 0x0033 //TX_PATCH_REG +3 0x2A28 //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0001 //TX_NUM_MIC +6 0x0003 //TX_SAMPLINGFREQ_SIG +7 0x0003 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009B //TX_DIST2REF1 +22 0x0000 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0915 //TX_PGA_0 +28 0x0800 //TX_PGA_1 +29 0x0800 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0000 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0001 //TX_MIC_DATA_SRC1 +43 0x0002 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3E00 //TX_DIST2REF_11 +73 0x0000 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0200 //TX_MIC_REFBLK_VOLUME +108 0x0800 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0000 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7EFF //TX_A_HP +129 0x4000 //TX_B_PE +130 0x1800 //TX_THR_PITCH_DET_0 +131 0x1000 //TX_THR_PITCH_DET_1 +132 0x0800 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x001E //TX_TAIL_LENGTH +147 0x0080 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x7000 //TX_EAD_THR +151 0x0800 //TX_THR_RE_EST +152 0x0800 //TX_MIN_EQ_RE_EST_0 +153 0x0800 //TX_MIN_EQ_RE_EST_1 +154 0x0800 //TX_MIN_EQ_RE_EST_2 +155 0x0800 //TX_MIN_EQ_RE_EST_3 +156 0x0800 //TX_MIN_EQ_RE_EST_4 +157 0x0800 //TX_MIN_EQ_RE_EST_5 +158 0x0800 //TX_MIN_EQ_RE_EST_6 +159 0x0800 //TX_MIN_EQ_RE_EST_7 +160 0x0800 //TX_MIN_EQ_RE_EST_8 +161 0x0800 //TX_MIN_EQ_RE_EST_9 +162 0x0800 //TX_MIN_EQ_RE_EST_10 +163 0x0800 //TX_MIN_EQ_RE_EST_11 +164 0x0800 //TX_MIN_EQ_RE_EST_12 +165 0x4000 //TX_LAMBDA_RE_EST +166 0x2000 //TX_LAMBDA_CB_NLE +167 0x6000 //TX_C_POST_FLT +168 0x7000 //TX_GAIN_NP +169 0x00C8 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x03E8 //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x7800 //TX_DTD_THR1_0 +198 0x7000 //TX_DTD_THR1_1 +199 0x7FFF //TX_DTD_THR1_2 +200 0x7FFF //TX_DTD_THR1_3 +201 0x7FFF //TX_DTD_THR1_4 +202 0x7FFF //TX_DTD_THR1_5 +203 0x7FFF //TX_DTD_THR1_6 +204 0x7FFF //TX_DTD_THR2_0 +205 0x7FFF //TX_DTD_THR2_1 +206 0x7FFF //TX_DTD_THR2_2 +207 0x7FFF //TX_DTD_THR2_3 +208 0x7FFF //TX_DTD_THR2_4 +209 0x7FFF //TX_DTD_THR2_5 +210 0x7FFF //TX_DTD_THR2_6 +211 0x1000 //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x0BB8 //TX_DT_CUT_K +214 0x0CCD //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x0400 //TX_ADPT_STRICT_L +222 0x0200 //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x0800 //TX_B_POST_FILT_ECHO_L +229 0x7FFF //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x7FFF //TX_B_LESSCUT_RTO_ECHO +232 0x00F0 //TX_EPD_OFFSET_00 +233 0x00F0 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x7FFF //TX_DTD_THR1_7 +238 0x7FFF //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xF400 //TX_THR_SN_EST_0 +243 0xF400 //TX_THR_SN_EST_1 +244 0xF600 //TX_THR_SN_EST_2 +245 0xF400 //TX_THR_SN_EST_3 +246 0xF400 //TX_THR_SN_EST_4 +247 0xF400 //TX_THR_SN_EST_5 +248 0xF400 //TX_THR_SN_EST_6 +249 0xF600 //TX_THR_SN_EST_7 +250 0x0000 //TX_DELTA_THR_SN_EST_0 +251 0x0200 //TX_DELTA_THR_SN_EST_1 +252 0x0200 //TX_DELTA_THR_SN_EST_2 +253 0x0200 //TX_DELTA_THR_SN_EST_3 +254 0x0200 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0000 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x6000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x6000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x1000 //TX_B_POST_FLT_0 +280 0x1000 //TX_B_POST_FLT_1 +281 0x000B //TX_NS_LVL_CTRL_0 +282 0x0011 //TX_NS_LVL_CTRL_1 +283 0x000F //TX_NS_LVL_CTRL_2 +284 0x000F //TX_NS_LVL_CTRL_3 +285 0x000F //TX_NS_LVL_CTRL_4 +286 0x000F //TX_NS_LVL_CTRL_5 +287 0x000F //TX_NS_LVL_CTRL_6 +288 0x0011 //TX_NS_LVL_CTRL_7 +289 0x000C //TX_MIN_GAIN_S_0 +290 0x000F //TX_MIN_GAIN_S_1 +291 0x000C //TX_MIN_GAIN_S_2 +292 0x000C //TX_MIN_GAIN_S_3 +293 0x000C //TX_MIN_GAIN_S_4 +294 0x000C //TX_MIN_GAIN_S_5 +295 0x000C //TX_MIN_GAIN_S_6 +296 0x000F //TX_MIN_GAIN_S_7 +297 0x7FFF //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x7FFF //TX_SNRI_SUP_1 +302 0x7FFF //TX_SNRI_SUP_2 +303 0x7FFF //TX_SNRI_SUP_3 +304 0x7FFF //TX_SNRI_SUP_4 +305 0x7FFF //TX_SNRI_SUP_5 +306 0x7FFF //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x000E //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x2000 //TX_A_POST_FILT_S_0 +315 0x5000 //TX_A_POST_FILT_S_1 +316 0x5000 //TX_A_POST_FILT_S_2 +317 0x5000 //TX_A_POST_FILT_S_3 +318 0x5000 //TX_A_POST_FILT_S_4 +319 0x5000 //TX_A_POST_FILT_S_5 +320 0x4000 //TX_A_POST_FILT_S_6 +321 0x5000 //TX_A_POST_FILT_S_7 +322 0x1000 //TX_B_POST_FILT_0 +323 0x1000 //TX_B_POST_FILT_1 +324 0x1000 //TX_B_POST_FILT_2 +325 0x1000 //TX_B_POST_FILT_3 +326 0x1000 //TX_B_POST_FILT_4 +327 0x1000 //TX_B_POST_FILT_5 +328 0x1000 //TX_B_POST_FILT_6 +329 0x1000 //TX_B_POST_FILT_7 +330 0x7FFF //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x7FFF //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7900 //TX_LAMBDA_PFILT +339 0x7B00 //TX_LAMBDA_PFILT_S_0 +340 0x7B00 //TX_LAMBDA_PFILT_S_1 +341 0x7B00 //TX_LAMBDA_PFILT_S_2 +342 0x7B00 //TX_LAMBDA_PFILT_S_3 +343 0x7B00 //TX_LAMBDA_PFILT_S_4 +344 0x7B00 //TX_LAMBDA_PFILT_S_5 +345 0x7B00 //TX_LAMBDA_PFILT_S_6 +346 0x7B00 //TX_LAMBDA_PFILT_S_7 +347 0x0000 //TX_K_PEPPER +348 0x0800 //TX_A_PEPPER +349 0x1EAA //TX_K_PEPPER_HF +350 0x0800 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0800 //TX_DT_BINVAD_TH_0 +354 0x0800 //TX_DT_BINVAD_TH_1 +355 0x0800 //TX_DT_BINVAD_TH_2 +356 0x0800 //TX_DT_BINVAD_TH_3 +357 0x1D4C //TX_DT_BINVAD_ENDF +358 0x0000 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0190 //TX_NDETCT +367 0x0050 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x07D0 //TX_NOISE_TH_1 +371 0x00C8 //TX_NOISE_TH_2 +372 0x3A98 //TX_NOISE_TH_3 +373 0x0FA0 //TX_NOISE_TH_4 +374 0x157C //TX_NOISE_TH_5 +375 0x7FFF //TX_NOISE_TH_5_2 +376 0x7FFF //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x044C //TX_NOISE_TH_6 +379 0x0014 //TX_MINENOISE_TH +380 0x4000 //TX_MORENS_TFMASK_TH +381 0xFFEE //TX_DRC_QUIET_FLOOR +382 0x6000 //TX_RATIODTL_CUT_TH +383 0xFFF3 //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x0333 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x0000 //TX_POST_MASK_SUP_HSNE +392 0x0000 //TX_TAIL_DET_TH +393 0x0000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0800 //TX_SUPHIGH_TH +396 0x00C8 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x0800 //TX_C_POST_FLT_MASK +399 0x0005 //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0002 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x0014 //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x2900 //TX_MIN_G_CTRL_SSNS +409 0x0800 //TX_METAL_RTO_THR +410 0x4848 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x4000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x01E0 //TX_NOR_OFF_THR +498 0x7C00 //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0xD333 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x6000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0x0000 //TX_DEREVERB_LF_MU +515 0x0000 //TX_DEREVERB_HF_MU +516 0x0000 //TX_DEREVERB_DELAY +517 0x0000 //TX_DEREVERB_COEF_LEN +518 0x0000 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x0000 //TX_GSC_RTOH_TH +523 0x0000 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0020 //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4848 //TX_FDEQ_GAIN_5 +573 0x4848 //TX_FDEQ_GAIN_6 +574 0x4848 //TX_FDEQ_GAIN_7 +575 0x4848 //TX_FDEQ_GAIN_8 +576 0x4848 //TX_FDEQ_GAIN_9 +577 0x4848 //TX_FDEQ_GAIN_10 +578 0x4848 //TX_FDEQ_GAIN_11 +579 0x4848 //TX_FDEQ_GAIN_12 +580 0x4848 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0303 //TX_FDEQ_BIN_2 +594 0x0304 //TX_FDEQ_BIN_3 +595 0x0405 //TX_FDEQ_BIN_4 +596 0x0506 //TX_FDEQ_BIN_5 +597 0x0708 //TX_FDEQ_BIN_6 +598 0x090A //TX_FDEQ_BIN_7 +599 0x0B0C //TX_FDEQ_BIN_8 +600 0x0D0E //TX_FDEQ_BIN_9 +601 0x1013 //TX_FDEQ_BIN_10 +602 0x1719 //TX_FDEQ_BIN_11 +603 0x1B1E //TX_FDEQ_BIN_12 +604 0x1E1E //TX_FDEQ_BIN_13 +605 0x1E28 //TX_FDEQ_BIN_14 +606 0x282C //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4868 //TX_PREEQ_GAIN_MIC0_8 +626 0x6860 //TX_PREEQ_GAIN_MIC0_9 +627 0x6048 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0E10 //TX_PREEQ_BIN_MIC0_0 +642 0x1010 //TX_PREEQ_BIN_MIC0_1 +643 0x1010 //TX_PREEQ_BIN_MIC0_2 +644 0x1010 //TX_PREEQ_BIN_MIC0_3 +645 0x1010 //TX_PREEQ_BIN_MIC0_4 +646 0x1010 //TX_PREEQ_BIN_MIC0_5 +647 0x1010 //TX_PREEQ_BIN_MIC0_6 +648 0x1010 //TX_PREEQ_BIN_MIC0_7 +649 0x1010 //TX_PREEQ_BIN_MIC0_8 +650 0x1010 //TX_PREEQ_BIN_MIC0_9 +651 0x1010 //TX_PREEQ_BIN_MIC0_10 +652 0x1010 //TX_PREEQ_BIN_MIC0_11 +653 0x1010 //TX_PREEQ_BIN_MIC0_12 +654 0x1010 //TX_PREEQ_BIN_MIC0_13 +655 0x1010 //TX_PREEQ_BIN_MIC0_14 +656 0x0200 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0E10 //TX_PREEQ_BIN_MIC1_0 +691 0x1010 //TX_PREEQ_BIN_MIC1_1 +692 0x1010 //TX_PREEQ_BIN_MIC1_2 +693 0x1010 //TX_PREEQ_BIN_MIC1_3 +694 0x1010 //TX_PREEQ_BIN_MIC1_4 +695 0x1010 //TX_PREEQ_BIN_MIC1_5 +696 0x1010 //TX_PREEQ_BIN_MIC1_6 +697 0x1010 //TX_PREEQ_BIN_MIC1_7 +698 0x1010 //TX_PREEQ_BIN_MIC1_8 +699 0x1010 //TX_PREEQ_BIN_MIC1_9 +700 0x1010 //TX_PREEQ_BIN_MIC1_10 +701 0x1010 //TX_PREEQ_BIN_MIC1_11 +702 0x1010 //TX_PREEQ_BIN_MIC1_12 +703 0x1010 //TX_PREEQ_BIN_MIC1_13 +704 0x1010 //TX_PREEQ_BIN_MIC1_14 +705 0x0200 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0E10 //TX_PREEQ_BIN_MIC2_0 +740 0x1010 //TX_PREEQ_BIN_MIC2_1 +741 0x1010 //TX_PREEQ_BIN_MIC2_2 +742 0x1010 //TX_PREEQ_BIN_MIC2_3 +743 0x1010 //TX_PREEQ_BIN_MIC2_4 +744 0x1010 //TX_PREEQ_BIN_MIC2_5 +745 0x1010 //TX_PREEQ_BIN_MIC2_6 +746 0x1010 //TX_PREEQ_BIN_MIC2_7 +747 0x1010 //TX_PREEQ_BIN_MIC2_8 +748 0x1010 //TX_PREEQ_BIN_MIC2_9 +749 0x1010 //TX_PREEQ_BIN_MIC2_10 +750 0x1010 //TX_PREEQ_BIN_MIC2_11 +751 0x1010 //TX_PREEQ_BIN_MIC2_12 +752 0x1010 //TX_PREEQ_BIN_MIC2_13 +753 0x1010 //TX_PREEQ_BIN_MIC2_14 +754 0x0200 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x0800 //TX_NND_WEIGHT +765 0x0062 //TX_MIC_CALIBRATION_0 +766 0x0062 //TX_MIC_CALIBRATION_1 +767 0x0062 //TX_MIC_CALIBRATION_2 +768 0x0062 //TX_MIC_CALIBRATION_3 +769 0x0046 //TX_MIC_PWR_BIAS_0 +770 0x0046 //TX_MIC_PWR_BIAS_1 +771 0x0046 //TX_MIC_PWR_BIAS_2 +772 0x0046 //TX_MIC_PWR_BIAS_3 +773 0x000C //TX_GAIN_LIMIT_0 +774 0x000C //TX_GAIN_LIMIT_1 +775 0x000C //TX_GAIN_LIMIT_2 +776 0x000C //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x3000 //TX_TDDRC_ALPHA_UP_01 +784 0x3000 //TX_TDDRC_ALPHA_UP_02 +785 0x3000 //TX_TDDRC_ALPHA_UP_03 +786 0x3000 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x78D6 //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0000 //TX_DEADMIC_SILENCE_TH +817 0x0000 //TX_MIC_DEGRADE_TH +818 0x0000 //TX_DEADMIC_CNT +819 0x0000 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x4848 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0000 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0000 //TX_FILTINDX +854 0x0000 //TX_TDDRC_THRD_0 +855 0x0000 //TX_TDDRC_THRD_1 +856 0x2000 //TX_TDDRC_THRD_2 +857 0x2000 //TX_TDDRC_THRD_3 +858 0x3000 //TX_TDDRC_SLANT_0 +859 0x6E00 //TX_TDDRC_SLANT_1 +860 0x3000 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x0970 //TX_TDDRC_DRC_GAIN +867 0x78D6 //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x0028 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x1000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x0000 //TX_SENDFUNC_REG_MICMUTE +898 0x0000 //TX_SENDFUNC_REG_MICMUTE1 +899 0x0000 //TX_MICMUTE_RATIO_THR +900 0x0000 //TX_MICMUTE_AMP_THR +901 0x0000 //TX_MICMUTE_HPF_IND +902 0x0000 //TX_MICMUTE_LOG_EYR_TH +903 0x0000 //TX_MICMUTE_CVG_TIME +904 0x0000 //TX_MICMUTE_RELEASE_TIME +905 0x0000 //TX_MIC_VOLUME_MIC0MUTE +906 0x0000 //TX_MICMUTE_EPD_OFFSET_0 +907 0x0000 //TX_MICMUTE_FRQ_AEC_L +908 0x0000 //TX_MICMUTE_EAD_THR +909 0x0000 //TX_MICMUTE_LAMBDA_CB_NLE +910 0x0000 //TX_MICMUTE_LAMBDA_RE_EST +911 0x0000 //TX_DTD_THR1_MICMUTE_0 +912 0x0000 //TX_DTD_THR1_MICMUTE_1 +913 0x0000 //TX_DTD_THR1_MICMUTE_2 +914 0x0000 //TX_DTD_THR1_MICMUTE_3 +915 0x0000 //TX_DTD_THR2_MICMUTE_0 +916 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x0000 //TX_MICMUTE_C_POST_FLT +922 0x0000 //TX_MICMUTE_DT_CUT_K +923 0x0000 //TX_MICMUTE_DT_CUT_THR +924 0x0000 //TX_MICMUTE_DT_CUT_K2 +925 0x0000 //TX_MICMUTE_DT_CUT_THR2 +926 0x0000 //TX_MICMUTE_DT2_HOLD_N +927 0x0000 //TX_MICMUTE_RATIODTH_THCUT +928 0x0000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x0000 //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0000 //TX_MICMUTE_C_POST_FLT_MASK +931 0x0000 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0000 //TX_MICMUTE_DT_CUT_K1 +933 0x0000 //TX_MICMUTE_N2_SN_EST +934 0x0000 //TX_MICMUTE_THR_SN_EST_0 +935 0x0000 //TX_MICMUTE_MIN_G_CTRL_0 +936 0x0000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x0000 //TX_MICMUTE_B_POST_FILT_0 +938 0x0000 //TX_MIC1RUB_AMP_THR +939 0x0000 //TX_MIC1MUTE_RATIO_THR +940 0x0000 //TX_MIC1MUTE_AMP_THR +941 0x0000 //TX_MIC1MUTE_CVG_TIME +942 0x0000 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x2064 //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0003 //RX_SAMPLINGFREQ_SIG +3 0x0003 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7FFF //RX_A_HP +12 0x0000 //RX_B_PE +13 0x1800 //RX_THR_PITCH_DET_0 +14 0x1000 //RX_THR_PITCH_DET_1 +15 0x0800 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0400 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x0003 //RX_NS_LVL_CTRL +23 0x9000 //RX_THR_SN_EST +24 0x7CCD //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0000 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x2000 //RX_MIN_G_FP +128 0x0080 //RX_MAX_G_FP +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x2064 //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0003 //RX_SAMPLINGFREQ_SIG +160 0x0003 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7FFF //RX_A_HP +169 0x0000 //RX_B_PE +170 0x1800 //RX_THR_PITCH_DET_0 +171 0x1000 //RX_THR_PITCH_DET_1 +172 0x0800 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0400 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x0003 //RX_NS_LVL_CTRL +180 0x9000 //RX_THR_SN_EST +181 0x7CCD //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0000 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x2000 //RX_MIN_G_FP +285 0x0080 //RX_MAX_G_FP +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME BLUETOOTH-BTWB_NREC-VOICE_GENERIC-FB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0009 //TX_OPERATION_MODE_0 +1 0x0009 //TX_OPERATION_MODE_1 +2 0x0020 //TX_PATCH_REG +3 0x286A //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0001 //TX_NUM_MIC +6 0x0004 //TX_SAMPLINGFREQ_SIG +7 0x0004 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009B //TX_DIST2REF1 +22 0x0000 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0915 //TX_PGA_0 +28 0x0800 //TX_PGA_1 +29 0x0000 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0000 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0001 //TX_MIC_DATA_SRC1 +43 0x0002 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3E00 //TX_DIST2REF_11 +73 0x0000 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0200 //TX_MIC_REFBLK_VOLUME +108 0x0800 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0000 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7E56 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x6800 //TX_THR_PITCH_DET_0 +131 0x6000 //TX_THR_PITCH_DET_1 +132 0x5800 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x001E //TX_TAIL_LENGTH +147 0x0200 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x6000 //TX_EAD_THR +151 0x0400 //TX_THR_RE_EST +152 0x3000 //TX_MIN_EQ_RE_EST_0 +153 0x3000 //TX_MIN_EQ_RE_EST_1 +154 0x4000 //TX_MIN_EQ_RE_EST_2 +155 0x0800 //TX_MIN_EQ_RE_EST_3 +156 0x0800 //TX_MIN_EQ_RE_EST_4 +157 0x0800 //TX_MIN_EQ_RE_EST_5 +158 0x6000 //TX_MIN_EQ_RE_EST_6 +159 0x6000 //TX_MIN_EQ_RE_EST_7 +160 0x6000 //TX_MIN_EQ_RE_EST_8 +161 0x6000 //TX_MIN_EQ_RE_EST_9 +162 0x4000 //TX_MIN_EQ_RE_EST_10 +163 0x4000 //TX_MIN_EQ_RE_EST_11 +164 0x4000 //TX_MIN_EQ_RE_EST_12 +165 0x3000 //TX_LAMBDA_RE_EST +166 0x4000 //TX_LAMBDA_CB_NLE +167 0x3000 //TX_C_POST_FLT +168 0x4500 //TX_GAIN_NP +169 0x00C8 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x03E8 //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x5000 //TX_DTD_THR1_0 +198 0x7000 //TX_DTD_THR1_1 +199 0x7F00 //TX_DTD_THR1_2 +200 0x7FFF //TX_DTD_THR1_3 +201 0x7FFF //TX_DTD_THR1_4 +202 0x7FFF //TX_DTD_THR1_5 +203 0x7FFF //TX_DTD_THR1_6 +204 0x0800 //TX_DTD_THR2_0 +205 0x0800 //TX_DTD_THR2_1 +206 0x0800 //TX_DTD_THR2_2 +207 0x0800 //TX_DTD_THR2_3 +208 0x0800 //TX_DTD_THR2_4 +209 0x0100 //TX_DTD_THR2_5 +210 0x0100 //TX_DTD_THR2_6 +211 0x7FFF //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x03E8 //TX_DT_CUT_K +214 0x0CCD //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x0400 //TX_ADPT_STRICT_L +222 0x0200 //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x0800 //TX_B_POST_FILT_ECHO_L +229 0x7FFF //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x7FFF //TX_B_LESSCUT_RTO_ECHO +232 0x00C0 //TX_EPD_OFFSET_00 +233 0x00C0 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x7FFF //TX_DTD_THR1_7 +238 0x7FFF //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xF700 //TX_THR_SN_EST_0 +243 0xFB00 //TX_THR_SN_EST_1 +244 0xFA00 //TX_THR_SN_EST_2 +245 0xF700 //TX_THR_SN_EST_3 +246 0xFA00 //TX_THR_SN_EST_4 +247 0xF600 //TX_THR_SN_EST_5 +248 0xF600 //TX_THR_SN_EST_6 +249 0xF600 //TX_THR_SN_EST_7 +250 0x0200 //TX_DELTA_THR_SN_EST_0 +251 0x0400 //TX_DELTA_THR_SN_EST_1 +252 0x0300 //TX_DELTA_THR_SN_EST_2 +253 0x0600 //TX_DELTA_THR_SN_EST_3 +254 0x0200 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0200 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x4000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x4000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x2000 //TX_B_POST_FLT_0 +280 0x2000 //TX_B_POST_FLT_1 +281 0x0012 //TX_NS_LVL_CTRL_0 +282 0x0016 //TX_NS_LVL_CTRL_1 +283 0x0016 //TX_NS_LVL_CTRL_2 +284 0x0019 //TX_NS_LVL_CTRL_3 +285 0x0010 //TX_NS_LVL_CTRL_4 +286 0x0010 //TX_NS_LVL_CTRL_5 +287 0x0019 //TX_NS_LVL_CTRL_6 +288 0x0010 //TX_NS_LVL_CTRL_7 +289 0x000C //TX_MIN_GAIN_S_0 +290 0x000C //TX_MIN_GAIN_S_1 +291 0x000C //TX_MIN_GAIN_S_2 +292 0x000F //TX_MIN_GAIN_S_3 +293 0x000C //TX_MIN_GAIN_S_4 +294 0x000C //TX_MIN_GAIN_S_5 +295 0x0011 //TX_MIN_GAIN_S_6 +296 0x000C //TX_MIN_GAIN_S_7 +297 0x7FFF //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7000 //TX_SNRI_SUP_0 +301 0x7000 //TX_SNRI_SUP_1 +302 0x7000 //TX_SNRI_SUP_2 +303 0x6000 //TX_SNRI_SUP_3 +304 0x7FFF //TX_SNRI_SUP_4 +305 0x7FFF //TX_SNRI_SUP_5 +306 0x6000 //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x0016 //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x6000 //TX_A_POST_FILT_S_0 +315 0x6000 //TX_A_POST_FILT_S_1 +316 0x6000 //TX_A_POST_FILT_S_2 +317 0x6000 //TX_A_POST_FILT_S_3 +318 0x6000 //TX_A_POST_FILT_S_4 +319 0x6000 //TX_A_POST_FILT_S_5 +320 0x6000 //TX_A_POST_FILT_S_6 +321 0x6000 //TX_A_POST_FILT_S_7 +322 0x2000 //TX_B_POST_FILT_0 +323 0x4000 //TX_B_POST_FILT_1 +324 0x2000 //TX_B_POST_FILT_2 +325 0x2000 //TX_B_POST_FILT_3 +326 0x2000 //TX_B_POST_FILT_4 +327 0x2000 //TX_B_POST_FILT_5 +328 0x2000 //TX_B_POST_FILT_6 +329 0x2000 //TX_B_POST_FILT_7 +330 0x7FFF //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x7FFF //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7CCD //TX_LAMBDA_PFILT +339 0x7CCD //TX_LAMBDA_PFILT_S_0 +340 0x7CCD //TX_LAMBDA_PFILT_S_1 +341 0x7CCD //TX_LAMBDA_PFILT_S_2 +342 0x7CCD //TX_LAMBDA_PFILT_S_3 +343 0x7CCD //TX_LAMBDA_PFILT_S_4 +344 0x7CCD //TX_LAMBDA_PFILT_S_5 +345 0x7CCD //TX_LAMBDA_PFILT_S_6 +346 0x7CCD //TX_LAMBDA_PFILT_S_7 +347 0x0200 //TX_K_PEPPER +348 0x0500 //TX_A_PEPPER +349 0x1600 //TX_K_PEPPER_HF +350 0x0400 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0800 //TX_DT_BINVAD_TH_0 +354 0x0800 //TX_DT_BINVAD_TH_1 +355 0x0800 //TX_DT_BINVAD_TH_2 +356 0x0800 //TX_DT_BINVAD_TH_3 +357 0x1D4C //TX_DT_BINVAD_ENDF +358 0x0000 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0190 //TX_NDETCT +367 0x0020 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x02A6 //TX_NOISE_TH_1 +371 0x04B0 //TX_NOISE_TH_2 +372 0x3194 //TX_NOISE_TH_3 +373 0x0960 //TX_NOISE_TH_4 +374 0x5555 //TX_NOISE_TH_5 +375 0x3FF4 //TX_NOISE_TH_5_2 +376 0x0001 //TX_NOISE_TH_5_3 +377 0x0000 //TX_NOISE_TH_5_4 +378 0x02BC //TX_NOISE_TH_6 +379 0x0020 //TX_MINENOISE_TH +380 0x4000 //TX_MORENS_TFMASK_TH +381 0xFFEE //TX_DRC_QUIET_FLOOR +382 0x6000 //TX_RATIODTL_CUT_TH +383 0xFFF3 //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x0333 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x0000 //TX_POST_MASK_SUP_HSNE +392 0x0000 //TX_TAIL_DET_TH +393 0x0000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0800 //TX_SUPHIGH_TH +396 0x00C8 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x0800 //TX_C_POST_FLT_MASK +399 0x0005 //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0002 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x0020 //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x2900 //TX_MIN_G_CTRL_SSNS +409 0x0800 //TX_METAL_RTO_THR +410 0x4848 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x4000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x01E0 //TX_NOR_OFF_THR +498 0x7C00 //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0xD333 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x6000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0x0000 //TX_DEREVERB_LF_MU +515 0x0000 //TX_DEREVERB_HF_MU +516 0x0000 //TX_DEREVERB_DELAY +517 0x0000 //TX_DEREVERB_COEF_LEN +518 0x0000 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x0000 //TX_GSC_RTOH_TH +523 0x0000 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0020 //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4848 //TX_FDEQ_GAIN_5 +573 0x4848 //TX_FDEQ_GAIN_6 +574 0x4848 //TX_FDEQ_GAIN_7 +575 0x4848 //TX_FDEQ_GAIN_8 +576 0x4848 //TX_FDEQ_GAIN_9 +577 0x4848 //TX_FDEQ_GAIN_10 +578 0x4848 //TX_FDEQ_GAIN_11 +579 0x4848 //TX_FDEQ_GAIN_12 +580 0x4848 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0304 //TX_FDEQ_BIN_2 +594 0x0405 //TX_FDEQ_BIN_3 +595 0x0607 //TX_FDEQ_BIN_4 +596 0x0809 //TX_FDEQ_BIN_5 +597 0x0A0B //TX_FDEQ_BIN_6 +598 0x0C0D //TX_FDEQ_BIN_7 +599 0x0E0F //TX_FDEQ_BIN_8 +600 0x1011 //TX_FDEQ_BIN_9 +601 0x1214 //TX_FDEQ_BIN_10 +602 0x1618 //TX_FDEQ_BIN_11 +603 0x1C1C //TX_FDEQ_BIN_12 +604 0x2020 //TX_FDEQ_BIN_13 +605 0x2020 //TX_FDEQ_BIN_14 +606 0x2011 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4848 //TX_PREEQ_GAIN_MIC0_8 +626 0x4848 //TX_PREEQ_GAIN_MIC0_9 +627 0x4848 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0E10 //TX_PREEQ_BIN_MIC0_0 +642 0x1010 //TX_PREEQ_BIN_MIC0_1 +643 0x1010 //TX_PREEQ_BIN_MIC0_2 +644 0x1010 //TX_PREEQ_BIN_MIC0_3 +645 0x1010 //TX_PREEQ_BIN_MIC0_4 +646 0x1010 //TX_PREEQ_BIN_MIC0_5 +647 0x1010 //TX_PREEQ_BIN_MIC0_6 +648 0x1010 //TX_PREEQ_BIN_MIC0_7 +649 0x1010 //TX_PREEQ_BIN_MIC0_8 +650 0x1010 //TX_PREEQ_BIN_MIC0_9 +651 0x1010 //TX_PREEQ_BIN_MIC0_10 +652 0x1010 //TX_PREEQ_BIN_MIC0_11 +653 0x1010 //TX_PREEQ_BIN_MIC0_12 +654 0x1010 //TX_PREEQ_BIN_MIC0_13 +655 0x1010 //TX_PREEQ_BIN_MIC0_14 +656 0x0200 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0E10 //TX_PREEQ_BIN_MIC1_0 +691 0x1010 //TX_PREEQ_BIN_MIC1_1 +692 0x1010 //TX_PREEQ_BIN_MIC1_2 +693 0x1010 //TX_PREEQ_BIN_MIC1_3 +694 0x1010 //TX_PREEQ_BIN_MIC1_4 +695 0x1010 //TX_PREEQ_BIN_MIC1_5 +696 0x1010 //TX_PREEQ_BIN_MIC1_6 +697 0x1010 //TX_PREEQ_BIN_MIC1_7 +698 0x1010 //TX_PREEQ_BIN_MIC1_8 +699 0x1010 //TX_PREEQ_BIN_MIC1_9 +700 0x1010 //TX_PREEQ_BIN_MIC1_10 +701 0x1010 //TX_PREEQ_BIN_MIC1_11 +702 0x1010 //TX_PREEQ_BIN_MIC1_12 +703 0x1010 //TX_PREEQ_BIN_MIC1_13 +704 0x1010 //TX_PREEQ_BIN_MIC1_14 +705 0x0200 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0E10 //TX_PREEQ_BIN_MIC2_0 +740 0x1010 //TX_PREEQ_BIN_MIC2_1 +741 0x1010 //TX_PREEQ_BIN_MIC2_2 +742 0x1010 //TX_PREEQ_BIN_MIC2_3 +743 0x1010 //TX_PREEQ_BIN_MIC2_4 +744 0x1010 //TX_PREEQ_BIN_MIC2_5 +745 0x1010 //TX_PREEQ_BIN_MIC2_6 +746 0x1010 //TX_PREEQ_BIN_MIC2_7 +747 0x1010 //TX_PREEQ_BIN_MIC2_8 +748 0x1010 //TX_PREEQ_BIN_MIC2_9 +749 0x1010 //TX_PREEQ_BIN_MIC2_10 +750 0x1010 //TX_PREEQ_BIN_MIC2_11 +751 0x1010 //TX_PREEQ_BIN_MIC2_12 +752 0x1010 //TX_PREEQ_BIN_MIC2_13 +753 0x1010 //TX_PREEQ_BIN_MIC2_14 +754 0x0200 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x2000 //TX_NND_WEIGHT +765 0x0060 //TX_MIC_CALIBRATION_0 +766 0x0060 //TX_MIC_CALIBRATION_1 +767 0x0070 //TX_MIC_CALIBRATION_2 +768 0x0070 //TX_MIC_CALIBRATION_3 +769 0x0050 //TX_MIC_PWR_BIAS_0 +770 0x0040 //TX_MIC_PWR_BIAS_1 +771 0x0040 //TX_MIC_PWR_BIAS_2 +772 0x0040 //TX_MIC_PWR_BIAS_3 +773 0x0009 //TX_GAIN_LIMIT_0 +774 0x000F //TX_GAIN_LIMIT_1 +775 0x000F //TX_GAIN_LIMIT_2 +776 0x000F //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x0C00 //TX_TDDRC_ALPHA_UP_01 +784 0x0C00 //TX_TDDRC_ALPHA_UP_02 +785 0x0C00 //TX_TDDRC_ALPHA_UP_03 +786 0x0C00 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x7FFF //TX_TDDRC_TD_DRC_LIMIT +792 0x2000 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0000 //TX_DEADMIC_SILENCE_TH +817 0x0000 //TX_MIC_DEGRADE_TH +818 0x0000 //TX_DEADMIC_CNT +819 0x0000 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x4848 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0000 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0002 //TX_FILTINDX +854 0x0001 //TX_TDDRC_THRD_0 +855 0x0001 //TX_TDDRC_THRD_1 +856 0x1900 //TX_TDDRC_THRD_2 +857 0x1900 //TX_TDDRC_THRD_3 +858 0x3000 //TX_TDDRC_SLANT_0 +859 0x7B00 //TX_TDDRC_SLANT_1 +860 0x0C00 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x0200 //TX_TDDRC_DRC_GAIN +867 0x7FFF //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x0028 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x7000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x0000 //TX_SENDFUNC_REG_MICMUTE +898 0x0000 //TX_SENDFUNC_REG_MICMUTE1 +899 0x0000 //TX_MICMUTE_RATIO_THR +900 0x0000 //TX_MICMUTE_AMP_THR +901 0x0000 //TX_MICMUTE_HPF_IND +902 0x0000 //TX_MICMUTE_LOG_EYR_TH +903 0x0000 //TX_MICMUTE_CVG_TIME +904 0x0000 //TX_MICMUTE_RELEASE_TIME +905 0x0000 //TX_MIC_VOLUME_MIC0MUTE +906 0x0000 //TX_MICMUTE_EPD_OFFSET_0 +907 0x0000 //TX_MICMUTE_FRQ_AEC_L +908 0x0000 //TX_MICMUTE_EAD_THR +909 0x0000 //TX_MICMUTE_LAMBDA_CB_NLE +910 0x0000 //TX_MICMUTE_LAMBDA_RE_EST +911 0x0000 //TX_DTD_THR1_MICMUTE_0 +912 0x0000 //TX_DTD_THR1_MICMUTE_1 +913 0x0000 //TX_DTD_THR1_MICMUTE_2 +914 0x0000 //TX_DTD_THR1_MICMUTE_3 +915 0x0000 //TX_DTD_THR2_MICMUTE_0 +916 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x0000 //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x0000 //TX_MICMUTE_C_POST_FLT +922 0x0000 //TX_MICMUTE_DT_CUT_K +923 0x0000 //TX_MICMUTE_DT_CUT_THR +924 0x0000 //TX_MICMUTE_DT_CUT_K2 +925 0x0000 //TX_MICMUTE_DT_CUT_THR2 +926 0x0000 //TX_MICMUTE_DT2_HOLD_N +927 0x0000 //TX_MICMUTE_RATIODTH_THCUT +928 0x0000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x0000 //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0000 //TX_MICMUTE_C_POST_FLT_MASK +931 0x0000 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0000 //TX_MICMUTE_DT_CUT_K1 +933 0x0000 //TX_MICMUTE_N2_SN_EST +934 0x0000 //TX_MICMUTE_THR_SN_EST_0 +935 0x0000 //TX_MICMUTE_MIN_G_CTRL_0 +936 0x0000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x0000 //TX_MICMUTE_B_POST_FILT_0 +938 0x0000 //TX_MIC1RUB_AMP_THR +939 0x0000 //TX_MIC1MUTE_RATIO_THR +940 0x0000 //TX_MIC1MUTE_AMP_THR +941 0x0000 //TX_MIC1MUTE_CVG_TIME +942 0x0000 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x2064 //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0004 //RX_SAMPLINGFREQ_SIG +3 0x0004 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7FFF //RX_A_HP +12 0x4000 //RX_B_PE +13 0x7800 //RX_THR_PITCH_DET_0 +14 0x7000 //RX_THR_PITCH_DET_1 +15 0x6000 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0500 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x000A //RX_NS_LVL_CTRL +23 0xF600 //RX_THR_SN_EST +24 0x7000 //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0000 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x2000 //RX_MIN_G_FP +128 0x0080 //RX_MAX_G_FP +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x7FFF //RX_TDDRC_THRD_2 +115 0x7FFF //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0155 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x0064 //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0004 //RX_SAMPLINGFREQ_SIG +160 0x0004 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7FFF //RX_A_HP +169 0x4000 //RX_B_PE +170 0x7800 //RX_THR_PITCH_DET_0 +171 0x7000 //RX_THR_PITCH_DET_1 +172 0x6000 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0500 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x000A //RX_NS_LVL_CTRL +180 0xF600 //RX_THR_SN_EST +181 0x7000 //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0000 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x2000 //RX_MIN_G_FP +285 0x0080 //RX_MAX_G_FP +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x7FFF //RX_TDDRC_THRD_2 +272 0x7FFF //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0155 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + diff --git a/audio/tegu/tuning/fortemedia/HANDSET.dat b/audio/tegu/tuning/fortemedia/HANDSET.dat new file mode 100644 index 0000000000000000000000000000000000000000..9c27e326e71f7cb757bf38123bf0bbecb384a990 GIT binary patch literal 202414 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zmRqs27^_PeliAoHTqc%WEm^Zc;8*@i z+RPc{+Dzws5jWaQcOln8o9S6d?#D%NJKO<_VF@gSa!+&eW)?@T;GC80+pEo76aLra z&6GtO@z&6~NZ{@cvzs`F-6rOnK3`q_W-W|nF*#k~XfuN%Z>Ai?(|o_YnVyztGgX;3vnHPAtLjfCXJ%R6%=bp_tIc$^tzF*C zLuoTB@@DEPJk9OAneV7k@-A_F4=v^U=p&C_-poDPOm~^5`Tp9>l7fA;nP{{BC-P=i zXfwTNGriujyqR8K3iY1Q3wnb`j~?Ae&z#&>7tZXb*A%AeHEa4q^|hG}Jk3KKLv>i_ zFm!-fx?aR^T|aV!j%sikIU2KdO!P<{+hmlEj~}hw?i?7S8@m6zHZ#q8K0e^NIwSJ} zbc`30!*Me8DY`43=Gk4RYJcvbgxY(WyBd6@!0Z{`P4M@O5PSXrCtvbC9q%bQuhLYpaK_y$ z5sc$$#%*PrSQ%-K#`D{(;<>ZqzXgm*{?KlKQ90uBP2#PrD$(w0^ zKh){>!~WXL27A^{i)h#Fybs?2i&^I^VS6d>4R^vaSPm;#JFR5xbQkrzSv%cx*u0rB zrFk=dc$Br%V_frbGfzE%4s&mQ#LC*tl7i=0JMHUfzQ4vUcRy`rPHBFtoVBc-idj3o z&e~}mYp3<>+rYXBZKl6w+Dz@h(>&x;)=o!9o0)_*(^uKk{0QaERCt=}Qcv?(@@B@m z&}5>`JP&QAr)q8Hi`IeK%;*XYz+a`!+;47Go)@KB-HQ28o4(oe=J49gJ@K~Vz~8#+ z<-I)`&u_De=gy8poyMWH9fulgppM4#(AkbdP{d)N9fzQZ!=AjE_V+`bem_)bGye}+ CnaNlH literal 0 HcmV?d00001 diff --git a/audio/tegu/tuning/fortemedia/HANDSFREE.mods b/audio/tegu/tuning/fortemedia/HANDSFREE.mods new file mode 100644 index 0000000..acf77bd --- /dev/null +++ b/audio/tegu/tuning/fortemedia/HANDSFREE.mods @@ -0,0 +1,18695 @@ +#PLATFORM_NAME gChip +#EXPORT_FLAG HANDSFREE +#SINGLE_API_VER 1.2.0 +#SAVE_TIME 2022-02-10 16:25:23 + +#CASE_NAME HANDSFREE-HANDFREE-RESERVE1-FB +#PARAM_MODE FULL +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0001 //TX_OPERATION_MODE_0 +1 0x0001 //TX_OPERATION_MODE_1 +2 0x0033 //TX_PATCH_REG +3 0x6B54 //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0003 //TX_NUM_MIC +6 0x0004 //TX_SAMPLINGFREQ_SIG +7 0x0004 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009D //TX_DIST2REF1 +22 0x0010 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0A19 //TX_PGA_0 +28 0x0A19 //TX_PGA_1 +29 0x0A19 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0001 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0002 //TX_MIC_DATA_SRC0 +42 0x0000 //TX_MIC_DATA_SRC1 +43 0x0001 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3B33 //TX_DIST2REF_11 +73 0x0A70 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0800 //TX_MIC_REFBLK_VOLUME +108 0x0CAE //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0015 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7E56 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x1800 //TX_THR_PITCH_DET_0 +131 0x1000 //TX_THR_PITCH_DET_1 +132 0x0800 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x0028 //TX_TAIL_LENGTH +147 0x0300 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x7A00 //TX_EAD_THR +151 0x1000 //TX_THR_RE_EST +152 0x0800 //TX_MIN_EQ_RE_EST_0 +153 0x2000 //TX_MIN_EQ_RE_EST_1 +154 0x2000 //TX_MIN_EQ_RE_EST_2 +155 0x4000 //TX_MIN_EQ_RE_EST_3 +156 0x4000 //TX_MIN_EQ_RE_EST_4 +157 0x7FFF //TX_MIN_EQ_RE_EST_5 +158 0x7FFF //TX_MIN_EQ_RE_EST_6 +159 0x7FFF //TX_MIN_EQ_RE_EST_7 +160 0x7FFF //TX_MIN_EQ_RE_EST_8 +161 0x7FFF //TX_MIN_EQ_RE_EST_9 +162 0x7FFF //TX_MIN_EQ_RE_EST_10 +163 0x7FFF //TX_MIN_EQ_RE_EST_11 +164 0x7FFF //TX_MIN_EQ_RE_EST_12 +165 0x4000 //TX_LAMBDA_RE_EST +166 0x0CCD //TX_LAMBDA_CB_NLE +167 0x2000 //TX_C_POST_FLT +168 0x7FFF //TX_GAIN_NP +169 0x0180 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x09C4 //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x7D00 //TX_DTD_THR1_0 +198 0x7FF0 //TX_DTD_THR1_1 +199 0x7FF0 //TX_DTD_THR1_2 +200 0x7FF0 //TX_DTD_THR1_3 +201 0x7FF0 //TX_DTD_THR1_4 +202 0x7FF0 //TX_DTD_THR1_5 +203 0x7FF0 //TX_DTD_THR1_6 +204 0x0CCD //TX_DTD_THR2_0 +205 0x0CCD //TX_DTD_THR2_1 +206 0x0CCD //TX_DTD_THR2_2 +207 0x0CCD //TX_DTD_THR2_3 +208 0x0CCD //TX_DTD_THR2_4 +209 0x0CCD //TX_DTD_THR2_5 +210 0x0CCD //TX_DTD_THR2_6 +211 0x7FFF //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x0DAC //TX_DT_CUT_K +214 0x0020 //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x7FFF //TX_DTD_MIC_BLK +221 0x023E //TX_ADPT_STRICT_L +222 0x023E //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x2000 //TX_B_POST_FILT_ECHO_L +229 0x2000 //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x1000 //TX_B_LESSCUT_RTO_ECHO +232 0x0063 //TX_EPD_OFFSET_00 +233 0x0000 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x0000 //TX_DTD_THR1_7 +238 0x0000 //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xF800 //TX_THR_SN_EST_0 +243 0xFA00 //TX_THR_SN_EST_1 +244 0xFA00 //TX_THR_SN_EST_2 +245 0xFB00 //TX_THR_SN_EST_3 +246 0xFA00 //TX_THR_SN_EST_4 +247 0xFA00 //TX_THR_SN_EST_5 +248 0xF800 //TX_THR_SN_EST_6 +249 0xF800 //TX_THR_SN_EST_7 +250 0x0100 //TX_DELTA_THR_SN_EST_0 +251 0x0100 //TX_DELTA_THR_SN_EST_1 +252 0x0200 //TX_DELTA_THR_SN_EST_2 +253 0x0100 //TX_DELTA_THR_SN_EST_3 +254 0x0100 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0200 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x4000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x4000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x2000 //TX_B_POST_FLT_0 +280 0x1000 //TX_B_POST_FLT_1 +281 0x0010 //TX_NS_LVL_CTRL_0 +282 0x0014 //TX_NS_LVL_CTRL_1 +283 0x0018 //TX_NS_LVL_CTRL_2 +284 0x0016 //TX_NS_LVL_CTRL_3 +285 0x0014 //TX_NS_LVL_CTRL_4 +286 0x0011 //TX_NS_LVL_CTRL_5 +287 0x0014 //TX_NS_LVL_CTRL_6 +288 0x0011 //TX_NS_LVL_CTRL_7 +289 0x000F //TX_MIN_GAIN_S_0 +290 0x0010 //TX_MIN_GAIN_S_1 +291 0x0010 //TX_MIN_GAIN_S_2 +292 0x0010 //TX_MIN_GAIN_S_3 +293 0x0010 //TX_MIN_GAIN_S_4 +294 0x0010 //TX_MIN_GAIN_S_5 +295 0x0010 //TX_MIN_GAIN_S_6 +296 0x000F //TX_MIN_GAIN_S_7 +297 0x6000 //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x4000 //TX_SNRI_SUP_1 +302 0x4000 //TX_SNRI_SUP_2 +303 0x4000 //TX_SNRI_SUP_3 +304 0x4000 //TX_SNRI_SUP_4 +305 0x50C0 //TX_SNRI_SUP_5 +306 0x4000 //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x0018 //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x5000 //TX_A_POST_FILT_S_0 +315 0x4C00 //TX_A_POST_FILT_S_1 +316 0x4000 //TX_A_POST_FILT_S_2 +317 0x6000 //TX_A_POST_FILT_S_3 +318 0x4000 //TX_A_POST_FILT_S_4 +319 0x5000 //TX_A_POST_FILT_S_5 +320 0x6000 //TX_A_POST_FILT_S_6 +321 0x7000 //TX_A_POST_FILT_S_7 +322 0x2000 //TX_B_POST_FILT_0 +323 0x2000 //TX_B_POST_FILT_1 +324 0x2000 //TX_B_POST_FILT_2 +325 0x4000 //TX_B_POST_FILT_3 +326 0x4000 //TX_B_POST_FILT_4 +327 0x1000 //TX_B_POST_FILT_5 +328 0x1000 //TX_B_POST_FILT_6 +329 0x2000 //TX_B_POST_FILT_7 +330 0x4000 //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x6000 //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7C00 //TX_LAMBDA_PFILT +339 0x7C00 //TX_LAMBDA_PFILT_S_0 +340 0x7C00 //TX_LAMBDA_PFILT_S_1 +341 0x7A00 //TX_LAMBDA_PFILT_S_2 +342 0x7C00 //TX_LAMBDA_PFILT_S_3 +343 0x7C00 //TX_LAMBDA_PFILT_S_4 +344 0x7C00 //TX_LAMBDA_PFILT_S_5 +345 0x7C00 //TX_LAMBDA_PFILT_S_6 +346 0x7C00 //TX_LAMBDA_PFILT_S_7 +347 0x0000 //TX_K_PEPPER +348 0x0800 //TX_A_PEPPER +349 0x1EAA //TX_K_PEPPER_HF +350 0x0600 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0200 //TX_DT_BINVAD_TH_0 +354 0x0200 //TX_DT_BINVAD_TH_1 +355 0x0200 //TX_DT_BINVAD_TH_2 +356 0x0200 //TX_DT_BINVAD_TH_3 +357 0x1F40 //TX_DT_BINVAD_ENDF +358 0x0100 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0064 //TX_NDETCT +367 0x0050 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x07D0 //TX_NOISE_TH_1 +371 0x0DAC //TX_NOISE_TH_2 +372 0x4E20 //TX_NOISE_TH_3 +373 0x4E20 //TX_NOISE_TH_4 +374 0x59D8 //TX_NOISE_TH_5 +375 0x7FFF //TX_NOISE_TH_5_2 +376 0x0000 //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x2710 //TX_NOISE_TH_6 +379 0x0033 //TX_MINENOISE_TH +380 0xD508 //TX_MORENS_TFMASK_TH +381 0x0001 //TX_DRC_QUIET_FLOOR +382 0x7999 //TX_RATIODTL_CUT_TH +383 0x0119 //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x0333 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x7FFF //TX_POST_MASK_SUP_HSNE +392 0x1388 //TX_TAIL_DET_TH +393 0x4000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0080 //TX_SUPHIGH_TH +396 0x0000 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x1800 //TX_C_POST_FLT_MASK +399 0x4000 //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0002 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x0033 //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x7FFF //TX_MIN_G_CTRL_SSNS +409 0x0000 //TX_METAL_RTO_THR +410 0x4848 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x4000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x0230 //TX_NOR_OFF_THR +498 0x0CCD //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x2000 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0x4650 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x7FFF //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0x3000 //TX_DEREVERB_LF_MU +515 0x34CD //TX_DEREVERB_HF_MU +516 0x0007 //TX_DEREVERB_DELAY +517 0x0004 //TX_DEREVERB_COEF_LEN +518 0x0003 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x3A98 //TX_GSC_RTOL_TH +522 0x3A98 //TX_GSC_RTOH_TH +523 0x7E2C //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0020 //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x5048 //TX_FDEQ_GAIN_5 +573 0x4848 //TX_FDEQ_GAIN_6 +574 0x4848 //TX_FDEQ_GAIN_7 +575 0x4848 //TX_FDEQ_GAIN_8 +576 0x4848 //TX_FDEQ_GAIN_9 +577 0x5B5B //TX_FDEQ_GAIN_10 +578 0x737B //TX_FDEQ_GAIN_11 +579 0x7B9A //TX_FDEQ_GAIN_12 +580 0x9AC4 //TX_FDEQ_GAIN_13 +581 0xC4C4 //TX_FDEQ_GAIN_14 +582 0xC4C4 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0304 //TX_FDEQ_BIN_2 +594 0x0405 //TX_FDEQ_BIN_3 +595 0x0607 //TX_FDEQ_BIN_4 +596 0x0809 //TX_FDEQ_BIN_5 +597 0x0A0B //TX_FDEQ_BIN_6 +598 0x0C0D //TX_FDEQ_BIN_7 +599 0x0E0F //TX_FDEQ_BIN_8 +600 0x1011 //TX_FDEQ_BIN_9 +601 0x1214 //TX_FDEQ_BIN_10 +602 0x1618 //TX_FDEQ_BIN_11 +603 0x1C1C //TX_FDEQ_BIN_12 +604 0x2020 //TX_FDEQ_BIN_13 +605 0x2020 //TX_FDEQ_BIN_14 +606 0x2011 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0030 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x484B //TX_PREEQ_GAIN_MIC0_8 +626 0x4848 //TX_PREEQ_GAIN_MIC0_9 +627 0x484C //TX_PREEQ_GAIN_MIC0_10 +628 0x4C4C //TX_PREEQ_GAIN_MIC0_11 +629 0x4038 //TX_PREEQ_GAIN_MIC0_12 +630 0x3838 //TX_PREEQ_GAIN_MIC0_13 +631 0x4840 //TX_PREEQ_GAIN_MIC0_14 +632 0x3848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0202 //TX_PREEQ_BIN_MIC0_0 +642 0x0203 //TX_PREEQ_BIN_MIC0_1 +643 0x0303 //TX_PREEQ_BIN_MIC0_2 +644 0x0304 //TX_PREEQ_BIN_MIC0_3 +645 0x0405 //TX_PREEQ_BIN_MIC0_4 +646 0x0506 //TX_PREEQ_BIN_MIC0_5 +647 0x0808 //TX_PREEQ_BIN_MIC0_6 +648 0x0809 //TX_PREEQ_BIN_MIC0_7 +649 0x0A0A //TX_PREEQ_BIN_MIC0_8 +650 0x0C10 //TX_PREEQ_BIN_MIC0_9 +651 0x1013 //TX_PREEQ_BIN_MIC0_10 +652 0x1414 //TX_PREEQ_BIN_MIC0_11 +653 0x261E //TX_PREEQ_BIN_MIC0_12 +654 0x1E14 //TX_PREEQ_BIN_MIC0_13 +655 0x1414 //TX_PREEQ_BIN_MIC0_14 +656 0x2814 //TX_PREEQ_BIN_MIC0_15 +657 0x4000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0030 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x1812 //TX_PREEQ_BIN_MIC1_0 +691 0x0A0A //TX_PREEQ_BIN_MIC1_1 +692 0x0808 //TX_PREEQ_BIN_MIC1_2 +693 0x080A //TX_PREEQ_BIN_MIC1_3 +694 0x0B09 //TX_PREEQ_BIN_MIC1_4 +695 0x0A06 //TX_PREEQ_BIN_MIC1_5 +696 0x0606 //TX_PREEQ_BIN_MIC1_6 +697 0x0605 //TX_PREEQ_BIN_MIC1_7 +698 0x050A //TX_PREEQ_BIN_MIC1_8 +699 0x1505 //TX_PREEQ_BIN_MIC1_9 +700 0x0506 //TX_PREEQ_BIN_MIC1_10 +701 0x0615 //TX_PREEQ_BIN_MIC1_11 +702 0x1516 //TX_PREEQ_BIN_MIC1_12 +703 0x2021 //TX_PREEQ_BIN_MIC1_13 +704 0x2021 //TX_PREEQ_BIN_MIC1_14 +705 0x2021 //TX_PREEQ_BIN_MIC1_15 +706 0x0800 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0E10 //TX_PREEQ_BIN_MIC2_0 +740 0x1010 //TX_PREEQ_BIN_MIC2_1 +741 0x1010 //TX_PREEQ_BIN_MIC2_2 +742 0x1010 //TX_PREEQ_BIN_MIC2_3 +743 0x1010 //TX_PREEQ_BIN_MIC2_4 +744 0x1010 //TX_PREEQ_BIN_MIC2_5 +745 0x1010 //TX_PREEQ_BIN_MIC2_6 +746 0x1010 //TX_PREEQ_BIN_MIC2_7 +747 0x1010 //TX_PREEQ_BIN_MIC2_8 +748 0x1010 //TX_PREEQ_BIN_MIC2_9 +749 0x1010 //TX_PREEQ_BIN_MIC2_10 +750 0x1010 //TX_PREEQ_BIN_MIC2_11 +751 0x1010 //TX_PREEQ_BIN_MIC2_12 +752 0x1010 //TX_PREEQ_BIN_MIC2_13 +753 0x1010 //TX_PREEQ_BIN_MIC2_14 +754 0x0200 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x2000 //TX_NND_WEIGHT +765 0x0060 //TX_MIC_CALIBRATION_0 +766 0x0060 //TX_MIC_CALIBRATION_1 +767 0x0070 //TX_MIC_CALIBRATION_2 +768 0x0070 //TX_MIC_CALIBRATION_3 +769 0x0050 //TX_MIC_PWR_BIAS_0 +770 0x0040 //TX_MIC_PWR_BIAS_1 +771 0x0040 //TX_MIC_PWR_BIAS_2 +772 0x0040 //TX_MIC_PWR_BIAS_3 +773 0x0009 //TX_GAIN_LIMIT_0 +774 0x000F //TX_GAIN_LIMIT_1 +775 0x000F //TX_GAIN_LIMIT_2 +776 0x000F //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x0C00 //TX_TDDRC_ALPHA_UP_01 +784 0x0C00 //TX_TDDRC_ALPHA_UP_02 +785 0x0C00 //TX_TDDRC_ALPHA_UP_03 +786 0x0C00 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x7FFF //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0010 //TX_DEADMIC_SILENCE_TH +817 0x0600 //TX_MIC_DEGRADE_TH +818 0x0078 //TX_DEADMIC_CNT +819 0x0078 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x4848 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0096 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0004 //TX_FILTINDX +854 0x0004 //TX_TDDRC_THRD_0 +855 0x0016 //TX_TDDRC_THRD_1 +856 0x1900 //TX_TDDRC_THRD_2 +857 0x1900 //TX_TDDRC_THRD_3 +858 0x3000 //TX_TDDRC_SLANT_0 +859 0x7B00 //TX_TDDRC_SLANT_1 +860 0x0C00 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x0FDA //TX_TDDRC_DRC_GAIN +867 0x7FFF //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x0028 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x1000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x2339 //TX_SENDFUNC_REG_MICMUTE +898 0x0021 //TX_SENDFUNC_REG_MICMUTE1 +899 0x02BC //TX_MICMUTE_RATIO_THR +900 0x0140 //TX_MICMUTE_AMP_THR +901 0x0004 //TX_MICMUTE_HPF_IND +902 0x00C0 //TX_MICMUTE_LOG_EYR_TH +903 0x0008 //TX_MICMUTE_CVG_TIME +904 0x0008 //TX_MICMUTE_RELEASE_TIME +905 0x01FE //TX_MIC_VOLUME_MIC0MUTE +906 0x0020 //TX_MICMUTE_EPD_OFFSET_0 +907 0x001E //TX_MICMUTE_FRQ_AEC_L +908 0x7999 //TX_MICMUTE_EAD_THR +909 0x7FFF //TX_MICMUTE_LAMBDA_CB_NLE +910 0x7FFF //TX_MICMUTE_LAMBDA_RE_EST +911 0x4000 //TX_DTD_THR1_MICMUTE_0 +912 0x7000 //TX_DTD_THR1_MICMUTE_1 +913 0x7FFF //TX_DTD_THR1_MICMUTE_2 +914 0x7FFF //TX_DTD_THR1_MICMUTE_3 +915 0x6CCC //TX_DTD_THR2_MICMUTE_0 +916 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x1000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x4000 //TX_MICMUTE_C_POST_FLT +922 0x03E8 //TX_MICMUTE_DT_CUT_K +923 0x0001 //TX_MICMUTE_DT_CUT_THR +924 0x03E8 //TX_MICMUTE_DT_CUT_K2 +925 0x0001 //TX_MICMUTE_DT_CUT_THR2 +926 0x0064 //TX_MICMUTE_DT2_HOLD_N +927 0x1000 //TX_MICMUTE_RATIODTH_THCUT +928 0x1000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x7FFF //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0400 //TX_MICMUTE_C_POST_FLT_MASK +931 0x7999 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0258 //TX_MICMUTE_DT_CUT_K1 +933 0x0800 //TX_MICMUTE_N2_SN_EST +934 0xFC00 //TX_MICMUTE_THR_SN_EST_0 +935 0x001C //TX_MICMUTE_MIN_G_CTRL_0 +936 0x6000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x7000 //TX_MICMUTE_B_POST_FILT_0 +938 0x2710 //TX_MIC1RUB_AMP_THR +939 0x0010 //TX_MIC1MUTE_RATIO_THR +940 0x0450 //TX_MIC1MUTE_AMP_THR +941 0x0008 //TX_MIC1MUTE_CVG_TIME +942 0x0008 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x006C //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0004 //RX_SAMPLINGFREQ_SIG +3 0x0004 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x4000 //RX_TDDRC_ALPHA_UP_1 +7 0x4000 //RX_TDDRC_ALPHA_UP_2 +8 0x4000 //RX_TDDRC_ALPHA_UP_3 +9 0x4000 //RX_TDDRC_ALPHA_UP_4 +10 0x065B //RX_PGA +11 0x7E56 //RX_A_HP +12 0x4000 //RX_B_PE +13 0x7800 //RX_THR_PITCH_DET_0 +14 0x7000 //RX_THR_PITCH_DET_1 +15 0x6000 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0400 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x0014 //RX_NS_LVL_CTRL +23 0xF400 //RX_THR_SN_EST +24 0x7E00 //RX_LAMBDA_PFILT +25 0x00C8 //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4870 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4850 //RX_FDEQ_GAIN_6 +46 0x485C //RX_FDEQ_GAIN_7 +47 0x5C60 //RX_FDEQ_GAIN_8 +48 0x685C //RX_FDEQ_GAIN_9 +49 0x5640 //RX_FDEQ_GAIN_10 +50 0x4040 //RX_FDEQ_GAIN_11 +51 0x5C58 //RX_FDEQ_GAIN_12 +52 0x5C60 //RX_FDEQ_GAIN_13 +53 0x6060 //RX_FDEQ_GAIN_14 +54 0x6060 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0402 //RX_FDEQ_BIN_3 +67 0x0504 //RX_FDEQ_BIN_4 +68 0x0209 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0002 //RX_FILTINDX +112 0x0001 //RX_TDDRC_THRD_0 +113 0x0002 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x6000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x4000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x03C3 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x2000 //RX_MIN_G_FP +128 0x0080 //RX_MAX_G_FP +129 0x0012 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x4000 //RX_TDDRC_ALPHA_UP_1 +7 0x4000 //RX_TDDRC_ALPHA_UP_2 +8 0x4000 //RX_TDDRC_ALPHA_UP_3 +9 0x4000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0001 //RX_TDDRC_THRD_0 +113 0x0002 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x6000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x4000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x03C3 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4870 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4850 //RX_FDEQ_GAIN_6 +46 0x485C //RX_FDEQ_GAIN_7 +47 0x5C60 //RX_FDEQ_GAIN_8 +48 0x685C //RX_FDEQ_GAIN_9 +49 0x5640 //RX_FDEQ_GAIN_10 +50 0x4040 //RX_FDEQ_GAIN_11 +51 0x5C58 //RX_FDEQ_GAIN_12 +52 0x5C60 //RX_FDEQ_GAIN_13 +53 0x6060 //RX_FDEQ_GAIN_14 +54 0x6060 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0402 //RX_FDEQ_BIN_3 +67 0x0504 //RX_FDEQ_BIN_4 +68 0x0209 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0012 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x4000 //RX_TDDRC_ALPHA_UP_1 +7 0x4000 //RX_TDDRC_ALPHA_UP_2 +8 0x4000 //RX_TDDRC_ALPHA_UP_3 +9 0x4000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0001 //RX_TDDRC_THRD_0 +113 0x0002 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x6000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x4000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x03C3 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4870 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4850 //RX_FDEQ_GAIN_6 +46 0x485C //RX_FDEQ_GAIN_7 +47 0x5C60 //RX_FDEQ_GAIN_8 +48 0x685C //RX_FDEQ_GAIN_9 +49 0x5640 //RX_FDEQ_GAIN_10 +50 0x4040 //RX_FDEQ_GAIN_11 +51 0x5C58 //RX_FDEQ_GAIN_12 +52 0x5C60 //RX_FDEQ_GAIN_13 +53 0x6060 //RX_FDEQ_GAIN_14 +54 0x6060 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0402 //RX_FDEQ_BIN_3 +67 0x0504 //RX_FDEQ_BIN_4 +68 0x0209 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x001A //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x4000 //RX_TDDRC_ALPHA_UP_1 +7 0x4000 //RX_TDDRC_ALPHA_UP_2 +8 0x4000 //RX_TDDRC_ALPHA_UP_3 +9 0x4000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0001 //RX_TDDRC_THRD_0 +113 0x0002 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x6000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x4000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x03C3 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4870 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4850 //RX_FDEQ_GAIN_6 +46 0x485C //RX_FDEQ_GAIN_7 +47 0x5C60 //RX_FDEQ_GAIN_8 +48 0x685C //RX_FDEQ_GAIN_9 +49 0x5640 //RX_FDEQ_GAIN_10 +50 0x4040 //RX_FDEQ_GAIN_11 +51 0x5C58 //RX_FDEQ_GAIN_12 +52 0x5C60 //RX_FDEQ_GAIN_13 +53 0x6060 //RX_FDEQ_GAIN_14 +54 0x6060 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0402 //RX_FDEQ_BIN_3 +67 0x0504 //RX_FDEQ_BIN_4 +68 0x0209 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0025 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x4000 //RX_TDDRC_ALPHA_UP_1 +7 0x4000 //RX_TDDRC_ALPHA_UP_2 +8 0x4000 //RX_TDDRC_ALPHA_UP_3 +9 0x4000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0001 //RX_TDDRC_THRD_0 +113 0x0002 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x6000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x4000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x03C3 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4870 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4850 //RX_FDEQ_GAIN_6 +46 0x485C //RX_FDEQ_GAIN_7 +47 0x5C60 //RX_FDEQ_GAIN_8 +48 0x685C //RX_FDEQ_GAIN_9 +49 0x5640 //RX_FDEQ_GAIN_10 +50 0x4040 //RX_FDEQ_GAIN_11 +51 0x5C58 //RX_FDEQ_GAIN_12 +52 0x5C60 //RX_FDEQ_GAIN_13 +53 0x6060 //RX_FDEQ_GAIN_14 +54 0x6060 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0402 //RX_FDEQ_BIN_3 +67 0x0504 //RX_FDEQ_BIN_4 +68 0x0209 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0034 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x4000 //RX_TDDRC_ALPHA_UP_1 +7 0x4000 //RX_TDDRC_ALPHA_UP_2 +8 0x4000 //RX_TDDRC_ALPHA_UP_3 +9 0x4000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0001 //RX_TDDRC_THRD_0 +113 0x0002 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x6000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x4000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x03C3 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4870 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4850 //RX_FDEQ_GAIN_6 +46 0x485C //RX_FDEQ_GAIN_7 +47 0x5C60 //RX_FDEQ_GAIN_8 +48 0x685C //RX_FDEQ_GAIN_9 +49 0x5640 //RX_FDEQ_GAIN_10 +50 0x4040 //RX_FDEQ_GAIN_11 +51 0x5C58 //RX_FDEQ_GAIN_12 +52 0x5C60 //RX_FDEQ_GAIN_13 +53 0x6060 //RX_FDEQ_GAIN_14 +54 0x6060 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0402 //RX_FDEQ_BIN_3 +67 0x0504 //RX_FDEQ_BIN_4 +68 0x0209 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x004D //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x4000 //RX_TDDRC_ALPHA_UP_1 +7 0x4000 //RX_TDDRC_ALPHA_UP_2 +8 0x4000 //RX_TDDRC_ALPHA_UP_3 +9 0x4000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0001 //RX_TDDRC_THRD_0 +113 0x0002 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x6000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x4000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x03C3 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4870 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4850 //RX_FDEQ_GAIN_6 +46 0x485C //RX_FDEQ_GAIN_7 +47 0x5C60 //RX_FDEQ_GAIN_8 +48 0x685C //RX_FDEQ_GAIN_9 +49 0x5640 //RX_FDEQ_GAIN_10 +50 0x4040 //RX_FDEQ_GAIN_11 +51 0x5C58 //RX_FDEQ_GAIN_12 +52 0x5C60 //RX_FDEQ_GAIN_13 +53 0x6060 //RX_FDEQ_GAIN_14 +54 0x6060 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0402 //RX_FDEQ_BIN_3 +67 0x0504 //RX_FDEQ_BIN_4 +68 0x0209 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0074 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x4000 //RX_TDDRC_ALPHA_UP_1 +7 0x4000 //RX_TDDRC_ALPHA_UP_2 +8 0x4000 //RX_TDDRC_ALPHA_UP_3 +9 0x4000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0001 //RX_TDDRC_THRD_0 +113 0x0002 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x6000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x4000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x03C3 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4870 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4850 //RX_FDEQ_GAIN_6 +46 0x485C //RX_FDEQ_GAIN_7 +47 0x5C60 //RX_FDEQ_GAIN_8 +48 0x685C //RX_FDEQ_GAIN_9 +49 0x5640 //RX_FDEQ_GAIN_10 +50 0x4040 //RX_FDEQ_GAIN_11 +51 0x5C58 //RX_FDEQ_GAIN_12 +52 0x5C60 //RX_FDEQ_GAIN_13 +53 0x6060 //RX_FDEQ_GAIN_14 +54 0x6060 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0402 //RX_FDEQ_BIN_3 +67 0x0504 //RX_FDEQ_BIN_4 +68 0x0209 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x006C //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0004 //RX_SAMPLINGFREQ_SIG +160 0x0004 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x4000 //RX_TDDRC_ALPHA_UP_1 +164 0x4000 //RX_TDDRC_ALPHA_UP_2 +165 0x4000 //RX_TDDRC_ALPHA_UP_3 +166 0x4000 //RX_TDDRC_ALPHA_UP_4 +167 0x065B //RX_PGA +168 0x7E56 //RX_A_HP +169 0x4000 //RX_B_PE +170 0x7800 //RX_THR_PITCH_DET_0 +171 0x7000 //RX_THR_PITCH_DET_1 +172 0x6000 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0400 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x0014 //RX_NS_LVL_CTRL +180 0xF400 //RX_THR_SN_EST +181 0x7E00 //RX_LAMBDA_PFILT +182 0x00C8 //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4870 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4850 //RX_FDEQ_GAIN_6 +203 0x485C //RX_FDEQ_GAIN_7 +204 0x5C60 //RX_FDEQ_GAIN_8 +205 0x685C //RX_FDEQ_GAIN_9 +206 0x5640 //RX_FDEQ_GAIN_10 +207 0x4040 //RX_FDEQ_GAIN_11 +208 0x5C58 //RX_FDEQ_GAIN_12 +209 0x5C60 //RX_FDEQ_GAIN_13 +210 0x6060 //RX_FDEQ_GAIN_14 +211 0x6060 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0402 //RX_FDEQ_BIN_3 +224 0x0504 //RX_FDEQ_BIN_4 +225 0x0209 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0002 //RX_FILTINDX +269 0x0001 //RX_TDDRC_THRD_0 +270 0x0002 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x6000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x4000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x03C3 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x2000 //RX_MIN_G_FP +285 0x0080 //RX_MAX_G_FP +286 0x0012 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x4000 //RX_TDDRC_ALPHA_UP_1 +164 0x4000 //RX_TDDRC_ALPHA_UP_2 +165 0x4000 //RX_TDDRC_ALPHA_UP_3 +166 0x4000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0001 //RX_TDDRC_THRD_0 +270 0x0002 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x6000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x4000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x03C3 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4870 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4850 //RX_FDEQ_GAIN_6 +203 0x485C //RX_FDEQ_GAIN_7 +204 0x5C60 //RX_FDEQ_GAIN_8 +205 0x685C //RX_FDEQ_GAIN_9 +206 0x5640 //RX_FDEQ_GAIN_10 +207 0x4040 //RX_FDEQ_GAIN_11 +208 0x5C58 //RX_FDEQ_GAIN_12 +209 0x5C60 //RX_FDEQ_GAIN_13 +210 0x6060 //RX_FDEQ_GAIN_14 +211 0x6060 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0402 //RX_FDEQ_BIN_3 +224 0x0504 //RX_FDEQ_BIN_4 +225 0x0209 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0012 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x4000 //RX_TDDRC_ALPHA_UP_1 +164 0x4000 //RX_TDDRC_ALPHA_UP_2 +165 0x4000 //RX_TDDRC_ALPHA_UP_3 +166 0x4000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0001 //RX_TDDRC_THRD_0 +270 0x0002 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x6000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x4000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x03C3 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4870 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4850 //RX_FDEQ_GAIN_6 +203 0x485C //RX_FDEQ_GAIN_7 +204 0x5C60 //RX_FDEQ_GAIN_8 +205 0x685C //RX_FDEQ_GAIN_9 +206 0x5640 //RX_FDEQ_GAIN_10 +207 0x4040 //RX_FDEQ_GAIN_11 +208 0x5C58 //RX_FDEQ_GAIN_12 +209 0x5C60 //RX_FDEQ_GAIN_13 +210 0x6060 //RX_FDEQ_GAIN_14 +211 0x6060 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0402 //RX_FDEQ_BIN_3 +224 0x0504 //RX_FDEQ_BIN_4 +225 0x0209 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x001A //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x4000 //RX_TDDRC_ALPHA_UP_1 +164 0x4000 //RX_TDDRC_ALPHA_UP_2 +165 0x4000 //RX_TDDRC_ALPHA_UP_3 +166 0x4000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0001 //RX_TDDRC_THRD_0 +270 0x0002 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x6000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x4000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x03C3 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4870 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4850 //RX_FDEQ_GAIN_6 +203 0x485C //RX_FDEQ_GAIN_7 +204 0x5C60 //RX_FDEQ_GAIN_8 +205 0x685C //RX_FDEQ_GAIN_9 +206 0x5640 //RX_FDEQ_GAIN_10 +207 0x4040 //RX_FDEQ_GAIN_11 +208 0x5C58 //RX_FDEQ_GAIN_12 +209 0x5C60 //RX_FDEQ_GAIN_13 +210 0x6060 //RX_FDEQ_GAIN_14 +211 0x6060 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0402 //RX_FDEQ_BIN_3 +224 0x0504 //RX_FDEQ_BIN_4 +225 0x0209 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0025 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x4000 //RX_TDDRC_ALPHA_UP_1 +164 0x4000 //RX_TDDRC_ALPHA_UP_2 +165 0x4000 //RX_TDDRC_ALPHA_UP_3 +166 0x4000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0001 //RX_TDDRC_THRD_0 +270 0x0002 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x6000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x4000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x03C3 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4870 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4850 //RX_FDEQ_GAIN_6 +203 0x485C //RX_FDEQ_GAIN_7 +204 0x5C60 //RX_FDEQ_GAIN_8 +205 0x685C //RX_FDEQ_GAIN_9 +206 0x5640 //RX_FDEQ_GAIN_10 +207 0x4040 //RX_FDEQ_GAIN_11 +208 0x5C58 //RX_FDEQ_GAIN_12 +209 0x5C60 //RX_FDEQ_GAIN_13 +210 0x6060 //RX_FDEQ_GAIN_14 +211 0x6060 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0402 //RX_FDEQ_BIN_3 +224 0x0504 //RX_FDEQ_BIN_4 +225 0x0209 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0034 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x4000 //RX_TDDRC_ALPHA_UP_1 +164 0x4000 //RX_TDDRC_ALPHA_UP_2 +165 0x4000 //RX_TDDRC_ALPHA_UP_3 +166 0x4000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0001 //RX_TDDRC_THRD_0 +270 0x0002 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x6000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x4000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x03C3 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4870 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4850 //RX_FDEQ_GAIN_6 +203 0x485C //RX_FDEQ_GAIN_7 +204 0x5C60 //RX_FDEQ_GAIN_8 +205 0x685C //RX_FDEQ_GAIN_9 +206 0x5640 //RX_FDEQ_GAIN_10 +207 0x4040 //RX_FDEQ_GAIN_11 +208 0x5C58 //RX_FDEQ_GAIN_12 +209 0x5C60 //RX_FDEQ_GAIN_13 +210 0x6060 //RX_FDEQ_GAIN_14 +211 0x6060 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0402 //RX_FDEQ_BIN_3 +224 0x0504 //RX_FDEQ_BIN_4 +225 0x0209 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x004D //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x4000 //RX_TDDRC_ALPHA_UP_1 +164 0x4000 //RX_TDDRC_ALPHA_UP_2 +165 0x4000 //RX_TDDRC_ALPHA_UP_3 +166 0x4000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0001 //RX_TDDRC_THRD_0 +270 0x0002 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x6000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x4000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x03C3 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4870 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4850 //RX_FDEQ_GAIN_6 +203 0x485C //RX_FDEQ_GAIN_7 +204 0x5C60 //RX_FDEQ_GAIN_8 +205 0x685C //RX_FDEQ_GAIN_9 +206 0x5640 //RX_FDEQ_GAIN_10 +207 0x4040 //RX_FDEQ_GAIN_11 +208 0x5C58 //RX_FDEQ_GAIN_12 +209 0x5C60 //RX_FDEQ_GAIN_13 +210 0x6060 //RX_FDEQ_GAIN_14 +211 0x6060 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0402 //RX_FDEQ_BIN_3 +224 0x0504 //RX_FDEQ_BIN_4 +225 0x0209 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0074 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x4000 //RX_TDDRC_ALPHA_UP_1 +164 0x4000 //RX_TDDRC_ALPHA_UP_2 +165 0x4000 //RX_TDDRC_ALPHA_UP_3 +166 0x4000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0001 //RX_TDDRC_THRD_0 +270 0x0002 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x6000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x4000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x03C3 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4870 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4850 //RX_FDEQ_GAIN_6 +203 0x485C //RX_FDEQ_GAIN_7 +204 0x5C60 //RX_FDEQ_GAIN_8 +205 0x685C //RX_FDEQ_GAIN_9 +206 0x5640 //RX_FDEQ_GAIN_10 +207 0x4040 //RX_FDEQ_GAIN_11 +208 0x5C58 //RX_FDEQ_GAIN_12 +209 0x5C60 //RX_FDEQ_GAIN_13 +210 0x6060 //RX_FDEQ_GAIN_14 +211 0x6060 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0402 //RX_FDEQ_BIN_3 +224 0x0504 //RX_FDEQ_BIN_4 +225 0x0209 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME HANDSFREE-HANDFREE-CUSTOM2-FB +#PARAM_MODE FULL +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0001 //TX_OPERATION_MODE_0 +1 0x0001 //TX_OPERATION_MODE_1 +2 0x0033 //TX_PATCH_REG +3 0x6B5C //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0003 //TX_NUM_MIC +6 0x0004 //TX_SAMPLINGFREQ_SIG +7 0x0004 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009D //TX_DIST2REF1 +22 0x0010 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0A19 //TX_PGA_0 +28 0x0A19 //TX_PGA_1 +29 0x0A19 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0001 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0002 //TX_MIC_DATA_SRC0 +42 0x0000 //TX_MIC_DATA_SRC1 +43 0x0001 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3B33 //TX_DIST2REF_11 +73 0x0A70 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0800 //TX_MIC_REFBLK_VOLUME +108 0x0CAE //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0015 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7E56 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x1800 //TX_THR_PITCH_DET_0 +131 0x1000 //TX_THR_PITCH_DET_1 +132 0x0800 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x0028 //TX_TAIL_LENGTH +147 0x0300 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x7A00 //TX_EAD_THR +151 0x1000 //TX_THR_RE_EST +152 0x0800 //TX_MIN_EQ_RE_EST_0 +153 0x2000 //TX_MIN_EQ_RE_EST_1 +154 0x2000 //TX_MIN_EQ_RE_EST_2 +155 0x4000 //TX_MIN_EQ_RE_EST_3 +156 0x4000 //TX_MIN_EQ_RE_EST_4 +157 0x7FFF //TX_MIN_EQ_RE_EST_5 +158 0x7FFF //TX_MIN_EQ_RE_EST_6 +159 0x7FFF //TX_MIN_EQ_RE_EST_7 +160 0x7FFF //TX_MIN_EQ_RE_EST_8 +161 0x7FFF //TX_MIN_EQ_RE_EST_9 +162 0x7FFF //TX_MIN_EQ_RE_EST_10 +163 0x7FFF //TX_MIN_EQ_RE_EST_11 +164 0x7FFF //TX_MIN_EQ_RE_EST_12 +165 0x4000 //TX_LAMBDA_RE_EST +166 0x0CCD //TX_LAMBDA_CB_NLE +167 0x2000 //TX_C_POST_FLT +168 0x7FFF //TX_GAIN_NP +169 0x0180 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x09C4 //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x7D00 //TX_DTD_THR1_0 +198 0x7FF0 //TX_DTD_THR1_1 +199 0x7FF0 //TX_DTD_THR1_2 +200 0x7FF0 //TX_DTD_THR1_3 +201 0x7FF0 //TX_DTD_THR1_4 +202 0x7FF0 //TX_DTD_THR1_5 +203 0x7FF0 //TX_DTD_THR1_6 +204 0x0CCD //TX_DTD_THR2_0 +205 0x0CCD //TX_DTD_THR2_1 +206 0x0CCD //TX_DTD_THR2_2 +207 0x0CCD //TX_DTD_THR2_3 +208 0x0CCD //TX_DTD_THR2_4 +209 0x0CCD //TX_DTD_THR2_5 +210 0x0CCD //TX_DTD_THR2_6 +211 0x7FFF //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x0DAC //TX_DT_CUT_K +214 0x0020 //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x7FFF //TX_DTD_MIC_BLK +221 0x023E //TX_ADPT_STRICT_L +222 0x023E //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x2000 //TX_B_POST_FILT_ECHO_L +229 0x2000 //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x1000 //TX_B_LESSCUT_RTO_ECHO +232 0x0063 //TX_EPD_OFFSET_00 +233 0x0000 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x0000 //TX_DTD_THR1_7 +238 0x0000 //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xF800 //TX_THR_SN_EST_0 +243 0xFA00 //TX_THR_SN_EST_1 +244 0xFA00 //TX_THR_SN_EST_2 +245 0xFB00 //TX_THR_SN_EST_3 +246 0xFA00 //TX_THR_SN_EST_4 +247 0xFA00 //TX_THR_SN_EST_5 +248 0xF800 //TX_THR_SN_EST_6 +249 0xF800 //TX_THR_SN_EST_7 +250 0x0100 //TX_DELTA_THR_SN_EST_0 +251 0x0100 //TX_DELTA_THR_SN_EST_1 +252 0x0200 //TX_DELTA_THR_SN_EST_2 +253 0x0100 //TX_DELTA_THR_SN_EST_3 +254 0x0100 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0200 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x4000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x4000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x2000 //TX_B_POST_FLT_0 +280 0x1000 //TX_B_POST_FLT_1 +281 0x0010 //TX_NS_LVL_CTRL_0 +282 0x0014 //TX_NS_LVL_CTRL_1 +283 0x0018 //TX_NS_LVL_CTRL_2 +284 0x0016 //TX_NS_LVL_CTRL_3 +285 0x0014 //TX_NS_LVL_CTRL_4 +286 0x0011 //TX_NS_LVL_CTRL_5 +287 0x0014 //TX_NS_LVL_CTRL_6 +288 0x0011 //TX_NS_LVL_CTRL_7 +289 0x000F //TX_MIN_GAIN_S_0 +290 0x0010 //TX_MIN_GAIN_S_1 +291 0x0010 //TX_MIN_GAIN_S_2 +292 0x0010 //TX_MIN_GAIN_S_3 +293 0x0010 //TX_MIN_GAIN_S_4 +294 0x0010 //TX_MIN_GAIN_S_5 +295 0x0010 //TX_MIN_GAIN_S_6 +296 0x000F //TX_MIN_GAIN_S_7 +297 0x6000 //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x4000 //TX_SNRI_SUP_1 +302 0x4000 //TX_SNRI_SUP_2 +303 0x4000 //TX_SNRI_SUP_3 +304 0x4000 //TX_SNRI_SUP_4 +305 0x50C0 //TX_SNRI_SUP_5 +306 0x4000 //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x0018 //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x5000 //TX_A_POST_FILT_S_0 +315 0x4C00 //TX_A_POST_FILT_S_1 +316 0x4000 //TX_A_POST_FILT_S_2 +317 0x6000 //TX_A_POST_FILT_S_3 +318 0x4000 //TX_A_POST_FILT_S_4 +319 0x5000 //TX_A_POST_FILT_S_5 +320 0x6000 //TX_A_POST_FILT_S_6 +321 0x7000 //TX_A_POST_FILT_S_7 +322 0x2000 //TX_B_POST_FILT_0 +323 0x2000 //TX_B_POST_FILT_1 +324 0x2000 //TX_B_POST_FILT_2 +325 0x4000 //TX_B_POST_FILT_3 +326 0x4000 //TX_B_POST_FILT_4 +327 0x1000 //TX_B_POST_FILT_5 +328 0x1000 //TX_B_POST_FILT_6 +329 0x2000 //TX_B_POST_FILT_7 +330 0x4000 //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x6000 //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7C00 //TX_LAMBDA_PFILT +339 0x7C00 //TX_LAMBDA_PFILT_S_0 +340 0x7C00 //TX_LAMBDA_PFILT_S_1 +341 0x7A00 //TX_LAMBDA_PFILT_S_2 +342 0x7C00 //TX_LAMBDA_PFILT_S_3 +343 0x7C00 //TX_LAMBDA_PFILT_S_4 +344 0x7C00 //TX_LAMBDA_PFILT_S_5 +345 0x7C00 //TX_LAMBDA_PFILT_S_6 +346 0x7C00 //TX_LAMBDA_PFILT_S_7 +347 0x0000 //TX_K_PEPPER +348 0x0800 //TX_A_PEPPER +349 0x1EAA //TX_K_PEPPER_HF +350 0x0600 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0200 //TX_DT_BINVAD_TH_0 +354 0x0200 //TX_DT_BINVAD_TH_1 +355 0x0200 //TX_DT_BINVAD_TH_2 +356 0x0200 //TX_DT_BINVAD_TH_3 +357 0x1F40 //TX_DT_BINVAD_ENDF +358 0x0100 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0064 //TX_NDETCT +367 0x0050 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x07D0 //TX_NOISE_TH_1 +371 0x0DAC //TX_NOISE_TH_2 +372 0x4E20 //TX_NOISE_TH_3 +373 0x4E20 //TX_NOISE_TH_4 +374 0x59D8 //TX_NOISE_TH_5 +375 0x7FFF //TX_NOISE_TH_5_2 +376 0x0000 //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x2710 //TX_NOISE_TH_6 +379 0x0033 //TX_MINENOISE_TH +380 0xD508 //TX_MORENS_TFMASK_TH +381 0x0001 //TX_DRC_QUIET_FLOOR +382 0x7999 //TX_RATIODTL_CUT_TH +383 0x0119 //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x0333 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x7FFF //TX_POST_MASK_SUP_HSNE +392 0x1388 //TX_TAIL_DET_TH +393 0x4000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0080 //TX_SUPHIGH_TH +396 0x0000 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x1800 //TX_C_POST_FLT_MASK +399 0x4000 //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0002 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x0033 //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x7FFF //TX_MIN_G_CTRL_SSNS +409 0x0000 //TX_METAL_RTO_THR +410 0x4848 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x4000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x0230 //TX_NOR_OFF_THR +498 0x0CCD //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x2000 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0x4650 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x7FFF //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0x3000 //TX_DEREVERB_LF_MU +515 0x34CD //TX_DEREVERB_HF_MU +516 0x0007 //TX_DEREVERB_DELAY +517 0x0004 //TX_DEREVERB_COEF_LEN +518 0x0003 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x3A98 //TX_GSC_RTOL_TH +522 0x3A98 //TX_GSC_RTOH_TH +523 0x7E2C //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0020 //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x5048 //TX_FDEQ_GAIN_5 +573 0x4848 //TX_FDEQ_GAIN_6 +574 0x4848 //TX_FDEQ_GAIN_7 +575 0x4848 //TX_FDEQ_GAIN_8 +576 0x4848 //TX_FDEQ_GAIN_9 +577 0x5B5B //TX_FDEQ_GAIN_10 +578 0x737B //TX_FDEQ_GAIN_11 +579 0x7B9A //TX_FDEQ_GAIN_12 +580 0x9AC4 //TX_FDEQ_GAIN_13 +581 0xC4C4 //TX_FDEQ_GAIN_14 +582 0xC4C4 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0304 //TX_FDEQ_BIN_2 +594 0x0405 //TX_FDEQ_BIN_3 +595 0x0607 //TX_FDEQ_BIN_4 +596 0x0809 //TX_FDEQ_BIN_5 +597 0x0A0B //TX_FDEQ_BIN_6 +598 0x0C0D //TX_FDEQ_BIN_7 +599 0x0E0F //TX_FDEQ_BIN_8 +600 0x1011 //TX_FDEQ_BIN_9 +601 0x1214 //TX_FDEQ_BIN_10 +602 0x1618 //TX_FDEQ_BIN_11 +603 0x1C1C //TX_FDEQ_BIN_12 +604 0x2020 //TX_FDEQ_BIN_13 +605 0x2020 //TX_FDEQ_BIN_14 +606 0x2011 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0030 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4849 //TX_PREEQ_GAIN_MIC0_6 +624 0x4A4B //TX_PREEQ_GAIN_MIC0_7 +625 0x4C4B //TX_PREEQ_GAIN_MIC0_8 +626 0x4A48 //TX_PREEQ_GAIN_MIC0_9 +627 0x4B4C //TX_PREEQ_GAIN_MIC0_10 +628 0x4C4B //TX_PREEQ_GAIN_MIC0_11 +629 0x4838 //TX_PREEQ_GAIN_MIC0_12 +630 0x3858 //TX_PREEQ_GAIN_MIC0_13 +631 0x7060 //TX_PREEQ_GAIN_MIC0_14 +632 0x9870 //TX_PREEQ_GAIN_MIC0_15 +633 0x5848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0202 //TX_PREEQ_BIN_MIC0_0 +642 0x0203 //TX_PREEQ_BIN_MIC0_1 +643 0x0303 //TX_PREEQ_BIN_MIC0_2 +644 0x0304 //TX_PREEQ_BIN_MIC0_3 +645 0x0405 //TX_PREEQ_BIN_MIC0_4 +646 0x0506 //TX_PREEQ_BIN_MIC0_5 +647 0x0808 //TX_PREEQ_BIN_MIC0_6 +648 0x0809 //TX_PREEQ_BIN_MIC0_7 +649 0x0A0A //TX_PREEQ_BIN_MIC0_8 +650 0x0C10 //TX_PREEQ_BIN_MIC0_9 +651 0x1013 //TX_PREEQ_BIN_MIC0_10 +652 0x1414 //TX_PREEQ_BIN_MIC0_11 +653 0x261E //TX_PREEQ_BIN_MIC0_12 +654 0x1E14 //TX_PREEQ_BIN_MIC0_13 +655 0x1414 //TX_PREEQ_BIN_MIC0_14 +656 0x2814 //TX_PREEQ_BIN_MIC0_15 +657 0x4000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0030 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x1812 //TX_PREEQ_BIN_MIC1_0 +691 0x0A0A //TX_PREEQ_BIN_MIC1_1 +692 0x0808 //TX_PREEQ_BIN_MIC1_2 +693 0x080A //TX_PREEQ_BIN_MIC1_3 +694 0x0B09 //TX_PREEQ_BIN_MIC1_4 +695 0x0A06 //TX_PREEQ_BIN_MIC1_5 +696 0x0606 //TX_PREEQ_BIN_MIC1_6 +697 0x0605 //TX_PREEQ_BIN_MIC1_7 +698 0x050A //TX_PREEQ_BIN_MIC1_8 +699 0x1505 //TX_PREEQ_BIN_MIC1_9 +700 0x0506 //TX_PREEQ_BIN_MIC1_10 +701 0x0615 //TX_PREEQ_BIN_MIC1_11 +702 0x1516 //TX_PREEQ_BIN_MIC1_12 +703 0x2021 //TX_PREEQ_BIN_MIC1_13 +704 0x2021 //TX_PREEQ_BIN_MIC1_14 +705 0x2021 //TX_PREEQ_BIN_MIC1_15 +706 0x0800 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0E10 //TX_PREEQ_BIN_MIC2_0 +740 0x1010 //TX_PREEQ_BIN_MIC2_1 +741 0x1010 //TX_PREEQ_BIN_MIC2_2 +742 0x1010 //TX_PREEQ_BIN_MIC2_3 +743 0x1010 //TX_PREEQ_BIN_MIC2_4 +744 0x1010 //TX_PREEQ_BIN_MIC2_5 +745 0x1010 //TX_PREEQ_BIN_MIC2_6 +746 0x1010 //TX_PREEQ_BIN_MIC2_7 +747 0x1010 //TX_PREEQ_BIN_MIC2_8 +748 0x1010 //TX_PREEQ_BIN_MIC2_9 +749 0x1010 //TX_PREEQ_BIN_MIC2_10 +750 0x1010 //TX_PREEQ_BIN_MIC2_11 +751 0x1010 //TX_PREEQ_BIN_MIC2_12 +752 0x1010 //TX_PREEQ_BIN_MIC2_13 +753 0x1010 //TX_PREEQ_BIN_MIC2_14 +754 0x0200 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x2000 //TX_NND_WEIGHT +765 0x0060 //TX_MIC_CALIBRATION_0 +766 0x0060 //TX_MIC_CALIBRATION_1 +767 0x0070 //TX_MIC_CALIBRATION_2 +768 0x0070 //TX_MIC_CALIBRATION_3 +769 0x0050 //TX_MIC_PWR_BIAS_0 +770 0x0040 //TX_MIC_PWR_BIAS_1 +771 0x0040 //TX_MIC_PWR_BIAS_2 +772 0x0040 //TX_MIC_PWR_BIAS_3 +773 0x0009 //TX_GAIN_LIMIT_0 +774 0x000F //TX_GAIN_LIMIT_1 +775 0x000F //TX_GAIN_LIMIT_2 +776 0x000F //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x0C00 //TX_TDDRC_ALPHA_UP_01 +784 0x0C00 //TX_TDDRC_ALPHA_UP_02 +785 0x0C00 //TX_TDDRC_ALPHA_UP_03 +786 0x0C00 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x7FFF //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0010 //TX_DEADMIC_SILENCE_TH +817 0x0600 //TX_MIC_DEGRADE_TH +818 0x0078 //TX_DEADMIC_CNT +819 0x0078 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x4848 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0096 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0004 //TX_FILTINDX +854 0x0004 //TX_TDDRC_THRD_0 +855 0x0016 //TX_TDDRC_THRD_1 +856 0x1900 //TX_TDDRC_THRD_2 +857 0x1900 //TX_TDDRC_THRD_3 +858 0x3000 //TX_TDDRC_SLANT_0 +859 0x7B00 //TX_TDDRC_SLANT_1 +860 0x0C00 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x0FDA //TX_TDDRC_DRC_GAIN +867 0x7FFF //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x0028 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x1000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x2339 //TX_SENDFUNC_REG_MICMUTE +898 0x0021 //TX_SENDFUNC_REG_MICMUTE1 +899 0x02BC //TX_MICMUTE_RATIO_THR +900 0x0140 //TX_MICMUTE_AMP_THR +901 0x0004 //TX_MICMUTE_HPF_IND +902 0x00C0 //TX_MICMUTE_LOG_EYR_TH +903 0x0008 //TX_MICMUTE_CVG_TIME +904 0x0008 //TX_MICMUTE_RELEASE_TIME +905 0x01FE //TX_MIC_VOLUME_MIC0MUTE +906 0x0020 //TX_MICMUTE_EPD_OFFSET_0 +907 0x001E //TX_MICMUTE_FRQ_AEC_L +908 0x7999 //TX_MICMUTE_EAD_THR +909 0x7FFF //TX_MICMUTE_LAMBDA_CB_NLE +910 0x7FFF //TX_MICMUTE_LAMBDA_RE_EST +911 0x4000 //TX_DTD_THR1_MICMUTE_0 +912 0x7000 //TX_DTD_THR1_MICMUTE_1 +913 0x7FFF //TX_DTD_THR1_MICMUTE_2 +914 0x7FFF //TX_DTD_THR1_MICMUTE_3 +915 0x6CCC //TX_DTD_THR2_MICMUTE_0 +916 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x1000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x4000 //TX_MICMUTE_C_POST_FLT +922 0x03E8 //TX_MICMUTE_DT_CUT_K +923 0x0001 //TX_MICMUTE_DT_CUT_THR +924 0x03E8 //TX_MICMUTE_DT_CUT_K2 +925 0x0001 //TX_MICMUTE_DT_CUT_THR2 +926 0x0064 //TX_MICMUTE_DT2_HOLD_N +927 0x1000 //TX_MICMUTE_RATIODTH_THCUT +928 0x1000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x7FFF //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0400 //TX_MICMUTE_C_POST_FLT_MASK +931 0x7999 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0258 //TX_MICMUTE_DT_CUT_K1 +933 0x0800 //TX_MICMUTE_N2_SN_EST +934 0xFC00 //TX_MICMUTE_THR_SN_EST_0 +935 0x001C //TX_MICMUTE_MIN_G_CTRL_0 +936 0x6000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x7000 //TX_MICMUTE_B_POST_FILT_0 +938 0x2710 //TX_MIC1RUB_AMP_THR +939 0x0010 //TX_MIC1MUTE_RATIO_THR +940 0x0450 //TX_MIC1MUTE_AMP_THR +941 0x0008 //TX_MIC1MUTE_CVG_TIME +942 0x0008 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x006C //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0004 //RX_SAMPLINGFREQ_SIG +3 0x0004 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x4000 //RX_TDDRC_ALPHA_UP_1 +7 0x4000 //RX_TDDRC_ALPHA_UP_2 +8 0x4000 //RX_TDDRC_ALPHA_UP_3 +9 0x4000 //RX_TDDRC_ALPHA_UP_4 +10 0x065B //RX_PGA +11 0x7E56 //RX_A_HP +12 0x4000 //RX_B_PE +13 0x7800 //RX_THR_PITCH_DET_0 +14 0x7000 //RX_THR_PITCH_DET_1 +15 0x6000 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0400 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x0014 //RX_NS_LVL_CTRL +23 0xF400 //RX_THR_SN_EST +24 0x7E00 //RX_LAMBDA_PFILT +25 0x00C8 //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4870 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4850 //RX_FDEQ_GAIN_6 +46 0x485C //RX_FDEQ_GAIN_7 +47 0x5C60 //RX_FDEQ_GAIN_8 +48 0x685C //RX_FDEQ_GAIN_9 +49 0x5640 //RX_FDEQ_GAIN_10 +50 0x4040 //RX_FDEQ_GAIN_11 +51 0x5C58 //RX_FDEQ_GAIN_12 +52 0x5C60 //RX_FDEQ_GAIN_13 +53 0x6060 //RX_FDEQ_GAIN_14 +54 0x6060 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0402 //RX_FDEQ_BIN_3 +67 0x0504 //RX_FDEQ_BIN_4 +68 0x0209 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0002 //RX_FILTINDX +112 0x0001 //RX_TDDRC_THRD_0 +113 0x0002 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x6000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x4000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x03C3 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x2000 //RX_MIN_G_FP +128 0x0080 //RX_MAX_G_FP +129 0x0012 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x4000 //RX_TDDRC_ALPHA_UP_1 +7 0x4000 //RX_TDDRC_ALPHA_UP_2 +8 0x4000 //RX_TDDRC_ALPHA_UP_3 +9 0x4000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0001 //RX_TDDRC_THRD_0 +113 0x0002 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x6000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x4000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x03C3 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4870 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4850 //RX_FDEQ_GAIN_6 +46 0x485C //RX_FDEQ_GAIN_7 +47 0x5C60 //RX_FDEQ_GAIN_8 +48 0x685C //RX_FDEQ_GAIN_9 +49 0x5640 //RX_FDEQ_GAIN_10 +50 0x4040 //RX_FDEQ_GAIN_11 +51 0x5C58 //RX_FDEQ_GAIN_12 +52 0x5C60 //RX_FDEQ_GAIN_13 +53 0x6060 //RX_FDEQ_GAIN_14 +54 0x6060 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0402 //RX_FDEQ_BIN_3 +67 0x0504 //RX_FDEQ_BIN_4 +68 0x0209 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0012 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x4000 //RX_TDDRC_ALPHA_UP_1 +7 0x4000 //RX_TDDRC_ALPHA_UP_2 +8 0x4000 //RX_TDDRC_ALPHA_UP_3 +9 0x4000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0001 //RX_TDDRC_THRD_0 +113 0x0002 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x6000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x4000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x03C3 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4870 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4850 //RX_FDEQ_GAIN_6 +46 0x485C //RX_FDEQ_GAIN_7 +47 0x5C60 //RX_FDEQ_GAIN_8 +48 0x685C //RX_FDEQ_GAIN_9 +49 0x5640 //RX_FDEQ_GAIN_10 +50 0x4040 //RX_FDEQ_GAIN_11 +51 0x5C58 //RX_FDEQ_GAIN_12 +52 0x5C60 //RX_FDEQ_GAIN_13 +53 0x6060 //RX_FDEQ_GAIN_14 +54 0x6060 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0402 //RX_FDEQ_BIN_3 +67 0x0504 //RX_FDEQ_BIN_4 +68 0x0209 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x001A //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x4000 //RX_TDDRC_ALPHA_UP_1 +7 0x4000 //RX_TDDRC_ALPHA_UP_2 +8 0x4000 //RX_TDDRC_ALPHA_UP_3 +9 0x4000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0001 //RX_TDDRC_THRD_0 +113 0x0002 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x6000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x4000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x03C3 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4870 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4850 //RX_FDEQ_GAIN_6 +46 0x485C //RX_FDEQ_GAIN_7 +47 0x5C60 //RX_FDEQ_GAIN_8 +48 0x685C //RX_FDEQ_GAIN_9 +49 0x5640 //RX_FDEQ_GAIN_10 +50 0x4040 //RX_FDEQ_GAIN_11 +51 0x5C58 //RX_FDEQ_GAIN_12 +52 0x5C60 //RX_FDEQ_GAIN_13 +53 0x6060 //RX_FDEQ_GAIN_14 +54 0x6060 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0402 //RX_FDEQ_BIN_3 +67 0x0504 //RX_FDEQ_BIN_4 +68 0x0209 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0025 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x4000 //RX_TDDRC_ALPHA_UP_1 +7 0x4000 //RX_TDDRC_ALPHA_UP_2 +8 0x4000 //RX_TDDRC_ALPHA_UP_3 +9 0x4000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0001 //RX_TDDRC_THRD_0 +113 0x0002 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x6000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x4000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x03C3 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4870 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4850 //RX_FDEQ_GAIN_6 +46 0x485C //RX_FDEQ_GAIN_7 +47 0x5C60 //RX_FDEQ_GAIN_8 +48 0x685C //RX_FDEQ_GAIN_9 +49 0x5640 //RX_FDEQ_GAIN_10 +50 0x4040 //RX_FDEQ_GAIN_11 +51 0x5C58 //RX_FDEQ_GAIN_12 +52 0x5C60 //RX_FDEQ_GAIN_13 +53 0x6060 //RX_FDEQ_GAIN_14 +54 0x6060 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0402 //RX_FDEQ_BIN_3 +67 0x0504 //RX_FDEQ_BIN_4 +68 0x0209 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0034 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x4000 //RX_TDDRC_ALPHA_UP_1 +7 0x4000 //RX_TDDRC_ALPHA_UP_2 +8 0x4000 //RX_TDDRC_ALPHA_UP_3 +9 0x4000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0001 //RX_TDDRC_THRD_0 +113 0x0002 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x6000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x4000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x03C3 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4870 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4850 //RX_FDEQ_GAIN_6 +46 0x485C //RX_FDEQ_GAIN_7 +47 0x5C60 //RX_FDEQ_GAIN_8 +48 0x685C //RX_FDEQ_GAIN_9 +49 0x5640 //RX_FDEQ_GAIN_10 +50 0x4040 //RX_FDEQ_GAIN_11 +51 0x5C58 //RX_FDEQ_GAIN_12 +52 0x5C60 //RX_FDEQ_GAIN_13 +53 0x6060 //RX_FDEQ_GAIN_14 +54 0x6060 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0402 //RX_FDEQ_BIN_3 +67 0x0504 //RX_FDEQ_BIN_4 +68 0x0209 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x004D //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x4000 //RX_TDDRC_ALPHA_UP_1 +7 0x4000 //RX_TDDRC_ALPHA_UP_2 +8 0x4000 //RX_TDDRC_ALPHA_UP_3 +9 0x4000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0001 //RX_TDDRC_THRD_0 +113 0x0002 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x6000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x4000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x03C3 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4870 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4850 //RX_FDEQ_GAIN_6 +46 0x485C //RX_FDEQ_GAIN_7 +47 0x5C60 //RX_FDEQ_GAIN_8 +48 0x685C //RX_FDEQ_GAIN_9 +49 0x5640 //RX_FDEQ_GAIN_10 +50 0x4040 //RX_FDEQ_GAIN_11 +51 0x5C58 //RX_FDEQ_GAIN_12 +52 0x5C60 //RX_FDEQ_GAIN_13 +53 0x6060 //RX_FDEQ_GAIN_14 +54 0x6060 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0402 //RX_FDEQ_BIN_3 +67 0x0504 //RX_FDEQ_BIN_4 +68 0x0209 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0074 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x4000 //RX_TDDRC_ALPHA_UP_1 +7 0x4000 //RX_TDDRC_ALPHA_UP_2 +8 0x4000 //RX_TDDRC_ALPHA_UP_3 +9 0x4000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0001 //RX_TDDRC_THRD_0 +113 0x0002 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x6000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x4000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x03C3 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4870 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4850 //RX_FDEQ_GAIN_6 +46 0x485C //RX_FDEQ_GAIN_7 +47 0x5C60 //RX_FDEQ_GAIN_8 +48 0x685C //RX_FDEQ_GAIN_9 +49 0x5640 //RX_FDEQ_GAIN_10 +50 0x4040 //RX_FDEQ_GAIN_11 +51 0x5C58 //RX_FDEQ_GAIN_12 +52 0x5C60 //RX_FDEQ_GAIN_13 +53 0x6060 //RX_FDEQ_GAIN_14 +54 0x6060 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0402 //RX_FDEQ_BIN_3 +67 0x0504 //RX_FDEQ_BIN_4 +68 0x0209 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x006C //_ +158 0x0000 //_ +159 0x0004 //_ +160 0x0004 //_ +161 0x000A //_ +162 0x0000 //_ +163 0x4000 //_ +164 0x4000 //_ +165 0x4000 //_ +166 0x4000 //_ +167 0x065B //_ +168 0x7E56 //_ +169 0x4000 //_ +170 0x7800 //_ +171 0x7000 //_ +172 0x6000 //_ +173 0x0008 //_ +174 0x0003 //_ +175 0x0100 //_ +176 0x0020 //_ +177 0x0400 //_ +178 0x000C //_ +179 0x0014 //_ +180 0xF400 //_ +181 0x7E00 //_ +182 0x00C8 //_ +183 0x0190 //_ +184 0x7EB8 //_ +185 0x7EB8 //_ +186 0x7EB8 //_ +187 0x0002 //_ +188 0x0800 //_ +189 0x7EB8 //_ +190 0x7FFF //_ +191 0x0800 //_ +192 0x199A //_ +193 0x0000 //_ +194 0x4000 //_ +195 0x0020 //_ +196 0x4848 //_ +197 0x4848 //_ +198 0x4848 //_ +199 0x4870 //_ +200 0x4848 //_ +201 0x4848 //_ +202 0x4850 //_ +203 0x485C //_ +204 0x5C60 //_ +205 0x685C //_ +206 0x5640 //_ +207 0x4040 //_ +208 0x5C58 //_ +209 0x5C60 //_ +210 0x6060 //_ +211 0x6060 //_ +212 0x4848 //_ +213 0x4848 //_ +214 0x4848 //_ +215 0x4848 //_ +216 0x4848 //_ +217 0x4848 //_ +218 0x4848 //_ +219 0x4848 //_ +220 0x0202 //_ +221 0x0203 //_ +222 0x0303 //_ +223 0x0402 //_ +224 0x0504 //_ +225 0x0209 //_ +226 0x0808 //_ +227 0x090A //_ +228 0x0B0C //_ +229 0x0D0E //_ +230 0x1013 //_ +231 0x1719 //_ +232 0x1B1E //_ +233 0x1E1E //_ +234 0x1E28 //_ +235 0x282C //_ +236 0x0000 //_ +237 0x0000 //_ +238 0x0000 //_ +239 0x0000 //_ +240 0x0000 //_ +241 0x0000 //_ +242 0x0000 //_ +243 0x0000 //_ +244 0x4000 //_ +245 0x0320 //_ +246 0x0018 //_ +247 0x0030 //_ +248 0x0050 //_ +249 0x0080 //_ +250 0x0004 //_ +251 0x5000 //_ +252 0x5000 //_ +253 0x2000 //_ +254 0x5000 //_ +255 0x6400 //_ +256 0x6400 //_ +257 0x2000 //_ +258 0x5000 //_ +259 0x4000 //_ +260 0x4000 //_ +261 0x4000 //_ +262 0x4000 //_ +263 0x7FFF //_ +264 0x7FFF //_ +265 0x7FFF //_ +266 0x7FFF //_ +267 0x0000 //_ +268 0x0002 //_ +269 0x0001 //_ +270 0x0002 //_ +271 0x1800 //_ +272 0x1800 //_ +273 0x6000 //_ +274 0x6E00 //_ +275 0x4000 //_ +276 0x7EB8 //_ +277 0x0000 //_ +278 0x199A //_ +279 0x0001 //_ +280 0x0CCD //_ +281 0x03C3 //_ +282 0x7C00 //_ +283 0x2000 //_ +284 0x2000 //_ +285 0x0080 //_ +286 0x0012 //_ +287 0x0000 //_ +288 0x0000 //_ +289 0x3000 //_ +290 0x3000 //_ +291 0x1800 //_ +292 0x1000 //_ +293 0x04CD //_ +294 0x0F33 //_ +295 0x7333 //_ +296 0x199A //_ +297 0x7333 //_ +298 0x0004 //_ +299 0x6CCD //_ +300 0x799A //_ +301 0x001E //_ +302 0x3000 //_ +303 0x3200 //_ +304 0x2000 //_ +305 0x2000 //_ +306 0x2000 //_ +307 0x2000 //_ +308 0x2000 //_ +309 0x2000 //_ +310 0x2000 //_ +311 0x0000 //_ +312 0x0000 //_ +313 0x0000 //_ +#VOL 0 +163 0x4000 //RX_TDDRC_ALPHA_UP_1 +164 0x4000 //RX_TDDRC_ALPHA_UP_2 +165 0x4000 //RX_TDDRC_ALPHA_UP_3 +166 0x4000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0001 //RX_TDDRC_THRD_0 +270 0x0002 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x6000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x4000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x03C3 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4870 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4850 //RX_FDEQ_GAIN_6 +203 0x485C //RX_FDEQ_GAIN_7 +204 0x5C60 //RX_FDEQ_GAIN_8 +205 0x685C //RX_FDEQ_GAIN_9 +206 0x5640 //RX_FDEQ_GAIN_10 +207 0x4040 //RX_FDEQ_GAIN_11 +208 0x5C58 //RX_FDEQ_GAIN_12 +209 0x5C60 //RX_FDEQ_GAIN_13 +210 0x6060 //RX_FDEQ_GAIN_14 +211 0x6060 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0402 //RX_FDEQ_BIN_3 +224 0x0504 //RX_FDEQ_BIN_4 +225 0x0209 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0012 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x4000 //RX_TDDRC_ALPHA_UP_1 +164 0x4000 //RX_TDDRC_ALPHA_UP_2 +165 0x4000 //RX_TDDRC_ALPHA_UP_3 +166 0x4000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0001 //RX_TDDRC_THRD_0 +270 0x0002 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x6000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x4000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x03C3 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4870 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4850 //RX_FDEQ_GAIN_6 +203 0x485C //RX_FDEQ_GAIN_7 +204 0x5C60 //RX_FDEQ_GAIN_8 +205 0x685C //RX_FDEQ_GAIN_9 +206 0x5640 //RX_FDEQ_GAIN_10 +207 0x4040 //RX_FDEQ_GAIN_11 +208 0x5C58 //RX_FDEQ_GAIN_12 +209 0x5C60 //RX_FDEQ_GAIN_13 +210 0x6060 //RX_FDEQ_GAIN_14 +211 0x6060 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0402 //RX_FDEQ_BIN_3 +224 0x0504 //RX_FDEQ_BIN_4 +225 0x0209 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x001A //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x4000 //RX_TDDRC_ALPHA_UP_1 +164 0x4000 //RX_TDDRC_ALPHA_UP_2 +165 0x4000 //RX_TDDRC_ALPHA_UP_3 +166 0x4000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0001 //RX_TDDRC_THRD_0 +270 0x0002 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x6000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x4000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x03C3 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4870 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4850 //RX_FDEQ_GAIN_6 +203 0x485C //RX_FDEQ_GAIN_7 +204 0x5C60 //RX_FDEQ_GAIN_8 +205 0x685C //RX_FDEQ_GAIN_9 +206 0x5640 //RX_FDEQ_GAIN_10 +207 0x4040 //RX_FDEQ_GAIN_11 +208 0x5C58 //RX_FDEQ_GAIN_12 +209 0x5C60 //RX_FDEQ_GAIN_13 +210 0x6060 //RX_FDEQ_GAIN_14 +211 0x6060 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0402 //RX_FDEQ_BIN_3 +224 0x0504 //RX_FDEQ_BIN_4 +225 0x0209 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0025 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x4000 //RX_TDDRC_ALPHA_UP_1 +164 0x4000 //RX_TDDRC_ALPHA_UP_2 +165 0x4000 //RX_TDDRC_ALPHA_UP_3 +166 0x4000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0001 //RX_TDDRC_THRD_0 +270 0x0002 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x6000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x4000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x03C3 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4870 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4850 //RX_FDEQ_GAIN_6 +203 0x485C //RX_FDEQ_GAIN_7 +204 0x5C60 //RX_FDEQ_GAIN_8 +205 0x685C //RX_FDEQ_GAIN_9 +206 0x5640 //RX_FDEQ_GAIN_10 +207 0x4040 //RX_FDEQ_GAIN_11 +208 0x5C58 //RX_FDEQ_GAIN_12 +209 0x5C60 //RX_FDEQ_GAIN_13 +210 0x6060 //RX_FDEQ_GAIN_14 +211 0x6060 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0402 //RX_FDEQ_BIN_3 +224 0x0504 //RX_FDEQ_BIN_4 +225 0x0209 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0034 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x4000 //RX_TDDRC_ALPHA_UP_1 +164 0x4000 //RX_TDDRC_ALPHA_UP_2 +165 0x4000 //RX_TDDRC_ALPHA_UP_3 +166 0x4000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0001 //RX_TDDRC_THRD_0 +270 0x0002 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x6000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x4000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x03C3 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4870 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4850 //RX_FDEQ_GAIN_6 +203 0x485C //RX_FDEQ_GAIN_7 +204 0x5C60 //RX_FDEQ_GAIN_8 +205 0x685C //RX_FDEQ_GAIN_9 +206 0x5640 //RX_FDEQ_GAIN_10 +207 0x4040 //RX_FDEQ_GAIN_11 +208 0x5C58 //RX_FDEQ_GAIN_12 +209 0x5C60 //RX_FDEQ_GAIN_13 +210 0x6060 //RX_FDEQ_GAIN_14 +211 0x6060 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0402 //RX_FDEQ_BIN_3 +224 0x0504 //RX_FDEQ_BIN_4 +225 0x0209 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x004D //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x4000 //RX_TDDRC_ALPHA_UP_1 +164 0x4000 //RX_TDDRC_ALPHA_UP_2 +165 0x4000 //RX_TDDRC_ALPHA_UP_3 +166 0x4000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0001 //RX_TDDRC_THRD_0 +270 0x0002 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x6000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x4000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x03C3 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4870 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4850 //RX_FDEQ_GAIN_6 +203 0x485C //RX_FDEQ_GAIN_7 +204 0x5C60 //RX_FDEQ_GAIN_8 +205 0x685C //RX_FDEQ_GAIN_9 +206 0x5640 //RX_FDEQ_GAIN_10 +207 0x4040 //RX_FDEQ_GAIN_11 +208 0x5C58 //RX_FDEQ_GAIN_12 +209 0x5C60 //RX_FDEQ_GAIN_13 +210 0x6060 //RX_FDEQ_GAIN_14 +211 0x6060 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0402 //RX_FDEQ_BIN_3 +224 0x0504 //RX_FDEQ_BIN_4 +225 0x0209 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0074 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x4000 //RX_TDDRC_ALPHA_UP_1 +164 0x4000 //RX_TDDRC_ALPHA_UP_2 +165 0x4000 //RX_TDDRC_ALPHA_UP_3 +166 0x4000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0001 //RX_TDDRC_THRD_0 +270 0x0002 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x6000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x4000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x03C3 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4870 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4850 //RX_FDEQ_GAIN_6 +203 0x485C //RX_FDEQ_GAIN_7 +204 0x5C60 //RX_FDEQ_GAIN_8 +205 0x685C //RX_FDEQ_GAIN_9 +206 0x5640 //RX_FDEQ_GAIN_10 +207 0x4040 //RX_FDEQ_GAIN_11 +208 0x5C58 //RX_FDEQ_GAIN_12 +209 0x5C60 //RX_FDEQ_GAIN_13 +210 0x6060 //RX_FDEQ_GAIN_14 +211 0x6060 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0402 //RX_FDEQ_BIN_3 +224 0x0504 //RX_FDEQ_BIN_4 +225 0x0209 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME HANDSFREE-HANDFREE-CUSTOM1-FB +#PARAM_MODE FULL +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0001 //TX_OPERATION_MODE_0 +1 0x0001 //TX_OPERATION_MODE_1 +2 0x0033 //TX_PATCH_REG +3 0x6B74 //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0003 //TX_NUM_MIC +6 0x0004 //TX_SAMPLINGFREQ_SIG +7 0x0004 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009D //TX_DIST2REF1 +22 0x0010 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0A19 //TX_PGA_0 +28 0x0A19 //TX_PGA_1 +29 0x0A19 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0001 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0002 //TX_MIC_DATA_SRC0 +42 0x0000 //TX_MIC_DATA_SRC1 +43 0x0001 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3B33 //TX_DIST2REF_11 +73 0x0A70 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0800 //TX_MIC_REFBLK_VOLUME +108 0x0CAE //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0015 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7E56 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x1800 //TX_THR_PITCH_DET_0 +131 0x1000 //TX_THR_PITCH_DET_1 +132 0x0800 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x0028 //TX_TAIL_LENGTH +147 0x0300 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x7A00 //TX_EAD_THR +151 0x1000 //TX_THR_RE_EST +152 0x0800 //TX_MIN_EQ_RE_EST_0 +153 0x2000 //TX_MIN_EQ_RE_EST_1 +154 0x2000 //TX_MIN_EQ_RE_EST_2 +155 0x4000 //TX_MIN_EQ_RE_EST_3 +156 0x4000 //TX_MIN_EQ_RE_EST_4 +157 0x7FFF //TX_MIN_EQ_RE_EST_5 +158 0x7FFF //TX_MIN_EQ_RE_EST_6 +159 0x7FFF //TX_MIN_EQ_RE_EST_7 +160 0x7FFF //TX_MIN_EQ_RE_EST_8 +161 0x7FFF //TX_MIN_EQ_RE_EST_9 +162 0x7FFF //TX_MIN_EQ_RE_EST_10 +163 0x7FFF //TX_MIN_EQ_RE_EST_11 +164 0x7FFF //TX_MIN_EQ_RE_EST_12 +165 0x4000 //TX_LAMBDA_RE_EST +166 0x0CCD //TX_LAMBDA_CB_NLE +167 0x2000 //TX_C_POST_FLT +168 0x7FFF //TX_GAIN_NP +169 0x0180 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x09C4 //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x7D00 //TX_DTD_THR1_0 +198 0x7FF0 //TX_DTD_THR1_1 +199 0x7FF0 //TX_DTD_THR1_2 +200 0x7FF0 //TX_DTD_THR1_3 +201 0x7FF0 //TX_DTD_THR1_4 +202 0x7FF0 //TX_DTD_THR1_5 +203 0x7FF0 //TX_DTD_THR1_6 +204 0x0CCD //TX_DTD_THR2_0 +205 0x0CCD //TX_DTD_THR2_1 +206 0x0CCD //TX_DTD_THR2_2 +207 0x0CCD //TX_DTD_THR2_3 +208 0x0CCD //TX_DTD_THR2_4 +209 0x0CCD //TX_DTD_THR2_5 +210 0x0CCD //TX_DTD_THR2_6 +211 0x7FFF //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x0DAC //TX_DT_CUT_K +214 0x0020 //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x7FFF //TX_DTD_MIC_BLK +221 0x023E //TX_ADPT_STRICT_L +222 0x023E //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x2000 //TX_B_POST_FILT_ECHO_L +229 0x2000 //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x1000 //TX_B_LESSCUT_RTO_ECHO +232 0x0063 //TX_EPD_OFFSET_00 +233 0x0000 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x0000 //TX_DTD_THR1_7 +238 0x0000 //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xF800 //TX_THR_SN_EST_0 +243 0xFA00 //TX_THR_SN_EST_1 +244 0xFA00 //TX_THR_SN_EST_2 +245 0xFB00 //TX_THR_SN_EST_3 +246 0xFA00 //TX_THR_SN_EST_4 +247 0xFA00 //TX_THR_SN_EST_5 +248 0xF800 //TX_THR_SN_EST_6 +249 0xF800 //TX_THR_SN_EST_7 +250 0x0100 //TX_DELTA_THR_SN_EST_0 +251 0x0100 //TX_DELTA_THR_SN_EST_1 +252 0x0200 //TX_DELTA_THR_SN_EST_2 +253 0x0100 //TX_DELTA_THR_SN_EST_3 +254 0x0100 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0200 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x4000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x4000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x2000 //TX_B_POST_FLT_0 +280 0x1000 //TX_B_POST_FLT_1 +281 0x0010 //TX_NS_LVL_CTRL_0 +282 0x0014 //TX_NS_LVL_CTRL_1 +283 0x0018 //TX_NS_LVL_CTRL_2 +284 0x0016 //TX_NS_LVL_CTRL_3 +285 0x0014 //TX_NS_LVL_CTRL_4 +286 0x0011 //TX_NS_LVL_CTRL_5 +287 0x0014 //TX_NS_LVL_CTRL_6 +288 0x0011 //TX_NS_LVL_CTRL_7 +289 0x000F //TX_MIN_GAIN_S_0 +290 0x0010 //TX_MIN_GAIN_S_1 +291 0x0010 //TX_MIN_GAIN_S_2 +292 0x0010 //TX_MIN_GAIN_S_3 +293 0x0010 //TX_MIN_GAIN_S_4 +294 0x0010 //TX_MIN_GAIN_S_5 +295 0x0010 //TX_MIN_GAIN_S_6 +296 0x000F //TX_MIN_GAIN_S_7 +297 0x6000 //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x4000 //TX_SNRI_SUP_1 +302 0x4000 //TX_SNRI_SUP_2 +303 0x4000 //TX_SNRI_SUP_3 +304 0x4000 //TX_SNRI_SUP_4 +305 0x50C0 //TX_SNRI_SUP_5 +306 0x4000 //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x0018 //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x5000 //TX_A_POST_FILT_S_0 +315 0x4C00 //TX_A_POST_FILT_S_1 +316 0x4000 //TX_A_POST_FILT_S_2 +317 0x6000 //TX_A_POST_FILT_S_3 +318 0x4000 //TX_A_POST_FILT_S_4 +319 0x5000 //TX_A_POST_FILT_S_5 +320 0x6000 //TX_A_POST_FILT_S_6 +321 0x7000 //TX_A_POST_FILT_S_7 +322 0x2000 //TX_B_POST_FILT_0 +323 0x2000 //TX_B_POST_FILT_1 +324 0x2000 //TX_B_POST_FILT_2 +325 0x4000 //TX_B_POST_FILT_3 +326 0x4000 //TX_B_POST_FILT_4 +327 0x1000 //TX_B_POST_FILT_5 +328 0x1000 //TX_B_POST_FILT_6 +329 0x2000 //TX_B_POST_FILT_7 +330 0x4000 //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x6000 //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7C00 //TX_LAMBDA_PFILT +339 0x7C00 //TX_LAMBDA_PFILT_S_0 +340 0x7C00 //TX_LAMBDA_PFILT_S_1 +341 0x7A00 //TX_LAMBDA_PFILT_S_2 +342 0x7C00 //TX_LAMBDA_PFILT_S_3 +343 0x7C00 //TX_LAMBDA_PFILT_S_4 +344 0x7C00 //TX_LAMBDA_PFILT_S_5 +345 0x7C00 //TX_LAMBDA_PFILT_S_6 +346 0x7C00 //TX_LAMBDA_PFILT_S_7 +347 0x0000 //TX_K_PEPPER +348 0x0800 //TX_A_PEPPER +349 0x1EAA //TX_K_PEPPER_HF +350 0x0600 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0200 //TX_DT_BINVAD_TH_0 +354 0x0200 //TX_DT_BINVAD_TH_1 +355 0x0200 //TX_DT_BINVAD_TH_2 +356 0x0200 //TX_DT_BINVAD_TH_3 +357 0x1F40 //TX_DT_BINVAD_ENDF +358 0x0100 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0064 //TX_NDETCT +367 0x0050 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x07D0 //TX_NOISE_TH_1 +371 0x0DAC //TX_NOISE_TH_2 +372 0x4E20 //TX_NOISE_TH_3 +373 0x4E20 //TX_NOISE_TH_4 +374 0x59D8 //TX_NOISE_TH_5 +375 0x7FFF //TX_NOISE_TH_5_2 +376 0x0000 //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x2710 //TX_NOISE_TH_6 +379 0x0033 //TX_MINENOISE_TH +380 0xD508 //TX_MORENS_TFMASK_TH +381 0x0001 //TX_DRC_QUIET_FLOOR +382 0x7999 //TX_RATIODTL_CUT_TH +383 0x0119 //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x0333 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x7FFF //TX_POST_MASK_SUP_HSNE +392 0x1388 //TX_TAIL_DET_TH +393 0x4000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0080 //TX_SUPHIGH_TH +396 0x0000 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x1800 //TX_C_POST_FLT_MASK +399 0x4000 //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0002 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x0033 //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x7FFF //TX_MIN_G_CTRL_SSNS +409 0x0000 //TX_METAL_RTO_THR +410 0x4848 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x4000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x0230 //TX_NOR_OFF_THR +498 0x0CCD //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x2000 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0x4650 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x7FFF //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0x3000 //TX_DEREVERB_LF_MU +515 0x34CD //TX_DEREVERB_HF_MU +516 0x0007 //TX_DEREVERB_DELAY +517 0x0004 //TX_DEREVERB_COEF_LEN +518 0x0003 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x3A98 //TX_GSC_RTOL_TH +522 0x3A98 //TX_GSC_RTOH_TH +523 0x7E2C //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0020 //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x5048 //TX_FDEQ_GAIN_5 +573 0x4848 //TX_FDEQ_GAIN_6 +574 0x4848 //TX_FDEQ_GAIN_7 +575 0x4848 //TX_FDEQ_GAIN_8 +576 0x4848 //TX_FDEQ_GAIN_9 +577 0x5B5B //TX_FDEQ_GAIN_10 +578 0x737B //TX_FDEQ_GAIN_11 +579 0x7B9A //TX_FDEQ_GAIN_12 +580 0x9AC4 //TX_FDEQ_GAIN_13 +581 0xC4C4 //TX_FDEQ_GAIN_14 +582 0xC4C4 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0304 //TX_FDEQ_BIN_2 +594 0x0405 //TX_FDEQ_BIN_3 +595 0x0607 //TX_FDEQ_BIN_4 +596 0x0809 //TX_FDEQ_BIN_5 +597 0x0A0B //TX_FDEQ_BIN_6 +598 0x0C0D //TX_FDEQ_BIN_7 +599 0x0E0F //TX_FDEQ_BIN_8 +600 0x1011 //TX_FDEQ_BIN_9 +601 0x1214 //TX_FDEQ_BIN_10 +602 0x1618 //TX_FDEQ_BIN_11 +603 0x1C1C //TX_FDEQ_BIN_12 +604 0x2020 //TX_FDEQ_BIN_13 +605 0x2020 //TX_FDEQ_BIN_14 +606 0x2011 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0030 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4849 //TX_PREEQ_GAIN_MIC0_6 +624 0x4A4B //TX_PREEQ_GAIN_MIC0_7 +625 0x4C4B //TX_PREEQ_GAIN_MIC0_8 +626 0x4A48 //TX_PREEQ_GAIN_MIC0_9 +627 0x4B4C //TX_PREEQ_GAIN_MIC0_10 +628 0x4C4B //TX_PREEQ_GAIN_MIC0_11 +629 0x4838 //TX_PREEQ_GAIN_MIC0_12 +630 0x3858 //TX_PREEQ_GAIN_MIC0_13 +631 0x7060 //TX_PREEQ_GAIN_MIC0_14 +632 0x9870 //TX_PREEQ_GAIN_MIC0_15 +633 0x5848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0202 //TX_PREEQ_BIN_MIC0_0 +642 0x0203 //TX_PREEQ_BIN_MIC0_1 +643 0x0303 //TX_PREEQ_BIN_MIC0_2 +644 0x0304 //TX_PREEQ_BIN_MIC0_3 +645 0x0405 //TX_PREEQ_BIN_MIC0_4 +646 0x0506 //TX_PREEQ_BIN_MIC0_5 +647 0x0808 //TX_PREEQ_BIN_MIC0_6 +648 0x0809 //TX_PREEQ_BIN_MIC0_7 +649 0x0A0A //TX_PREEQ_BIN_MIC0_8 +650 0x0C10 //TX_PREEQ_BIN_MIC0_9 +651 0x1013 //TX_PREEQ_BIN_MIC0_10 +652 0x1414 //TX_PREEQ_BIN_MIC0_11 +653 0x261E //TX_PREEQ_BIN_MIC0_12 +654 0x1E14 //TX_PREEQ_BIN_MIC0_13 +655 0x1414 //TX_PREEQ_BIN_MIC0_14 +656 0x2814 //TX_PREEQ_BIN_MIC0_15 +657 0x4000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0030 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x1812 //TX_PREEQ_BIN_MIC1_0 +691 0x0A0A //TX_PREEQ_BIN_MIC1_1 +692 0x0808 //TX_PREEQ_BIN_MIC1_2 +693 0x080A //TX_PREEQ_BIN_MIC1_3 +694 0x0B09 //TX_PREEQ_BIN_MIC1_4 +695 0x0A06 //TX_PREEQ_BIN_MIC1_5 +696 0x0606 //TX_PREEQ_BIN_MIC1_6 +697 0x0605 //TX_PREEQ_BIN_MIC1_7 +698 0x050A //TX_PREEQ_BIN_MIC1_8 +699 0x1505 //TX_PREEQ_BIN_MIC1_9 +700 0x0506 //TX_PREEQ_BIN_MIC1_10 +701 0x0615 //TX_PREEQ_BIN_MIC1_11 +702 0x1516 //TX_PREEQ_BIN_MIC1_12 +703 0x2021 //TX_PREEQ_BIN_MIC1_13 +704 0x2021 //TX_PREEQ_BIN_MIC1_14 +705 0x2021 //TX_PREEQ_BIN_MIC1_15 +706 0x0800 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0E10 //TX_PREEQ_BIN_MIC2_0 +740 0x1010 //TX_PREEQ_BIN_MIC2_1 +741 0x1010 //TX_PREEQ_BIN_MIC2_2 +742 0x1010 //TX_PREEQ_BIN_MIC2_3 +743 0x1010 //TX_PREEQ_BIN_MIC2_4 +744 0x1010 //TX_PREEQ_BIN_MIC2_5 +745 0x1010 //TX_PREEQ_BIN_MIC2_6 +746 0x1010 //TX_PREEQ_BIN_MIC2_7 +747 0x1010 //TX_PREEQ_BIN_MIC2_8 +748 0x1010 //TX_PREEQ_BIN_MIC2_9 +749 0x1010 //TX_PREEQ_BIN_MIC2_10 +750 0x1010 //TX_PREEQ_BIN_MIC2_11 +751 0x1010 //TX_PREEQ_BIN_MIC2_12 +752 0x1010 //TX_PREEQ_BIN_MIC2_13 +753 0x1010 //TX_PREEQ_BIN_MIC2_14 +754 0x0200 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x2000 //TX_NND_WEIGHT +765 0x0060 //TX_MIC_CALIBRATION_0 +766 0x0060 //TX_MIC_CALIBRATION_1 +767 0x0070 //TX_MIC_CALIBRATION_2 +768 0x0070 //TX_MIC_CALIBRATION_3 +769 0x0050 //TX_MIC_PWR_BIAS_0 +770 0x0040 //TX_MIC_PWR_BIAS_1 +771 0x0040 //TX_MIC_PWR_BIAS_2 +772 0x0040 //TX_MIC_PWR_BIAS_3 +773 0x0009 //TX_GAIN_LIMIT_0 +774 0x000F //TX_GAIN_LIMIT_1 +775 0x000F //TX_GAIN_LIMIT_2 +776 0x000F //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x0C00 //TX_TDDRC_ALPHA_UP_01 +784 0x0C00 //TX_TDDRC_ALPHA_UP_02 +785 0x0C00 //TX_TDDRC_ALPHA_UP_03 +786 0x0C00 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x7FFF //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0010 //TX_DEADMIC_SILENCE_TH +817 0x0600 //TX_MIC_DEGRADE_TH +818 0x0078 //TX_DEADMIC_CNT +819 0x0078 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x4848 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0096 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0004 //TX_FILTINDX +854 0x0004 //TX_TDDRC_THRD_0 +855 0x0016 //TX_TDDRC_THRD_1 +856 0x1900 //TX_TDDRC_THRD_2 +857 0x1900 //TX_TDDRC_THRD_3 +858 0x3000 //TX_TDDRC_SLANT_0 +859 0x7B00 //TX_TDDRC_SLANT_1 +860 0x0C00 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x0FDA //TX_TDDRC_DRC_GAIN +867 0x7FFF //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x0028 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x1000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x2339 //TX_SENDFUNC_REG_MICMUTE +898 0x0021 //TX_SENDFUNC_REG_MICMUTE1 +899 0x02BC //TX_MICMUTE_RATIO_THR +900 0x0140 //TX_MICMUTE_AMP_THR +901 0x0004 //TX_MICMUTE_HPF_IND +902 0x00C0 //TX_MICMUTE_LOG_EYR_TH +903 0x0008 //TX_MICMUTE_CVG_TIME +904 0x0008 //TX_MICMUTE_RELEASE_TIME +905 0x01FE //TX_MIC_VOLUME_MIC0MUTE +906 0x0020 //TX_MICMUTE_EPD_OFFSET_0 +907 0x001E //TX_MICMUTE_FRQ_AEC_L +908 0x7999 //TX_MICMUTE_EAD_THR +909 0x7FFF //TX_MICMUTE_LAMBDA_CB_NLE +910 0x7FFF //TX_MICMUTE_LAMBDA_RE_EST +911 0x4000 //TX_DTD_THR1_MICMUTE_0 +912 0x7000 //TX_DTD_THR1_MICMUTE_1 +913 0x7FFF //TX_DTD_THR1_MICMUTE_2 +914 0x7FFF //TX_DTD_THR1_MICMUTE_3 +915 0x6CCC //TX_DTD_THR2_MICMUTE_0 +916 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x1000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x4000 //TX_MICMUTE_C_POST_FLT +922 0x03E8 //TX_MICMUTE_DT_CUT_K +923 0x0001 //TX_MICMUTE_DT_CUT_THR +924 0x03E8 //TX_MICMUTE_DT_CUT_K2 +925 0x0001 //TX_MICMUTE_DT_CUT_THR2 +926 0x0064 //TX_MICMUTE_DT2_HOLD_N +927 0x1000 //TX_MICMUTE_RATIODTH_THCUT +928 0x1000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x7FFF //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0400 //TX_MICMUTE_C_POST_FLT_MASK +931 0x7999 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0258 //TX_MICMUTE_DT_CUT_K1 +933 0x0800 //TX_MICMUTE_N2_SN_EST +934 0xFC00 //TX_MICMUTE_THR_SN_EST_0 +935 0x001C //TX_MICMUTE_MIN_G_CTRL_0 +936 0x6000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x7000 //TX_MICMUTE_B_POST_FILT_0 +938 0x2710 //TX_MIC1RUB_AMP_THR +939 0x0010 //TX_MIC1MUTE_RATIO_THR +940 0x0450 //TX_MIC1MUTE_AMP_THR +941 0x0008 //TX_MIC1MUTE_CVG_TIME +942 0x0008 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x006C //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0004 //RX_SAMPLINGFREQ_SIG +3 0x0004 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x4000 //RX_TDDRC_ALPHA_UP_1 +7 0x4000 //RX_TDDRC_ALPHA_UP_2 +8 0x4000 //RX_TDDRC_ALPHA_UP_3 +9 0x4000 //RX_TDDRC_ALPHA_UP_4 +10 0x065B //RX_PGA +11 0x7E56 //RX_A_HP +12 0x4000 //RX_B_PE +13 0x7800 //RX_THR_PITCH_DET_0 +14 0x7000 //RX_THR_PITCH_DET_1 +15 0x6000 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0400 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x0014 //RX_NS_LVL_CTRL +23 0xF400 //RX_THR_SN_EST +24 0x7E00 //RX_LAMBDA_PFILT +25 0x00C8 //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4870 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4850 //RX_FDEQ_GAIN_6 +46 0x485C //RX_FDEQ_GAIN_7 +47 0x5C60 //RX_FDEQ_GAIN_8 +48 0x685C //RX_FDEQ_GAIN_9 +49 0x5640 //RX_FDEQ_GAIN_10 +50 0x4040 //RX_FDEQ_GAIN_11 +51 0x5C58 //RX_FDEQ_GAIN_12 +52 0x5C60 //RX_FDEQ_GAIN_13 +53 0x6060 //RX_FDEQ_GAIN_14 +54 0x6060 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0402 //RX_FDEQ_BIN_3 +67 0x0504 //RX_FDEQ_BIN_4 +68 0x0209 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0002 //RX_FILTINDX +112 0x0001 //RX_TDDRC_THRD_0 +113 0x0002 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x6000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x4000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x03C3 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x2000 //RX_MIN_G_FP +128 0x0080 //RX_MAX_G_FP +129 0x0012 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x4000 //RX_TDDRC_ALPHA_UP_1 +7 0x4000 //RX_TDDRC_ALPHA_UP_2 +8 0x4000 //RX_TDDRC_ALPHA_UP_3 +9 0x4000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0001 //RX_TDDRC_THRD_0 +113 0x0002 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x6000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x4000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x03C3 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4870 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4850 //RX_FDEQ_GAIN_6 +46 0x485C //RX_FDEQ_GAIN_7 +47 0x5C60 //RX_FDEQ_GAIN_8 +48 0x685C //RX_FDEQ_GAIN_9 +49 0x5640 //RX_FDEQ_GAIN_10 +50 0x4040 //RX_FDEQ_GAIN_11 +51 0x5C58 //RX_FDEQ_GAIN_12 +52 0x5C60 //RX_FDEQ_GAIN_13 +53 0x6060 //RX_FDEQ_GAIN_14 +54 0x6060 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0402 //RX_FDEQ_BIN_3 +67 0x0504 //RX_FDEQ_BIN_4 +68 0x0209 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0012 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x4000 //RX_TDDRC_ALPHA_UP_1 +7 0x4000 //RX_TDDRC_ALPHA_UP_2 +8 0x4000 //RX_TDDRC_ALPHA_UP_3 +9 0x4000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0001 //RX_TDDRC_THRD_0 +113 0x0002 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x6000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x4000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x03C3 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4870 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4850 //RX_FDEQ_GAIN_6 +46 0x485C //RX_FDEQ_GAIN_7 +47 0x5C60 //RX_FDEQ_GAIN_8 +48 0x685C //RX_FDEQ_GAIN_9 +49 0x5640 //RX_FDEQ_GAIN_10 +50 0x4040 //RX_FDEQ_GAIN_11 +51 0x5C58 //RX_FDEQ_GAIN_12 +52 0x5C60 //RX_FDEQ_GAIN_13 +53 0x6060 //RX_FDEQ_GAIN_14 +54 0x6060 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0402 //RX_FDEQ_BIN_3 +67 0x0504 //RX_FDEQ_BIN_4 +68 0x0209 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x001A //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x4000 //RX_TDDRC_ALPHA_UP_1 +7 0x4000 //RX_TDDRC_ALPHA_UP_2 +8 0x4000 //RX_TDDRC_ALPHA_UP_3 +9 0x4000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0001 //RX_TDDRC_THRD_0 +113 0x0002 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x6000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x4000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x03C3 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4870 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4850 //RX_FDEQ_GAIN_6 +46 0x485C //RX_FDEQ_GAIN_7 +47 0x5C60 //RX_FDEQ_GAIN_8 +48 0x685C //RX_FDEQ_GAIN_9 +49 0x5640 //RX_FDEQ_GAIN_10 +50 0x4040 //RX_FDEQ_GAIN_11 +51 0x5C58 //RX_FDEQ_GAIN_12 +52 0x5C60 //RX_FDEQ_GAIN_13 +53 0x6060 //RX_FDEQ_GAIN_14 +54 0x6060 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0402 //RX_FDEQ_BIN_3 +67 0x0504 //RX_FDEQ_BIN_4 +68 0x0209 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0025 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x4000 //RX_TDDRC_ALPHA_UP_1 +7 0x4000 //RX_TDDRC_ALPHA_UP_2 +8 0x4000 //RX_TDDRC_ALPHA_UP_3 +9 0x4000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0001 //RX_TDDRC_THRD_0 +113 0x0002 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x6000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x4000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x03C3 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4870 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4850 //RX_FDEQ_GAIN_6 +46 0x485C //RX_FDEQ_GAIN_7 +47 0x5C60 //RX_FDEQ_GAIN_8 +48 0x685C //RX_FDEQ_GAIN_9 +49 0x5640 //RX_FDEQ_GAIN_10 +50 0x4040 //RX_FDEQ_GAIN_11 +51 0x5C58 //RX_FDEQ_GAIN_12 +52 0x5C60 //RX_FDEQ_GAIN_13 +53 0x6060 //RX_FDEQ_GAIN_14 +54 0x6060 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0402 //RX_FDEQ_BIN_3 +67 0x0504 //RX_FDEQ_BIN_4 +68 0x0209 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0034 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x4000 //RX_TDDRC_ALPHA_UP_1 +7 0x4000 //RX_TDDRC_ALPHA_UP_2 +8 0x4000 //RX_TDDRC_ALPHA_UP_3 +9 0x4000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0001 //RX_TDDRC_THRD_0 +113 0x0002 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x6000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x4000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x03C3 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4870 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4850 //RX_FDEQ_GAIN_6 +46 0x485C //RX_FDEQ_GAIN_7 +47 0x5C60 //RX_FDEQ_GAIN_8 +48 0x685C //RX_FDEQ_GAIN_9 +49 0x5640 //RX_FDEQ_GAIN_10 +50 0x4040 //RX_FDEQ_GAIN_11 +51 0x5C58 //RX_FDEQ_GAIN_12 +52 0x5C60 //RX_FDEQ_GAIN_13 +53 0x6060 //RX_FDEQ_GAIN_14 +54 0x6060 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0402 //RX_FDEQ_BIN_3 +67 0x0504 //RX_FDEQ_BIN_4 +68 0x0209 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x004D //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x4000 //RX_TDDRC_ALPHA_UP_1 +7 0x4000 //RX_TDDRC_ALPHA_UP_2 +8 0x4000 //RX_TDDRC_ALPHA_UP_3 +9 0x4000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0001 //RX_TDDRC_THRD_0 +113 0x0002 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x6000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x4000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x03C3 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4870 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4850 //RX_FDEQ_GAIN_6 +46 0x485C //RX_FDEQ_GAIN_7 +47 0x5C60 //RX_FDEQ_GAIN_8 +48 0x685C //RX_FDEQ_GAIN_9 +49 0x5640 //RX_FDEQ_GAIN_10 +50 0x4040 //RX_FDEQ_GAIN_11 +51 0x5C58 //RX_FDEQ_GAIN_12 +52 0x5C60 //RX_FDEQ_GAIN_13 +53 0x6060 //RX_FDEQ_GAIN_14 +54 0x6060 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0402 //RX_FDEQ_BIN_3 +67 0x0504 //RX_FDEQ_BIN_4 +68 0x0209 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0074 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x4000 //RX_TDDRC_ALPHA_UP_1 +7 0x4000 //RX_TDDRC_ALPHA_UP_2 +8 0x4000 //RX_TDDRC_ALPHA_UP_3 +9 0x4000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0001 //RX_TDDRC_THRD_0 +113 0x0002 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x6000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x4000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x03C3 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4870 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4850 //RX_FDEQ_GAIN_6 +46 0x485C //RX_FDEQ_GAIN_7 +47 0x5C60 //RX_FDEQ_GAIN_8 +48 0x685C //RX_FDEQ_GAIN_9 +49 0x5640 //RX_FDEQ_GAIN_10 +50 0x4040 //RX_FDEQ_GAIN_11 +51 0x5C58 //RX_FDEQ_GAIN_12 +52 0x5C60 //RX_FDEQ_GAIN_13 +53 0x6060 //RX_FDEQ_GAIN_14 +54 0x6060 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0402 //RX_FDEQ_BIN_3 +67 0x0504 //RX_FDEQ_BIN_4 +68 0x0209 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x006C //_ +158 0x0000 //_ +159 0x0004 //_ +160 0x0004 //_ +161 0x000A //_ +162 0x0000 //_ +163 0x4000 //_ +164 0x4000 //_ +165 0x4000 //_ +166 0x4000 //_ +167 0x065B //_ +168 0x7E56 //_ +169 0x4000 //_ +170 0x7800 //_ +171 0x7000 //_ +172 0x6000 //_ +173 0x0008 //_ +174 0x0003 //_ +175 0x0100 //_ +176 0x0020 //_ +177 0x0400 //_ +178 0x000C //_ +179 0x0014 //_ +180 0xF400 //_ +181 0x7E00 //_ +182 0x00C8 //_ +183 0x0190 //_ +184 0x7EB8 //_ +185 0x7EB8 //_ +186 0x7EB8 //_ +187 0x0002 //_ +188 0x0800 //_ +189 0x7EB8 //_ +190 0x7FFF //_ +191 0x0800 //_ +192 0x199A //_ +193 0x0000 //_ +194 0x4000 //_ +195 0x0020 //_ +196 0x4848 //_ +197 0x4848 //_ +198 0x4848 //_ +199 0x4870 //_ +200 0x4848 //_ +201 0x4848 //_ +202 0x4850 //_ +203 0x485C //_ +204 0x5C60 //_ +205 0x685C //_ +206 0x5640 //_ +207 0x4040 //_ +208 0x5C58 //_ +209 0x5C60 //_ +210 0x6060 //_ +211 0x6060 //_ +212 0x4848 //_ +213 0x4848 //_ +214 0x4848 //_ +215 0x4848 //_ +216 0x4848 //_ +217 0x4848 //_ +218 0x4848 //_ +219 0x4848 //_ +220 0x0202 //_ +221 0x0203 //_ +222 0x0303 //_ +223 0x0402 //_ +224 0x0504 //_ +225 0x0209 //_ +226 0x0808 //_ +227 0x090A //_ +228 0x0B0C //_ +229 0x0D0E //_ +230 0x1013 //_ +231 0x1719 //_ +232 0x1B1E //_ +233 0x1E1E //_ +234 0x1E28 //_ +235 0x282C //_ +236 0x0000 //_ +237 0x0000 //_ +238 0x0000 //_ +239 0x0000 //_ +240 0x0000 //_ +241 0x0000 //_ +242 0x0000 //_ +243 0x0000 //_ +244 0x4000 //_ +245 0x0320 //_ +246 0x0018 //_ +247 0x0030 //_ +248 0x0050 //_ +249 0x0080 //_ +250 0x0004 //_ +251 0x5000 //_ +252 0x5000 //_ +253 0x2000 //_ +254 0x5000 //_ +255 0x6400 //_ +256 0x6400 //_ +257 0x2000 //_ +258 0x5000 //_ +259 0x4000 //_ +260 0x4000 //_ +261 0x4000 //_ +262 0x4000 //_ +263 0x7FFF //_ +264 0x7FFF //_ +265 0x7FFF //_ +266 0x7FFF //_ +267 0x0000 //_ +268 0x0002 //_ +269 0x0001 //_ +270 0x0002 //_ +271 0x1800 //_ +272 0x1800 //_ +273 0x6000 //_ +274 0x6E00 //_ +275 0x4000 //_ +276 0x7EB8 //_ +277 0x0000 //_ +278 0x199A //_ +279 0x0001 //_ +280 0x0CCD //_ +281 0x03C3 //_ +282 0x7C00 //_ +283 0x2000 //_ +284 0x2000 //_ +285 0x0080 //_ +286 0x0012 //_ +287 0x0000 //_ +288 0x0000 //_ +289 0x3000 //_ +290 0x3000 //_ +291 0x1800 //_ +292 0x1000 //_ +293 0x04CD //_ +294 0x0F33 //_ +295 0x7333 //_ +296 0x199A //_ +297 0x7333 //_ +298 0x0004 //_ +299 0x6CCD //_ +300 0x799A //_ +301 0x001E //_ +302 0x3000 //_ +303 0x3200 //_ +304 0x2000 //_ +305 0x2000 //_ +306 0x2000 //_ +307 0x2000 //_ +308 0x2000 //_ +309 0x2000 //_ +310 0x2000 //_ +311 0x0000 //_ +312 0x0000 //_ +313 0x0000 //_ +#VOL 0 +163 0x4000 //RX_TDDRC_ALPHA_UP_1 +164 0x4000 //RX_TDDRC_ALPHA_UP_2 +165 0x4000 //RX_TDDRC_ALPHA_UP_3 +166 0x4000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0001 //RX_TDDRC_THRD_0 +270 0x0002 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x6000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x4000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x03C3 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4870 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4850 //RX_FDEQ_GAIN_6 +203 0x485C //RX_FDEQ_GAIN_7 +204 0x5C60 //RX_FDEQ_GAIN_8 +205 0x685C //RX_FDEQ_GAIN_9 +206 0x5640 //RX_FDEQ_GAIN_10 +207 0x4040 //RX_FDEQ_GAIN_11 +208 0x5C58 //RX_FDEQ_GAIN_12 +209 0x5C60 //RX_FDEQ_GAIN_13 +210 0x6060 //RX_FDEQ_GAIN_14 +211 0x6060 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0402 //RX_FDEQ_BIN_3 +224 0x0504 //RX_FDEQ_BIN_4 +225 0x0209 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0012 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x4000 //RX_TDDRC_ALPHA_UP_1 +164 0x4000 //RX_TDDRC_ALPHA_UP_2 +165 0x4000 //RX_TDDRC_ALPHA_UP_3 +166 0x4000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0001 //RX_TDDRC_THRD_0 +270 0x0002 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x6000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x4000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x03C3 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4870 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4850 //RX_FDEQ_GAIN_6 +203 0x485C //RX_FDEQ_GAIN_7 +204 0x5C60 //RX_FDEQ_GAIN_8 +205 0x685C //RX_FDEQ_GAIN_9 +206 0x5640 //RX_FDEQ_GAIN_10 +207 0x4040 //RX_FDEQ_GAIN_11 +208 0x5C58 //RX_FDEQ_GAIN_12 +209 0x5C60 //RX_FDEQ_GAIN_13 +210 0x6060 //RX_FDEQ_GAIN_14 +211 0x6060 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0402 //RX_FDEQ_BIN_3 +224 0x0504 //RX_FDEQ_BIN_4 +225 0x0209 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x001A //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x4000 //RX_TDDRC_ALPHA_UP_1 +164 0x4000 //RX_TDDRC_ALPHA_UP_2 +165 0x4000 //RX_TDDRC_ALPHA_UP_3 +166 0x4000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0001 //RX_TDDRC_THRD_0 +270 0x0002 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x6000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x4000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x03C3 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4870 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4850 //RX_FDEQ_GAIN_6 +203 0x485C //RX_FDEQ_GAIN_7 +204 0x5C60 //RX_FDEQ_GAIN_8 +205 0x685C //RX_FDEQ_GAIN_9 +206 0x5640 //RX_FDEQ_GAIN_10 +207 0x4040 //RX_FDEQ_GAIN_11 +208 0x5C58 //RX_FDEQ_GAIN_12 +209 0x5C60 //RX_FDEQ_GAIN_13 +210 0x6060 //RX_FDEQ_GAIN_14 +211 0x6060 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0402 //RX_FDEQ_BIN_3 +224 0x0504 //RX_FDEQ_BIN_4 +225 0x0209 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0025 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x4000 //RX_TDDRC_ALPHA_UP_1 +164 0x4000 //RX_TDDRC_ALPHA_UP_2 +165 0x4000 //RX_TDDRC_ALPHA_UP_3 +166 0x4000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0001 //RX_TDDRC_THRD_0 +270 0x0002 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x6000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x4000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x03C3 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4870 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4850 //RX_FDEQ_GAIN_6 +203 0x485C //RX_FDEQ_GAIN_7 +204 0x5C60 //RX_FDEQ_GAIN_8 +205 0x685C //RX_FDEQ_GAIN_9 +206 0x5640 //RX_FDEQ_GAIN_10 +207 0x4040 //RX_FDEQ_GAIN_11 +208 0x5C58 //RX_FDEQ_GAIN_12 +209 0x5C60 //RX_FDEQ_GAIN_13 +210 0x6060 //RX_FDEQ_GAIN_14 +211 0x6060 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0402 //RX_FDEQ_BIN_3 +224 0x0504 //RX_FDEQ_BIN_4 +225 0x0209 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0034 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x4000 //RX_TDDRC_ALPHA_UP_1 +164 0x4000 //RX_TDDRC_ALPHA_UP_2 +165 0x4000 //RX_TDDRC_ALPHA_UP_3 +166 0x4000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0001 //RX_TDDRC_THRD_0 +270 0x0002 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x6000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x4000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x03C3 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4870 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4850 //RX_FDEQ_GAIN_6 +203 0x485C //RX_FDEQ_GAIN_7 +204 0x5C60 //RX_FDEQ_GAIN_8 +205 0x685C //RX_FDEQ_GAIN_9 +206 0x5640 //RX_FDEQ_GAIN_10 +207 0x4040 //RX_FDEQ_GAIN_11 +208 0x5C58 //RX_FDEQ_GAIN_12 +209 0x5C60 //RX_FDEQ_GAIN_13 +210 0x6060 //RX_FDEQ_GAIN_14 +211 0x6060 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0402 //RX_FDEQ_BIN_3 +224 0x0504 //RX_FDEQ_BIN_4 +225 0x0209 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x004D //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x4000 //RX_TDDRC_ALPHA_UP_1 +164 0x4000 //RX_TDDRC_ALPHA_UP_2 +165 0x4000 //RX_TDDRC_ALPHA_UP_3 +166 0x4000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0001 //RX_TDDRC_THRD_0 +270 0x0002 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x6000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x4000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x03C3 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4870 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4850 //RX_FDEQ_GAIN_6 +203 0x485C //RX_FDEQ_GAIN_7 +204 0x5C60 //RX_FDEQ_GAIN_8 +205 0x685C //RX_FDEQ_GAIN_9 +206 0x5640 //RX_FDEQ_GAIN_10 +207 0x4040 //RX_FDEQ_GAIN_11 +208 0x5C58 //RX_FDEQ_GAIN_12 +209 0x5C60 //RX_FDEQ_GAIN_13 +210 0x6060 //RX_FDEQ_GAIN_14 +211 0x6060 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0402 //RX_FDEQ_BIN_3 +224 0x0504 //RX_FDEQ_BIN_4 +225 0x0209 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0074 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x4000 //RX_TDDRC_ALPHA_UP_1 +164 0x4000 //RX_TDDRC_ALPHA_UP_2 +165 0x4000 //RX_TDDRC_ALPHA_UP_3 +166 0x4000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0001 //RX_TDDRC_THRD_0 +270 0x0002 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x6000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x4000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x03C3 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4870 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4850 //RX_FDEQ_GAIN_6 +203 0x485C //RX_FDEQ_GAIN_7 +204 0x5C60 //RX_FDEQ_GAIN_8 +205 0x685C //RX_FDEQ_GAIN_9 +206 0x5640 //RX_FDEQ_GAIN_10 +207 0x4040 //RX_FDEQ_GAIN_11 +208 0x5C58 //RX_FDEQ_GAIN_12 +209 0x5C60 //RX_FDEQ_GAIN_13 +210 0x6060 //RX_FDEQ_GAIN_14 +211 0x6060 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0402 //RX_FDEQ_BIN_3 +224 0x0504 //RX_FDEQ_BIN_4 +225 0x0209 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME HANDSFREE-HANDFREE-VOICE_GENERIC-NB +#PARAM_MODE FULL +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0001 //TX_OPERATION_MODE_0 +1 0x0001 //TX_OPERATION_MODE_1 +2 0x0073 //TX_PATCH_REG +3 0x2F7C //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0003 //TX_NUM_MIC +6 0x0000 //TX_SAMPLINGFREQ_SIG +7 0x0000 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009C //TX_DIST2REF1 +22 0x0019 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x1000 //TX_PGA_0 +28 0x1000 //TX_PGA_1 +29 0x1000 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0001 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0002 //TX_MIC_DATA_SRC1 +43 0x0001 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3A66 //TX_DIST2REF_11 +73 0x053D //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0200 //TX_MIC_REFBLK_VOLUME +108 0x0CAE //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0000 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7652 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x5000 //TX_THR_PITCH_DET_0 +131 0x4800 //TX_THR_PITCH_DET_1 +132 0x4000 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x0028 //TX_TAIL_LENGTH +147 0x0100 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x7A00 //TX_EAD_THR +151 0x1000 //TX_THR_RE_EST +152 0x0200 //TX_MIN_EQ_RE_EST_0 +153 0x0200 //TX_MIN_EQ_RE_EST_1 +154 0x0200 //TX_MIN_EQ_RE_EST_2 +155 0x0200 //TX_MIN_EQ_RE_EST_3 +156 0x0200 //TX_MIN_EQ_RE_EST_4 +157 0x0200 //TX_MIN_EQ_RE_EST_5 +158 0x0200 //TX_MIN_EQ_RE_EST_6 +159 0x1800 //TX_MIN_EQ_RE_EST_7 +160 0x1800 //TX_MIN_EQ_RE_EST_8 +161 0x3000 //TX_MIN_EQ_RE_EST_9 +162 0x4000 //TX_MIN_EQ_RE_EST_10 +163 0x6000 //TX_MIN_EQ_RE_EST_11 +164 0x7FFF //TX_MIN_EQ_RE_EST_12 +165 0x2000 //TX_LAMBDA_RE_EST +166 0x0000 //TX_LAMBDA_CB_NLE +167 0x7FFF //TX_C_POST_FLT +168 0x2000 //TX_GAIN_NP +169 0x0180 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x0200 //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x7148 //TX_DTD_THR1_0 +198 0x7148 //TX_DTD_THR1_1 +199 0x7148 //TX_DTD_THR1_2 +200 0x5DC0 //TX_DTD_THR1_3 +201 0x7FF0 //TX_DTD_THR1_4 +202 0x7FF0 //TX_DTD_THR1_5 +203 0x7FF0 //TX_DTD_THR1_6 +204 0x0CCD //TX_DTD_THR2_0 +205 0x0CCD //TX_DTD_THR2_1 +206 0x0CCD //TX_DTD_THR2_2 +207 0x0CCD //TX_DTD_THR2_3 +208 0x0CCD //TX_DTD_THR2_4 +209 0x0CCD //TX_DTD_THR2_5 +210 0x0CCD //TX_DTD_THR2_6 +211 0x7FFF //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x157C //TX_DT_CUT_K +214 0x0100 //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x1000 //TX_ADPT_STRICT_L +222 0x1000 //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x2000 //TX_B_POST_FILT_ECHO_L +229 0x2000 //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x1000 //TX_B_LESSCUT_RTO_ECHO +232 0x0000 //TX_EPD_OFFSET_00 +233 0x0000 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x0000 //TX_DTD_THR1_7 +238 0x0000 //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xF800 //TX_THR_SN_EST_0 +243 0xFA00 //TX_THR_SN_EST_1 +244 0xFA00 //TX_THR_SN_EST_2 +245 0xF900 //TX_THR_SN_EST_3 +246 0xFA00 //TX_THR_SN_EST_4 +247 0xFA00 //TX_THR_SN_EST_5 +248 0xF800 //TX_THR_SN_EST_6 +249 0xF800 //TX_THR_SN_EST_7 +250 0x0050 //TX_DELTA_THR_SN_EST_0 +251 0x0200 //TX_DELTA_THR_SN_EST_1 +252 0x0200 //TX_DELTA_THR_SN_EST_2 +253 0x0100 //TX_DELTA_THR_SN_EST_3 +254 0x0200 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x01A0 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x4000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x4000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x7F00 //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0800 //TX_MAINREFRTO_TH_EQ +279 0x1000 //TX_B_POST_FLT_0 +280 0x1000 //TX_B_POST_FLT_1 +281 0x0010 //TX_NS_LVL_CTRL_0 +282 0x0017 //TX_NS_LVL_CTRL_1 +283 0x0015 //TX_NS_LVL_CTRL_2 +284 0x0012 //TX_NS_LVL_CTRL_3 +285 0x0012 //TX_NS_LVL_CTRL_4 +286 0x0011 //TX_NS_LVL_CTRL_5 +287 0x0012 //TX_NS_LVL_CTRL_6 +288 0x0011 //TX_NS_LVL_CTRL_7 +289 0x0018 //TX_MIN_GAIN_S_0 +290 0x0018 //TX_MIN_GAIN_S_1 +291 0x0018 //TX_MIN_GAIN_S_2 +292 0x0018 //TX_MIN_GAIN_S_3 +293 0x0018 //TX_MIN_GAIN_S_4 +294 0x0018 //TX_MIN_GAIN_S_5 +295 0x0018 //TX_MIN_GAIN_S_6 +296 0x0018 //TX_MIN_GAIN_S_7 +297 0x4000 //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x1000 //TX_SNRI_SUP_1 +302 0x4000 //TX_SNRI_SUP_2 +303 0x2400 //TX_SNRI_SUP_3 +304 0x4000 //TX_SNRI_SUP_4 +305 0x4000 //TX_SNRI_SUP_5 +306 0x4000 //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x0018 //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x7FFF //TX_A_POST_FILT_S_0 +315 0x7FFF //TX_A_POST_FILT_S_1 +316 0x7FFF //TX_A_POST_FILT_S_2 +317 0x7FFF //TX_A_POST_FILT_S_3 +318 0x7FFF //TX_A_POST_FILT_S_4 +319 0x7FFF //TX_A_POST_FILT_S_5 +320 0x7FFF //TX_A_POST_FILT_S_6 +321 0x7FFF //TX_A_POST_FILT_S_7 +322 0x1000 //TX_B_POST_FILT_0 +323 0x1000 //TX_B_POST_FILT_1 +324 0x1000 //TX_B_POST_FILT_2 +325 0x5000 //TX_B_POST_FILT_3 +326 0x3000 //TX_B_POST_FILT_4 +327 0x1000 //TX_B_POST_FILT_5 +328 0x1000 //TX_B_POST_FILT_6 +329 0x2000 //TX_B_POST_FILT_7 +330 0x4000 //TX_B_LESSCUT_RTO_S_0 +331 0x6000 //TX_B_LESSCUT_RTO_S_1 +332 0x6000 //TX_B_LESSCUT_RTO_S_2 +333 0x6000 //TX_B_LESSCUT_RTO_S_3 +334 0x6000 //TX_B_LESSCUT_RTO_S_4 +335 0x6000 //TX_B_LESSCUT_RTO_S_5 +336 0x6000 //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7E00 //TX_LAMBDA_PFILT +339 0x7E00 //TX_LAMBDA_PFILT_S_0 +340 0x7E00 //TX_LAMBDA_PFILT_S_1 +341 0x7E00 //TX_LAMBDA_PFILT_S_2 +342 0x7E00 //TX_LAMBDA_PFILT_S_3 +343 0x7E00 //TX_LAMBDA_PFILT_S_4 +344 0x7E00 //TX_LAMBDA_PFILT_S_5 +345 0x7E00 //TX_LAMBDA_PFILT_S_6 +346 0x7E00 //TX_LAMBDA_PFILT_S_7 +347 0x0200 //TX_K_PEPPER +348 0x0800 //TX_A_PEPPER +349 0x1EAA //TX_K_PEPPER_HF +350 0x0600 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0800 //TX_DT_BINVAD_TH_0 +354 0x0800 //TX_DT_BINVAD_TH_1 +355 0x0800 //TX_DT_BINVAD_TH_2 +356 0x0800 //TX_DT_BINVAD_TH_3 +357 0x0FA0 //TX_DT_BINVAD_ENDF +358 0x0400 //TX_C_POST_FLT_DT +359 0x4000 //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0064 //TX_NDETCT +367 0x0050 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x07D0 //TX_NOISE_TH_1 +371 0x03ED //TX_NOISE_TH_2 +372 0x2EE0 //TX_NOISE_TH_3 +373 0x5528 //TX_NOISE_TH_4 +374 0x7FFF //TX_NOISE_TH_5 +375 0x7FFF //TX_NOISE_TH_5_2 +376 0x0000 //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x0FA0 //TX_NOISE_TH_6 +379 0x000A //TX_MINENOISE_TH +380 0xD508 //TX_MORENS_TFMASK_TH +381 0x0001 //TX_DRC_QUIET_FLOOR +382 0x3A98 //TX_RATIODTL_CUT_TH +383 0x0DAC //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x1000 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x7FFF //TX_POST_MASK_SUP_HSNE +392 0x7000 //TX_TAIL_DET_TH +393 0x4000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0080 //TX_SUPHIGH_TH +396 0x0000 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x1800 //TX_C_POST_FLT_MASK +399 0x7FFF //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0001 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x000A //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x7FFF //TX_MIN_G_CTRL_SSNS +409 0x0000 //TX_METAL_RTO_THR +410 0x4848 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x007A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x5000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x01E0 //TX_NOR_OFF_THR +498 0x7C00 //TX_MORE_ON_700HZ_THR +499 0x0000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0xD333 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x7FFF //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x000A //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0x3000 //TX_DEREVERB_LF_MU +515 0x34CD //TX_DEREVERB_HF_MU +516 0x0007 //TX_DEREVERB_DELAY +517 0x0004 //TX_DEREVERB_COEF_LEN +518 0x0003 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x3A98 //TX_GSC_RTOL_TH +522 0x3A98 //TX_GSC_RTOH_TH +523 0x7E2C //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0014 //TX_FDEQ_SUBNUM +567 0x5250 //TX_FDEQ_GAIN_0 +568 0x4C48 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4A43 //TX_FDEQ_GAIN_3 +571 0x374B //TX_FDEQ_GAIN_4 +572 0x3444 //TX_FDEQ_GAIN_5 +573 0x433C //TX_FDEQ_GAIN_6 +574 0x403C //TX_FDEQ_GAIN_7 +575 0x2627 //TX_FDEQ_GAIN_8 +576 0x2929 //TX_FDEQ_GAIN_9 +577 0x4848 //TX_FDEQ_GAIN_10 +578 0x4848 //TX_FDEQ_GAIN_11 +579 0x4848 //TX_FDEQ_GAIN_12 +580 0x4848 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0303 //TX_FDEQ_BIN_2 +594 0x0304 //TX_FDEQ_BIN_3 +595 0x0405 //TX_FDEQ_BIN_4 +596 0x0506 //TX_FDEQ_BIN_5 +597 0x0708 //TX_FDEQ_BIN_6 +598 0x090A //TX_FDEQ_BIN_7 +599 0x0B0C //TX_FDEQ_BIN_8 +600 0x0D0E //TX_FDEQ_BIN_9 +601 0x0000 //TX_FDEQ_BIN_10 +602 0x0000 //TX_FDEQ_BIN_11 +603 0x0000 //TX_FDEQ_BIN_12 +604 0x0000 //TX_FDEQ_BIN_13 +605 0x0000 //TX_FDEQ_BIN_14 +606 0x0000 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0014 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4848 //TX_PREEQ_GAIN_MIC0_8 +626 0x4848 //TX_PREEQ_GAIN_MIC0_9 +627 0x4848 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0202 //TX_PREEQ_BIN_MIC0_0 +642 0x0203 //TX_PREEQ_BIN_MIC0_1 +643 0x0303 //TX_PREEQ_BIN_MIC0_2 +644 0x0304 //TX_PREEQ_BIN_MIC0_3 +645 0x0405 //TX_PREEQ_BIN_MIC0_4 +646 0x0506 //TX_PREEQ_BIN_MIC0_5 +647 0x0708 //TX_PREEQ_BIN_MIC0_6 +648 0x090A //TX_PREEQ_BIN_MIC0_7 +649 0x0B0C //TX_PREEQ_BIN_MIC0_8 +650 0x0D0E //TX_PREEQ_BIN_MIC0_9 +651 0x0000 //TX_PREEQ_BIN_MIC0_10 +652 0x0000 //TX_PREEQ_BIN_MIC0_11 +653 0x0000 //TX_PREEQ_BIN_MIC0_12 +654 0x0000 //TX_PREEQ_BIN_MIC0_13 +655 0x0000 //TX_PREEQ_BIN_MIC0_14 +656 0x0000 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4849 //TX_PREEQ_GAIN_MIC1_8 +675 0x4A4B //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0202 //TX_PREEQ_BIN_MIC1_0 +691 0x0203 //TX_PREEQ_BIN_MIC1_1 +692 0x0303 //TX_PREEQ_BIN_MIC1_2 +693 0x0304 //TX_PREEQ_BIN_MIC1_3 +694 0x0405 //TX_PREEQ_BIN_MIC1_4 +695 0x0506 //TX_PREEQ_BIN_MIC1_5 +696 0x0708 //TX_PREEQ_BIN_MIC1_6 +697 0x090A //TX_PREEQ_BIN_MIC1_7 +698 0x0B0C //TX_PREEQ_BIN_MIC1_8 +699 0x0D0E //TX_PREEQ_BIN_MIC1_9 +700 0x0000 //TX_PREEQ_BIN_MIC1_10 +701 0x0000 //TX_PREEQ_BIN_MIC1_11 +702 0x0000 //TX_PREEQ_BIN_MIC1_12 +703 0x0000 //TX_PREEQ_BIN_MIC1_13 +704 0x0000 //TX_PREEQ_BIN_MIC1_14 +705 0x0000 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4849 //TX_PREEQ_GAIN_MIC2_7 +723 0x4B4C //TX_PREEQ_GAIN_MIC2_8 +724 0x4D50 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0202 //TX_PREEQ_BIN_MIC2_0 +740 0x0203 //TX_PREEQ_BIN_MIC2_1 +741 0x0303 //TX_PREEQ_BIN_MIC2_2 +742 0x0304 //TX_PREEQ_BIN_MIC2_3 +743 0x0405 //TX_PREEQ_BIN_MIC2_4 +744 0x0506 //TX_PREEQ_BIN_MIC2_5 +745 0x0708 //TX_PREEQ_BIN_MIC2_6 +746 0x090A //TX_PREEQ_BIN_MIC2_7 +747 0x0B0C //TX_PREEQ_BIN_MIC2_8 +748 0x0D0E //TX_PREEQ_BIN_MIC2_9 +749 0x0000 //TX_PREEQ_BIN_MIC2_10 +750 0x0000 //TX_PREEQ_BIN_MIC2_11 +751 0x0000 //TX_PREEQ_BIN_MIC2_12 +752 0x0000 //TX_PREEQ_BIN_MIC2_13 +753 0x0000 //TX_PREEQ_BIN_MIC2_14 +754 0x0000 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x0800 //TX_NND_WEIGHT +765 0x0065 //TX_MIC_CALIBRATION_0 +766 0x0065 //TX_MIC_CALIBRATION_1 +767 0x0065 //TX_MIC_CALIBRATION_2 +768 0x0065 //TX_MIC_CALIBRATION_3 +769 0x0044 //TX_MIC_PWR_BIAS_0 +770 0x0044 //TX_MIC_PWR_BIAS_1 +771 0x0044 //TX_MIC_PWR_BIAS_2 +772 0x0044 //TX_MIC_PWR_BIAS_3 +773 0x0009 //TX_GAIN_LIMIT_0 +774 0x000F //TX_GAIN_LIMIT_1 +775 0x000F //TX_GAIN_LIMIT_2 +776 0x000F //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x4000 //TX_TDDRC_ALPHA_UP_01 +784 0x4000 //TX_TDDRC_ALPHA_UP_02 +785 0x4000 //TX_TDDRC_ALPHA_UP_03 +786 0x4000 //TX_TDDRC_ALPHA_UP_04 +787 0x6000 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x7FFF //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0010 //TX_DEADMIC_SILENCE_TH +817 0x0600 //TX_MIC_DEGRADE_TH +818 0x0078 //TX_DEADMIC_CNT +819 0x0078 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x4848 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0096 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0002 //TX_FILTINDX +854 0x0004 //TX_TDDRC_THRD_0 +855 0x0010 //TX_TDDRC_THRD_1 +856 0x1800 //TX_TDDRC_THRD_2 +857 0x1800 //TX_TDDRC_THRD_3 +858 0x6000 //TX_TDDRC_SLANT_0 +859 0x6000 //TX_TDDRC_SLANT_1 +860 0x4000 //TX_TDDRC_ALPHA_UP_00 +861 0x6000 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x0A00 //TX_TDDRC_DRC_GAIN +867 0x7FFF //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x0028 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x1000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x2339 //TX_SENDFUNC_REG_MICMUTE +898 0x0021 //TX_SENDFUNC_REG_MICMUTE1 +899 0x02BC //TX_MICMUTE_RATIO_THR +900 0x0140 //TX_MICMUTE_AMP_THR +901 0x0004 //TX_MICMUTE_HPF_IND +902 0x00C0 //TX_MICMUTE_LOG_EYR_TH +903 0x0008 //TX_MICMUTE_CVG_TIME +904 0x0008 //TX_MICMUTE_RELEASE_TIME +905 0x01FE //TX_MIC_VOLUME_MIC0MUTE +906 0x0020 //TX_MICMUTE_EPD_OFFSET_0 +907 0x001E //TX_MICMUTE_FRQ_AEC_L +908 0x7999 //TX_MICMUTE_EAD_THR +909 0x7FFF //TX_MICMUTE_LAMBDA_CB_NLE +910 0x7FFF //TX_MICMUTE_LAMBDA_RE_EST +911 0x4000 //TX_DTD_THR1_MICMUTE_0 +912 0x7000 //TX_DTD_THR1_MICMUTE_1 +913 0x7FFF //TX_DTD_THR1_MICMUTE_2 +914 0x7FFF //TX_DTD_THR1_MICMUTE_3 +915 0x6CCC //TX_DTD_THR2_MICMUTE_0 +916 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x1000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x4000 //TX_MICMUTE_C_POST_FLT +922 0x03E8 //TX_MICMUTE_DT_CUT_K +923 0x0001 //TX_MICMUTE_DT_CUT_THR +924 0x03E8 //TX_MICMUTE_DT_CUT_K2 +925 0x0001 //TX_MICMUTE_DT_CUT_THR2 +926 0x0064 //TX_MICMUTE_DT2_HOLD_N +927 0x1000 //TX_MICMUTE_RATIODTH_THCUT +928 0x1000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x7FFF //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0400 //TX_MICMUTE_C_POST_FLT_MASK +931 0x7999 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0258 //TX_MICMUTE_DT_CUT_K1 +933 0x0800 //TX_MICMUTE_N2_SN_EST +934 0xFC00 //TX_MICMUTE_THR_SN_EST_0 +935 0x001C //TX_MICMUTE_MIN_G_CTRL_0 +936 0x6000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x7000 //TX_MICMUTE_B_POST_FILT_0 +938 0x2710 //TX_MIC1RUB_AMP_THR +939 0x0010 //TX_MIC1MUTE_RATIO_THR +940 0x0450 //TX_MIC1MUTE_AMP_THR +941 0x0008 //TX_MIC1MUTE_CVG_TIME +942 0x0008 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x206C //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0000 //RX_SAMPLINGFREQ_SIG +3 0x0000 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7652 //RX_A_HP +12 0x4000 //RX_B_PE +13 0x7800 //RX_THR_PITCH_DET_0 +14 0x7000 //RX_THR_PITCH_DET_1 +15 0x6000 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0400 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x0010 //RX_NS_LVL_CTRL +23 0xF800 //RX_THR_SN_EST +24 0x7E00 //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x4000 //RX_TDDRC_ALPHA_DWN_2 +29 0x4000 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x4000 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0014 //RX_FDEQ_SUBNUM +39 0x5252 //RX_FDEQ_GAIN_0 +40 0x4E4F //RX_FDEQ_GAIN_1 +41 0x4743 //RX_FDEQ_GAIN_2 +42 0x454C //RX_FDEQ_GAIN_3 +43 0x4C49 //RX_FDEQ_GAIN_4 +44 0x584A //RX_FDEQ_GAIN_5 +45 0x4642 //RX_FDEQ_GAIN_6 +46 0x4043 //RX_FDEQ_GAIN_7 +47 0x454A //RX_FDEQ_GAIN_8 +48 0x4C53 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0503 //RX_FDEQ_BIN_4 +68 0x0107 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x0060 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x0600 //RX_FDDRC_THRD_2_0 +95 0x0600 //RX_FDDRC_THRD_2_1 +96 0x0600 //RX_FDDRC_THRD_2_2 +97 0x0600 //RX_FDDRC_THRD_2_3 +98 0x0800 //RX_FDDRC_THRD_3_0 +99 0x0800 //RX_FDDRC_THRD_3_1 +100 0x0800 //RX_FDDRC_THRD_3_2 +101 0x0800 //RX_FDDRC_THRD_3_3 +102 0x0000 //RX_FDDRC_SLANT_0_0 +103 0x0000 //RX_FDDRC_SLANT_0_1 +104 0x0000 //RX_FDDRC_SLANT_0_2 +105 0x0000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0005 //RX_FILTINDX +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x02D2 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x2000 //RX_MIN_G_FP +128 0x0080 //RX_MAX_G_FP +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x4000 //RX_TDDRC_ALPHA_DWN_2 +29 0x4000 //RX_TDDRC_ALPHA_DWN_3 +32 0x4000 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x02D2 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x5252 //RX_FDEQ_GAIN_0 +40 0x4E4F //RX_FDEQ_GAIN_1 +41 0x4743 //RX_FDEQ_GAIN_2 +42 0x454C //RX_FDEQ_GAIN_3 +43 0x4C49 //RX_FDEQ_GAIN_4 +44 0x584A //RX_FDEQ_GAIN_5 +45 0x4642 //RX_FDEQ_GAIN_6 +46 0x4043 //RX_FDEQ_GAIN_7 +47 0x454A //RX_FDEQ_GAIN_8 +48 0x4C53 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0503 //RX_FDEQ_BIN_4 +68 0x0107 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x0060 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x0600 //RX_FDDRC_THRD_2_0 +95 0x0600 //RX_FDDRC_THRD_2_1 +96 0x0600 //RX_FDDRC_THRD_2_2 +97 0x0600 //RX_FDDRC_THRD_2_3 +98 0x0800 //RX_FDDRC_THRD_3_0 +99 0x0800 //RX_FDDRC_THRD_3_1 +100 0x0800 //RX_FDDRC_THRD_3_2 +101 0x0800 //RX_FDDRC_THRD_3_3 +102 0x0000 //RX_FDDRC_SLANT_0_0 +103 0x0000 //RX_FDDRC_SLANT_0_1 +104 0x0000 //RX_FDDRC_SLANT_0_2 +105 0x0000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0015 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x4000 //RX_TDDRC_ALPHA_DWN_2 +29 0x4000 //RX_TDDRC_ALPHA_DWN_3 +32 0x4000 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x02D2 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x5252 //RX_FDEQ_GAIN_0 +40 0x4E4F //RX_FDEQ_GAIN_1 +41 0x4743 //RX_FDEQ_GAIN_2 +42 0x454C //RX_FDEQ_GAIN_3 +43 0x4C49 //RX_FDEQ_GAIN_4 +44 0x584A //RX_FDEQ_GAIN_5 +45 0x4642 //RX_FDEQ_GAIN_6 +46 0x4043 //RX_FDEQ_GAIN_7 +47 0x454A //RX_FDEQ_GAIN_8 +48 0x4C53 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0503 //RX_FDEQ_BIN_4 +68 0x0107 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x0060 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x0600 //RX_FDDRC_THRD_2_0 +95 0x0600 //RX_FDDRC_THRD_2_1 +96 0x0600 //RX_FDDRC_THRD_2_2 +97 0x0600 //RX_FDDRC_THRD_2_3 +98 0x0800 //RX_FDDRC_THRD_3_0 +99 0x0800 //RX_FDDRC_THRD_3_1 +100 0x0800 //RX_FDDRC_THRD_3_2 +101 0x0800 //RX_FDDRC_THRD_3_3 +102 0x0000 //RX_FDDRC_SLANT_0_0 +103 0x0000 //RX_FDDRC_SLANT_0_1 +104 0x0000 //RX_FDDRC_SLANT_0_2 +105 0x0000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x001E //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x4000 //RX_TDDRC_ALPHA_DWN_2 +29 0x4000 //RX_TDDRC_ALPHA_DWN_3 +32 0x4000 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x02D2 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x5252 //RX_FDEQ_GAIN_0 +40 0x4E4F //RX_FDEQ_GAIN_1 +41 0x4743 //RX_FDEQ_GAIN_2 +42 0x454C //RX_FDEQ_GAIN_3 +43 0x4C49 //RX_FDEQ_GAIN_4 +44 0x584A //RX_FDEQ_GAIN_5 +45 0x4642 //RX_FDEQ_GAIN_6 +46 0x4043 //RX_FDEQ_GAIN_7 +47 0x454A //RX_FDEQ_GAIN_8 +48 0x4C53 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0503 //RX_FDEQ_BIN_4 +68 0x0107 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x0060 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x0600 //RX_FDDRC_THRD_2_0 +95 0x0600 //RX_FDDRC_THRD_2_1 +96 0x0600 //RX_FDDRC_THRD_2_2 +97 0x0600 //RX_FDDRC_THRD_2_3 +98 0x0800 //RX_FDDRC_THRD_3_0 +99 0x0800 //RX_FDDRC_THRD_3_1 +100 0x0800 //RX_FDDRC_THRD_3_2 +101 0x0800 //RX_FDDRC_THRD_3_3 +102 0x0000 //RX_FDDRC_SLANT_0_0 +103 0x0000 //RX_FDDRC_SLANT_0_1 +104 0x0000 //RX_FDDRC_SLANT_0_2 +105 0x0000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x002A //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x4000 //RX_TDDRC_ALPHA_DWN_2 +29 0x4000 //RX_TDDRC_ALPHA_DWN_3 +32 0x4000 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x02D2 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x5252 //RX_FDEQ_GAIN_0 +40 0x4E4F //RX_FDEQ_GAIN_1 +41 0x4743 //RX_FDEQ_GAIN_2 +42 0x454C //RX_FDEQ_GAIN_3 +43 0x4C49 //RX_FDEQ_GAIN_4 +44 0x584A //RX_FDEQ_GAIN_5 +45 0x4642 //RX_FDEQ_GAIN_6 +46 0x4043 //RX_FDEQ_GAIN_7 +47 0x454A //RX_FDEQ_GAIN_8 +48 0x4C53 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0503 //RX_FDEQ_BIN_4 +68 0x0107 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x0060 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x0600 //RX_FDDRC_THRD_2_0 +95 0x0600 //RX_FDDRC_THRD_2_1 +96 0x0600 //RX_FDDRC_THRD_2_2 +97 0x0600 //RX_FDDRC_THRD_2_3 +98 0x0800 //RX_FDDRC_THRD_3_0 +99 0x0800 //RX_FDDRC_THRD_3_1 +100 0x0800 //RX_FDDRC_THRD_3_2 +101 0x0800 //RX_FDDRC_THRD_3_3 +102 0x0000 //RX_FDDRC_SLANT_0_0 +103 0x0000 //RX_FDDRC_SLANT_0_1 +104 0x0000 //RX_FDDRC_SLANT_0_2 +105 0x0000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x003C //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x4000 //RX_TDDRC_ALPHA_DWN_2 +29 0x4000 //RX_TDDRC_ALPHA_DWN_3 +32 0x4000 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x02D2 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x5252 //RX_FDEQ_GAIN_0 +40 0x4E4F //RX_FDEQ_GAIN_1 +41 0x4743 //RX_FDEQ_GAIN_2 +42 0x454C //RX_FDEQ_GAIN_3 +43 0x4C49 //RX_FDEQ_GAIN_4 +44 0x584A //RX_FDEQ_GAIN_5 +45 0x4642 //RX_FDEQ_GAIN_6 +46 0x4043 //RX_FDEQ_GAIN_7 +47 0x454A //RX_FDEQ_GAIN_8 +48 0x4C53 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0503 //RX_FDEQ_BIN_4 +68 0x0107 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x0060 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x0600 //RX_FDDRC_THRD_2_0 +95 0x0600 //RX_FDDRC_THRD_2_1 +96 0x0600 //RX_FDDRC_THRD_2_2 +97 0x0600 //RX_FDDRC_THRD_2_3 +98 0x0800 //RX_FDDRC_THRD_3_0 +99 0x0800 //RX_FDDRC_THRD_3_1 +100 0x0800 //RX_FDDRC_THRD_3_2 +101 0x0800 //RX_FDDRC_THRD_3_3 +102 0x0000 //RX_FDDRC_SLANT_0_0 +103 0x0000 //RX_FDDRC_SLANT_0_1 +104 0x0000 //RX_FDDRC_SLANT_0_2 +105 0x0000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0058 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x4000 //RX_TDDRC_ALPHA_DWN_2 +29 0x4000 //RX_TDDRC_ALPHA_DWN_3 +32 0x4000 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x02D2 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x5252 //RX_FDEQ_GAIN_0 +40 0x4E4F //RX_FDEQ_GAIN_1 +41 0x4743 //RX_FDEQ_GAIN_2 +42 0x454C //RX_FDEQ_GAIN_3 +43 0x4C49 //RX_FDEQ_GAIN_4 +44 0x584A //RX_FDEQ_GAIN_5 +45 0x4642 //RX_FDEQ_GAIN_6 +46 0x4043 //RX_FDEQ_GAIN_7 +47 0x454A //RX_FDEQ_GAIN_8 +48 0x4C53 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0503 //RX_FDEQ_BIN_4 +68 0x0107 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x0060 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x0600 //RX_FDDRC_THRD_2_0 +95 0x0600 //RX_FDDRC_THRD_2_1 +96 0x0600 //RX_FDDRC_THRD_2_2 +97 0x0600 //RX_FDDRC_THRD_2_3 +98 0x0800 //RX_FDDRC_THRD_3_0 +99 0x0800 //RX_FDDRC_THRD_3_1 +100 0x0800 //RX_FDDRC_THRD_3_2 +101 0x0800 //RX_FDDRC_THRD_3_3 +102 0x0000 //RX_FDDRC_SLANT_0_0 +103 0x0000 //RX_FDDRC_SLANT_0_1 +104 0x0000 //RX_FDDRC_SLANT_0_2 +105 0x0000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0082 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x4000 //RX_TDDRC_ALPHA_DWN_2 +29 0x4000 //RX_TDDRC_ALPHA_DWN_3 +32 0x4000 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x02D2 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x5252 //RX_FDEQ_GAIN_0 +40 0x4E4F //RX_FDEQ_GAIN_1 +41 0x4743 //RX_FDEQ_GAIN_2 +42 0x454C //RX_FDEQ_GAIN_3 +43 0x4C49 //RX_FDEQ_GAIN_4 +44 0x584A //RX_FDEQ_GAIN_5 +45 0x4642 //RX_FDEQ_GAIN_6 +46 0x4043 //RX_FDEQ_GAIN_7 +47 0x454A //RX_FDEQ_GAIN_8 +48 0x4C53 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0503 //RX_FDEQ_BIN_4 +68 0x0107 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x0060 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x0600 //RX_FDDRC_THRD_2_0 +95 0x0600 //RX_FDDRC_THRD_2_1 +96 0x0600 //RX_FDDRC_THRD_2_2 +97 0x0600 //RX_FDDRC_THRD_2_3 +98 0x0800 //RX_FDDRC_THRD_3_0 +99 0x0800 //RX_FDDRC_THRD_3_1 +100 0x0800 //RX_FDDRC_THRD_3_2 +101 0x0800 //RX_FDDRC_THRD_3_3 +102 0x0000 //RX_FDDRC_SLANT_0_0 +103 0x0000 //RX_FDDRC_SLANT_0_1 +104 0x0000 //RX_FDDRC_SLANT_0_2 +105 0x0000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x027C //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0000 //RX_SAMPLINGFREQ_SIG +160 0x0000 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7652 //RX_A_HP +169 0x4000 //RX_B_PE +170 0x7800 //RX_THR_PITCH_DET_0 +171 0x7000 //RX_THR_PITCH_DET_1 +172 0x6000 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0400 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x0010 //RX_NS_LVL_CTRL +180 0xF800 //RX_THR_SN_EST +181 0x7E00 //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x4000 //RX_TDDRC_ALPHA_DWN_2 +186 0x4000 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x4000 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0014 //RX_FDEQ_SUBNUM +196 0x8080 //RX_FDEQ_GAIN_0 +197 0x8054 //RX_FDEQ_GAIN_1 +198 0x5050 //RX_FDEQ_GAIN_2 +199 0x5058 //RX_FDEQ_GAIN_3 +200 0x5C70 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x484C //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x485A //RX_FDEQ_GAIN_8 +205 0x5A58 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0604 //RX_FDEQ_BIN_4 +225 0x0406 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x0060 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x0600 //RX_FDDRC_THRD_2_0 +252 0x0600 //RX_FDDRC_THRD_2_1 +253 0x0600 //RX_FDDRC_THRD_2_2 +254 0x0600 //RX_FDDRC_THRD_2_3 +255 0x0800 //RX_FDDRC_THRD_3_0 +256 0x0800 //RX_FDDRC_THRD_3_1 +257 0x0800 //RX_FDDRC_THRD_3_2 +258 0x0800 //RX_FDDRC_THRD_3_3 +259 0x0000 //RX_FDDRC_SLANT_0_0 +260 0x0000 //RX_FDDRC_SLANT_0_1 +261 0x0000 //RX_FDDRC_SLANT_0_2 +262 0x0000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0005 //RX_FILTINDX +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0780 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x2000 //RX_MIN_G_FP +285 0x0080 //RX_MAX_G_FP +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x4000 //RX_TDDRC_ALPHA_DWN_2 +186 0x4000 //RX_TDDRC_ALPHA_DWN_3 +189 0x4000 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0780 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x8080 //RX_FDEQ_GAIN_0 +197 0x8054 //RX_FDEQ_GAIN_1 +198 0x5050 //RX_FDEQ_GAIN_2 +199 0x5058 //RX_FDEQ_GAIN_3 +200 0x5C70 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x484C //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x485A //RX_FDEQ_GAIN_8 +205 0x5A58 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0604 //RX_FDEQ_BIN_4 +225 0x0406 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x0060 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x0600 //RX_FDDRC_THRD_2_0 +252 0x0600 //RX_FDDRC_THRD_2_1 +253 0x0600 //RX_FDDRC_THRD_2_2 +254 0x0600 //RX_FDDRC_THRD_2_3 +255 0x0800 //RX_FDDRC_THRD_3_0 +256 0x0800 //RX_FDDRC_THRD_3_1 +257 0x0800 //RX_FDDRC_THRD_3_2 +258 0x0800 //RX_FDDRC_THRD_3_3 +259 0x0000 //RX_FDDRC_SLANT_0_0 +260 0x0000 //RX_FDDRC_SLANT_0_1 +261 0x0000 //RX_FDDRC_SLANT_0_2 +262 0x0000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0015 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x4000 //RX_TDDRC_ALPHA_DWN_2 +186 0x4000 //RX_TDDRC_ALPHA_DWN_3 +189 0x4000 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0780 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x8080 //RX_FDEQ_GAIN_0 +197 0x8054 //RX_FDEQ_GAIN_1 +198 0x5050 //RX_FDEQ_GAIN_2 +199 0x5058 //RX_FDEQ_GAIN_3 +200 0x5C70 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x484C //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x485A //RX_FDEQ_GAIN_8 +205 0x5A58 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0604 //RX_FDEQ_BIN_4 +225 0x0406 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x0060 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x0600 //RX_FDDRC_THRD_2_0 +252 0x0600 //RX_FDDRC_THRD_2_1 +253 0x0600 //RX_FDDRC_THRD_2_2 +254 0x0600 //RX_FDDRC_THRD_2_3 +255 0x0800 //RX_FDDRC_THRD_3_0 +256 0x0800 //RX_FDDRC_THRD_3_1 +257 0x0800 //RX_FDDRC_THRD_3_2 +258 0x0800 //RX_FDDRC_THRD_3_3 +259 0x0000 //RX_FDDRC_SLANT_0_0 +260 0x0000 //RX_FDDRC_SLANT_0_1 +261 0x0000 //RX_FDDRC_SLANT_0_2 +262 0x0000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x001E //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x4000 //RX_TDDRC_ALPHA_DWN_2 +186 0x4000 //RX_TDDRC_ALPHA_DWN_3 +189 0x4000 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0780 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x8080 //RX_FDEQ_GAIN_0 +197 0x8054 //RX_FDEQ_GAIN_1 +198 0x5050 //RX_FDEQ_GAIN_2 +199 0x5058 //RX_FDEQ_GAIN_3 +200 0x5C70 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x484C //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x485A //RX_FDEQ_GAIN_8 +205 0x5A58 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0604 //RX_FDEQ_BIN_4 +225 0x0406 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x0060 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x0600 //RX_FDDRC_THRD_2_0 +252 0x0600 //RX_FDDRC_THRD_2_1 +253 0x0600 //RX_FDDRC_THRD_2_2 +254 0x0600 //RX_FDDRC_THRD_2_3 +255 0x0800 //RX_FDDRC_THRD_3_0 +256 0x0800 //RX_FDDRC_THRD_3_1 +257 0x0800 //RX_FDDRC_THRD_3_2 +258 0x0800 //RX_FDDRC_THRD_3_3 +259 0x0000 //RX_FDDRC_SLANT_0_0 +260 0x0000 //RX_FDDRC_SLANT_0_1 +261 0x0000 //RX_FDDRC_SLANT_0_2 +262 0x0000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x002A //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x4000 //RX_TDDRC_ALPHA_DWN_2 +186 0x4000 //RX_TDDRC_ALPHA_DWN_3 +189 0x4000 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0780 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x8080 //RX_FDEQ_GAIN_0 +197 0x8054 //RX_FDEQ_GAIN_1 +198 0x5050 //RX_FDEQ_GAIN_2 +199 0x5058 //RX_FDEQ_GAIN_3 +200 0x5C70 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x484C //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x485A //RX_FDEQ_GAIN_8 +205 0x5A58 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0604 //RX_FDEQ_BIN_4 +225 0x0406 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x0060 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x0600 //RX_FDDRC_THRD_2_0 +252 0x0600 //RX_FDDRC_THRD_2_1 +253 0x0600 //RX_FDDRC_THRD_2_2 +254 0x0600 //RX_FDDRC_THRD_2_3 +255 0x0800 //RX_FDDRC_THRD_3_0 +256 0x0800 //RX_FDDRC_THRD_3_1 +257 0x0800 //RX_FDDRC_THRD_3_2 +258 0x0800 //RX_FDDRC_THRD_3_3 +259 0x0000 //RX_FDDRC_SLANT_0_0 +260 0x0000 //RX_FDDRC_SLANT_0_1 +261 0x0000 //RX_FDDRC_SLANT_0_2 +262 0x0000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x003C //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x4000 //RX_TDDRC_ALPHA_DWN_2 +186 0x4000 //RX_TDDRC_ALPHA_DWN_3 +189 0x4000 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0780 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x8080 //RX_FDEQ_GAIN_0 +197 0x8054 //RX_FDEQ_GAIN_1 +198 0x5050 //RX_FDEQ_GAIN_2 +199 0x5058 //RX_FDEQ_GAIN_3 +200 0x5C70 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x484C //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x485A //RX_FDEQ_GAIN_8 +205 0x5A58 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0604 //RX_FDEQ_BIN_4 +225 0x0406 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x0060 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x0600 //RX_FDDRC_THRD_2_0 +252 0x0600 //RX_FDDRC_THRD_2_1 +253 0x0600 //RX_FDDRC_THRD_2_2 +254 0x0600 //RX_FDDRC_THRD_2_3 +255 0x0800 //RX_FDDRC_THRD_3_0 +256 0x0800 //RX_FDDRC_THRD_3_1 +257 0x0800 //RX_FDDRC_THRD_3_2 +258 0x0800 //RX_FDDRC_THRD_3_3 +259 0x0000 //RX_FDDRC_SLANT_0_0 +260 0x0000 //RX_FDDRC_SLANT_0_1 +261 0x0000 //RX_FDDRC_SLANT_0_2 +262 0x0000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0058 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x4000 //RX_TDDRC_ALPHA_DWN_2 +186 0x4000 //RX_TDDRC_ALPHA_DWN_3 +189 0x4000 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0780 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x8080 //RX_FDEQ_GAIN_0 +197 0x8054 //RX_FDEQ_GAIN_1 +198 0x5050 //RX_FDEQ_GAIN_2 +199 0x5058 //RX_FDEQ_GAIN_3 +200 0x5C70 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x484C //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x485A //RX_FDEQ_GAIN_8 +205 0x5A58 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0604 //RX_FDEQ_BIN_4 +225 0x0406 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x0060 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x0600 //RX_FDDRC_THRD_2_0 +252 0x0600 //RX_FDDRC_THRD_2_1 +253 0x0600 //RX_FDDRC_THRD_2_2 +254 0x0600 //RX_FDDRC_THRD_2_3 +255 0x0800 //RX_FDDRC_THRD_3_0 +256 0x0800 //RX_FDDRC_THRD_3_1 +257 0x0800 //RX_FDDRC_THRD_3_2 +258 0x0800 //RX_FDDRC_THRD_3_3 +259 0x0000 //RX_FDDRC_SLANT_0_0 +260 0x0000 //RX_FDDRC_SLANT_0_1 +261 0x0000 //RX_FDDRC_SLANT_0_2 +262 0x0000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0082 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x4000 //RX_TDDRC_ALPHA_DWN_2 +186 0x4000 //RX_TDDRC_ALPHA_DWN_3 +189 0x4000 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0780 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x8080 //RX_FDEQ_GAIN_0 +197 0x8054 //RX_FDEQ_GAIN_1 +198 0x5050 //RX_FDEQ_GAIN_2 +199 0x5058 //RX_FDEQ_GAIN_3 +200 0x5C70 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x484C //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x485A //RX_FDEQ_GAIN_8 +205 0x5A58 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0604 //RX_FDEQ_BIN_4 +225 0x0406 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x0060 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x0600 //RX_FDDRC_THRD_2_0 +252 0x0600 //RX_FDDRC_THRD_2_1 +253 0x0600 //RX_FDDRC_THRD_2_2 +254 0x0600 //RX_FDDRC_THRD_2_3 +255 0x0800 //RX_FDDRC_THRD_3_0 +256 0x0800 //RX_FDDRC_THRD_3_1 +257 0x0800 //RX_FDDRC_THRD_3_2 +258 0x0800 //RX_FDDRC_THRD_3_3 +259 0x0000 //RX_FDDRC_SLANT_0_0 +260 0x0000 //RX_FDDRC_SLANT_0_1 +261 0x0000 //RX_FDDRC_SLANT_0_2 +262 0x0000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME HANDSFREE-HANDFREE-VOICE_GENERIC-WB +#PARAM_MODE FULL +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0001 //TX_OPERATION_MODE_0 +1 0x0001 //TX_OPERATION_MODE_1 +2 0x0033 //TX_PATCH_REG +3 0x2F7C //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0003 //TX_NUM_MIC +6 0x0001 //TX_SAMPLINGFREQ_SIG +7 0x0001 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009C //TX_DIST2REF1 +22 0x0019 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x1000 //TX_PGA_0 +28 0x1000 //TX_PGA_1 +29 0x1000 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0001 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0002 //TX_MIC_DATA_SRC1 +43 0x0001 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3A66 //TX_DIST2REF_11 +73 0x053D //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0800 //TX_MIC_REFBLK_VOLUME +108 0x0C00 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0000 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7B02 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x5000 //TX_THR_PITCH_DET_0 +131 0x4800 //TX_THR_PITCH_DET_1 +132 0x4000 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x0028 //TX_TAIL_LENGTH +147 0x0300 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x6C00 //TX_EAD_THR +151 0x1000 //TX_THR_RE_EST +152 0x0200 //TX_MIN_EQ_RE_EST_0 +153 0x0100 //TX_MIN_EQ_RE_EST_1 +154 0x0200 //TX_MIN_EQ_RE_EST_2 +155 0x0200 //TX_MIN_EQ_RE_EST_3 +156 0x0200 //TX_MIN_EQ_RE_EST_4 +157 0x0200 //TX_MIN_EQ_RE_EST_5 +158 0x0200 //TX_MIN_EQ_RE_EST_6 +159 0x1000 //TX_MIN_EQ_RE_EST_7 +160 0x1000 //TX_MIN_EQ_RE_EST_8 +161 0x1000 //TX_MIN_EQ_RE_EST_9 +162 0x1000 //TX_MIN_EQ_RE_EST_10 +163 0x1000 //TX_MIN_EQ_RE_EST_11 +164 0x1000 //TX_MIN_EQ_RE_EST_12 +165 0x4000 //TX_LAMBDA_RE_EST +166 0x4000 //TX_LAMBDA_CB_NLE +167 0x7FFF //TX_C_POST_FLT +168 0x5000 //TX_GAIN_NP +169 0x0180 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x05DC //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x6590 //TX_DTD_THR1_0 +198 0x6590 //TX_DTD_THR1_1 +199 0x6590 //TX_DTD_THR1_2 +200 0x7FF0 //TX_DTD_THR1_3 +201 0x7FF0 //TX_DTD_THR1_4 +202 0x7FF0 //TX_DTD_THR1_5 +203 0x7FF0 //TX_DTD_THR1_6 +204 0x5000 //TX_DTD_THR2_0 +205 0x5000 //TX_DTD_THR2_1 +206 0x5000 //TX_DTD_THR2_2 +207 0x5000 //TX_DTD_THR2_3 +208 0x5000 //TX_DTD_THR2_4 +209 0x5000 //TX_DTD_THR2_5 +210 0x5000 //TX_DTD_THR2_6 +211 0x7FFF //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x07D0 //TX_DT_CUT_K +214 0x0100 //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x023E //TX_ADPT_STRICT_L +222 0x023E //TX_ADPT_STRICT_H +223 0x03E8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x0578 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x0001 //TX_RATIO_DT_L0_TH +228 0x7FFF //TX_B_POST_FILT_ECHO_L +229 0x7FFF //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x1000 //TX_B_LESSCUT_RTO_ECHO +232 0x0000 //TX_EPD_OFFSET_00 +233 0x0000 //TX_EPD_OFFST_01 +234 0x03E8 //TX_RATIO_DT_L0_TH_HIGH +235 0x7FFF //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x0000 //TX_DTD_THR1_7 +238 0x0000 //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xF800 //TX_THR_SN_EST_0 +243 0xFA00 //TX_THR_SN_EST_1 +244 0xFA00 //TX_THR_SN_EST_2 +245 0xFB00 //TX_THR_SN_EST_3 +246 0xFA00 //TX_THR_SN_EST_4 +247 0xFA00 //TX_THR_SN_EST_5 +248 0xF800 //TX_THR_SN_EST_6 +249 0xF800 //TX_THR_SN_EST_7 +250 0x0100 //TX_DELTA_THR_SN_EST_0 +251 0x0100 //TX_DELTA_THR_SN_EST_1 +252 0x0200 //TX_DELTA_THR_SN_EST_2 +253 0x0100 //TX_DELTA_THR_SN_EST_3 +254 0x0100 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0200 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x4000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x4000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x2000 //TX_B_POST_FLT_0 +280 0x1000 //TX_B_POST_FLT_1 +281 0x0010 //TX_NS_LVL_CTRL_0 +282 0x0014 //TX_NS_LVL_CTRL_1 +283 0x0018 //TX_NS_LVL_CTRL_2 +284 0x0016 //TX_NS_LVL_CTRL_3 +285 0x0014 //TX_NS_LVL_CTRL_4 +286 0x0011 //TX_NS_LVL_CTRL_5 +287 0x0014 //TX_NS_LVL_CTRL_6 +288 0x0011 //TX_NS_LVL_CTRL_7 +289 0x000F //TX_MIN_GAIN_S_0 +290 0x0010 //TX_MIN_GAIN_S_1 +291 0x0010 //TX_MIN_GAIN_S_2 +292 0x0010 //TX_MIN_GAIN_S_3 +293 0x0010 //TX_MIN_GAIN_S_4 +294 0x0010 //TX_MIN_GAIN_S_5 +295 0x0010 //TX_MIN_GAIN_S_6 +296 0x000F //TX_MIN_GAIN_S_7 +297 0x6000 //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x4000 //TX_SNRI_SUP_1 +302 0x4000 //TX_SNRI_SUP_2 +303 0x4000 //TX_SNRI_SUP_3 +304 0x4000 //TX_SNRI_SUP_4 +305 0x50C0 //TX_SNRI_SUP_5 +306 0x4000 //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x0018 //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x5000 //TX_A_POST_FILT_S_0 +315 0x4C00 //TX_A_POST_FILT_S_1 +316 0x4000 //TX_A_POST_FILT_S_2 +317 0x6000 //TX_A_POST_FILT_S_3 +318 0x4000 //TX_A_POST_FILT_S_4 +319 0x5000 //TX_A_POST_FILT_S_5 +320 0x6000 //TX_A_POST_FILT_S_6 +321 0x7000 //TX_A_POST_FILT_S_7 +322 0x2000 //TX_B_POST_FILT_0 +323 0x2000 //TX_B_POST_FILT_1 +324 0x2000 //TX_B_POST_FILT_2 +325 0x4000 //TX_B_POST_FILT_3 +326 0x4000 //TX_B_POST_FILT_4 +327 0x1000 //TX_B_POST_FILT_5 +328 0x1000 //TX_B_POST_FILT_6 +329 0x2000 //TX_B_POST_FILT_7 +330 0x4000 //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x6000 //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7C00 //TX_LAMBDA_PFILT +339 0x7C00 //TX_LAMBDA_PFILT_S_0 +340 0x7C00 //TX_LAMBDA_PFILT_S_1 +341 0x7A00 //TX_LAMBDA_PFILT_S_2 +342 0x7C00 //TX_LAMBDA_PFILT_S_3 +343 0x7C00 //TX_LAMBDA_PFILT_S_4 +344 0x7C00 //TX_LAMBDA_PFILT_S_5 +345 0x7C00 //TX_LAMBDA_PFILT_S_6 +346 0x7C00 //TX_LAMBDA_PFILT_S_7 +347 0x0200 //TX_K_PEPPER +348 0x0800 //TX_A_PEPPER +349 0x1EAA //TX_K_PEPPER_HF +350 0x0600 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0200 //TX_DT_BINVAD_TH_0 +354 0x0200 //TX_DT_BINVAD_TH_1 +355 0x0200 //TX_DT_BINVAD_TH_2 +356 0x0200 //TX_DT_BINVAD_TH_3 +357 0x1D4C //TX_DT_BINVAD_ENDF +358 0x0800 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0140 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0064 //TX_NDETCT +367 0x0032 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x017E //TX_NOISE_TH_1 +371 0x0230 //TX_NOISE_TH_2 +372 0x3492 //TX_NOISE_TH_3 +373 0x4E20 //TX_NOISE_TH_4 +374 0x55B8 //TX_NOISE_TH_5 +375 0x49E6 //TX_NOISE_TH_5_2 +376 0x0001 //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x0F0A //TX_NOISE_TH_6 +379 0x0033 //TX_MINENOISE_TH +380 0xD508 //TX_MORENS_TFMASK_TH +381 0x0001 //TX_DRC_QUIET_FLOOR +382 0x7999 //TX_RATIODTL_CUT_TH +383 0x0119 //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x0333 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x7FFF //TX_POST_MASK_SUP_HSNE +392 0x7FFF //TX_TAIL_DET_TH +393 0x4000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0080 //TX_SUPHIGH_TH +396 0x0000 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x1800 //TX_C_POST_FLT_MASK +399 0x4000 //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0001 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x0033 //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x7FFF //TX_MIN_G_CTRL_SSNS +409 0x0000 //TX_METAL_RTO_THR +410 0x4848 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x4000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x01E0 //TX_NOR_OFF_THR +498 0x7C00 //TX_MORE_ON_700HZ_THR +499 0x0000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0xD333 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x4000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x000A //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0x3000 //TX_DEREVERB_LF_MU +515 0x34CD //TX_DEREVERB_HF_MU +516 0x0007 //TX_DEREVERB_DELAY +517 0x0004 //TX_DEREVERB_COEF_LEN +518 0x0003 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x3A98 //TX_GSC_RTOL_TH +522 0x3A98 //TX_GSC_RTOH_TH +523 0x7E2C //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0020 //TX_FDEQ_SUBNUM +567 0x5050 //TX_FDEQ_GAIN_0 +568 0x544B //TX_FDEQ_GAIN_1 +569 0x4B4B //TX_FDEQ_GAIN_2 +570 0x4B48 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4850 //TX_FDEQ_GAIN_5 +573 0x5458 //TX_FDEQ_GAIN_6 +574 0x5A4C //TX_FDEQ_GAIN_7 +575 0x464C //TX_FDEQ_GAIN_8 +576 0x4844 //TX_FDEQ_GAIN_9 +577 0x393C //TX_FDEQ_GAIN_10 +578 0x3C3C //TX_FDEQ_GAIN_11 +579 0x4848 //TX_FDEQ_GAIN_12 +580 0x4848 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0303 //TX_FDEQ_BIN_2 +594 0x0304 //TX_FDEQ_BIN_3 +595 0x0405 //TX_FDEQ_BIN_4 +596 0x0506 //TX_FDEQ_BIN_5 +597 0x0708 //TX_FDEQ_BIN_6 +598 0x090A //TX_FDEQ_BIN_7 +599 0x0B0C //TX_FDEQ_BIN_8 +600 0x0D0E //TX_FDEQ_BIN_9 +601 0x0F10 //TX_FDEQ_BIN_10 +602 0x1011 //TX_FDEQ_BIN_11 +603 0x1112 //TX_FDEQ_BIN_12 +604 0x120B //TX_FDEQ_BIN_13 +605 0x0000 //TX_FDEQ_BIN_14 +606 0x0000 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4848 //TX_PREEQ_GAIN_MIC0_8 +626 0x4848 //TX_PREEQ_GAIN_MIC0_9 +627 0x4848 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0202 //TX_PREEQ_BIN_MIC0_0 +642 0x0203 //TX_PREEQ_BIN_MIC0_1 +643 0x0303 //TX_PREEQ_BIN_MIC0_2 +644 0x0304 //TX_PREEQ_BIN_MIC0_3 +645 0x0405 //TX_PREEQ_BIN_MIC0_4 +646 0x0506 //TX_PREEQ_BIN_MIC0_5 +647 0x0708 //TX_PREEQ_BIN_MIC0_6 +648 0x090A //TX_PREEQ_BIN_MIC0_7 +649 0x0B0C //TX_PREEQ_BIN_MIC0_8 +650 0x0D0E //TX_PREEQ_BIN_MIC0_9 +651 0x0F10 //TX_PREEQ_BIN_MIC0_10 +652 0x1011 //TX_PREEQ_BIN_MIC0_11 +653 0x1112 //TX_PREEQ_BIN_MIC0_12 +654 0x120B //TX_PREEQ_BIN_MIC0_13 +655 0x0000 //TX_PREEQ_BIN_MIC0_14 +656 0x0000 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4A4B //TX_PREEQ_GAIN_MIC1_9 +676 0x4B4A //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x494C //TX_PREEQ_GAIN_MIC1_12 +679 0x4C4C //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0202 //TX_PREEQ_BIN_MIC1_0 +691 0x0203 //TX_PREEQ_BIN_MIC1_1 +692 0x0303 //TX_PREEQ_BIN_MIC1_2 +693 0x0304 //TX_PREEQ_BIN_MIC1_3 +694 0x0405 //TX_PREEQ_BIN_MIC1_4 +695 0x0506 //TX_PREEQ_BIN_MIC1_5 +696 0x0708 //TX_PREEQ_BIN_MIC1_6 +697 0x090A //TX_PREEQ_BIN_MIC1_7 +698 0x0B0C //TX_PREEQ_BIN_MIC1_8 +699 0x0D0E //TX_PREEQ_BIN_MIC1_9 +700 0x0F10 //TX_PREEQ_BIN_MIC1_10 +701 0x1011 //TX_PREEQ_BIN_MIC1_11 +702 0x1112 //TX_PREEQ_BIN_MIC1_12 +703 0x120B //TX_PREEQ_BIN_MIC1_13 +704 0x0000 //TX_PREEQ_BIN_MIC1_14 +705 0x0000 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x494A //TX_PREEQ_GAIN_MIC2_4 +720 0x4B4C //TX_PREEQ_GAIN_MIC2_5 +721 0x4D4D //TX_PREEQ_GAIN_MIC2_6 +722 0x4E4F //TX_PREEQ_GAIN_MIC2_7 +723 0x4F50 //TX_PREEQ_GAIN_MIC2_8 +724 0x5051 //TX_PREEQ_GAIN_MIC2_9 +725 0x5252 //TX_PREEQ_GAIN_MIC2_10 +726 0x5253 //TX_PREEQ_GAIN_MIC2_11 +727 0x5353 //TX_PREEQ_GAIN_MIC2_12 +728 0x5454 //TX_PREEQ_GAIN_MIC2_13 +729 0x5455 //TX_PREEQ_GAIN_MIC2_14 +730 0x5657 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0608 //TX_PREEQ_BIN_MIC2_0 +740 0x0808 //TX_PREEQ_BIN_MIC2_1 +741 0x0808 //TX_PREEQ_BIN_MIC2_2 +742 0x0808 //TX_PREEQ_BIN_MIC2_3 +743 0x0808 //TX_PREEQ_BIN_MIC2_4 +744 0x0808 //TX_PREEQ_BIN_MIC2_5 +745 0x0808 //TX_PREEQ_BIN_MIC2_6 +746 0x0808 //TX_PREEQ_BIN_MIC2_7 +747 0x0808 //TX_PREEQ_BIN_MIC2_8 +748 0x0808 //TX_PREEQ_BIN_MIC2_9 +749 0x0808 //TX_PREEQ_BIN_MIC2_10 +750 0x0808 //TX_PREEQ_BIN_MIC2_11 +751 0x0808 //TX_PREEQ_BIN_MIC2_12 +752 0x0808 //TX_PREEQ_BIN_MIC2_13 +753 0x0808 //TX_PREEQ_BIN_MIC2_14 +754 0x0808 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x0800 //TX_NND_WEIGHT +765 0x0062 //TX_MIC_CALIBRATION_0 +766 0x0062 //TX_MIC_CALIBRATION_1 +767 0x0062 //TX_MIC_CALIBRATION_2 +768 0x0062 //TX_MIC_CALIBRATION_3 +769 0x0046 //TX_MIC_PWR_BIAS_0 +770 0x0046 //TX_MIC_PWR_BIAS_1 +771 0x0046 //TX_MIC_PWR_BIAS_2 +772 0x0046 //TX_MIC_PWR_BIAS_3 +773 0x0009 //TX_GAIN_LIMIT_0 +774 0x000F //TX_GAIN_LIMIT_1 +775 0x000F //TX_GAIN_LIMIT_2 +776 0x000F //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x0800 //TX_TDDRC_ALPHA_UP_01 +784 0x0800 //TX_TDDRC_ALPHA_UP_02 +785 0x0800 //TX_TDDRC_ALPHA_UP_03 +786 0x0800 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x7FFF //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0010 //TX_DEADMIC_SILENCE_TH +817 0x0600 //TX_MIC_DEGRADE_TH +818 0x0078 //TX_DEADMIC_CNT +819 0x0078 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x4848 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0096 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0002 //TX_FILTINDX +854 0x0001 //TX_TDDRC_THRD_0 +855 0x0002 //TX_TDDRC_THRD_1 +856 0x1800 //TX_TDDRC_THRD_2 +857 0x1800 //TX_TDDRC_THRD_3 +858 0x6000 //TX_TDDRC_SLANT_0 +859 0x6000 //TX_TDDRC_SLANT_1 +860 0x0800 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x0C97 //TX_TDDRC_DRC_GAIN +867 0x7FFF //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x0028 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x4000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x2339 //TX_SENDFUNC_REG_MICMUTE +898 0x0021 //TX_SENDFUNC_REG_MICMUTE1 +899 0x02BC //TX_MICMUTE_RATIO_THR +900 0x0140 //TX_MICMUTE_AMP_THR +901 0x0004 //TX_MICMUTE_HPF_IND +902 0x00C0 //TX_MICMUTE_LOG_EYR_TH +903 0x0008 //TX_MICMUTE_CVG_TIME +904 0x0008 //TX_MICMUTE_RELEASE_TIME +905 0x01FE //TX_MIC_VOLUME_MIC0MUTE +906 0x0020 //TX_MICMUTE_EPD_OFFSET_0 +907 0x001E //TX_MICMUTE_FRQ_AEC_L +908 0x7999 //TX_MICMUTE_EAD_THR +909 0x7FFF //TX_MICMUTE_LAMBDA_CB_NLE +910 0x7FFF //TX_MICMUTE_LAMBDA_RE_EST +911 0x4000 //TX_DTD_THR1_MICMUTE_0 +912 0x7000 //TX_DTD_THR1_MICMUTE_1 +913 0x7FFF //TX_DTD_THR1_MICMUTE_2 +914 0x7FFF //TX_DTD_THR1_MICMUTE_3 +915 0x6CCC //TX_DTD_THR2_MICMUTE_0 +916 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x1000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x4000 //TX_MICMUTE_C_POST_FLT +922 0x03E8 //TX_MICMUTE_DT_CUT_K +923 0x0001 //TX_MICMUTE_DT_CUT_THR +924 0x03E8 //TX_MICMUTE_DT_CUT_K2 +925 0x0001 //TX_MICMUTE_DT_CUT_THR2 +926 0x0064 //TX_MICMUTE_DT2_HOLD_N +927 0x1000 //TX_MICMUTE_RATIODTH_THCUT +928 0x1000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x7FFF //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0400 //TX_MICMUTE_C_POST_FLT_MASK +931 0x7999 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0258 //TX_MICMUTE_DT_CUT_K1 +933 0x0800 //TX_MICMUTE_N2_SN_EST +934 0xFC00 //TX_MICMUTE_THR_SN_EST_0 +935 0x001C //TX_MICMUTE_MIN_G_CTRL_0 +936 0x6000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x7000 //TX_MICMUTE_B_POST_FILT_0 +938 0x2710 //TX_MIC1RUB_AMP_THR +939 0x0010 //TX_MIC1MUTE_RATIO_THR +940 0x0450 //TX_MIC1MUTE_AMP_THR +941 0x0008 //TX_MIC1MUTE_CVG_TIME +942 0x0008 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x206C //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0001 //RX_SAMPLINGFREQ_SIG +3 0x0001 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x6000 //RX_TDDRC_ALPHA_UP_1 +7 0x6000 //RX_TDDRC_ALPHA_UP_2 +8 0x6000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7B02 //RX_A_HP +12 0x4000 //RX_B_PE +13 0x7800 //RX_THR_PITCH_DET_0 +14 0x7000 //RX_THR_PITCH_DET_1 +15 0x6000 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0400 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x0010 //RX_NS_LVL_CTRL +23 0xF800 //RX_THR_SN_EST +24 0x7E00 //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4844 //RX_FDEQ_GAIN_1 +41 0x3E3B //RX_FDEQ_GAIN_2 +42 0x4143 //RX_FDEQ_GAIN_3 +43 0x4348 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4E56 //RX_FDEQ_GAIN_11 +51 0x595C //RX_FDEQ_GAIN_12 +52 0x5959 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0404 //RX_FDEQ_BIN_4 +68 0x0204 //RX_FDEQ_BIN_5 +69 0x0A0A //RX_FDEQ_BIN_6 +70 0x0A0A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +92 0x0120 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0002 //RX_FILTINDX +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1C00 //RX_TDDRC_THRD_2 +115 0x1C00 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x6000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0284 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x2000 //RX_MIN_G_FP +128 0x0080 //RX_MAX_G_FP +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x6000 //RX_TDDRC_ALPHA_UP_1 +7 0x6000 //RX_TDDRC_ALPHA_UP_2 +8 0x6000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1C00 //RX_TDDRC_THRD_2 +115 0x1C00 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x6000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0284 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4844 //RX_FDEQ_GAIN_1 +41 0x3E3B //RX_FDEQ_GAIN_2 +42 0x4143 //RX_FDEQ_GAIN_3 +43 0x4348 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4E56 //RX_FDEQ_GAIN_11 +51 0x595C //RX_FDEQ_GAIN_12 +52 0x5959 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0404 //RX_FDEQ_BIN_4 +68 0x0204 //RX_FDEQ_BIN_5 +69 0x0A0A //RX_FDEQ_BIN_6 +70 0x0A0A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +92 0x0120 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0011 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x6000 //RX_TDDRC_ALPHA_UP_1 +7 0x6000 //RX_TDDRC_ALPHA_UP_2 +8 0x6000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1C00 //RX_TDDRC_THRD_2 +115 0x1C00 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x6000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0284 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4844 //RX_FDEQ_GAIN_1 +41 0x3E3B //RX_FDEQ_GAIN_2 +42 0x4143 //RX_FDEQ_GAIN_3 +43 0x4348 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4E56 //RX_FDEQ_GAIN_11 +51 0x595C //RX_FDEQ_GAIN_12 +52 0x5959 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0404 //RX_FDEQ_BIN_4 +68 0x0204 //RX_FDEQ_BIN_5 +69 0x0A0A //RX_FDEQ_BIN_6 +70 0x0A0A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +92 0x0120 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0019 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x6000 //RX_TDDRC_ALPHA_UP_1 +7 0x6000 //RX_TDDRC_ALPHA_UP_2 +8 0x6000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1C00 //RX_TDDRC_THRD_2 +115 0x1C00 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x6000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0284 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4844 //RX_FDEQ_GAIN_1 +41 0x3E3B //RX_FDEQ_GAIN_2 +42 0x4143 //RX_FDEQ_GAIN_3 +43 0x4348 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4E56 //RX_FDEQ_GAIN_11 +51 0x595C //RX_FDEQ_GAIN_12 +52 0x5959 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0404 //RX_FDEQ_BIN_4 +68 0x0204 //RX_FDEQ_BIN_5 +69 0x0A0A //RX_FDEQ_BIN_6 +70 0x0A0A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +92 0x0120 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0024 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x6000 //RX_TDDRC_ALPHA_UP_1 +7 0x6000 //RX_TDDRC_ALPHA_UP_2 +8 0x6000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1C00 //RX_TDDRC_THRD_2 +115 0x1C00 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x6000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0284 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4844 //RX_FDEQ_GAIN_1 +41 0x3E3B //RX_FDEQ_GAIN_2 +42 0x4143 //RX_FDEQ_GAIN_3 +43 0x4348 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4E56 //RX_FDEQ_GAIN_11 +51 0x595C //RX_FDEQ_GAIN_12 +52 0x5959 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0404 //RX_FDEQ_BIN_4 +68 0x0204 //RX_FDEQ_BIN_5 +69 0x0A0A //RX_FDEQ_BIN_6 +70 0x0A0A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +92 0x0120 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0033 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x6000 //RX_TDDRC_ALPHA_UP_1 +7 0x6000 //RX_TDDRC_ALPHA_UP_2 +8 0x6000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1C00 //RX_TDDRC_THRD_2 +115 0x1C00 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x6000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0284 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4844 //RX_FDEQ_GAIN_1 +41 0x3E3B //RX_FDEQ_GAIN_2 +42 0x4143 //RX_FDEQ_GAIN_3 +43 0x4348 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4E56 //RX_FDEQ_GAIN_11 +51 0x595C //RX_FDEQ_GAIN_12 +52 0x5959 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0404 //RX_FDEQ_BIN_4 +68 0x0204 //RX_FDEQ_BIN_5 +69 0x0A0A //RX_FDEQ_BIN_6 +70 0x0A0A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +92 0x0120 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0049 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x6000 //RX_TDDRC_ALPHA_UP_1 +7 0x6000 //RX_TDDRC_ALPHA_UP_2 +8 0x6000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1C00 //RX_TDDRC_THRD_2 +115 0x1C00 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x6000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0284 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4844 //RX_FDEQ_GAIN_1 +41 0x3E3B //RX_FDEQ_GAIN_2 +42 0x4143 //RX_FDEQ_GAIN_3 +43 0x4348 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4E56 //RX_FDEQ_GAIN_11 +51 0x595C //RX_FDEQ_GAIN_12 +52 0x5959 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0404 //RX_FDEQ_BIN_4 +68 0x0204 //RX_FDEQ_BIN_5 +69 0x0A0A //RX_FDEQ_BIN_6 +70 0x0A0A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +92 0x0120 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0074 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x6000 //RX_TDDRC_ALPHA_UP_1 +7 0x6000 //RX_TDDRC_ALPHA_UP_2 +8 0x6000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1C00 //RX_TDDRC_THRD_2 +115 0x1C00 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x6000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0284 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4844 //RX_FDEQ_GAIN_1 +41 0x3E3B //RX_FDEQ_GAIN_2 +42 0x4143 //RX_FDEQ_GAIN_3 +43 0x4348 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4E56 //RX_FDEQ_GAIN_11 +51 0x595C //RX_FDEQ_GAIN_12 +52 0x5959 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0404 //RX_FDEQ_BIN_4 +68 0x0204 //RX_FDEQ_BIN_5 +69 0x0A0A //RX_FDEQ_BIN_6 +70 0x0A0A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +92 0x0120 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x027C //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0001 //RX_SAMPLINGFREQ_SIG +160 0x0001 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x6000 //RX_TDDRC_ALPHA_UP_1 +164 0x6000 //RX_TDDRC_ALPHA_UP_2 +165 0x6000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7B02 //RX_A_HP +169 0x4000 //RX_B_PE +170 0x7800 //RX_THR_PITCH_DET_0 +171 0x7000 //RX_THR_PITCH_DET_1 +172 0x6000 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0400 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x0010 //RX_NS_LVL_CTRL +180 0xF800 //RX_THR_SN_EST +181 0x7E00 //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x001C //RX_FDEQ_SUBNUM +196 0x6868 //RX_FDEQ_GAIN_0 +197 0x6858 //RX_FDEQ_GAIN_1 +198 0x5858 //RX_FDEQ_GAIN_2 +199 0x5858 //RX_FDEQ_GAIN_3 +200 0x5C5C //RX_FDEQ_GAIN_4 +201 0x5C54 //RX_FDEQ_GAIN_5 +202 0x544C //RX_FDEQ_GAIN_6 +203 0x4A48 //RX_FDEQ_GAIN_7 +204 0x4860 //RX_FDEQ_GAIN_8 +205 0x6068 //RX_FDEQ_GAIN_9 +206 0x6C6C //RX_FDEQ_GAIN_10 +207 0x6C68 //RX_FDEQ_GAIN_11 +208 0x5A5A //RX_FDEQ_GAIN_12 +209 0x5A5C //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0404 //RX_FDEQ_BIN_4 +225 0x0204 //RX_FDEQ_BIN_5 +226 0x0A0A //RX_FDEQ_BIN_6 +227 0x0A0A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +249 0x0120 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0002 //RX_FILTINDX +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1C00 //RX_TDDRC_THRD_2 +272 0x1C00 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x6000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0715 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x2000 //RX_MIN_G_FP +285 0x0080 //RX_MAX_G_FP +286 0x0011 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x6000 //RX_TDDRC_ALPHA_UP_1 +164 0x6000 //RX_TDDRC_ALPHA_UP_2 +165 0x6000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1C00 //RX_TDDRC_THRD_2 +272 0x1C00 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x6000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0715 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x6868 //RX_FDEQ_GAIN_0 +197 0x6858 //RX_FDEQ_GAIN_1 +198 0x5858 //RX_FDEQ_GAIN_2 +199 0x5858 //RX_FDEQ_GAIN_3 +200 0x5C5C //RX_FDEQ_GAIN_4 +201 0x5C54 //RX_FDEQ_GAIN_5 +202 0x544C //RX_FDEQ_GAIN_6 +203 0x4A48 //RX_FDEQ_GAIN_7 +204 0x4860 //RX_FDEQ_GAIN_8 +205 0x6068 //RX_FDEQ_GAIN_9 +206 0x6C6C //RX_FDEQ_GAIN_10 +207 0x6C68 //RX_FDEQ_GAIN_11 +208 0x5A5A //RX_FDEQ_GAIN_12 +209 0x5A5C //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0404 //RX_FDEQ_BIN_4 +225 0x0204 //RX_FDEQ_BIN_5 +226 0x0A0A //RX_FDEQ_BIN_6 +227 0x0A0A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +249 0x0120 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0011 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x6000 //RX_TDDRC_ALPHA_UP_1 +164 0x6000 //RX_TDDRC_ALPHA_UP_2 +165 0x6000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1C00 //RX_TDDRC_THRD_2 +272 0x1C00 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x6000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0715 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x6868 //RX_FDEQ_GAIN_0 +197 0x6858 //RX_FDEQ_GAIN_1 +198 0x5858 //RX_FDEQ_GAIN_2 +199 0x5858 //RX_FDEQ_GAIN_3 +200 0x5C5C //RX_FDEQ_GAIN_4 +201 0x5C54 //RX_FDEQ_GAIN_5 +202 0x544C //RX_FDEQ_GAIN_6 +203 0x4A48 //RX_FDEQ_GAIN_7 +204 0x4860 //RX_FDEQ_GAIN_8 +205 0x6068 //RX_FDEQ_GAIN_9 +206 0x6C6C //RX_FDEQ_GAIN_10 +207 0x6C68 //RX_FDEQ_GAIN_11 +208 0x5A5A //RX_FDEQ_GAIN_12 +209 0x5A5C //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0404 //RX_FDEQ_BIN_4 +225 0x0204 //RX_FDEQ_BIN_5 +226 0x0A0A //RX_FDEQ_BIN_6 +227 0x0A0A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +249 0x0120 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0019 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x6000 //RX_TDDRC_ALPHA_UP_1 +164 0x6000 //RX_TDDRC_ALPHA_UP_2 +165 0x6000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1C00 //RX_TDDRC_THRD_2 +272 0x1C00 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x6000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0715 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x6868 //RX_FDEQ_GAIN_0 +197 0x6858 //RX_FDEQ_GAIN_1 +198 0x5858 //RX_FDEQ_GAIN_2 +199 0x5858 //RX_FDEQ_GAIN_3 +200 0x5C5C //RX_FDEQ_GAIN_4 +201 0x5C54 //RX_FDEQ_GAIN_5 +202 0x544C //RX_FDEQ_GAIN_6 +203 0x4A48 //RX_FDEQ_GAIN_7 +204 0x4860 //RX_FDEQ_GAIN_8 +205 0x6068 //RX_FDEQ_GAIN_9 +206 0x6C6C //RX_FDEQ_GAIN_10 +207 0x6C68 //RX_FDEQ_GAIN_11 +208 0x5A5A //RX_FDEQ_GAIN_12 +209 0x5A5C //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0404 //RX_FDEQ_BIN_4 +225 0x0204 //RX_FDEQ_BIN_5 +226 0x0A0A //RX_FDEQ_BIN_6 +227 0x0A0A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +249 0x0120 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0024 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x6000 //RX_TDDRC_ALPHA_UP_1 +164 0x6000 //RX_TDDRC_ALPHA_UP_2 +165 0x6000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1C00 //RX_TDDRC_THRD_2 +272 0x1C00 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x6000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0715 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x6868 //RX_FDEQ_GAIN_0 +197 0x6858 //RX_FDEQ_GAIN_1 +198 0x5858 //RX_FDEQ_GAIN_2 +199 0x5858 //RX_FDEQ_GAIN_3 +200 0x5C5C //RX_FDEQ_GAIN_4 +201 0x5C54 //RX_FDEQ_GAIN_5 +202 0x544C //RX_FDEQ_GAIN_6 +203 0x4A48 //RX_FDEQ_GAIN_7 +204 0x4860 //RX_FDEQ_GAIN_8 +205 0x6068 //RX_FDEQ_GAIN_9 +206 0x6C6C //RX_FDEQ_GAIN_10 +207 0x6C68 //RX_FDEQ_GAIN_11 +208 0x5A5A //RX_FDEQ_GAIN_12 +209 0x5A5C //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0404 //RX_FDEQ_BIN_4 +225 0x0204 //RX_FDEQ_BIN_5 +226 0x0A0A //RX_FDEQ_BIN_6 +227 0x0A0A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +249 0x0120 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0033 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x6000 //RX_TDDRC_ALPHA_UP_1 +164 0x6000 //RX_TDDRC_ALPHA_UP_2 +165 0x6000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1C00 //RX_TDDRC_THRD_2 +272 0x1C00 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x6000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0715 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x6868 //RX_FDEQ_GAIN_0 +197 0x6858 //RX_FDEQ_GAIN_1 +198 0x5858 //RX_FDEQ_GAIN_2 +199 0x5858 //RX_FDEQ_GAIN_3 +200 0x5C5C //RX_FDEQ_GAIN_4 +201 0x8854 //RX_FDEQ_GAIN_5 +202 0x5448 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4860 //RX_FDEQ_GAIN_8 +205 0x6068 //RX_FDEQ_GAIN_9 +206 0x7070 //RX_FDEQ_GAIN_10 +207 0x8070 //RX_FDEQ_GAIN_11 +208 0x6060 //RX_FDEQ_GAIN_12 +209 0x7070 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0404 //RX_FDEQ_BIN_4 +225 0x0204 //RX_FDEQ_BIN_5 +226 0x0A0A //RX_FDEQ_BIN_6 +227 0x0A0A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +249 0x0120 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0049 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x6000 //RX_TDDRC_ALPHA_UP_1 +164 0x6000 //RX_TDDRC_ALPHA_UP_2 +165 0x6000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1C00 //RX_TDDRC_THRD_2 +272 0x1C00 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x6000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0715 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x6868 //RX_FDEQ_GAIN_0 +197 0x6858 //RX_FDEQ_GAIN_1 +198 0x5858 //RX_FDEQ_GAIN_2 +199 0x5858 //RX_FDEQ_GAIN_3 +200 0x5C5C //RX_FDEQ_GAIN_4 +201 0x8854 //RX_FDEQ_GAIN_5 +202 0x5448 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4860 //RX_FDEQ_GAIN_8 +205 0x6068 //RX_FDEQ_GAIN_9 +206 0x7070 //RX_FDEQ_GAIN_10 +207 0x8070 //RX_FDEQ_GAIN_11 +208 0x6060 //RX_FDEQ_GAIN_12 +209 0x7070 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0404 //RX_FDEQ_BIN_4 +225 0x0204 //RX_FDEQ_BIN_5 +226 0x0A0A //RX_FDEQ_BIN_6 +227 0x0A0A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +249 0x0120 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0074 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x6000 //RX_TDDRC_ALPHA_UP_1 +164 0x6000 //RX_TDDRC_ALPHA_UP_2 +165 0x6000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1C00 //RX_TDDRC_THRD_2 +272 0x1C00 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x6000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0715 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x6868 //RX_FDEQ_GAIN_0 +197 0x6864 //RX_FDEQ_GAIN_1 +198 0x7070 //RX_FDEQ_GAIN_2 +199 0x6058 //RX_FDEQ_GAIN_3 +200 0x5C5C //RX_FDEQ_GAIN_4 +201 0x8854 //RX_FDEQ_GAIN_5 +202 0x5448 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4860 //RX_FDEQ_GAIN_8 +205 0x6068 //RX_FDEQ_GAIN_9 +206 0x7070 //RX_FDEQ_GAIN_10 +207 0x8070 //RX_FDEQ_GAIN_11 +208 0x6060 //RX_FDEQ_GAIN_12 +209 0x7070 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0404 //RX_FDEQ_BIN_4 +225 0x0204 //RX_FDEQ_BIN_5 +226 0x0A0A //RX_FDEQ_BIN_6 +227 0x0A0A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +249 0x0120 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME HANDSFREE-HANDFREE-VOICE_GENERIC-SWB +#PARAM_MODE FULL +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0001 //TX_OPERATION_MODE_0 +1 0x0001 //TX_OPERATION_MODE_1 +2 0x0073 //TX_PATCH_REG +3 0x2F7C //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0003 //TX_NUM_MIC +6 0x0003 //TX_SAMPLINGFREQ_SIG +7 0x0003 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009C //TX_DIST2REF1 +22 0x0019 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x1000 //TX_PGA_0 +28 0x1000 //TX_PGA_1 +29 0x1000 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0001 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0002 //TX_MIC_DATA_SRC1 +43 0x0001 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3B33 //TX_DIST2REF_11 +73 0x0A70 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0800 //TX_MIC_REFBLK_VOLUME +108 0x0CAE //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0015 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7B02 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x5000 //TX_THR_PITCH_DET_0 +131 0x4800 //TX_THR_PITCH_DET_1 +132 0x4000 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x0028 //TX_TAIL_LENGTH +147 0x0400 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x7600 //TX_EAD_THR +151 0x1000 //TX_THR_RE_EST +152 0x2000 //TX_MIN_EQ_RE_EST_0 +153 0x0600 //TX_MIN_EQ_RE_EST_1 +154 0x3000 //TX_MIN_EQ_RE_EST_2 +155 0x3000 //TX_MIN_EQ_RE_EST_3 +156 0x3000 //TX_MIN_EQ_RE_EST_4 +157 0x3000 //TX_MIN_EQ_RE_EST_5 +158 0x3000 //TX_MIN_EQ_RE_EST_6 +159 0x1000 //TX_MIN_EQ_RE_EST_7 +160 0x7800 //TX_MIN_EQ_RE_EST_8 +161 0x7800 //TX_MIN_EQ_RE_EST_9 +162 0x7800 //TX_MIN_EQ_RE_EST_10 +163 0x7800 //TX_MIN_EQ_RE_EST_11 +164 0x7800 //TX_MIN_EQ_RE_EST_12 +165 0x4000 //TX_LAMBDA_RE_EST +166 0x3000 //TX_LAMBDA_CB_NLE +167 0x7FFF //TX_C_POST_FLT +168 0x4000 //TX_GAIN_NP +169 0x0180 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x05DC //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x7FF0 //TX_DTD_THR1_0 +198 0x7FF0 //TX_DTD_THR1_1 +199 0x7FF0 //TX_DTD_THR1_2 +200 0x7FF0 //TX_DTD_THR1_3 +201 0x7FF0 //TX_DTD_THR1_4 +202 0x7FF0 //TX_DTD_THR1_5 +203 0x7FF0 //TX_DTD_THR1_6 +204 0x7E00 //TX_DTD_THR2_0 +205 0x7E00 //TX_DTD_THR2_1 +206 0x5000 //TX_DTD_THR2_2 +207 0x5000 //TX_DTD_THR2_3 +208 0x5000 //TX_DTD_THR2_4 +209 0x5000 //TX_DTD_THR2_5 +210 0x5000 //TX_DTD_THR2_6 +211 0x7FFF //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x36B0 //TX_DT_CUT_K +214 0x0100 //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x7FFF //TX_DTD_MIC_BLK +221 0x023E //TX_ADPT_STRICT_L +222 0x023E //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1F40 //TX_RATIO_DT_L_TH_HIGH +226 0x5014 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x7FFF //TX_B_POST_FILT_ECHO_L +229 0x7FFF //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x1000 //TX_B_LESSCUT_RTO_ECHO +232 0x0000 //TX_EPD_OFFSET_00 +233 0x0000 //TX_EPD_OFFST_01 +234 0x2328 //TX_RATIO_DT_L0_TH_HIGH +235 0x7FFF //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x0000 //TX_DTD_THR1_7 +238 0x0000 //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xF800 //TX_THR_SN_EST_0 +243 0xFA00 //TX_THR_SN_EST_1 +244 0xFA00 //TX_THR_SN_EST_2 +245 0xFA00 //TX_THR_SN_EST_3 +246 0xF800 //TX_THR_SN_EST_4 +247 0xFA00 //TX_THR_SN_EST_5 +248 0xF800 //TX_THR_SN_EST_6 +249 0xF800 //TX_THR_SN_EST_7 +250 0x0100 //TX_DELTA_THR_SN_EST_0 +251 0x0100 //TX_DELTA_THR_SN_EST_1 +252 0x0100 //TX_DELTA_THR_SN_EST_2 +253 0x0000 //TX_DELTA_THR_SN_EST_3 +254 0x0100 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0100 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x4000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x4000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x2000 //TX_B_POST_FLT_0 +280 0x1000 //TX_B_POST_FLT_1 +281 0x0010 //TX_NS_LVL_CTRL_0 +282 0x003C //TX_NS_LVL_CTRL_1 +283 0x0024 //TX_NS_LVL_CTRL_2 +284 0x003C //TX_NS_LVL_CTRL_3 +285 0x0014 //TX_NS_LVL_CTRL_4 +286 0x0011 //TX_NS_LVL_CTRL_5 +287 0x003C //TX_NS_LVL_CTRL_6 +288 0x0011 //TX_NS_LVL_CTRL_7 +289 0x0020 //TX_MIN_GAIN_S_0 +290 0x0020 //TX_MIN_GAIN_S_1 +291 0x0020 //TX_MIN_GAIN_S_2 +292 0x0020 //TX_MIN_GAIN_S_3 +293 0x0020 //TX_MIN_GAIN_S_4 +294 0x0020 //TX_MIN_GAIN_S_5 +295 0x0020 //TX_MIN_GAIN_S_6 +296 0x0020 //TX_MIN_GAIN_S_7 +297 0x6000 //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x4000 //TX_SNRI_SUP_1 +302 0x4000 //TX_SNRI_SUP_2 +303 0x4000 //TX_SNRI_SUP_3 +304 0x4000 //TX_SNRI_SUP_4 +305 0x4000 //TX_SNRI_SUP_5 +306 0x4000 //TX_SNRI_SUP_6 +307 0x4000 //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x0018 //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x7FFF //TX_A_POST_FILT_S_0 +315 0x7FFF //TX_A_POST_FILT_S_1 +316 0x7FFF //TX_A_POST_FILT_S_2 +317 0x7FFF //TX_A_POST_FILT_S_3 +318 0x7FFF //TX_A_POST_FILT_S_4 +319 0x7FFF //TX_A_POST_FILT_S_5 +320 0x7FFF //TX_A_POST_FILT_S_6 +321 0x7FFF //TX_A_POST_FILT_S_7 +322 0x2000 //TX_B_POST_FILT_0 +323 0x6000 //TX_B_POST_FILT_1 +324 0x6000 //TX_B_POST_FILT_2 +325 0x6000 //TX_B_POST_FILT_3 +326 0x4000 //TX_B_POST_FILT_4 +327 0x1000 //TX_B_POST_FILT_5 +328 0x1000 //TX_B_POST_FILT_6 +329 0x2000 //TX_B_POST_FILT_7 +330 0x4000 //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x6000 //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7F00 //TX_LAMBDA_PFILT +339 0x7F00 //TX_LAMBDA_PFILT_S_0 +340 0x7F00 //TX_LAMBDA_PFILT_S_1 +341 0x7F00 //TX_LAMBDA_PFILT_S_2 +342 0x7F00 //TX_LAMBDA_PFILT_S_3 +343 0x7F00 //TX_LAMBDA_PFILT_S_4 +344 0x7F00 //TX_LAMBDA_PFILT_S_5 +345 0x7F00 //TX_LAMBDA_PFILT_S_6 +346 0x7F00 //TX_LAMBDA_PFILT_S_7 +347 0x0200 //TX_K_PEPPER +348 0x0400 //TX_A_PEPPER +349 0x1EAA //TX_K_PEPPER_HF +350 0x0600 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0040 //TX_DT_BINVAD_TH_0 +354 0x0040 //TX_DT_BINVAD_TH_1 +355 0x0100 //TX_DT_BINVAD_TH_2 +356 0x0100 //TX_DT_BINVAD_TH_3 +357 0x36B0 //TX_DT_BINVAD_ENDF +358 0x0200 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0140 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0064 //TX_NDETCT +367 0x0050 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x07D0 //TX_NOISE_TH_1 +371 0x01F4 //TX_NOISE_TH_2 +372 0x36B0 //TX_NOISE_TH_3 +373 0x2710 //TX_NOISE_TH_4 +374 0x2CEC //TX_NOISE_TH_5 +375 0x7FFF //TX_NOISE_TH_5_2 +376 0x0000 //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x0DAC //TX_NOISE_TH_6 +379 0x0050 //TX_MINENOISE_TH +380 0xD508 //TX_MORENS_TFMASK_TH +381 0x0001 //TX_DRC_QUIET_FLOOR +382 0x3A98 //TX_RATIODTL_CUT_TH +383 0x07D0 //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x0333 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x7FFF //TX_POST_MASK_SUP_HSNE +392 0x1388 //TX_TAIL_DET_TH +393 0x4000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0080 //TX_SUPHIGH_TH +396 0x0000 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x1800 //TX_C_POST_FLT_MASK +399 0x7FFF //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0001 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x0050 //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x4000 //TX_MIN_G_CTRL_SSNS +409 0x0000 //TX_METAL_RTO_THR +410 0x4848 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x4000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x0230 //TX_NOR_OFF_THR +498 0x0CCD //TX_MORE_ON_700HZ_THR +499 0x0000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x2000 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0x4650 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x4000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x000A //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0x3000 //TX_DEREVERB_LF_MU +515 0x34CD //TX_DEREVERB_HF_MU +516 0x0007 //TX_DEREVERB_DELAY +517 0x0004 //TX_DEREVERB_COEF_LEN +518 0x0003 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x3A98 //TX_GSC_RTOL_TH +522 0x3A98 //TX_GSC_RTOH_TH +523 0x7E2C //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0020 //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4850 //TX_FDEQ_GAIN_2 +570 0x5050 //TX_FDEQ_GAIN_3 +571 0x4B4B //TX_FDEQ_GAIN_4 +572 0x4B4E //TX_FDEQ_GAIN_5 +573 0x4E5E //TX_FDEQ_GAIN_6 +574 0x584E //TX_FDEQ_GAIN_7 +575 0x4C4E //TX_FDEQ_GAIN_8 +576 0x4E45 //TX_FDEQ_GAIN_9 +577 0x494A //TX_FDEQ_GAIN_10 +578 0x534D //TX_FDEQ_GAIN_11 +579 0x5C5C //TX_FDEQ_GAIN_12 +580 0x5F77 //TX_FDEQ_GAIN_13 +581 0x788F //TX_FDEQ_GAIN_14 +582 0x929A //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0303 //TX_FDEQ_BIN_2 +594 0x0304 //TX_FDEQ_BIN_3 +595 0x0405 //TX_FDEQ_BIN_4 +596 0x0506 //TX_FDEQ_BIN_5 +597 0x0708 //TX_FDEQ_BIN_6 +598 0x090A //TX_FDEQ_BIN_7 +599 0x0B0C //TX_FDEQ_BIN_8 +600 0x0D0E //TX_FDEQ_BIN_9 +601 0x1013 //TX_FDEQ_BIN_10 +602 0x1719 //TX_FDEQ_BIN_11 +603 0x1B1E //TX_FDEQ_BIN_12 +604 0x1E1E //TX_FDEQ_BIN_13 +605 0x1E28 //TX_FDEQ_BIN_14 +606 0x282C //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0030 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4848 //TX_PREEQ_GAIN_MIC0_8 +626 0x4848 //TX_PREEQ_GAIN_MIC0_9 +627 0x4848 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0202 //TX_PREEQ_BIN_MIC0_0 +642 0x0203 //TX_PREEQ_BIN_MIC0_1 +643 0x0303 //TX_PREEQ_BIN_MIC0_2 +644 0x0304 //TX_PREEQ_BIN_MIC0_3 +645 0x0405 //TX_PREEQ_BIN_MIC0_4 +646 0x0506 //TX_PREEQ_BIN_MIC0_5 +647 0x0808 //TX_PREEQ_BIN_MIC0_6 +648 0x0809 //TX_PREEQ_BIN_MIC0_7 +649 0x0A0A //TX_PREEQ_BIN_MIC0_8 +650 0x0C10 //TX_PREEQ_BIN_MIC0_9 +651 0x1013 //TX_PREEQ_BIN_MIC0_10 +652 0x1414 //TX_PREEQ_BIN_MIC0_11 +653 0x261E //TX_PREEQ_BIN_MIC0_12 +654 0x1E14 //TX_PREEQ_BIN_MIC0_13 +655 0x1414 //TX_PREEQ_BIN_MIC0_14 +656 0x2814 //TX_PREEQ_BIN_MIC0_15 +657 0x401E //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0030 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x494A //TX_PREEQ_GAIN_MIC1_9 +676 0x4B4B //TX_PREEQ_GAIN_MIC1_10 +677 0x4B48 //TX_PREEQ_GAIN_MIC1_11 +678 0x4D4C //TX_PREEQ_GAIN_MIC1_12 +679 0x4A48 //TX_PREEQ_GAIN_MIC1_13 +680 0x4840 //TX_PREEQ_GAIN_MIC1_14 +681 0x3434 //TX_PREEQ_GAIN_MIC1_15 +682 0x3C48 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0202 //TX_PREEQ_BIN_MIC1_0 +691 0x0203 //TX_PREEQ_BIN_MIC1_1 +692 0x0303 //TX_PREEQ_BIN_MIC1_2 +693 0x0304 //TX_PREEQ_BIN_MIC1_3 +694 0x0405 //TX_PREEQ_BIN_MIC1_4 +695 0x0506 //TX_PREEQ_BIN_MIC1_5 +696 0x0808 //TX_PREEQ_BIN_MIC1_6 +697 0x0809 //TX_PREEQ_BIN_MIC1_7 +698 0x0A0A //TX_PREEQ_BIN_MIC1_8 +699 0x0C10 //TX_PREEQ_BIN_MIC1_9 +700 0x1013 //TX_PREEQ_BIN_MIC1_10 +701 0x1414 //TX_PREEQ_BIN_MIC1_11 +702 0x261E //TX_PREEQ_BIN_MIC1_12 +703 0x1E14 //TX_PREEQ_BIN_MIC1_13 +704 0x1414 //TX_PREEQ_BIN_MIC1_14 +705 0x2814 //TX_PREEQ_BIN_MIC1_15 +706 0x401E //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x484A //TX_PREEQ_GAIN_MIC2_6 +722 0x4B4D //TX_PREEQ_GAIN_MIC2_7 +723 0x4E4F //TX_PREEQ_GAIN_MIC2_8 +724 0x5051 //TX_PREEQ_GAIN_MIC2_9 +725 0x5253 //TX_PREEQ_GAIN_MIC2_10 +726 0x5456 //TX_PREEQ_GAIN_MIC2_11 +727 0x5251 //TX_PREEQ_GAIN_MIC2_12 +728 0x4F48 //TX_PREEQ_GAIN_MIC2_13 +729 0x423C //TX_PREEQ_GAIN_MIC2_14 +730 0x3C48 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0203 //TX_PREEQ_BIN_MIC2_0 +740 0x0303 //TX_PREEQ_BIN_MIC2_1 +741 0x0304 //TX_PREEQ_BIN_MIC2_2 +742 0x0405 //TX_PREEQ_BIN_MIC2_3 +743 0x0506 //TX_PREEQ_BIN_MIC2_4 +744 0x0808 //TX_PREEQ_BIN_MIC2_5 +745 0x0809 //TX_PREEQ_BIN_MIC2_6 +746 0x0A0A //TX_PREEQ_BIN_MIC2_7 +747 0x0C10 //TX_PREEQ_BIN_MIC2_8 +748 0x1013 //TX_PREEQ_BIN_MIC2_9 +749 0x1414 //TX_PREEQ_BIN_MIC2_10 +750 0x261E //TX_PREEQ_BIN_MIC2_11 +751 0x1E14 //TX_PREEQ_BIN_MIC2_12 +752 0x1414 //TX_PREEQ_BIN_MIC2_13 +753 0x2814 //TX_PREEQ_BIN_MIC2_14 +754 0x4022 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x0800 //TX_NND_WEIGHT +765 0x0050 //TX_MIC_CALIBRATION_0 +766 0x0065 //TX_MIC_CALIBRATION_1 +767 0x0050 //TX_MIC_CALIBRATION_2 +768 0x0050 //TX_MIC_CALIBRATION_3 +769 0x0046 //TX_MIC_PWR_BIAS_0 +770 0x0040 //TX_MIC_PWR_BIAS_1 +771 0x0046 //TX_MIC_PWR_BIAS_2 +772 0x0046 //TX_MIC_PWR_BIAS_3 +773 0x0000 //TX_GAIN_LIMIT_0 +774 0x000F //TX_GAIN_LIMIT_1 +775 0x0000 //TX_GAIN_LIMIT_2 +776 0x0000 //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x0800 //TX_TDDRC_ALPHA_UP_01 +784 0x0800 //TX_TDDRC_ALPHA_UP_02 +785 0x0800 //TX_TDDRC_ALPHA_UP_03 +786 0x0800 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x7FFF //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0010 //TX_DEADMIC_SILENCE_TH +817 0x0600 //TX_MIC_DEGRADE_TH +818 0x0078 //TX_DEADMIC_CNT +819 0x0078 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x4848 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0096 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0002 //TX_FILTINDX +854 0x0003 //TX_TDDRC_THRD_0 +855 0x0004 //TX_TDDRC_THRD_1 +856 0x1000 //TX_TDDRC_THRD_2 +857 0x1000 //TX_TDDRC_THRD_3 +858 0x6000 //TX_TDDRC_SLANT_0 +859 0x6000 //TX_TDDRC_SLANT_1 +860 0x0800 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x0E21 //TX_TDDRC_DRC_GAIN +867 0x7FFF //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x00C8 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x4000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x2339 //TX_SENDFUNC_REG_MICMUTE +898 0x0021 //TX_SENDFUNC_REG_MICMUTE1 +899 0x02BC //TX_MICMUTE_RATIO_THR +900 0x0140 //TX_MICMUTE_AMP_THR +901 0x0004 //TX_MICMUTE_HPF_IND +902 0x00C0 //TX_MICMUTE_LOG_EYR_TH +903 0x0008 //TX_MICMUTE_CVG_TIME +904 0x0008 //TX_MICMUTE_RELEASE_TIME +905 0x01FE //TX_MIC_VOLUME_MIC0MUTE +906 0x0020 //TX_MICMUTE_EPD_OFFSET_0 +907 0x001E //TX_MICMUTE_FRQ_AEC_L +908 0x7999 //TX_MICMUTE_EAD_THR +909 0x7FFF //TX_MICMUTE_LAMBDA_CB_NLE +910 0x7FFF //TX_MICMUTE_LAMBDA_RE_EST +911 0x4000 //TX_DTD_THR1_MICMUTE_0 +912 0x7000 //TX_DTD_THR1_MICMUTE_1 +913 0x7FFF //TX_DTD_THR1_MICMUTE_2 +914 0x7FFF //TX_DTD_THR1_MICMUTE_3 +915 0x6CCC //TX_DTD_THR2_MICMUTE_0 +916 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x1000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x4000 //TX_MICMUTE_C_POST_FLT +922 0x03E8 //TX_MICMUTE_DT_CUT_K +923 0x0001 //TX_MICMUTE_DT_CUT_THR +924 0x03E8 //TX_MICMUTE_DT_CUT_K2 +925 0x0001 //TX_MICMUTE_DT_CUT_THR2 +926 0x0064 //TX_MICMUTE_DT2_HOLD_N +927 0x1000 //TX_MICMUTE_RATIODTH_THCUT +928 0x1000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x7FFF //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0400 //TX_MICMUTE_C_POST_FLT_MASK +931 0x7999 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0258 //TX_MICMUTE_DT_CUT_K1 +933 0x0800 //TX_MICMUTE_N2_SN_EST +934 0xFC00 //TX_MICMUTE_THR_SN_EST_0 +935 0x001C //TX_MICMUTE_MIN_G_CTRL_0 +936 0x6000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x7000 //TX_MICMUTE_B_POST_FILT_0 +938 0x2710 //TX_MIC1RUB_AMP_THR +939 0x0010 //TX_MIC1MUTE_RATIO_THR +940 0x0450 //TX_MIC1MUTE_AMP_THR +941 0x0008 //TX_MIC1MUTE_CVG_TIME +942 0x0008 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x206C //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0003 //RX_SAMPLINGFREQ_SIG +3 0x0003 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x6000 //RX_TDDRC_ALPHA_UP_1 +7 0x6000 //RX_TDDRC_ALPHA_UP_2 +8 0x6000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7652 //RX_A_HP +12 0x4000 //RX_B_PE +13 0x7800 //RX_THR_PITCH_DET_0 +14 0x7000 //RX_THR_PITCH_DET_1 +15 0x6000 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0400 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x0010 //RX_NS_LVL_CTRL +23 0xF800 //RX_THR_SN_EST +24 0x7E00 //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x3B3B //RX_FDEQ_GAIN_1 +41 0x3942 //RX_FDEQ_GAIN_2 +42 0x4645 //RX_FDEQ_GAIN_3 +43 0x494A //RX_FDEQ_GAIN_4 +44 0x5D5A //RX_FDEQ_GAIN_5 +45 0x5B5B //RX_FDEQ_GAIN_6 +46 0x5A51 //RX_FDEQ_GAIN_7 +47 0x514F //RX_FDEQ_GAIN_8 +48 0x5555 //RX_FDEQ_GAIN_9 +49 0x5052 //RX_FDEQ_GAIN_10 +50 0x5453 //RX_FDEQ_GAIN_11 +51 0x514E //RX_FDEQ_GAIN_12 +52 0x4F59 //RX_FDEQ_GAIN_13 +53 0x6C76 //RX_FDEQ_GAIN_14 +54 0x787B //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0404 //RX_FDEQ_BIN_4 +68 0x0308 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +92 0x0120 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0002 //RX_FILTINDX +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x7EB8 //RX_TDDRC_SLANT_0 +117 0x2500 //RX_TDDRC_SLANT_1 +118 0x6000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x032A //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x2000 //RX_MIN_G_FP +128 0x0080 //RX_MAX_G_FP +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x6000 //RX_TDDRC_ALPHA_UP_1 +7 0x6000 //RX_TDDRC_ALPHA_UP_2 +8 0x6000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x7EB8 //RX_TDDRC_SLANT_0 +117 0x2500 //RX_TDDRC_SLANT_1 +118 0x6000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x032A //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x3B3B //RX_FDEQ_GAIN_1 +41 0x3942 //RX_FDEQ_GAIN_2 +42 0x4645 //RX_FDEQ_GAIN_3 +43 0x494A //RX_FDEQ_GAIN_4 +44 0x5D5A //RX_FDEQ_GAIN_5 +45 0x5B5B //RX_FDEQ_GAIN_6 +46 0x5A51 //RX_FDEQ_GAIN_7 +47 0x514F //RX_FDEQ_GAIN_8 +48 0x5555 //RX_FDEQ_GAIN_9 +49 0x5052 //RX_FDEQ_GAIN_10 +50 0x5453 //RX_FDEQ_GAIN_11 +51 0x514E //RX_FDEQ_GAIN_12 +52 0x4F59 //RX_FDEQ_GAIN_13 +53 0x6C76 //RX_FDEQ_GAIN_14 +54 0x787B //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0404 //RX_FDEQ_BIN_4 +68 0x0308 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +92 0x0120 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0014 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x6000 //RX_TDDRC_ALPHA_UP_1 +7 0x6000 //RX_TDDRC_ALPHA_UP_2 +8 0x6000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x7EB8 //RX_TDDRC_SLANT_0 +117 0x2500 //RX_TDDRC_SLANT_1 +118 0x6000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x032A //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x3B3B //RX_FDEQ_GAIN_1 +41 0x3942 //RX_FDEQ_GAIN_2 +42 0x4645 //RX_FDEQ_GAIN_3 +43 0x494A //RX_FDEQ_GAIN_4 +44 0x5D5A //RX_FDEQ_GAIN_5 +45 0x5B5B //RX_FDEQ_GAIN_6 +46 0x5A51 //RX_FDEQ_GAIN_7 +47 0x514F //RX_FDEQ_GAIN_8 +48 0x5555 //RX_FDEQ_GAIN_9 +49 0x5052 //RX_FDEQ_GAIN_10 +50 0x5453 //RX_FDEQ_GAIN_11 +51 0x514E //RX_FDEQ_GAIN_12 +52 0x4F59 //RX_FDEQ_GAIN_13 +53 0x6C76 //RX_FDEQ_GAIN_14 +54 0x787B //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0404 //RX_FDEQ_BIN_4 +68 0x0308 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +92 0x0120 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x001D //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x6000 //RX_TDDRC_ALPHA_UP_1 +7 0x6000 //RX_TDDRC_ALPHA_UP_2 +8 0x6000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x7EB8 //RX_TDDRC_SLANT_0 +117 0x2500 //RX_TDDRC_SLANT_1 +118 0x6000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x032A //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x3B3B //RX_FDEQ_GAIN_1 +41 0x3942 //RX_FDEQ_GAIN_2 +42 0x4645 //RX_FDEQ_GAIN_3 +43 0x494A //RX_FDEQ_GAIN_4 +44 0x5D5A //RX_FDEQ_GAIN_5 +45 0x5B5B //RX_FDEQ_GAIN_6 +46 0x5A51 //RX_FDEQ_GAIN_7 +47 0x514F //RX_FDEQ_GAIN_8 +48 0x5555 //RX_FDEQ_GAIN_9 +49 0x5052 //RX_FDEQ_GAIN_10 +50 0x5453 //RX_FDEQ_GAIN_11 +51 0x514E //RX_FDEQ_GAIN_12 +52 0x4F59 //RX_FDEQ_GAIN_13 +53 0x6C76 //RX_FDEQ_GAIN_14 +54 0x787B //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0404 //RX_FDEQ_BIN_4 +68 0x0308 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +92 0x0120 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0029 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x6000 //RX_TDDRC_ALPHA_UP_1 +7 0x6000 //RX_TDDRC_ALPHA_UP_2 +8 0x6000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x7EB8 //RX_TDDRC_SLANT_0 +117 0x2500 //RX_TDDRC_SLANT_1 +118 0x6000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x032A //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x3B3B //RX_FDEQ_GAIN_1 +41 0x3942 //RX_FDEQ_GAIN_2 +42 0x4645 //RX_FDEQ_GAIN_3 +43 0x494A //RX_FDEQ_GAIN_4 +44 0x5D5A //RX_FDEQ_GAIN_5 +45 0x5B5B //RX_FDEQ_GAIN_6 +46 0x5A51 //RX_FDEQ_GAIN_7 +47 0x514F //RX_FDEQ_GAIN_8 +48 0x5555 //RX_FDEQ_GAIN_9 +49 0x5052 //RX_FDEQ_GAIN_10 +50 0x5453 //RX_FDEQ_GAIN_11 +51 0x514E //RX_FDEQ_GAIN_12 +52 0x4F59 //RX_FDEQ_GAIN_13 +53 0x6C76 //RX_FDEQ_GAIN_14 +54 0x787B //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0404 //RX_FDEQ_BIN_4 +68 0x0308 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +92 0x0120 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0039 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x6000 //RX_TDDRC_ALPHA_UP_1 +7 0x6000 //RX_TDDRC_ALPHA_UP_2 +8 0x6000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x7EB8 //RX_TDDRC_SLANT_0 +117 0x2500 //RX_TDDRC_SLANT_1 +118 0x6000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x032A //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x3B3B //RX_FDEQ_GAIN_1 +41 0x3942 //RX_FDEQ_GAIN_2 +42 0x4645 //RX_FDEQ_GAIN_3 +43 0x494A //RX_FDEQ_GAIN_4 +44 0x5D5A //RX_FDEQ_GAIN_5 +45 0x5B5B //RX_FDEQ_GAIN_6 +46 0x5A51 //RX_FDEQ_GAIN_7 +47 0x514F //RX_FDEQ_GAIN_8 +48 0x5555 //RX_FDEQ_GAIN_9 +49 0x5052 //RX_FDEQ_GAIN_10 +50 0x5453 //RX_FDEQ_GAIN_11 +51 0x514E //RX_FDEQ_GAIN_12 +52 0x4F59 //RX_FDEQ_GAIN_13 +53 0x6C76 //RX_FDEQ_GAIN_14 +54 0x787B //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0404 //RX_FDEQ_BIN_4 +68 0x0308 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +92 0x0120 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x005F //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x6000 //RX_TDDRC_ALPHA_UP_1 +7 0x6000 //RX_TDDRC_ALPHA_UP_2 +8 0x6000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x7EB8 //RX_TDDRC_SLANT_0 +117 0x2500 //RX_TDDRC_SLANT_1 +118 0x6000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x032A //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x3B3B //RX_FDEQ_GAIN_1 +41 0x3942 //RX_FDEQ_GAIN_2 +42 0x4645 //RX_FDEQ_GAIN_3 +43 0x494A //RX_FDEQ_GAIN_4 +44 0x5D5A //RX_FDEQ_GAIN_5 +45 0x5B5B //RX_FDEQ_GAIN_6 +46 0x5A51 //RX_FDEQ_GAIN_7 +47 0x514F //RX_FDEQ_GAIN_8 +48 0x5555 //RX_FDEQ_GAIN_9 +49 0x5052 //RX_FDEQ_GAIN_10 +50 0x5453 //RX_FDEQ_GAIN_11 +51 0x514E //RX_FDEQ_GAIN_12 +52 0x4F59 //RX_FDEQ_GAIN_13 +53 0x6C76 //RX_FDEQ_GAIN_14 +54 0x787B //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0404 //RX_FDEQ_BIN_4 +68 0x0308 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +92 0x0120 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x008E //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x6000 //RX_TDDRC_ALPHA_UP_1 +7 0x6000 //RX_TDDRC_ALPHA_UP_2 +8 0x6000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x7EB8 //RX_TDDRC_SLANT_0 +117 0x2500 //RX_TDDRC_SLANT_1 +118 0x6000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x032A //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x3B3B //RX_FDEQ_GAIN_1 +41 0x3942 //RX_FDEQ_GAIN_2 +42 0x4645 //RX_FDEQ_GAIN_3 +43 0x494A //RX_FDEQ_GAIN_4 +44 0x5D5A //RX_FDEQ_GAIN_5 +45 0x5B5B //RX_FDEQ_GAIN_6 +46 0x5A51 //RX_FDEQ_GAIN_7 +47 0x514F //RX_FDEQ_GAIN_8 +48 0x5555 //RX_FDEQ_GAIN_9 +49 0x5052 //RX_FDEQ_GAIN_10 +50 0x5453 //RX_FDEQ_GAIN_11 +51 0x514E //RX_FDEQ_GAIN_12 +52 0x4F59 //RX_FDEQ_GAIN_13 +53 0x6C76 //RX_FDEQ_GAIN_14 +54 0x787B //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0404 //RX_FDEQ_BIN_4 +68 0x0308 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +92 0x0120 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x027C //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0003 //RX_SAMPLINGFREQ_SIG +160 0x0003 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x6000 //RX_TDDRC_ALPHA_UP_1 +164 0x6000 //RX_TDDRC_ALPHA_UP_2 +165 0x6000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7652 //RX_A_HP +169 0x4000 //RX_B_PE +170 0x7800 //RX_THR_PITCH_DET_0 +171 0x7000 //RX_THR_PITCH_DET_1 +172 0x6000 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0400 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x0010 //RX_NS_LVL_CTRL +180 0xF800 //RX_THR_SN_EST +181 0x7E00 //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4850 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4860 //RX_FDEQ_GAIN_8 +205 0x7468 //RX_FDEQ_GAIN_9 +206 0x6060 //RX_FDEQ_GAIN_10 +207 0x6060 //RX_FDEQ_GAIN_11 +208 0x5C54 //RX_FDEQ_GAIN_12 +209 0x5450 //RX_FDEQ_GAIN_13 +210 0x5050 //RX_FDEQ_GAIN_14 +211 0x5860 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0404 //RX_FDEQ_BIN_4 +225 0x0308 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +249 0x0120 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0002 //RX_FILTINDX +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x7EB8 //RX_TDDRC_SLANT_0 +274 0x2500 //RX_TDDRC_SLANT_1 +275 0x6000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0550 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x2000 //RX_MIN_G_FP +285 0x0080 //RX_MAX_G_FP +286 0x0014 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x6000 //RX_TDDRC_ALPHA_UP_1 +164 0x6000 //RX_TDDRC_ALPHA_UP_2 +165 0x6000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x7EB8 //RX_TDDRC_SLANT_0 +274 0x2500 //RX_TDDRC_SLANT_1 +275 0x6000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0550 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4850 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4860 //RX_FDEQ_GAIN_8 +205 0x7468 //RX_FDEQ_GAIN_9 +206 0x6060 //RX_FDEQ_GAIN_10 +207 0x6060 //RX_FDEQ_GAIN_11 +208 0x5C54 //RX_FDEQ_GAIN_12 +209 0x5450 //RX_FDEQ_GAIN_13 +210 0x5050 //RX_FDEQ_GAIN_14 +211 0x5860 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0404 //RX_FDEQ_BIN_4 +225 0x0308 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +249 0x0120 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0014 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x6000 //RX_TDDRC_ALPHA_UP_1 +164 0x6000 //RX_TDDRC_ALPHA_UP_2 +165 0x6000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x7EB8 //RX_TDDRC_SLANT_0 +274 0x2500 //RX_TDDRC_SLANT_1 +275 0x6000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0550 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4850 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4860 //RX_FDEQ_GAIN_8 +205 0x7468 //RX_FDEQ_GAIN_9 +206 0x6060 //RX_FDEQ_GAIN_10 +207 0x6060 //RX_FDEQ_GAIN_11 +208 0x5C54 //RX_FDEQ_GAIN_12 +209 0x5450 //RX_FDEQ_GAIN_13 +210 0x5050 //RX_FDEQ_GAIN_14 +211 0x5860 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0404 //RX_FDEQ_BIN_4 +225 0x0308 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +249 0x0120 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x001D //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x6000 //RX_TDDRC_ALPHA_UP_1 +164 0x6000 //RX_TDDRC_ALPHA_UP_2 +165 0x6000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x7EB8 //RX_TDDRC_SLANT_0 +274 0x2500 //RX_TDDRC_SLANT_1 +275 0x6000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0550 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4850 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4860 //RX_FDEQ_GAIN_8 +205 0x7468 //RX_FDEQ_GAIN_9 +206 0x6060 //RX_FDEQ_GAIN_10 +207 0x6060 //RX_FDEQ_GAIN_11 +208 0x5C54 //RX_FDEQ_GAIN_12 +209 0x5450 //RX_FDEQ_GAIN_13 +210 0x5050 //RX_FDEQ_GAIN_14 +211 0x5860 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0404 //RX_FDEQ_BIN_4 +225 0x0308 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +249 0x0120 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0029 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x6000 //RX_TDDRC_ALPHA_UP_1 +164 0x6000 //RX_TDDRC_ALPHA_UP_2 +165 0x6000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x7EB8 //RX_TDDRC_SLANT_0 +274 0x2500 //RX_TDDRC_SLANT_1 +275 0x6000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0550 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4850 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4860 //RX_FDEQ_GAIN_8 +205 0x7468 //RX_FDEQ_GAIN_9 +206 0x6060 //RX_FDEQ_GAIN_10 +207 0x6060 //RX_FDEQ_GAIN_11 +208 0x5C54 //RX_FDEQ_GAIN_12 +209 0x5450 //RX_FDEQ_GAIN_13 +210 0x5050 //RX_FDEQ_GAIN_14 +211 0x5860 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0404 //RX_FDEQ_BIN_4 +225 0x0308 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +249 0x0120 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0039 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x6000 //RX_TDDRC_ALPHA_UP_1 +164 0x6000 //RX_TDDRC_ALPHA_UP_2 +165 0x6000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x7EB8 //RX_TDDRC_SLANT_0 +274 0x2500 //RX_TDDRC_SLANT_1 +275 0x6000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0550 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x5454 //RX_FDEQ_GAIN_4 +201 0x7C54 //RX_FDEQ_GAIN_5 +202 0x4850 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4860 //RX_FDEQ_GAIN_8 +205 0x7468 //RX_FDEQ_GAIN_9 +206 0x6060 //RX_FDEQ_GAIN_10 +207 0x6060 //RX_FDEQ_GAIN_11 +208 0x5C54 //RX_FDEQ_GAIN_12 +209 0x5450 //RX_FDEQ_GAIN_13 +210 0x5050 //RX_FDEQ_GAIN_14 +211 0x5860 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0404 //RX_FDEQ_BIN_4 +225 0x0308 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +249 0x0120 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x005F //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x6000 //RX_TDDRC_ALPHA_UP_1 +164 0x6000 //RX_TDDRC_ALPHA_UP_2 +165 0x6000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x7EB8 //RX_TDDRC_SLANT_0 +274 0x2500 //RX_TDDRC_SLANT_1 +275 0x6000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0550 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x5454 //RX_FDEQ_GAIN_4 +201 0x7C54 //RX_FDEQ_GAIN_5 +202 0x4850 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4860 //RX_FDEQ_GAIN_8 +205 0x7468 //RX_FDEQ_GAIN_9 +206 0x6060 //RX_FDEQ_GAIN_10 +207 0x6060 //RX_FDEQ_GAIN_11 +208 0x5C54 //RX_FDEQ_GAIN_12 +209 0x5450 //RX_FDEQ_GAIN_13 +210 0x5050 //RX_FDEQ_GAIN_14 +211 0x5860 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0404 //RX_FDEQ_BIN_4 +225 0x0308 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +249 0x0120 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x008E //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x6000 //RX_TDDRC_ALPHA_UP_1 +164 0x6000 //RX_TDDRC_ALPHA_UP_2 +165 0x6000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x7EB8 //RX_TDDRC_SLANT_0 +274 0x2500 //RX_TDDRC_SLANT_1 +275 0x6000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0550 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x5454 //RX_FDEQ_GAIN_4 +201 0x7C54 //RX_FDEQ_GAIN_5 +202 0x4850 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4860 //RX_FDEQ_GAIN_8 +205 0x7468 //RX_FDEQ_GAIN_9 +206 0x6060 //RX_FDEQ_GAIN_10 +207 0x6060 //RX_FDEQ_GAIN_11 +208 0x5C54 //RX_FDEQ_GAIN_12 +209 0x5450 //RX_FDEQ_GAIN_13 +210 0x5050 //RX_FDEQ_GAIN_14 +211 0x5860 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0404 //RX_FDEQ_BIN_4 +225 0x0308 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +249 0x0120 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME HANDSFREE-HANDFREE-VOICE_GENERIC-FB +#PARAM_MODE FULL +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0001 //TX_OPERATION_MODE_0 +1 0x0001 //TX_OPERATION_MODE_1 +2 0x0033 //TX_PATCH_REG +3 0x4B7C //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0003 //TX_NUM_MIC +6 0x0004 //TX_SAMPLINGFREQ_SIG +7 0x0004 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009D //TX_DIST2REF1 +22 0x0010 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0A19 //TX_PGA_0 +28 0x0A19 //TX_PGA_1 +29 0x0A19 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0001 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0002 //TX_MIC_DATA_SRC0 +42 0x0000 //TX_MIC_DATA_SRC1 +43 0x0001 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3B33 //TX_DIST2REF_11 +73 0x0A70 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0800 //TX_MIC_REFBLK_VOLUME +108 0x0CAE //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0015 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7E56 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x1800 //TX_THR_PITCH_DET_0 +131 0x1000 //TX_THR_PITCH_DET_1 +132 0x0800 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x0028 //TX_TAIL_LENGTH +147 0x0300 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x7A00 //TX_EAD_THR +151 0x1000 //TX_THR_RE_EST +152 0x0800 //TX_MIN_EQ_RE_EST_0 +153 0x2000 //TX_MIN_EQ_RE_EST_1 +154 0x2000 //TX_MIN_EQ_RE_EST_2 +155 0x4000 //TX_MIN_EQ_RE_EST_3 +156 0x4000 //TX_MIN_EQ_RE_EST_4 +157 0x7FFF //TX_MIN_EQ_RE_EST_5 +158 0x7FFF //TX_MIN_EQ_RE_EST_6 +159 0x7FFF //TX_MIN_EQ_RE_EST_7 +160 0x7FFF //TX_MIN_EQ_RE_EST_8 +161 0x7FFF //TX_MIN_EQ_RE_EST_9 +162 0x7FFF //TX_MIN_EQ_RE_EST_10 +163 0x7FFF //TX_MIN_EQ_RE_EST_11 +164 0x7FFF //TX_MIN_EQ_RE_EST_12 +165 0x4000 //TX_LAMBDA_RE_EST +166 0x0CCD //TX_LAMBDA_CB_NLE +167 0x2000 //TX_C_POST_FLT +168 0x7FFF //TX_GAIN_NP +169 0x0180 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x09C4 //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x7D00 //TX_DTD_THR1_0 +198 0x7FF0 //TX_DTD_THR1_1 +199 0x7FF0 //TX_DTD_THR1_2 +200 0x7FF0 //TX_DTD_THR1_3 +201 0x7FF0 //TX_DTD_THR1_4 +202 0x7FF0 //TX_DTD_THR1_5 +203 0x7FF0 //TX_DTD_THR1_6 +204 0x0CCD //TX_DTD_THR2_0 +205 0x0CCD //TX_DTD_THR2_1 +206 0x0CCD //TX_DTD_THR2_2 +207 0x0CCD //TX_DTD_THR2_3 +208 0x0CCD //TX_DTD_THR2_4 +209 0x0CCD //TX_DTD_THR2_5 +210 0x0CCD //TX_DTD_THR2_6 +211 0x7FFF //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x0DAC //TX_DT_CUT_K +214 0x0020 //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x7FFF //TX_DTD_MIC_BLK +221 0x023E //TX_ADPT_STRICT_L +222 0x023E //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x2000 //TX_B_POST_FILT_ECHO_L +229 0x2000 //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x1000 //TX_B_LESSCUT_RTO_ECHO +232 0x0063 //TX_EPD_OFFSET_00 +233 0x0000 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x0000 //TX_DTD_THR1_7 +238 0x0000 //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xF800 //TX_THR_SN_EST_0 +243 0xFA00 //TX_THR_SN_EST_1 +244 0xFA00 //TX_THR_SN_EST_2 +245 0xFB00 //TX_THR_SN_EST_3 +246 0xFA00 //TX_THR_SN_EST_4 +247 0xFA00 //TX_THR_SN_EST_5 +248 0xF800 //TX_THR_SN_EST_6 +249 0xF800 //TX_THR_SN_EST_7 +250 0x0100 //TX_DELTA_THR_SN_EST_0 +251 0x0100 //TX_DELTA_THR_SN_EST_1 +252 0x0200 //TX_DELTA_THR_SN_EST_2 +253 0x0100 //TX_DELTA_THR_SN_EST_3 +254 0x0100 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0200 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x4000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x4000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x2000 //TX_B_POST_FLT_0 +280 0x1000 //TX_B_POST_FLT_1 +281 0x0010 //TX_NS_LVL_CTRL_0 +282 0x0014 //TX_NS_LVL_CTRL_1 +283 0x0018 //TX_NS_LVL_CTRL_2 +284 0x0016 //TX_NS_LVL_CTRL_3 +285 0x0014 //TX_NS_LVL_CTRL_4 +286 0x0011 //TX_NS_LVL_CTRL_5 +287 0x0014 //TX_NS_LVL_CTRL_6 +288 0x0011 //TX_NS_LVL_CTRL_7 +289 0x000F //TX_MIN_GAIN_S_0 +290 0x0010 //TX_MIN_GAIN_S_1 +291 0x0010 //TX_MIN_GAIN_S_2 +292 0x0010 //TX_MIN_GAIN_S_3 +293 0x0010 //TX_MIN_GAIN_S_4 +294 0x0010 //TX_MIN_GAIN_S_5 +295 0x0010 //TX_MIN_GAIN_S_6 +296 0x000F //TX_MIN_GAIN_S_7 +297 0x6000 //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x4000 //TX_SNRI_SUP_1 +302 0x4000 //TX_SNRI_SUP_2 +303 0x4000 //TX_SNRI_SUP_3 +304 0x4000 //TX_SNRI_SUP_4 +305 0x50C0 //TX_SNRI_SUP_5 +306 0x4000 //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x0018 //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x5000 //TX_A_POST_FILT_S_0 +315 0x4C00 //TX_A_POST_FILT_S_1 +316 0x4000 //TX_A_POST_FILT_S_2 +317 0x6000 //TX_A_POST_FILT_S_3 +318 0x4000 //TX_A_POST_FILT_S_4 +319 0x5000 //TX_A_POST_FILT_S_5 +320 0x6000 //TX_A_POST_FILT_S_6 +321 0x7000 //TX_A_POST_FILT_S_7 +322 0x2000 //TX_B_POST_FILT_0 +323 0x2000 //TX_B_POST_FILT_1 +324 0x2000 //TX_B_POST_FILT_2 +325 0x4000 //TX_B_POST_FILT_3 +326 0x4000 //TX_B_POST_FILT_4 +327 0x1000 //TX_B_POST_FILT_5 +328 0x1000 //TX_B_POST_FILT_6 +329 0x2000 //TX_B_POST_FILT_7 +330 0x4000 //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x6000 //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7C00 //TX_LAMBDA_PFILT +339 0x7C00 //TX_LAMBDA_PFILT_S_0 +340 0x7C00 //TX_LAMBDA_PFILT_S_1 +341 0x7A00 //TX_LAMBDA_PFILT_S_2 +342 0x7C00 //TX_LAMBDA_PFILT_S_3 +343 0x7C00 //TX_LAMBDA_PFILT_S_4 +344 0x7C00 //TX_LAMBDA_PFILT_S_5 +345 0x7C00 //TX_LAMBDA_PFILT_S_6 +346 0x7C00 //TX_LAMBDA_PFILT_S_7 +347 0x0000 //TX_K_PEPPER +348 0x0800 //TX_A_PEPPER +349 0x1EAA //TX_K_PEPPER_HF +350 0x0600 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0200 //TX_DT_BINVAD_TH_0 +354 0x0200 //TX_DT_BINVAD_TH_1 +355 0x0200 //TX_DT_BINVAD_TH_2 +356 0x0200 //TX_DT_BINVAD_TH_3 +357 0x1F40 //TX_DT_BINVAD_ENDF +358 0x0100 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0064 //TX_NDETCT +367 0x0050 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x07D0 //TX_NOISE_TH_1 +371 0x0DAC //TX_NOISE_TH_2 +372 0x4E20 //TX_NOISE_TH_3 +373 0x4E20 //TX_NOISE_TH_4 +374 0x59D8 //TX_NOISE_TH_5 +375 0x7FFF //TX_NOISE_TH_5_2 +376 0x0000 //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x2710 //TX_NOISE_TH_6 +379 0x0033 //TX_MINENOISE_TH +380 0xD508 //TX_MORENS_TFMASK_TH +381 0x0001 //TX_DRC_QUIET_FLOOR +382 0x7999 //TX_RATIODTL_CUT_TH +383 0x0119 //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x0333 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x7FFF //TX_POST_MASK_SUP_HSNE +392 0x1388 //TX_TAIL_DET_TH +393 0x4000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0080 //TX_SUPHIGH_TH +396 0x0000 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x1800 //TX_C_POST_FLT_MASK +399 0x4000 //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0002 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x0033 //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x7FFF //TX_MIN_G_CTRL_SSNS +409 0x0000 //TX_METAL_RTO_THR +410 0x4848 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x4000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x0230 //TX_NOR_OFF_THR +498 0x0CCD //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x2000 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0x4650 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x7FFF //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0x3000 //TX_DEREVERB_LF_MU +515 0x34CD //TX_DEREVERB_HF_MU +516 0x0007 //TX_DEREVERB_DELAY +517 0x0004 //TX_DEREVERB_COEF_LEN +518 0x0003 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x3A98 //TX_GSC_RTOL_TH +522 0x3A98 //TX_GSC_RTOH_TH +523 0x7E2C //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0020 //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x5048 //TX_FDEQ_GAIN_5 +573 0x4848 //TX_FDEQ_GAIN_6 +574 0x4848 //TX_FDEQ_GAIN_7 +575 0x4848 //TX_FDEQ_GAIN_8 +576 0x4848 //TX_FDEQ_GAIN_9 +577 0x5B5B //TX_FDEQ_GAIN_10 +578 0x737B //TX_FDEQ_GAIN_11 +579 0x7B9A //TX_FDEQ_GAIN_12 +580 0x9AC4 //TX_FDEQ_GAIN_13 +581 0xC4C4 //TX_FDEQ_GAIN_14 +582 0xC4C4 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0304 //TX_FDEQ_BIN_2 +594 0x0405 //TX_FDEQ_BIN_3 +595 0x0607 //TX_FDEQ_BIN_4 +596 0x0809 //TX_FDEQ_BIN_5 +597 0x0A0B //TX_FDEQ_BIN_6 +598 0x0C0D //TX_FDEQ_BIN_7 +599 0x0E0F //TX_FDEQ_BIN_8 +600 0x1011 //TX_FDEQ_BIN_9 +601 0x1214 //TX_FDEQ_BIN_10 +602 0x1618 //TX_FDEQ_BIN_11 +603 0x1C1C //TX_FDEQ_BIN_12 +604 0x2020 //TX_FDEQ_BIN_13 +605 0x2020 //TX_FDEQ_BIN_14 +606 0x2011 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0030 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4849 //TX_PREEQ_GAIN_MIC0_6 +624 0x4A4B //TX_PREEQ_GAIN_MIC0_7 +625 0x4C4B //TX_PREEQ_GAIN_MIC0_8 +626 0x4A48 //TX_PREEQ_GAIN_MIC0_9 +627 0x4B4C //TX_PREEQ_GAIN_MIC0_10 +628 0x4C4B //TX_PREEQ_GAIN_MIC0_11 +629 0x4838 //TX_PREEQ_GAIN_MIC0_12 +630 0x3858 //TX_PREEQ_GAIN_MIC0_13 +631 0x7060 //TX_PREEQ_GAIN_MIC0_14 +632 0x9870 //TX_PREEQ_GAIN_MIC0_15 +633 0x5848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0202 //TX_PREEQ_BIN_MIC0_0 +642 0x0203 //TX_PREEQ_BIN_MIC0_1 +643 0x0303 //TX_PREEQ_BIN_MIC0_2 +644 0x0304 //TX_PREEQ_BIN_MIC0_3 +645 0x0405 //TX_PREEQ_BIN_MIC0_4 +646 0x0506 //TX_PREEQ_BIN_MIC0_5 +647 0x0808 //TX_PREEQ_BIN_MIC0_6 +648 0x0809 //TX_PREEQ_BIN_MIC0_7 +649 0x0A0A //TX_PREEQ_BIN_MIC0_8 +650 0x0C10 //TX_PREEQ_BIN_MIC0_9 +651 0x1013 //TX_PREEQ_BIN_MIC0_10 +652 0x1414 //TX_PREEQ_BIN_MIC0_11 +653 0x261E //TX_PREEQ_BIN_MIC0_12 +654 0x1E14 //TX_PREEQ_BIN_MIC0_13 +655 0x1414 //TX_PREEQ_BIN_MIC0_14 +656 0x2814 //TX_PREEQ_BIN_MIC0_15 +657 0x4000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0030 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4645 //TX_PREEQ_GAIN_MIC1_6 +673 0x4442 //TX_PREEQ_GAIN_MIC1_7 +674 0x4140 //TX_PREEQ_GAIN_MIC1_8 +675 0x3E3D //TX_PREEQ_GAIN_MIC1_9 +676 0x3C3C //TX_PREEQ_GAIN_MIC1_10 +677 0x3C3C //TX_PREEQ_GAIN_MIC1_11 +678 0x3938 //TX_PREEQ_GAIN_MIC1_12 +679 0x3A3C //TX_PREEQ_GAIN_MIC1_13 +680 0x3C3E //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0202 //TX_PREEQ_BIN_MIC1_0 +691 0x0203 //TX_PREEQ_BIN_MIC1_1 +692 0x0303 //TX_PREEQ_BIN_MIC1_2 +693 0x0304 //TX_PREEQ_BIN_MIC1_3 +694 0x0405 //TX_PREEQ_BIN_MIC1_4 +695 0x0506 //TX_PREEQ_BIN_MIC1_5 +696 0x0808 //TX_PREEQ_BIN_MIC1_6 +697 0x0809 //TX_PREEQ_BIN_MIC1_7 +698 0x0A0A //TX_PREEQ_BIN_MIC1_8 +699 0x0C10 //TX_PREEQ_BIN_MIC1_9 +700 0x1013 //TX_PREEQ_BIN_MIC1_10 +701 0x1414 //TX_PREEQ_BIN_MIC1_11 +702 0x261E //TX_PREEQ_BIN_MIC1_12 +703 0x1E14 //TX_PREEQ_BIN_MIC1_13 +704 0x1414 //TX_PREEQ_BIN_MIC1_14 +705 0x2814 //TX_PREEQ_BIN_MIC1_15 +706 0x4000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0E10 //TX_PREEQ_BIN_MIC2_0 +740 0x1010 //TX_PREEQ_BIN_MIC2_1 +741 0x1010 //TX_PREEQ_BIN_MIC2_2 +742 0x1010 //TX_PREEQ_BIN_MIC2_3 +743 0x1010 //TX_PREEQ_BIN_MIC2_4 +744 0x1010 //TX_PREEQ_BIN_MIC2_5 +745 0x1010 //TX_PREEQ_BIN_MIC2_6 +746 0x1010 //TX_PREEQ_BIN_MIC2_7 +747 0x1010 //TX_PREEQ_BIN_MIC2_8 +748 0x1010 //TX_PREEQ_BIN_MIC2_9 +749 0x1010 //TX_PREEQ_BIN_MIC2_10 +750 0x1010 //TX_PREEQ_BIN_MIC2_11 +751 0x1010 //TX_PREEQ_BIN_MIC2_12 +752 0x1010 //TX_PREEQ_BIN_MIC2_13 +753 0x1010 //TX_PREEQ_BIN_MIC2_14 +754 0x0200 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x2000 //TX_NND_WEIGHT +765 0x0060 //TX_MIC_CALIBRATION_0 +766 0x0060 //TX_MIC_CALIBRATION_1 +767 0x0070 //TX_MIC_CALIBRATION_2 +768 0x0070 //TX_MIC_CALIBRATION_3 +769 0x0050 //TX_MIC_PWR_BIAS_0 +770 0x0040 //TX_MIC_PWR_BIAS_1 +771 0x0040 //TX_MIC_PWR_BIAS_2 +772 0x0040 //TX_MIC_PWR_BIAS_3 +773 0x0009 //TX_GAIN_LIMIT_0 +774 0x000F //TX_GAIN_LIMIT_1 +775 0x000F //TX_GAIN_LIMIT_2 +776 0x000F //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x0C00 //TX_TDDRC_ALPHA_UP_01 +784 0x0C00 //TX_TDDRC_ALPHA_UP_02 +785 0x0C00 //TX_TDDRC_ALPHA_UP_03 +786 0x0C00 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x7FFF //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0010 //TX_DEADMIC_SILENCE_TH +817 0x0600 //TX_MIC_DEGRADE_TH +818 0x0078 //TX_DEADMIC_CNT +819 0x0078 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x4848 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0096 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0004 //TX_FILTINDX +854 0x0004 //TX_TDDRC_THRD_0 +855 0x0016 //TX_TDDRC_THRD_1 +856 0x1900 //TX_TDDRC_THRD_2 +857 0x1900 //TX_TDDRC_THRD_3 +858 0x3000 //TX_TDDRC_SLANT_0 +859 0x7B00 //TX_TDDRC_SLANT_1 +860 0x0C00 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x0FDA //TX_TDDRC_DRC_GAIN +867 0x7FFF //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x0028 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x1000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x2339 //TX_SENDFUNC_REG_MICMUTE +898 0x0021 //TX_SENDFUNC_REG_MICMUTE1 +899 0x02BC //TX_MICMUTE_RATIO_THR +900 0x0140 //TX_MICMUTE_AMP_THR +901 0x0004 //TX_MICMUTE_HPF_IND +902 0x00C0 //TX_MICMUTE_LOG_EYR_TH +903 0x0008 //TX_MICMUTE_CVG_TIME +904 0x0008 //TX_MICMUTE_RELEASE_TIME +905 0x01FE //TX_MIC_VOLUME_MIC0MUTE +906 0x0020 //TX_MICMUTE_EPD_OFFSET_0 +907 0x001E //TX_MICMUTE_FRQ_AEC_L +908 0x7999 //TX_MICMUTE_EAD_THR +909 0x7FFF //TX_MICMUTE_LAMBDA_CB_NLE +910 0x7FFF //TX_MICMUTE_LAMBDA_RE_EST +911 0x4000 //TX_DTD_THR1_MICMUTE_0 +912 0x7000 //TX_DTD_THR1_MICMUTE_1 +913 0x7FFF //TX_DTD_THR1_MICMUTE_2 +914 0x7FFF //TX_DTD_THR1_MICMUTE_3 +915 0x6CCC //TX_DTD_THR2_MICMUTE_0 +916 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x1000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x4000 //TX_MICMUTE_C_POST_FLT +922 0x03E8 //TX_MICMUTE_DT_CUT_K +923 0x0001 //TX_MICMUTE_DT_CUT_THR +924 0x03E8 //TX_MICMUTE_DT_CUT_K2 +925 0x0001 //TX_MICMUTE_DT_CUT_THR2 +926 0x0064 //TX_MICMUTE_DT2_HOLD_N +927 0x1000 //TX_MICMUTE_RATIODTH_THCUT +928 0x1000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x7FFF //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0400 //TX_MICMUTE_C_POST_FLT_MASK +931 0x7999 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0258 //TX_MICMUTE_DT_CUT_K1 +933 0x0800 //TX_MICMUTE_N2_SN_EST +934 0xFC00 //TX_MICMUTE_THR_SN_EST_0 +935 0x001C //TX_MICMUTE_MIN_G_CTRL_0 +936 0x6000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x7000 //TX_MICMUTE_B_POST_FILT_0 +938 0x2710 //TX_MIC1RUB_AMP_THR +939 0x0010 //TX_MIC1MUTE_RATIO_THR +940 0x0450 //TX_MIC1MUTE_AMP_THR +941 0x0008 //TX_MIC1MUTE_CVG_TIME +942 0x0008 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x006C //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0004 //RX_SAMPLINGFREQ_SIG +3 0x0004 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x4000 //RX_TDDRC_ALPHA_UP_1 +7 0x4000 //RX_TDDRC_ALPHA_UP_2 +8 0x4000 //RX_TDDRC_ALPHA_UP_3 +9 0x4000 //RX_TDDRC_ALPHA_UP_4 +10 0x065B //RX_PGA +11 0x7E56 //RX_A_HP +12 0x4000 //RX_B_PE +13 0x7800 //RX_THR_PITCH_DET_0 +14 0x7000 //RX_THR_PITCH_DET_1 +15 0x6000 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0400 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x0014 //RX_NS_LVL_CTRL +23 0xF400 //RX_THR_SN_EST +24 0x7E00 //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4870 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4850 //RX_FDEQ_GAIN_6 +46 0x485C //RX_FDEQ_GAIN_7 +47 0x5C60 //RX_FDEQ_GAIN_8 +48 0x685C //RX_FDEQ_GAIN_9 +49 0x5640 //RX_FDEQ_GAIN_10 +50 0x4040 //RX_FDEQ_GAIN_11 +51 0x5C58 //RX_FDEQ_GAIN_12 +52 0x5C60 //RX_FDEQ_GAIN_13 +53 0x6060 //RX_FDEQ_GAIN_14 +54 0x6060 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0402 //RX_FDEQ_BIN_3 +67 0x0504 //RX_FDEQ_BIN_4 +68 0x0209 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0002 //RX_FILTINDX +112 0x0001 //RX_TDDRC_THRD_0 +113 0x0002 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x6000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x4000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x03C3 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x2000 //RX_MIN_G_FP +128 0x0080 //RX_MAX_G_FP +129 0x0012 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x4000 //RX_TDDRC_ALPHA_UP_1 +7 0x4000 //RX_TDDRC_ALPHA_UP_2 +8 0x4000 //RX_TDDRC_ALPHA_UP_3 +9 0x4000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0001 //RX_TDDRC_THRD_0 +113 0x0002 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x6000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x4000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x03C3 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4870 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4850 //RX_FDEQ_GAIN_6 +46 0x485C //RX_FDEQ_GAIN_7 +47 0x5C60 //RX_FDEQ_GAIN_8 +48 0x685C //RX_FDEQ_GAIN_9 +49 0x5640 //RX_FDEQ_GAIN_10 +50 0x4040 //RX_FDEQ_GAIN_11 +51 0x5C58 //RX_FDEQ_GAIN_12 +52 0x5C60 //RX_FDEQ_GAIN_13 +53 0x6060 //RX_FDEQ_GAIN_14 +54 0x6060 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0402 //RX_FDEQ_BIN_3 +67 0x0504 //RX_FDEQ_BIN_4 +68 0x0209 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0012 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x4000 //RX_TDDRC_ALPHA_UP_1 +7 0x4000 //RX_TDDRC_ALPHA_UP_2 +8 0x4000 //RX_TDDRC_ALPHA_UP_3 +9 0x4000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0001 //RX_TDDRC_THRD_0 +113 0x0002 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x6000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x4000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x03C3 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4870 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4850 //RX_FDEQ_GAIN_6 +46 0x485C //RX_FDEQ_GAIN_7 +47 0x5C60 //RX_FDEQ_GAIN_8 +48 0x685C //RX_FDEQ_GAIN_9 +49 0x5640 //RX_FDEQ_GAIN_10 +50 0x4040 //RX_FDEQ_GAIN_11 +51 0x5C58 //RX_FDEQ_GAIN_12 +52 0x5C60 //RX_FDEQ_GAIN_13 +53 0x6060 //RX_FDEQ_GAIN_14 +54 0x6060 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0402 //RX_FDEQ_BIN_3 +67 0x0504 //RX_FDEQ_BIN_4 +68 0x0209 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x001A //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x4000 //RX_TDDRC_ALPHA_UP_1 +7 0x4000 //RX_TDDRC_ALPHA_UP_2 +8 0x4000 //RX_TDDRC_ALPHA_UP_3 +9 0x4000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0001 //RX_TDDRC_THRD_0 +113 0x0002 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x6000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x4000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x03C3 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4870 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4850 //RX_FDEQ_GAIN_6 +46 0x485C //RX_FDEQ_GAIN_7 +47 0x5C60 //RX_FDEQ_GAIN_8 +48 0x685C //RX_FDEQ_GAIN_9 +49 0x5640 //RX_FDEQ_GAIN_10 +50 0x4040 //RX_FDEQ_GAIN_11 +51 0x5C58 //RX_FDEQ_GAIN_12 +52 0x5C60 //RX_FDEQ_GAIN_13 +53 0x6060 //RX_FDEQ_GAIN_14 +54 0x6060 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0402 //RX_FDEQ_BIN_3 +67 0x0504 //RX_FDEQ_BIN_4 +68 0x0209 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0025 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x4000 //RX_TDDRC_ALPHA_UP_1 +7 0x4000 //RX_TDDRC_ALPHA_UP_2 +8 0x4000 //RX_TDDRC_ALPHA_UP_3 +9 0x4000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0001 //RX_TDDRC_THRD_0 +113 0x0002 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x6000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x4000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x03C3 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4870 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4850 //RX_FDEQ_GAIN_6 +46 0x485C //RX_FDEQ_GAIN_7 +47 0x5C60 //RX_FDEQ_GAIN_8 +48 0x685C //RX_FDEQ_GAIN_9 +49 0x5640 //RX_FDEQ_GAIN_10 +50 0x4040 //RX_FDEQ_GAIN_11 +51 0x5C58 //RX_FDEQ_GAIN_12 +52 0x5C60 //RX_FDEQ_GAIN_13 +53 0x6060 //RX_FDEQ_GAIN_14 +54 0x6060 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0402 //RX_FDEQ_BIN_3 +67 0x0504 //RX_FDEQ_BIN_4 +68 0x0209 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0034 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x4000 //RX_TDDRC_ALPHA_UP_1 +7 0x4000 //RX_TDDRC_ALPHA_UP_2 +8 0x4000 //RX_TDDRC_ALPHA_UP_3 +9 0x4000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0001 //RX_TDDRC_THRD_0 +113 0x0002 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x6000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x4000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x03C3 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4870 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4850 //RX_FDEQ_GAIN_6 +46 0x485C //RX_FDEQ_GAIN_7 +47 0x5C60 //RX_FDEQ_GAIN_8 +48 0x685C //RX_FDEQ_GAIN_9 +49 0x5640 //RX_FDEQ_GAIN_10 +50 0x4040 //RX_FDEQ_GAIN_11 +51 0x5C58 //RX_FDEQ_GAIN_12 +52 0x5C60 //RX_FDEQ_GAIN_13 +53 0x6060 //RX_FDEQ_GAIN_14 +54 0x6060 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0402 //RX_FDEQ_BIN_3 +67 0x0504 //RX_FDEQ_BIN_4 +68 0x0209 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x004D //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x4000 //RX_TDDRC_ALPHA_UP_1 +7 0x4000 //RX_TDDRC_ALPHA_UP_2 +8 0x4000 //RX_TDDRC_ALPHA_UP_3 +9 0x4000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0001 //RX_TDDRC_THRD_0 +113 0x0002 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x6000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x4000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x03C3 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4870 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4850 //RX_FDEQ_GAIN_6 +46 0x485C //RX_FDEQ_GAIN_7 +47 0x5C60 //RX_FDEQ_GAIN_8 +48 0x685C //RX_FDEQ_GAIN_9 +49 0x5640 //RX_FDEQ_GAIN_10 +50 0x4040 //RX_FDEQ_GAIN_11 +51 0x5C58 //RX_FDEQ_GAIN_12 +52 0x5C60 //RX_FDEQ_GAIN_13 +53 0x6060 //RX_FDEQ_GAIN_14 +54 0x6060 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0402 //RX_FDEQ_BIN_3 +67 0x0504 //RX_FDEQ_BIN_4 +68 0x0209 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0074 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x4000 //RX_TDDRC_ALPHA_UP_1 +7 0x4000 //RX_TDDRC_ALPHA_UP_2 +8 0x4000 //RX_TDDRC_ALPHA_UP_3 +9 0x4000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0001 //RX_TDDRC_THRD_0 +113 0x0002 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x6000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x4000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x03C3 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4870 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4850 //RX_FDEQ_GAIN_6 +46 0x485C //RX_FDEQ_GAIN_7 +47 0x5C60 //RX_FDEQ_GAIN_8 +48 0x685C //RX_FDEQ_GAIN_9 +49 0x5640 //RX_FDEQ_GAIN_10 +50 0x4040 //RX_FDEQ_GAIN_11 +51 0x5C58 //RX_FDEQ_GAIN_12 +52 0x5C60 //RX_FDEQ_GAIN_13 +53 0x6060 //RX_FDEQ_GAIN_14 +54 0x6060 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0402 //RX_FDEQ_BIN_3 +67 0x0504 //RX_FDEQ_BIN_4 +68 0x0209 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x006C //_ +158 0x0000 //_ +159 0x0004 //_ +160 0x0004 //_ +161 0x000A //_ +162 0x0000 //_ +163 0x4000 //_ +164 0x4000 //_ +165 0x4000 //_ +166 0x4000 //_ +167 0x065B //_ +168 0x7E56 //_ +169 0x4000 //_ +170 0x7800 //_ +171 0x7000 //_ +172 0x6000 //_ +173 0x0008 //_ +174 0x0003 //_ +175 0x0100 //_ +176 0x0020 //_ +177 0x0400 //_ +178 0x000C //_ +179 0x0014 //_ +180 0xF400 //_ +181 0x7E00 //_ +182 0x000A //_ +183 0x0190 //_ +184 0x7EB8 //_ +185 0x7EB8 //_ +186 0x7EB8 //_ +187 0x0002 //_ +188 0x0800 //_ +189 0x7EB8 //_ +190 0x7FFF //_ +191 0x0800 //_ +192 0x199A //_ +193 0x0000 //_ +194 0x4000 //_ +195 0x0020 //_ +196 0x4848 //_ +197 0x4848 //_ +198 0x4848 //_ +199 0x4870 //_ +200 0x4848 //_ +201 0x4848 //_ +202 0x4850 //_ +203 0x485C //_ +204 0x5C60 //_ +205 0x685C //_ +206 0x5640 //_ +207 0x4040 //_ +208 0x5C58 //_ +209 0x5C60 //_ +210 0x6060 //_ +211 0x6060 //_ +212 0x4848 //_ +213 0x4848 //_ +214 0x4848 //_ +215 0x4848 //_ +216 0x4848 //_ +217 0x4848 //_ +218 0x4848 //_ +219 0x4848 //_ +220 0x0202 //_ +221 0x0203 //_ +222 0x0303 //_ +223 0x0402 //_ +224 0x0504 //_ +225 0x0209 //_ +226 0x0808 //_ +227 0x090A //_ +228 0x0B0C //_ +229 0x0D0E //_ +230 0x1013 //_ +231 0x1719 //_ +232 0x1B1E //_ +233 0x1E1E //_ +234 0x1E28 //_ +235 0x282C //_ +236 0x0000 //_ +237 0x0000 //_ +238 0x0000 //_ +239 0x0000 //_ +240 0x0000 //_ +241 0x0000 //_ +242 0x0000 //_ +243 0x0000 //_ +244 0x4000 //_ +245 0x0320 //_ +246 0x0018 //_ +247 0x0030 //_ +248 0x0050 //_ +249 0x0080 //_ +250 0x0004 //_ +251 0x5000 //_ +252 0x5000 //_ +253 0x2000 //_ +254 0x5000 //_ +255 0x6400 //_ +256 0x6400 //_ +257 0x2000 //_ +258 0x5000 //_ +259 0x4000 //_ +260 0x4000 //_ +261 0x4000 //_ +262 0x4000 //_ +263 0x7FFF //_ +264 0x7FFF //_ +265 0x7FFF //_ +266 0x7FFF //_ +267 0x0000 //_ +268 0x0002 //_ +269 0x0001 //_ +270 0x0002 //_ +271 0x1800 //_ +272 0x1800 //_ +273 0x6000 //_ +274 0x6E00 //_ +275 0x4000 //_ +276 0x7EB8 //_ +277 0x0000 //_ +278 0x199A //_ +279 0x0001 //_ +280 0x0CCD //_ +281 0x03C3 //_ +282 0x7C00 //_ +283 0x2000 //_ +284 0x2000 //_ +285 0x0080 //_ +286 0x0012 //_ +287 0x0000 //_ +288 0x0000 //_ +289 0x3000 //_ +290 0x3000 //_ +291 0x1800 //_ +292 0x1000 //_ +293 0x04CD //_ +294 0x0F33 //_ +295 0x7333 //_ +296 0x199A //_ +297 0x7333 //_ +298 0x0004 //_ +299 0x6CCD //_ +300 0x799A //_ +301 0x001E //_ +302 0x3000 //_ +303 0x3200 //_ +304 0x2000 //_ +305 0x2000 //_ +306 0x2000 //_ +307 0x2000 //_ +308 0x2000 //_ +309 0x2000 //_ +310 0x2000 //_ +311 0x0000 //_ +312 0x0000 //_ +313 0x0000 //_ +#VOL 0 +163 0x4000 //RX_TDDRC_ALPHA_UP_1 +164 0x4000 //RX_TDDRC_ALPHA_UP_2 +165 0x4000 //RX_TDDRC_ALPHA_UP_3 +166 0x4000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0001 //RX_TDDRC_THRD_0 +270 0x0002 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x6000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x4000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x03C3 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4870 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4850 //RX_FDEQ_GAIN_6 +203 0x485C //RX_FDEQ_GAIN_7 +204 0x5C60 //RX_FDEQ_GAIN_8 +205 0x685C //RX_FDEQ_GAIN_9 +206 0x5640 //RX_FDEQ_GAIN_10 +207 0x4040 //RX_FDEQ_GAIN_11 +208 0x5C58 //RX_FDEQ_GAIN_12 +209 0x5C60 //RX_FDEQ_GAIN_13 +210 0x6060 //RX_FDEQ_GAIN_14 +211 0x6060 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0402 //RX_FDEQ_BIN_3 +224 0x0504 //RX_FDEQ_BIN_4 +225 0x0209 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0012 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x4000 //RX_TDDRC_ALPHA_UP_1 +164 0x4000 //RX_TDDRC_ALPHA_UP_2 +165 0x4000 //RX_TDDRC_ALPHA_UP_3 +166 0x4000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0001 //RX_TDDRC_THRD_0 +270 0x0002 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x6000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x4000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x03C3 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4870 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4850 //RX_FDEQ_GAIN_6 +203 0x485C //RX_FDEQ_GAIN_7 +204 0x5C60 //RX_FDEQ_GAIN_8 +205 0x685C //RX_FDEQ_GAIN_9 +206 0x5640 //RX_FDEQ_GAIN_10 +207 0x4040 //RX_FDEQ_GAIN_11 +208 0x5C58 //RX_FDEQ_GAIN_12 +209 0x5C60 //RX_FDEQ_GAIN_13 +210 0x6060 //RX_FDEQ_GAIN_14 +211 0x6060 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0402 //RX_FDEQ_BIN_3 +224 0x0504 //RX_FDEQ_BIN_4 +225 0x0209 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x001A //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x4000 //RX_TDDRC_ALPHA_UP_1 +164 0x4000 //RX_TDDRC_ALPHA_UP_2 +165 0x4000 //RX_TDDRC_ALPHA_UP_3 +166 0x4000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0001 //RX_TDDRC_THRD_0 +270 0x0002 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x6000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x4000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x03C3 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4870 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4850 //RX_FDEQ_GAIN_6 +203 0x485C //RX_FDEQ_GAIN_7 +204 0x5C60 //RX_FDEQ_GAIN_8 +205 0x685C //RX_FDEQ_GAIN_9 +206 0x5640 //RX_FDEQ_GAIN_10 +207 0x4040 //RX_FDEQ_GAIN_11 +208 0x5C58 //RX_FDEQ_GAIN_12 +209 0x5C60 //RX_FDEQ_GAIN_13 +210 0x6060 //RX_FDEQ_GAIN_14 +211 0x6060 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0402 //RX_FDEQ_BIN_3 +224 0x0504 //RX_FDEQ_BIN_4 +225 0x0209 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0025 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x4000 //RX_TDDRC_ALPHA_UP_1 +164 0x4000 //RX_TDDRC_ALPHA_UP_2 +165 0x4000 //RX_TDDRC_ALPHA_UP_3 +166 0x4000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0001 //RX_TDDRC_THRD_0 +270 0x0002 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x6000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x4000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x03C3 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4870 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4850 //RX_FDEQ_GAIN_6 +203 0x485C //RX_FDEQ_GAIN_7 +204 0x5C60 //RX_FDEQ_GAIN_8 +205 0x685C //RX_FDEQ_GAIN_9 +206 0x5640 //RX_FDEQ_GAIN_10 +207 0x4040 //RX_FDEQ_GAIN_11 +208 0x5C58 //RX_FDEQ_GAIN_12 +209 0x5C60 //RX_FDEQ_GAIN_13 +210 0x6060 //RX_FDEQ_GAIN_14 +211 0x6060 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0402 //RX_FDEQ_BIN_3 +224 0x0504 //RX_FDEQ_BIN_4 +225 0x0209 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0034 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x4000 //RX_TDDRC_ALPHA_UP_1 +164 0x4000 //RX_TDDRC_ALPHA_UP_2 +165 0x4000 //RX_TDDRC_ALPHA_UP_3 +166 0x4000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0001 //RX_TDDRC_THRD_0 +270 0x0002 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x6000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x4000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x03C3 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4870 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4850 //RX_FDEQ_GAIN_6 +203 0x485C //RX_FDEQ_GAIN_7 +204 0x5C60 //RX_FDEQ_GAIN_8 +205 0x685C //RX_FDEQ_GAIN_9 +206 0x5640 //RX_FDEQ_GAIN_10 +207 0x4040 //RX_FDEQ_GAIN_11 +208 0x5C58 //RX_FDEQ_GAIN_12 +209 0x5C60 //RX_FDEQ_GAIN_13 +210 0x6060 //RX_FDEQ_GAIN_14 +211 0x6060 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0402 //RX_FDEQ_BIN_3 +224 0x0504 //RX_FDEQ_BIN_4 +225 0x0209 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x004D //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x4000 //RX_TDDRC_ALPHA_UP_1 +164 0x4000 //RX_TDDRC_ALPHA_UP_2 +165 0x4000 //RX_TDDRC_ALPHA_UP_3 +166 0x4000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0001 //RX_TDDRC_THRD_0 +270 0x0002 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x6000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x4000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x03C3 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4870 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4850 //RX_FDEQ_GAIN_6 +203 0x485C //RX_FDEQ_GAIN_7 +204 0x5C60 //RX_FDEQ_GAIN_8 +205 0x685C //RX_FDEQ_GAIN_9 +206 0x5640 //RX_FDEQ_GAIN_10 +207 0x4040 //RX_FDEQ_GAIN_11 +208 0x5C58 //RX_FDEQ_GAIN_12 +209 0x5C60 //RX_FDEQ_GAIN_13 +210 0x6060 //RX_FDEQ_GAIN_14 +211 0x6060 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0402 //RX_FDEQ_BIN_3 +224 0x0504 //RX_FDEQ_BIN_4 +225 0x0209 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0074 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x4000 //RX_TDDRC_ALPHA_UP_1 +164 0x4000 //RX_TDDRC_ALPHA_UP_2 +165 0x4000 //RX_TDDRC_ALPHA_UP_3 +166 0x4000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0001 //RX_TDDRC_THRD_0 +270 0x0002 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x6000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x4000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x03C3 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4870 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4850 //RX_FDEQ_GAIN_6 +203 0x485C //RX_FDEQ_GAIN_7 +204 0x5C60 //RX_FDEQ_GAIN_8 +205 0x685C //RX_FDEQ_GAIN_9 +206 0x5640 //RX_FDEQ_GAIN_10 +207 0x4040 //RX_FDEQ_GAIN_11 +208 0x5C58 //RX_FDEQ_GAIN_12 +209 0x5C60 //RX_FDEQ_GAIN_13 +210 0x6060 //RX_FDEQ_GAIN_14 +211 0x6060 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0402 //RX_FDEQ_BIN_3 +224 0x0504 //RX_FDEQ_BIN_4 +225 0x0209 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + diff --git a/audio/tegu/tuning/fortemedia/HEADSET.dat b/audio/tegu/tuning/fortemedia/HEADSET.dat new file mode 100644 index 0000000000000000000000000000000000000000..22e3e3050da078c91a7c82edae51e90dcc2989e8 GIT binary patch literal 340890 zcmeF431Ab|+J?V#CT-I;Z39$jp_HJgEh1Km2*?t)5};sZlT9sKMMbP^vPq}lzFph} zML}8IP*hZ8R}oPu;Cl7`UUyazQ4tWm_J3m9P)aB*v?Sg;{`dK3GMP+f<~xBL^Z0%l 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zKOW%U$@~!jRTr&1>aD8mjmqAr?9Hj!8}+%QGJ$FgXH~znqSQrK-_sTAd)k}L4Dt1y xR5nv(GgUTIWiwSaQ)M$%CQxMpRYq22WV3${sLZ&^j5{1}krh{&aUtru{}0k8gTnv- literal 0 HcmV?d00001 diff --git a/audio/tegu/tuning/fortemedia/HEADSET.mods b/audio/tegu/tuning/fortemedia/HEADSET.mods new file mode 100644 index 0000000..ac10ce5 --- /dev/null +++ b/audio/tegu/tuning/fortemedia/HEADSET.mods @@ -0,0 +1,85445 @@ +#PLATFORM_NAME gChip +#EXPORT_FLAG HEADSET +#SINGLE_API_VER 1.2.0 +#SAVE_TIME 2022-02-11 16:30:04 + +#CASE_NAME HEADSET-USB_BLACKBIRD-VOICE_GENERIC-NB +#PARAM_MODE FULL +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0009 //TX_OPERATION_MODE_0 +1 0x0009 //TX_OPERATION_MODE_1 +2 0x0033 //TX_PATCH_REG +3 0x2B68 //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0001 //TX_NUM_MIC +6 0x0000 //TX_SAMPLINGFREQ_SIG +7 0x0000 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009B //TX_DIST2REF1 +22 0x0000 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0B80 //TX_PGA_0 +28 0x0800 //TX_PGA_1 +29 0x0000 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0000 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0001 //TX_MIC_DATA_SRC1 +43 0x0002 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3E00 //TX_DIST2REF_11 +73 0x0000 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0200 //TX_MIC_REFBLK_VOLUME +108 0x0800 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0000 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7646 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x7CCC //TX_THR_PITCH_DET_0 +131 0x7000 //TX_THR_PITCH_DET_1 +132 0x6333 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x001E //TX_TAIL_LENGTH +147 0x0010 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x4000 //TX_EAD_THR +151 0x1000 //TX_THR_RE_EST +152 0x2900 //TX_MIN_EQ_RE_EST_0 +153 0x1000 //TX_MIN_EQ_RE_EST_1 +154 0x1000 //TX_MIN_EQ_RE_EST_2 +155 0x0800 //TX_MIN_EQ_RE_EST_3 +156 0x0800 //TX_MIN_EQ_RE_EST_4 +157 0x0800 //TX_MIN_EQ_RE_EST_5 +158 0x0800 //TX_MIN_EQ_RE_EST_6 +159 0x0800 //TX_MIN_EQ_RE_EST_7 +160 0x0800 //TX_MIN_EQ_RE_EST_8 +161 0x0800 //TX_MIN_EQ_RE_EST_9 +162 0x0800 //TX_MIN_EQ_RE_EST_10 +163 0x0800 //TX_MIN_EQ_RE_EST_11 +164 0x0800 //TX_MIN_EQ_RE_EST_12 +165 0x4000 //TX_LAMBDA_RE_EST +166 0x2000 //TX_LAMBDA_CB_NLE +167 0x2000 //TX_C_POST_FLT +168 0x2000 //TX_GAIN_NP +169 0x0064 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x03E8 //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x5000 //TX_DTD_THR1_0 +198 0x7000 //TX_DTD_THR1_1 +199 0x7F00 //TX_DTD_THR1_2 +200 0x7FFF //TX_DTD_THR1_3 +201 0x7FFF //TX_DTD_THR1_4 +202 0x7FFF //TX_DTD_THR1_5 +203 0x7FFF //TX_DTD_THR1_6 +204 0x2000 //TX_DTD_THR2_0 +205 0x2000 //TX_DTD_THR2_1 +206 0x2000 //TX_DTD_THR2_2 +207 0x2000 //TX_DTD_THR2_3 +208 0x2000 //TX_DTD_THR2_4 +209 0x2000 //TX_DTD_THR2_5 +210 0x2000 //TX_DTD_THR2_6 +211 0x4100 //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x0BB8 //TX_DT_CUT_K +214 0x2000 //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x0400 //TX_ADPT_STRICT_L +222 0x0200 //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x0800 //TX_B_POST_FILT_ECHO_L +229 0x7FFF //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x1000 //TX_B_LESSCUT_RTO_ECHO +232 0x0010 //TX_EPD_OFFSET_00 +233 0x0010 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x7FFF //TX_DTD_THR1_7 +238 0x7FFF //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xFA00 //TX_THR_SN_EST_0 +243 0xFD00 //TX_THR_SN_EST_1 +244 0xFA00 //TX_THR_SN_EST_2 +245 0xFA00 //TX_THR_SN_EST_3 +246 0xFA00 //TX_THR_SN_EST_4 +247 0xFA00 //TX_THR_SN_EST_5 +248 0xFA00 //TX_THR_SN_EST_6 +249 0xFA00 //TX_THR_SN_EST_7 +250 0x0000 //TX_DELTA_THR_SN_EST_0 +251 0x0000 //TX_DELTA_THR_SN_EST_1 +252 0x0400 //TX_DELTA_THR_SN_EST_2 +253 0x0000 //TX_DELTA_THR_SN_EST_3 +254 0x0000 //TX_DELTA_THR_SN_EST_4 +255 0x0000 //TX_DELTA_THR_SN_EST_5 +256 0x0100 //TX_DELTA_THR_SN_EST_6 +257 0x0000 //TX_DELTA_THR_SN_EST_7 +258 0x4000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x4000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x0400 //TX_B_POST_FLT_0 +280 0x0400 //TX_B_POST_FLT_1 +281 0x0010 //TX_NS_LVL_CTRL_0 +282 0x0014 //TX_NS_LVL_CTRL_1 +283 0x0016 //TX_NS_LVL_CTRL_2 +284 0x0014 //TX_NS_LVL_CTRL_3 +285 0x0010 //TX_NS_LVL_CTRL_4 +286 0x0010 //TX_NS_LVL_CTRL_5 +287 0x0014 //TX_NS_LVL_CTRL_6 +288 0x0010 //TX_NS_LVL_CTRL_7 +289 0x000D //TX_MIN_GAIN_S_0 +290 0x0012 //TX_MIN_GAIN_S_1 +291 0x0012 //TX_MIN_GAIN_S_2 +292 0x0012 //TX_MIN_GAIN_S_3 +293 0x000D //TX_MIN_GAIN_S_4 +294 0x000D //TX_MIN_GAIN_S_5 +295 0x0012 //TX_MIN_GAIN_S_6 +296 0x000D //TX_MIN_GAIN_S_7 +297 0x7FFF //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x5000 //TX_SNRI_SUP_1 +302 0x5000 //TX_SNRI_SUP_2 +303 0x6000 //TX_SNRI_SUP_3 +304 0x7FFF //TX_SNRI_SUP_4 +305 0x7FFF //TX_SNRI_SUP_5 +306 0x7FFF //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x0014 //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x4000 //TX_A_POST_FILT_S_0 +315 0x1000 //TX_A_POST_FILT_S_1 +316 0x7000 //TX_A_POST_FILT_S_2 +317 0x4000 //TX_A_POST_FILT_S_3 +318 0x4000 //TX_A_POST_FILT_S_4 +319 0x4000 //TX_A_POST_FILT_S_5 +320 0x7FFF //TX_A_POST_FILT_S_6 +321 0x4000 //TX_A_POST_FILT_S_7 +322 0x0400 //TX_B_POST_FILT_0 +323 0x2000 //TX_B_POST_FILT_1 +324 0x2000 //TX_B_POST_FILT_2 +325 0x4000 //TX_B_POST_FILT_3 +326 0x2000 //TX_B_POST_FILT_4 +327 0x2000 //TX_B_POST_FILT_5 +328 0x0400 //TX_B_POST_FILT_6 +329 0x2000 //TX_B_POST_FILT_7 +330 0x7FFF //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x7FFF //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7E14 //TX_LAMBDA_PFILT +339 0x7C29 //TX_LAMBDA_PFILT_S_0 +340 0x7C29 //TX_LAMBDA_PFILT_S_1 +341 0x6000 //TX_LAMBDA_PFILT_S_2 +342 0x7C29 //TX_LAMBDA_PFILT_S_3 +343 0x7C29 //TX_LAMBDA_PFILT_S_4 +344 0x7C29 //TX_LAMBDA_PFILT_S_5 +345 0x7F00 //TX_LAMBDA_PFILT_S_6 +346 0x7C29 //TX_LAMBDA_PFILT_S_7 +347 0x0200 //TX_K_PEPPER +348 0x0400 //TX_A_PEPPER +349 0x0FA0 //TX_K_PEPPER_HF +350 0x0400 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x4000 //TX_HMNC_BST_THR +353 0x0800 //TX_DT_BINVAD_TH_0 +354 0x0800 //TX_DT_BINVAD_TH_1 +355 0x0800 //TX_DT_BINVAD_TH_2 +356 0x0800 //TX_DT_BINVAD_TH_3 +357 0x1D4C //TX_DT_BINVAD_ENDF +358 0x0000 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0190 //TX_NDETCT +367 0x003B //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x0900 //TX_NOISE_TH_1 +371 0x0033 //TX_NOISE_TH_2 +372 0x36B0 //TX_NOISE_TH_3 +373 0x0231 //TX_NOISE_TH_4 +374 0x68DE //TX_NOISE_TH_5 +375 0x5784 //TX_NOISE_TH_5_2 +376 0x0000 //TX_NOISE_TH_5_3 +377 0x0000 //TX_NOISE_TH_5_4 +378 0x00C8 //TX_NOISE_TH_6 +379 0x00C8 //TX_MINENOISE_TH +380 0xD508 //TX_MORENS_TFMASK_TH +381 0x0001 //TX_DRC_QUIET_FLOOR +382 0x3A98 //TX_RATIODTL_CUT_TH +383 0x0DAC //TX_DT_CUT_K1 +384 0x00A5 //TX_OUT_ENER_S_TH_CLEAN +385 0x00A5 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x00A5 //TX_OUT_ENER_S_TH_NOISY +387 0x0029 //TX_OUT_ENER_TH_NOISE +388 0x00CE //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x7FFF //TX_POST_MASK_SUP_HSNE +392 0x1388 //TX_TAIL_DET_TH +393 0x4000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0080 //TX_SUPHIGH_TH +396 0x0000 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x1800 //TX_C_POST_FLT_MASK +399 0x7FFF //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0002 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x0032 //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x7FFF //TX_MIN_G_CTRL_SSNS +409 0x0000 //TX_METAL_RTO_THR +410 0x4848 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0280 //TX_N_HOLD_HS +416 0x006E //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0333 //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2400 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0640 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x2000 //TX_WTA_EN_RTO_TH +429 0x1400 //TX_TOP_ENER_TH_F +430 0x0064 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x003C //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x0D9A //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x2A3D //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x01E0 //TX_NOR_OFF_THR +498 0x7C00 //TX_MORE_ON_700HZ_THR +499 0x0000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0xD333 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x6000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0xC000 //TX_DEREVERB_LF_MU +515 0xC000 //TX_DEREVERB_HF_MU +516 0xCCCC //TX_DEREVERB_DELAY +517 0xD999 //TX_DEREVERB_COEF_LEN +518 0x1F40 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x7000 //TX_GSC_RTOH_TH +523 0x0064 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0014 //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x443C //TX_FDEQ_GAIN_5 +573 0x2A30 //TX_FDEQ_GAIN_6 +574 0x2C2C //TX_FDEQ_GAIN_7 +575 0x2820 //TX_FDEQ_GAIN_8 +576 0x2024 //TX_FDEQ_GAIN_9 +577 0x4848 //TX_FDEQ_GAIN_10 +578 0x4848 //TX_FDEQ_GAIN_11 +579 0x4848 //TX_FDEQ_GAIN_12 +580 0x4848 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0303 //TX_FDEQ_BIN_2 +594 0x0304 //TX_FDEQ_BIN_3 +595 0x0405 //TX_FDEQ_BIN_4 +596 0x0506 //TX_FDEQ_BIN_5 +597 0x0708 //TX_FDEQ_BIN_6 +598 0x090A //TX_FDEQ_BIN_7 +599 0x0B0C //TX_FDEQ_BIN_8 +600 0x0D0E //TX_FDEQ_BIN_9 +601 0x0000 //TX_FDEQ_BIN_10 +602 0x0000 //TX_FDEQ_BIN_11 +603 0x0000 //TX_FDEQ_BIN_12 +604 0x0000 //TX_FDEQ_BIN_13 +605 0x0000 //TX_FDEQ_BIN_14 +606 0x0000 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0010 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4848 //TX_PREEQ_GAIN_MIC0_8 +626 0x4848 //TX_PREEQ_GAIN_MIC0_9 +627 0x4848 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0608 //TX_PREEQ_BIN_MIC0_0 +642 0x0808 //TX_PREEQ_BIN_MIC0_1 +643 0x0808 //TX_PREEQ_BIN_MIC0_2 +644 0x0808 //TX_PREEQ_BIN_MIC0_3 +645 0x0808 //TX_PREEQ_BIN_MIC0_4 +646 0x0808 //TX_PREEQ_BIN_MIC0_5 +647 0x0808 //TX_PREEQ_BIN_MIC0_6 +648 0x0802 //TX_PREEQ_BIN_MIC0_7 +649 0x0000 //TX_PREEQ_BIN_MIC0_8 +650 0x0000 //TX_PREEQ_BIN_MIC0_9 +651 0x0000 //TX_PREEQ_BIN_MIC0_10 +652 0x0000 //TX_PREEQ_BIN_MIC0_11 +653 0x0000 //TX_PREEQ_BIN_MIC0_12 +654 0x0000 //TX_PREEQ_BIN_MIC0_13 +655 0x0000 //TX_PREEQ_BIN_MIC0_14 +656 0x0000 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0010 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0608 //TX_PREEQ_BIN_MIC1_0 +691 0x0808 //TX_PREEQ_BIN_MIC1_1 +692 0x0808 //TX_PREEQ_BIN_MIC1_2 +693 0x0808 //TX_PREEQ_BIN_MIC1_3 +694 0x0808 //TX_PREEQ_BIN_MIC1_4 +695 0x0808 //TX_PREEQ_BIN_MIC1_5 +696 0x0808 //TX_PREEQ_BIN_MIC1_6 +697 0x0802 //TX_PREEQ_BIN_MIC1_7 +698 0x0000 //TX_PREEQ_BIN_MIC1_8 +699 0x0000 //TX_PREEQ_BIN_MIC1_9 +700 0x0000 //TX_PREEQ_BIN_MIC1_10 +701 0x0000 //TX_PREEQ_BIN_MIC1_11 +702 0x0000 //TX_PREEQ_BIN_MIC1_12 +703 0x0000 //TX_PREEQ_BIN_MIC1_13 +704 0x0000 //TX_PREEQ_BIN_MIC1_14 +705 0x0000 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0010 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0608 //TX_PREEQ_BIN_MIC2_0 +740 0x0808 //TX_PREEQ_BIN_MIC2_1 +741 0x0808 //TX_PREEQ_BIN_MIC2_2 +742 0x0808 //TX_PREEQ_BIN_MIC2_3 +743 0x0808 //TX_PREEQ_BIN_MIC2_4 +744 0x0808 //TX_PREEQ_BIN_MIC2_5 +745 0x0808 //TX_PREEQ_BIN_MIC2_6 +746 0x0802 //TX_PREEQ_BIN_MIC2_7 +747 0x0000 //TX_PREEQ_BIN_MIC2_8 +748 0x0000 //TX_PREEQ_BIN_MIC2_9 +749 0x0000 //TX_PREEQ_BIN_MIC2_10 +750 0x0000 //TX_PREEQ_BIN_MIC2_11 +751 0x0000 //TX_PREEQ_BIN_MIC2_12 +752 0x0000 //TX_PREEQ_BIN_MIC2_13 +753 0x0000 //TX_PREEQ_BIN_MIC2_14 +754 0x0000 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x0800 //TX_NND_WEIGHT +765 0x0065 //TX_MIC_CALIBRATION_0 +766 0x0065 //TX_MIC_CALIBRATION_1 +767 0x0065 //TX_MIC_CALIBRATION_2 +768 0x0065 //TX_MIC_CALIBRATION_3 +769 0x0044 //TX_MIC_PWR_BIAS_0 +770 0x0044 //TX_MIC_PWR_BIAS_1 +771 0x0044 //TX_MIC_PWR_BIAS_2 +772 0x0044 //TX_MIC_PWR_BIAS_3 +773 0x000B //TX_GAIN_LIMIT_0 +774 0x000B //TX_GAIN_LIMIT_1 +775 0x000B //TX_GAIN_LIMIT_2 +776 0x000B //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x1000 //TX_TDDRC_ALPHA_UP_01 +784 0x1000 //TX_TDDRC_ALPHA_UP_02 +785 0x1000 //TX_TDDRC_ALPHA_UP_03 +786 0x1000 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x7FFF //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0000 //TX_DEADMIC_SILENCE_TH +817 0x0000 //TX_MIC_DEGRADE_TH +818 0x0000 //TX_DEADMIC_CNT +819 0x0000 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x4848 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0000 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0001 //TX_FILTINDX +854 0x0002 //TX_TDDRC_THRD_0 +855 0x0008 //TX_TDDRC_THRD_1 +856 0x2000 //TX_TDDRC_THRD_2 +857 0x2000 //TX_TDDRC_THRD_3 +858 0x3000 //TX_TDDRC_SLANT_0 +859 0x6E00 //TX_TDDRC_SLANT_1 +860 0x1000 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x0700 //TX_TDDRC_DRC_GAIN +867 0x7FFF //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0xF800 //TX_TFMASKLTH_DOA +875 0x0CCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x0028 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x4000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x2339 //TX_SENDFUNC_REG_MICMUTE +898 0x0021 //TX_SENDFUNC_REG_MICMUTE1 +899 0x02BC //TX_MICMUTE_RATIO_THR +900 0x0140 //TX_MICMUTE_AMP_THR +901 0x0004 //TX_MICMUTE_HPF_IND +902 0x00C0 //TX_MICMUTE_LOG_EYR_TH +903 0x0008 //TX_MICMUTE_CVG_TIME +904 0x0008 //TX_MICMUTE_RELEASE_TIME +905 0x01FE //TX_MIC_VOLUME_MIC0MUTE +906 0x0020 //TX_MICMUTE_EPD_OFFSET_0 +907 0x001E //TX_MICMUTE_FRQ_AEC_L +908 0x7999 //TX_MICMUTE_EAD_THR +909 0x7FFF //TX_MICMUTE_LAMBDA_CB_NLE +910 0x7FFF //TX_MICMUTE_LAMBDA_RE_EST +911 0x4000 //TX_DTD_THR1_MICMUTE_0 +912 0x7000 //TX_DTD_THR1_MICMUTE_1 +913 0x7FFF //TX_DTD_THR1_MICMUTE_2 +914 0x7FFF //TX_DTD_THR1_MICMUTE_3 +915 0x6CCC //TX_DTD_THR2_MICMUTE_0 +916 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x1000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x4000 //TX_MICMUTE_C_POST_FLT +922 0x03E8 //TX_MICMUTE_DT_CUT_K +923 0x0001 //TX_MICMUTE_DT_CUT_THR +924 0x03E8 //TX_MICMUTE_DT_CUT_K2 +925 0x0001 //TX_MICMUTE_DT_CUT_THR2 +926 0x0064 //TX_MICMUTE_DT2_HOLD_N +927 0x1000 //TX_MICMUTE_RATIODTH_THCUT +928 0x1000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x7FFF //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0400 //TX_MICMUTE_C_POST_FLT_MASK +931 0x7999 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0258 //TX_MICMUTE_DT_CUT_K1 +933 0x0800 //TX_MICMUTE_N2_SN_EST +934 0xFC00 //TX_MICMUTE_THR_SN_EST_0 +935 0x001C //TX_MICMUTE_MIN_G_CTRL_0 +936 0x6000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x7000 //TX_MICMUTE_B_POST_FILT_0 +938 0x2710 //TX_MIC1RUB_AMP_THR +939 0x0010 //TX_MIC1MUTE_RATIO_THR +940 0x0450 //TX_MIC1MUTE_AMP_THR +941 0x0008 //TX_MIC1MUTE_CVG_TIME +942 0x0008 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x242C //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0000 //RX_SAMPLINGFREQ_SIG +3 0x0000 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7FFF //RX_A_HP +12 0x0000 //RX_B_PE +13 0x3800 //RX_THR_PITCH_DET_0 +14 0x3000 //RX_THR_PITCH_DET_1 +15 0x2800 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0600 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x0010 //RX_NS_LVL_CTRL +23 0xF800 //RX_THR_SN_EST +24 0x7CCD //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7220 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0002 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0211 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x280A //RX_TPKA_FP +127 0x032D //RX_MIN_G_FP +128 0x0A00 //RX_MAX_G_FP +129 0x0009 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7220 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0211 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0009 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7220 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0211 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x000F //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7220 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0211 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0019 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7220 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0211 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x002B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7220 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0211 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0048 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7220 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0211 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x007A //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7220 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0211 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x242C //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0000 //RX_SAMPLINGFREQ_SIG +160 0x0000 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7FFF //RX_A_HP +169 0x0000 //RX_B_PE +170 0x3800 //RX_THR_PITCH_DET_0 +171 0x3000 //RX_THR_PITCH_DET_1 +172 0x2800 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0600 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x0010 //RX_NS_LVL_CTRL +180 0xF800 //RX_THR_SN_EST +181 0x7CCD //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7220 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0002 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0211 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x280A //RX_TPKA_FP +284 0x032D //RX_MIN_G_FP +285 0x0A00 //RX_MAX_G_FP +286 0x0009 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7220 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0211 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0009 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7220 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0211 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x000F //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7220 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0211 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0019 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7220 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0211 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x002B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7220 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0211 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0048 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7220 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0211 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x007A //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7220 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0211 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME HEADSET-USB_BLACKBIRD-VOICE_GENERIC-WB +#PARAM_MODE FULL +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0009 //TX_OPERATION_MODE_0 +1 0x0009 //TX_OPERATION_MODE_1 +2 0x0033 //TX_PATCH_REG +3 0x2B68 //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0001 //TX_NUM_MIC +6 0x0001 //TX_SAMPLINGFREQ_SIG +7 0x0001 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009B //TX_DIST2REF1 +22 0x0000 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0B80 //TX_PGA_0 +28 0x0800 //TX_PGA_1 +29 0x0800 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0000 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0001 //TX_MIC_DATA_SRC1 +43 0x0002 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3E00 //TX_DIST2REF_11 +73 0x0000 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0200 //TX_MIC_REFBLK_VOLUME +108 0x0800 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0000 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7D83 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x6800 //TX_THR_PITCH_DET_0 +131 0x6000 //TX_THR_PITCH_DET_1 +132 0x5800 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x001E //TX_TAIL_LENGTH +147 0x0080 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x36B0 //TX_EAD_THR +151 0x0800 //TX_THR_RE_EST +152 0x0800 //TX_MIN_EQ_RE_EST_0 +153 0x0800 //TX_MIN_EQ_RE_EST_1 +154 0x0800 //TX_MIN_EQ_RE_EST_2 +155 0x0800 //TX_MIN_EQ_RE_EST_3 +156 0x0800 //TX_MIN_EQ_RE_EST_4 +157 0x0800 //TX_MIN_EQ_RE_EST_5 +158 0x0800 //TX_MIN_EQ_RE_EST_6 +159 0x0800 //TX_MIN_EQ_RE_EST_7 +160 0x0800 //TX_MIN_EQ_RE_EST_8 +161 0x0800 //TX_MIN_EQ_RE_EST_9 +162 0x0800 //TX_MIN_EQ_RE_EST_10 +163 0x0800 //TX_MIN_EQ_RE_EST_11 +164 0x0800 //TX_MIN_EQ_RE_EST_12 +165 0x4000 //TX_LAMBDA_RE_EST +166 0x2000 //TX_LAMBDA_CB_NLE +167 0x6000 //TX_C_POST_FLT +168 0x7000 //TX_GAIN_NP +169 0x0064 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x03E8 //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x7D00 //TX_DTD_THR1_0 +198 0x7D00 //TX_DTD_THR1_1 +199 0x7D00 //TX_DTD_THR1_2 +200 0x7D00 //TX_DTD_THR1_3 +201 0x7D00 //TX_DTD_THR1_4 +202 0x7D00 //TX_DTD_THR1_5 +203 0x7D00 //TX_DTD_THR1_6 +204 0x4000 //TX_DTD_THR2_0 +205 0x1000 //TX_DTD_THR2_1 +206 0x1000 //TX_DTD_THR2_2 +207 0x1000 //TX_DTD_THR2_3 +208 0x1000 //TX_DTD_THR2_4 +209 0x1000 //TX_DTD_THR2_5 +210 0x1000 //TX_DTD_THR2_6 +211 0x1000 //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x1B58 //TX_DT_CUT_K +214 0x1000 //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x0400 //TX_ADPT_STRICT_L +222 0x0200 //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x0800 //TX_B_POST_FILT_ECHO_L +229 0x7FFF //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x7FFF //TX_B_LESSCUT_RTO_ECHO +232 0x0019 //TX_EPD_OFFSET_00 +233 0x0019 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x7FFF //TX_DTD_THR1_7 +238 0x7FFF //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xFA00 //TX_THR_SN_EST_0 +243 0xFA00 //TX_THR_SN_EST_1 +244 0xF700 //TX_THR_SN_EST_2 +245 0xFC00 //TX_THR_SN_EST_3 +246 0xF800 //TX_THR_SN_EST_4 +247 0xF400 //TX_THR_SN_EST_5 +248 0xF400 //TX_THR_SN_EST_6 +249 0xF600 //TX_THR_SN_EST_7 +250 0x0000 //TX_DELTA_THR_SN_EST_0 +251 0x0200 //TX_DELTA_THR_SN_EST_1 +252 0x0200 //TX_DELTA_THR_SN_EST_2 +253 0x0100 //TX_DELTA_THR_SN_EST_3 +254 0x0200 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0100 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x6000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x6000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x1000 //TX_B_POST_FLT_0 +280 0x1000 //TX_B_POST_FLT_1 +281 0x000F //TX_NS_LVL_CTRL_0 +282 0x0014 //TX_NS_LVL_CTRL_1 +283 0x001C //TX_NS_LVL_CTRL_2 +284 0x0012 //TX_NS_LVL_CTRL_3 +285 0x000F //TX_NS_LVL_CTRL_4 +286 0x000F //TX_NS_LVL_CTRL_5 +287 0x0018 //TX_NS_LVL_CTRL_6 +288 0x0011 //TX_NS_LVL_CTRL_7 +289 0x000C //TX_MIN_GAIN_S_0 +290 0x000F //TX_MIN_GAIN_S_1 +291 0x000C //TX_MIN_GAIN_S_2 +292 0x0009 //TX_MIN_GAIN_S_3 +293 0x000C //TX_MIN_GAIN_S_4 +294 0x000C //TX_MIN_GAIN_S_5 +295 0x000C //TX_MIN_GAIN_S_6 +296 0x000F //TX_MIN_GAIN_S_7 +297 0x7FFF //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x6000 //TX_SNRI_SUP_1 +302 0x2000 //TX_SNRI_SUP_2 +303 0x6000 //TX_SNRI_SUP_3 +304 0x7FFF //TX_SNRI_SUP_4 +305 0x7FFF //TX_SNRI_SUP_5 +306 0x7FFF //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x000E //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x4000 //TX_A_POST_FILT_S_0 +315 0x5000 //TX_A_POST_FILT_S_1 +316 0x5000 //TX_A_POST_FILT_S_2 +317 0x5000 //TX_A_POST_FILT_S_3 +318 0x5000 //TX_A_POST_FILT_S_4 +319 0x5000 //TX_A_POST_FILT_S_5 +320 0x4000 //TX_A_POST_FILT_S_6 +321 0x5000 //TX_A_POST_FILT_S_7 +322 0x1000 //TX_B_POST_FILT_0 +323 0x1000 //TX_B_POST_FILT_1 +324 0x3000 //TX_B_POST_FILT_2 +325 0x1000 //TX_B_POST_FILT_3 +326 0x1000 //TX_B_POST_FILT_4 +327 0x1000 //TX_B_POST_FILT_5 +328 0x1000 //TX_B_POST_FILT_6 +329 0x1000 //TX_B_POST_FILT_7 +330 0x7FFF //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x7FFF //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7CCD //TX_LAMBDA_PFILT +339 0x7B00 //TX_LAMBDA_PFILT_S_0 +340 0x7B00 //TX_LAMBDA_PFILT_S_1 +341 0x7B00 //TX_LAMBDA_PFILT_S_2 +342 0x7B00 //TX_LAMBDA_PFILT_S_3 +343 0x7B00 //TX_LAMBDA_PFILT_S_4 +344 0x7B00 //TX_LAMBDA_PFILT_S_5 +345 0x7F00 //TX_LAMBDA_PFILT_S_6 +346 0x7B00 //TX_LAMBDA_PFILT_S_7 +347 0x0200 //TX_K_PEPPER +348 0x0400 //TX_A_PEPPER +349 0x1EAA //TX_K_PEPPER_HF +350 0x0800 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0800 //TX_DT_BINVAD_TH_0 +354 0x0800 //TX_DT_BINVAD_TH_1 +355 0x0800 //TX_DT_BINVAD_TH_2 +356 0x0800 //TX_DT_BINVAD_TH_3 +357 0x1D4C //TX_DT_BINVAD_ENDF +358 0x0000 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0190 //TX_NDETCT +367 0x0102 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x0900 //TX_NOISE_TH_1 +371 0x009B //TX_NOISE_TH_2 +372 0x4149 //TX_NOISE_TH_3 +373 0x0331 //TX_NOISE_TH_4 +374 0x542C //TX_NOISE_TH_5 +375 0x55E5 //TX_NOISE_TH_5_2 +376 0x7FFF //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x00FB //TX_NOISE_TH_6 +379 0x00F8 //TX_MINENOISE_TH +380 0xD508 //TX_MORENS_TFMASK_TH +381 0x0001 //TX_DRC_QUIET_FLOOR +382 0x3A98 //TX_RATIODTL_CUT_TH +383 0x0DAC //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x0333 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x7FFF //TX_POST_MASK_SUP_HSNE +392 0x1388 //TX_TAIL_DET_TH +393 0x4000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0080 //TX_SUPHIGH_TH +396 0x0000 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x1800 //TX_C_POST_FLT_MASK +399 0x7FFF //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0002 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x00DC //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x7FFF //TX_MIN_G_CTRL_SSNS +409 0x0800 //TX_METAL_RTO_THR +410 0x4848 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x4000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x01E0 //TX_NOR_OFF_THR +498 0x7C00 //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0xD333 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x6000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0xC000 //TX_DEREVERB_LF_MU +515 0xC000 //TX_DEREVERB_HF_MU +516 0xCCCC //TX_DEREVERB_DELAY +517 0xD999 //TX_DEREVERB_COEF_LEN +518 0x1F40 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x7000 //TX_GSC_RTOH_TH +523 0x0064 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x001C //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4849 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4140 //TX_FDEQ_GAIN_5 +573 0x3838 //TX_FDEQ_GAIN_6 +574 0x3839 //TX_FDEQ_GAIN_7 +575 0x3830 //TX_FDEQ_GAIN_8 +576 0x3033 //TX_FDEQ_GAIN_9 +577 0x2E2E //TX_FDEQ_GAIN_10 +578 0x2A2A //TX_FDEQ_GAIN_11 +579 0x2A32 //TX_FDEQ_GAIN_12 +580 0x3838 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0303 //TX_FDEQ_BIN_2 +594 0x0304 //TX_FDEQ_BIN_3 +595 0x0405 //TX_FDEQ_BIN_4 +596 0x0506 //TX_FDEQ_BIN_5 +597 0x0708 //TX_FDEQ_BIN_6 +598 0x090A //TX_FDEQ_BIN_7 +599 0x0B0C //TX_FDEQ_BIN_8 +600 0x0D0E //TX_FDEQ_BIN_9 +601 0x0E0F //TX_FDEQ_BIN_10 +602 0x0F10 //TX_FDEQ_BIN_11 +603 0x1011 //TX_FDEQ_BIN_12 +604 0x1112 //TX_FDEQ_BIN_13 +605 0x0000 //TX_FDEQ_BIN_14 +606 0x0000 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4848 //TX_PREEQ_GAIN_MIC0_8 +626 0x4848 //TX_PREEQ_GAIN_MIC0_9 +627 0x4848 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0608 //TX_PREEQ_BIN_MIC0_0 +642 0x0808 //TX_PREEQ_BIN_MIC0_1 +643 0x0808 //TX_PREEQ_BIN_MIC0_2 +644 0x0808 //TX_PREEQ_BIN_MIC0_3 +645 0x0808 //TX_PREEQ_BIN_MIC0_4 +646 0x0808 //TX_PREEQ_BIN_MIC0_5 +647 0x0808 //TX_PREEQ_BIN_MIC0_6 +648 0x0808 //TX_PREEQ_BIN_MIC0_7 +649 0x0808 //TX_PREEQ_BIN_MIC0_8 +650 0x0808 //TX_PREEQ_BIN_MIC0_9 +651 0x0808 //TX_PREEQ_BIN_MIC0_10 +652 0x0808 //TX_PREEQ_BIN_MIC0_11 +653 0x0808 //TX_PREEQ_BIN_MIC0_12 +654 0x0808 //TX_PREEQ_BIN_MIC0_13 +655 0x0808 //TX_PREEQ_BIN_MIC0_14 +656 0x0200 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0608 //TX_PREEQ_BIN_MIC1_0 +691 0x0808 //TX_PREEQ_BIN_MIC1_1 +692 0x0808 //TX_PREEQ_BIN_MIC1_2 +693 0x0808 //TX_PREEQ_BIN_MIC1_3 +694 0x0808 //TX_PREEQ_BIN_MIC1_4 +695 0x0808 //TX_PREEQ_BIN_MIC1_5 +696 0x0808 //TX_PREEQ_BIN_MIC1_6 +697 0x0808 //TX_PREEQ_BIN_MIC1_7 +698 0x0808 //TX_PREEQ_BIN_MIC1_8 +699 0x0808 //TX_PREEQ_BIN_MIC1_9 +700 0x0808 //TX_PREEQ_BIN_MIC1_10 +701 0x0808 //TX_PREEQ_BIN_MIC1_11 +702 0x0808 //TX_PREEQ_BIN_MIC1_12 +703 0x0808 //TX_PREEQ_BIN_MIC1_13 +704 0x0808 //TX_PREEQ_BIN_MIC1_14 +705 0x0200 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0608 //TX_PREEQ_BIN_MIC2_0 +740 0x0808 //TX_PREEQ_BIN_MIC2_1 +741 0x0808 //TX_PREEQ_BIN_MIC2_2 +742 0x0808 //TX_PREEQ_BIN_MIC2_3 +743 0x0808 //TX_PREEQ_BIN_MIC2_4 +744 0x0808 //TX_PREEQ_BIN_MIC2_5 +745 0x0808 //TX_PREEQ_BIN_MIC2_6 +746 0x0808 //TX_PREEQ_BIN_MIC2_7 +747 0x0808 //TX_PREEQ_BIN_MIC2_8 +748 0x0808 //TX_PREEQ_BIN_MIC2_9 +749 0x0808 //TX_PREEQ_BIN_MIC2_10 +750 0x0808 //TX_PREEQ_BIN_MIC2_11 +751 0x0808 //TX_PREEQ_BIN_MIC2_12 +752 0x0808 //TX_PREEQ_BIN_MIC2_13 +753 0x0808 //TX_PREEQ_BIN_MIC2_14 +754 0x0200 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x0800 //TX_NND_WEIGHT +765 0x0062 //TX_MIC_CALIBRATION_0 +766 0x0062 //TX_MIC_CALIBRATION_1 +767 0x0062 //TX_MIC_CALIBRATION_2 +768 0x0062 //TX_MIC_CALIBRATION_3 +769 0x0046 //TX_MIC_PWR_BIAS_0 +770 0x0046 //TX_MIC_PWR_BIAS_1 +771 0x0046 //TX_MIC_PWR_BIAS_2 +772 0x0046 //TX_MIC_PWR_BIAS_3 +773 0x000C //TX_GAIN_LIMIT_0 +774 0x000C //TX_GAIN_LIMIT_1 +775 0x000C //TX_GAIN_LIMIT_2 +776 0x000C //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x1000 //TX_TDDRC_ALPHA_UP_01 +784 0x1000 //TX_TDDRC_ALPHA_UP_02 +785 0x1000 //TX_TDDRC_ALPHA_UP_03 +786 0x1000 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x7FFF //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0000 //TX_DEADMIC_SILENCE_TH +817 0x0000 //TX_MIC_DEGRADE_TH +818 0x0000 //TX_DEADMIC_CNT +819 0x0000 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x4848 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0000 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0001 //TX_FILTINDX +854 0x0000 //TX_TDDRC_THRD_0 +855 0x0000 //TX_TDDRC_THRD_1 +856 0x2000 //TX_TDDRC_THRD_2 +857 0x2000 //TX_TDDRC_THRD_3 +858 0x3000 //TX_TDDRC_SLANT_0 +859 0x6E00 //TX_TDDRC_SLANT_1 +860 0x1000 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x0700 //TX_TDDRC_DRC_GAIN +867 0x7FFF //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xCCCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x0000 //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x00C8 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x4000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x2339 //TX_SENDFUNC_REG_MICMUTE +898 0x0021 //TX_SENDFUNC_REG_MICMUTE1 +899 0x02BC //TX_MICMUTE_RATIO_THR +900 0x0140 //TX_MICMUTE_AMP_THR +901 0x0004 //TX_MICMUTE_HPF_IND +902 0x00C0 //TX_MICMUTE_LOG_EYR_TH +903 0x0008 //TX_MICMUTE_CVG_TIME +904 0x0008 //TX_MICMUTE_RELEASE_TIME +905 0x01FE //TX_MIC_VOLUME_MIC0MUTE +906 0x0020 //TX_MICMUTE_EPD_OFFSET_0 +907 0x001E //TX_MICMUTE_FRQ_AEC_L +908 0x7999 //TX_MICMUTE_EAD_THR +909 0x7FFF //TX_MICMUTE_LAMBDA_CB_NLE +910 0x7FFF //TX_MICMUTE_LAMBDA_RE_EST +911 0x4000 //TX_DTD_THR1_MICMUTE_0 +912 0x7000 //TX_DTD_THR1_MICMUTE_1 +913 0x7FFF //TX_DTD_THR1_MICMUTE_2 +914 0x7FFF //TX_DTD_THR1_MICMUTE_3 +915 0x6CCC //TX_DTD_THR2_MICMUTE_0 +916 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x1000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x4000 //TX_MICMUTE_C_POST_FLT +922 0x03E8 //TX_MICMUTE_DT_CUT_K +923 0x0001 //TX_MICMUTE_DT_CUT_THR +924 0x03E8 //TX_MICMUTE_DT_CUT_K2 +925 0x0001 //TX_MICMUTE_DT_CUT_THR2 +926 0x0064 //TX_MICMUTE_DT2_HOLD_N +927 0x1000 //TX_MICMUTE_RATIODTH_THCUT +928 0x1000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x7FFF //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0400 //TX_MICMUTE_C_POST_FLT_MASK +931 0x7999 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0258 //TX_MICMUTE_DT_CUT_K1 +933 0x0800 //TX_MICMUTE_N2_SN_EST +934 0xFC00 //TX_MICMUTE_THR_SN_EST_0 +935 0x001C //TX_MICMUTE_MIN_G_CTRL_0 +936 0x6000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x7000 //TX_MICMUTE_B_POST_FILT_0 +938 0x2710 //TX_MIC1RUB_AMP_THR +939 0x0010 //TX_MIC1MUTE_RATIO_THR +940 0x0450 //TX_MIC1MUTE_AMP_THR +941 0x0008 //TX_MIC1MUTE_CVG_TIME +942 0x0008 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x242C //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0001 //RX_SAMPLINGFREQ_SIG +3 0x0001 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7FFF //RX_A_HP +12 0x4000 //RX_B_PE +13 0x3800 //RX_THR_PITCH_DET_0 +14 0x3000 //RX_THR_PITCH_DET_1 +15 0x2800 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0600 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x0010 //RX_NS_LVL_CTRL +23 0xF800 //RX_THR_SN_EST +24 0x7CCD //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x484B //RX_FDEQ_GAIN_6 +46 0x4B48 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4846 //RX_FDEQ_GAIN_10 +50 0x403F //RX_FDEQ_GAIN_11 +51 0x3F40 //RX_FDEQ_GAIN_12 +52 0x4248 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0002 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1C00 //RX_TDDRC_THRD_2 +115 0x1D00 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x01AE //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x280A //RX_TPKA_FP +127 0x032D //RX_MIN_G_FP +128 0x0A00 //RX_MAX_G_FP +129 0x000B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7220 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x01A0 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x484B //RX_FDEQ_GAIN_6 +46 0x4B48 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4846 //RX_FDEQ_GAIN_10 +50 0x403F //RX_FDEQ_GAIN_11 +51 0x3F40 //RX_FDEQ_GAIN_12 +52 0x4248 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x000A //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7220 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x01A0 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x484B //RX_FDEQ_GAIN_6 +46 0x4B48 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4846 //RX_FDEQ_GAIN_10 +50 0x403F //RX_FDEQ_GAIN_11 +51 0x3F40 //RX_FDEQ_GAIN_12 +52 0x4248 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0011 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7220 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x01A0 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x484B //RX_FDEQ_GAIN_6 +46 0x4B48 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4846 //RX_FDEQ_GAIN_10 +50 0x403F //RX_FDEQ_GAIN_11 +51 0x3F40 //RX_FDEQ_GAIN_12 +52 0x4248 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x001D //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7220 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x01A0 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x484B //RX_FDEQ_GAIN_6 +46 0x4B48 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4846 //RX_FDEQ_GAIN_10 +50 0x403F //RX_FDEQ_GAIN_11 +51 0x3F40 //RX_FDEQ_GAIN_12 +52 0x4248 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0030 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7220 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x01A0 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x484B //RX_FDEQ_GAIN_6 +46 0x4B48 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4846 //RX_FDEQ_GAIN_10 +50 0x403F //RX_FDEQ_GAIN_11 +51 0x3F40 //RX_FDEQ_GAIN_12 +52 0x4248 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0050 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7220 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x01A0 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x484B //RX_FDEQ_GAIN_6 +46 0x4B48 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4846 //RX_FDEQ_GAIN_10 +50 0x403F //RX_FDEQ_GAIN_11 +51 0x3F40 //RX_FDEQ_GAIN_12 +52 0x4248 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0087 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7220 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x01A0 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x484B //RX_FDEQ_GAIN_6 +46 0x4B48 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4846 //RX_FDEQ_GAIN_10 +50 0x403F //RX_FDEQ_GAIN_11 +51 0x3F40 //RX_FDEQ_GAIN_12 +52 0x4248 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x242C //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0001 //RX_SAMPLINGFREQ_SIG +160 0x0001 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7FFF //RX_A_HP +169 0x4000 //RX_B_PE +170 0x3800 //RX_THR_PITCH_DET_0 +171 0x3000 //RX_THR_PITCH_DET_1 +172 0x2800 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0600 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x0010 //RX_NS_LVL_CTRL +180 0xF800 //RX_THR_SN_EST +181 0x7CCD //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x484B //RX_FDEQ_GAIN_6 +203 0x4B48 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4846 //RX_FDEQ_GAIN_10 +207 0x403F //RX_FDEQ_GAIN_11 +208 0x3F40 //RX_FDEQ_GAIN_12 +209 0x4248 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0002 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1C00 //RX_TDDRC_THRD_2 +272 0x1D00 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x01AE //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x280A //RX_TPKA_FP +284 0x032D //RX_MIN_G_FP +285 0x0A00 //RX_MAX_G_FP +286 0x000B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7220 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x01A0 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x484B //RX_FDEQ_GAIN_6 +203 0x4B48 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4846 //RX_FDEQ_GAIN_10 +207 0x403F //RX_FDEQ_GAIN_11 +208 0x3F40 //RX_FDEQ_GAIN_12 +209 0x4248 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x000A //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7220 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x01A0 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x484B //RX_FDEQ_GAIN_6 +203 0x4B48 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4846 //RX_FDEQ_GAIN_10 +207 0x403F //RX_FDEQ_GAIN_11 +208 0x3F40 //RX_FDEQ_GAIN_12 +209 0x4248 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0011 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7220 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x01A0 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x484B //RX_FDEQ_GAIN_6 +203 0x4B48 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4846 //RX_FDEQ_GAIN_10 +207 0x403F //RX_FDEQ_GAIN_11 +208 0x3F40 //RX_FDEQ_GAIN_12 +209 0x4248 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x001D //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7220 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x01A0 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x484B //RX_FDEQ_GAIN_6 +203 0x4B48 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4846 //RX_FDEQ_GAIN_10 +207 0x403F //RX_FDEQ_GAIN_11 +208 0x3F40 //RX_FDEQ_GAIN_12 +209 0x4248 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0030 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7220 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x01A0 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x484B //RX_FDEQ_GAIN_6 +203 0x4B48 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4846 //RX_FDEQ_GAIN_10 +207 0x403F //RX_FDEQ_GAIN_11 +208 0x3F40 //RX_FDEQ_GAIN_12 +209 0x4248 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0050 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7220 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x01A0 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x484B //RX_FDEQ_GAIN_6 +203 0x4B48 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4846 //RX_FDEQ_GAIN_10 +207 0x403F //RX_FDEQ_GAIN_11 +208 0x3F40 //RX_FDEQ_GAIN_12 +209 0x4248 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0087 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7220 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x01A0 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x484B //RX_FDEQ_GAIN_6 +203 0x4B48 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4846 //RX_FDEQ_GAIN_10 +207 0x403F //RX_FDEQ_GAIN_11 +208 0x3F40 //RX_FDEQ_GAIN_12 +209 0x4248 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME HEADSET-USB_BLACKBIRD-VOICE_GENERIC-SWB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0009 //TX_OPERATION_MODE_0 +1 0x0001 //TX_OPERATION_MODE_1 +2 0x0033 //TX_PATCH_REG +3 0x6B68 //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0001 //TX_NUM_MIC +6 0x0003 //TX_SAMPLINGFREQ_SIG +7 0x0003 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009B //TX_DIST2REF1 +22 0x0000 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0B80 //TX_PGA_0 +28 0x0800 //TX_PGA_1 +29 0x0800 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0000 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0001 //TX_MIC_DATA_SRC1 +43 0x0002 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3E00 //TX_DIST2REF_11 +73 0x0000 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0200 //TX_MIC_REFBLK_VOLUME +108 0x0800 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0000 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7EFF //TX_A_HP +129 0x4000 //TX_B_PE +130 0x1800 //TX_THR_PITCH_DET_0 +131 0x1000 //TX_THR_PITCH_DET_1 +132 0x0800 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x001E //TX_TAIL_LENGTH +147 0x0080 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x6D60 //TX_EAD_THR +151 0x0800 //TX_THR_RE_EST +152 0x0800 //TX_MIN_EQ_RE_EST_0 +153 0x0800 //TX_MIN_EQ_RE_EST_1 +154 0x0800 //TX_MIN_EQ_RE_EST_2 +155 0x0800 //TX_MIN_EQ_RE_EST_3 +156 0x0800 //TX_MIN_EQ_RE_EST_4 +157 0x0800 //TX_MIN_EQ_RE_EST_5 +158 0x0800 //TX_MIN_EQ_RE_EST_6 +159 0x0800 //TX_MIN_EQ_RE_EST_7 +160 0x0800 //TX_MIN_EQ_RE_EST_8 +161 0x0800 //TX_MIN_EQ_RE_EST_9 +162 0x0800 //TX_MIN_EQ_RE_EST_10 +163 0x0800 //TX_MIN_EQ_RE_EST_11 +164 0x0800 //TX_MIN_EQ_RE_EST_12 +165 0x4000 //TX_LAMBDA_RE_EST +166 0x2000 //TX_LAMBDA_CB_NLE +167 0x6000 //TX_C_POST_FLT +168 0x7000 //TX_GAIN_NP +169 0x00C8 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x03E8 //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x7D00 //TX_DTD_THR1_0 +198 0x7D00 //TX_DTD_THR1_1 +199 0x7FFF //TX_DTD_THR1_2 +200 0x7FFF //TX_DTD_THR1_3 +201 0x7FFF //TX_DTD_THR1_4 +202 0x7FFF //TX_DTD_THR1_5 +203 0x7FFF //TX_DTD_THR1_6 +204 0x0CCD //TX_DTD_THR2_0 +205 0x0CCD //TX_DTD_THR2_1 +206 0x0CCD //TX_DTD_THR2_2 +207 0x0CCD //TX_DTD_THR2_3 +208 0x0CCD //TX_DTD_THR2_4 +209 0x0CCD //TX_DTD_THR2_5 +210 0x0CCD //TX_DTD_THR2_6 +211 0x7FFF //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x0BB8 //TX_DT_CUT_K +214 0x0CCD //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x0400 //TX_ADPT_STRICT_L +222 0x0200 //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x0800 //TX_B_POST_FILT_ECHO_L +229 0x7FFF //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x7FFF //TX_B_LESSCUT_RTO_ECHO +232 0x00F0 //TX_EPD_OFFSET_00 +233 0x00F0 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x7FFF //TX_DTD_THR1_7 +238 0x7FFF //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xFA00 //TX_THR_SN_EST_0 +243 0xFA00 //TX_THR_SN_EST_1 +244 0xF700 //TX_THR_SN_EST_2 +245 0xFA00 //TX_THR_SN_EST_3 +246 0xF800 //TX_THR_SN_EST_4 +247 0xF400 //TX_THR_SN_EST_5 +248 0xF400 //TX_THR_SN_EST_6 +249 0xF600 //TX_THR_SN_EST_7 +250 0x0000 //TX_DELTA_THR_SN_EST_0 +251 0x0200 //TX_DELTA_THR_SN_EST_1 +252 0x0200 //TX_DELTA_THR_SN_EST_2 +253 0x0100 //TX_DELTA_THR_SN_EST_3 +254 0x0200 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0100 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x6000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x6000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x1000 //TX_B_POST_FLT_0 +280 0x1000 //TX_B_POST_FLT_1 +281 0x000F //TX_NS_LVL_CTRL_0 +282 0x0014 //TX_NS_LVL_CTRL_1 +283 0x0018 //TX_NS_LVL_CTRL_2 +284 0x0012 //TX_NS_LVL_CTRL_3 +285 0x000F //TX_NS_LVL_CTRL_4 +286 0x000F //TX_NS_LVL_CTRL_5 +287 0x0018 //TX_NS_LVL_CTRL_6 +288 0x0011 //TX_NS_LVL_CTRL_7 +289 0x000C //TX_MIN_GAIN_S_0 +290 0x000F //TX_MIN_GAIN_S_1 +291 0x000C //TX_MIN_GAIN_S_2 +292 0x0009 //TX_MIN_GAIN_S_3 +293 0x000C //TX_MIN_GAIN_S_4 +294 0x000C //TX_MIN_GAIN_S_5 +295 0x000C //TX_MIN_GAIN_S_6 +296 0x000F //TX_MIN_GAIN_S_7 +297 0x7FFF //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x6000 //TX_SNRI_SUP_1 +302 0x5000 //TX_SNRI_SUP_2 +303 0x6000 //TX_SNRI_SUP_3 +304 0x7FFF //TX_SNRI_SUP_4 +305 0x7FFF //TX_SNRI_SUP_5 +306 0x7FFF //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x000E //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x4000 //TX_A_POST_FILT_S_0 +315 0x5000 //TX_A_POST_FILT_S_1 +316 0x5000 //TX_A_POST_FILT_S_2 +317 0x5000 //TX_A_POST_FILT_S_3 +318 0x5000 //TX_A_POST_FILT_S_4 +319 0x5000 //TX_A_POST_FILT_S_5 +320 0x4000 //TX_A_POST_FILT_S_6 +321 0x5000 //TX_A_POST_FILT_S_7 +322 0x1000 //TX_B_POST_FILT_0 +323 0x1000 //TX_B_POST_FILT_1 +324 0x3000 //TX_B_POST_FILT_2 +325 0x1000 //TX_B_POST_FILT_3 +326 0x1000 //TX_B_POST_FILT_4 +327 0x1000 //TX_B_POST_FILT_5 +328 0x1000 //TX_B_POST_FILT_6 +329 0x1000 //TX_B_POST_FILT_7 +330 0x7FFF //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x7FFF //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7CCD //TX_LAMBDA_PFILT +339 0x7B00 //TX_LAMBDA_PFILT_S_0 +340 0x7B00 //TX_LAMBDA_PFILT_S_1 +341 0x7000 //TX_LAMBDA_PFILT_S_2 +342 0x7B00 //TX_LAMBDA_PFILT_S_3 +343 0x7B00 //TX_LAMBDA_PFILT_S_4 +344 0x7B00 //TX_LAMBDA_PFILT_S_5 +345 0x7F00 //TX_LAMBDA_PFILT_S_6 +346 0x7B00 //TX_LAMBDA_PFILT_S_7 +347 0x0200 //TX_K_PEPPER +348 0x0400 //TX_A_PEPPER +349 0x1EAA //TX_K_PEPPER_HF +350 0x0800 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0800 //TX_DT_BINVAD_TH_0 +354 0x0800 //TX_DT_BINVAD_TH_1 +355 0x0800 //TX_DT_BINVAD_TH_2 +356 0x0800 //TX_DT_BINVAD_TH_3 +357 0x1D4C //TX_DT_BINVAD_ENDF +358 0x0000 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0190 //TX_NDETCT +367 0x0383 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x07D0 //TX_NOISE_TH_1 +371 0x00C8 //TX_NOISE_TH_2 +372 0x2904 //TX_NOISE_TH_3 +373 0x0FA0 //TX_NOISE_TH_4 +374 0x157C //TX_NOISE_TH_5 +375 0x7FFF //TX_NOISE_TH_5_2 +376 0x7FFF //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x044C //TX_NOISE_TH_6 +379 0x044C //TX_MINENOISE_TH +380 0xD508 //TX_MORENS_TFMASK_TH +381 0x0001 //TX_DRC_QUIET_FLOOR +382 0x3A98 //TX_RATIODTL_CUT_TH +383 0x0DAC //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x0333 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x7FFF //TX_POST_MASK_SUP_HSNE +392 0x1388 //TX_TAIL_DET_TH +393 0x4000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0080 //TX_SUPHIGH_TH +396 0x0000 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x1800 //TX_C_POST_FLT_MASK +399 0x7FFF //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0004 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x02F3 //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x7FFF //TX_MIN_G_CTRL_SSNS +409 0x0800 //TX_METAL_RTO_THR +410 0x4848 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x4000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x01E0 //TX_NOR_OFF_THR +498 0x7C00 //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0xD333 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x6000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0xC000 //TX_DEREVERB_LF_MU +515 0xC000 //TX_DEREVERB_HF_MU +516 0xCCCC //TX_DEREVERB_DELAY +517 0xD999 //TX_DEREVERB_COEF_LEN +518 0x1F40 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x7000 //TX_GSC_RTOH_TH +523 0x0064 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0020 //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4848 //TX_FDEQ_GAIN_5 +573 0x4040 //TX_FDEQ_GAIN_6 +574 0x4040 //TX_FDEQ_GAIN_7 +575 0x4040 //TX_FDEQ_GAIN_8 +576 0x3838 //TX_FDEQ_GAIN_9 +577 0x3838 //TX_FDEQ_GAIN_10 +578 0x3828 //TX_FDEQ_GAIN_11 +579 0x2828 //TX_FDEQ_GAIN_12 +580 0x2828 //TX_FDEQ_GAIN_13 +581 0x1C1C //TX_FDEQ_GAIN_14 +582 0x1C1C //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0303 //TX_FDEQ_BIN_2 +594 0x0304 //TX_FDEQ_BIN_3 +595 0x0405 //TX_FDEQ_BIN_4 +596 0x0506 //TX_FDEQ_BIN_5 +597 0x0708 //TX_FDEQ_BIN_6 +598 0x090A //TX_FDEQ_BIN_7 +599 0x0B0C //TX_FDEQ_BIN_8 +600 0x0D0E //TX_FDEQ_BIN_9 +601 0x1013 //TX_FDEQ_BIN_10 +602 0x1719 //TX_FDEQ_BIN_11 +603 0x1B1E //TX_FDEQ_BIN_12 +604 0x1E1E //TX_FDEQ_BIN_13 +605 0x1E28 //TX_FDEQ_BIN_14 +606 0x284A //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4848 //TX_PREEQ_GAIN_MIC0_8 +626 0x4848 //TX_PREEQ_GAIN_MIC0_9 +627 0x4848 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0E10 //TX_PREEQ_BIN_MIC0_0 +642 0x1010 //TX_PREEQ_BIN_MIC0_1 +643 0x1010 //TX_PREEQ_BIN_MIC0_2 +644 0x1010 //TX_PREEQ_BIN_MIC0_3 +645 0x1010 //TX_PREEQ_BIN_MIC0_4 +646 0x1010 //TX_PREEQ_BIN_MIC0_5 +647 0x1010 //TX_PREEQ_BIN_MIC0_6 +648 0x1010 //TX_PREEQ_BIN_MIC0_7 +649 0x1010 //TX_PREEQ_BIN_MIC0_8 +650 0x1010 //TX_PREEQ_BIN_MIC0_9 +651 0x1010 //TX_PREEQ_BIN_MIC0_10 +652 0x1010 //TX_PREEQ_BIN_MIC0_11 +653 0x1010 //TX_PREEQ_BIN_MIC0_12 +654 0x1010 //TX_PREEQ_BIN_MIC0_13 +655 0x1010 //TX_PREEQ_BIN_MIC0_14 +656 0x0200 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0E10 //TX_PREEQ_BIN_MIC1_0 +691 0x1010 //TX_PREEQ_BIN_MIC1_1 +692 0x1010 //TX_PREEQ_BIN_MIC1_2 +693 0x1010 //TX_PREEQ_BIN_MIC1_3 +694 0x1010 //TX_PREEQ_BIN_MIC1_4 +695 0x1010 //TX_PREEQ_BIN_MIC1_5 +696 0x1010 //TX_PREEQ_BIN_MIC1_6 +697 0x1010 //TX_PREEQ_BIN_MIC1_7 +698 0x1010 //TX_PREEQ_BIN_MIC1_8 +699 0x1010 //TX_PREEQ_BIN_MIC1_9 +700 0x1010 //TX_PREEQ_BIN_MIC1_10 +701 0x1010 //TX_PREEQ_BIN_MIC1_11 +702 0x1010 //TX_PREEQ_BIN_MIC1_12 +703 0x1010 //TX_PREEQ_BIN_MIC1_13 +704 0x1010 //TX_PREEQ_BIN_MIC1_14 +705 0x0200 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0E10 //TX_PREEQ_BIN_MIC2_0 +740 0x1010 //TX_PREEQ_BIN_MIC2_1 +741 0x1010 //TX_PREEQ_BIN_MIC2_2 +742 0x1010 //TX_PREEQ_BIN_MIC2_3 +743 0x1010 //TX_PREEQ_BIN_MIC2_4 +744 0x1010 //TX_PREEQ_BIN_MIC2_5 +745 0x1010 //TX_PREEQ_BIN_MIC2_6 +746 0x1010 //TX_PREEQ_BIN_MIC2_7 +747 0x1010 //TX_PREEQ_BIN_MIC2_8 +748 0x1010 //TX_PREEQ_BIN_MIC2_9 +749 0x1010 //TX_PREEQ_BIN_MIC2_10 +750 0x1010 //TX_PREEQ_BIN_MIC2_11 +751 0x1010 //TX_PREEQ_BIN_MIC2_12 +752 0x1010 //TX_PREEQ_BIN_MIC2_13 +753 0x1010 //TX_PREEQ_BIN_MIC2_14 +754 0x0200 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x0800 //TX_NND_WEIGHT +765 0x0062 //TX_MIC_CALIBRATION_0 +766 0x0062 //TX_MIC_CALIBRATION_1 +767 0x0062 //TX_MIC_CALIBRATION_2 +768 0x0062 //TX_MIC_CALIBRATION_3 +769 0x0046 //TX_MIC_PWR_BIAS_0 +770 0x0046 //TX_MIC_PWR_BIAS_1 +771 0x0046 //TX_MIC_PWR_BIAS_2 +772 0x0046 //TX_MIC_PWR_BIAS_3 +773 0x000C //TX_GAIN_LIMIT_0 +774 0x000C //TX_GAIN_LIMIT_1 +775 0x000C //TX_GAIN_LIMIT_2 +776 0x000C //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x3000 //TX_TDDRC_ALPHA_UP_01 +784 0x3000 //TX_TDDRC_ALPHA_UP_02 +785 0x3000 //TX_TDDRC_ALPHA_UP_03 +786 0x3000 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x78D6 //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0000 //TX_DEADMIC_SILENCE_TH +817 0x0000 //TX_MIC_DEGRADE_TH +818 0x0000 //TX_DEADMIC_CNT +819 0x0000 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x4848 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0000 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0000 //TX_FILTINDX +854 0x0000 //TX_TDDRC_THRD_0 +855 0x0020 //TX_TDDRC_THRD_1 +856 0x2000 //TX_TDDRC_THRD_2 +857 0x2000 //TX_TDDRC_THRD_3 +858 0x3000 //TX_TDDRC_SLANT_0 +859 0x6E00 //TX_TDDRC_SLANT_1 +860 0x3000 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x07F2 //TX_TDDRC_DRC_GAIN +867 0x78D6 //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0x0CCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x0000 //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x00C8 //TX_FASTNS_ARSPC_TH +889 0x8000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x4000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x2339 //TX_SENDFUNC_REG_MICMUTE +898 0x0021 //TX_SENDFUNC_REG_MICMUTE1 +899 0x02BC //TX_MICMUTE_RATIO_THR +900 0x0140 //TX_MICMUTE_AMP_THR +901 0x0004 //TX_MICMUTE_HPF_IND +902 0x00C0 //TX_MICMUTE_LOG_EYR_TH +903 0x0008 //TX_MICMUTE_CVG_TIME +904 0x0008 //TX_MICMUTE_RELEASE_TIME +905 0x01FE //TX_MIC_VOLUME_MIC0MUTE +906 0x0020 //TX_MICMUTE_EPD_OFFSET_0 +907 0x001E //TX_MICMUTE_FRQ_AEC_L +908 0x7999 //TX_MICMUTE_EAD_THR +909 0x7FFF //TX_MICMUTE_LAMBDA_CB_NLE +910 0x7FFF //TX_MICMUTE_LAMBDA_RE_EST +911 0x4000 //TX_DTD_THR1_MICMUTE_0 +912 0x7000 //TX_DTD_THR1_MICMUTE_1 +913 0x7FFF //TX_DTD_THR1_MICMUTE_2 +914 0x7FFF //TX_DTD_THR1_MICMUTE_3 +915 0x6CCC //TX_DTD_THR2_MICMUTE_0 +916 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x1000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x4000 //TX_MICMUTE_C_POST_FLT +922 0x03E8 //TX_MICMUTE_DT_CUT_K +923 0x0001 //TX_MICMUTE_DT_CUT_THR +924 0x03E8 //TX_MICMUTE_DT_CUT_K2 +925 0x0001 //TX_MICMUTE_DT_CUT_THR2 +926 0x0064 //TX_MICMUTE_DT2_HOLD_N +927 0x1000 //TX_MICMUTE_RATIODTH_THCUT +928 0x1000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x7FFF //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0400 //TX_MICMUTE_C_POST_FLT_MASK +931 0x7999 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0258 //TX_MICMUTE_DT_CUT_K1 +933 0x0800 //TX_MICMUTE_N2_SN_EST +934 0xFC00 //TX_MICMUTE_THR_SN_EST_0 +935 0x001C //TX_MICMUTE_MIN_G_CTRL_0 +936 0x6000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x7000 //TX_MICMUTE_B_POST_FILT_0 +938 0x2710 //TX_MIC1RUB_AMP_THR +939 0x0010 //TX_MIC1MUTE_RATIO_THR +940 0x0450 //TX_MIC1MUTE_AMP_THR +941 0x0008 //TX_MIC1MUTE_CVG_TIME +942 0x0008 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x242C //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0003 //RX_SAMPLINGFREQ_SIG +3 0x0003 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x5000 //RX_TDDRC_ALPHA_UP_1 +7 0x5000 //RX_TDDRC_ALPHA_UP_2 +8 0x5000 //RX_TDDRC_ALPHA_UP_3 +9 0x2000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7FFF //RX_A_HP +12 0x0000 //RX_B_PE +13 0x1800 //RX_THR_PITCH_DET_0 +14 0x1000 //RX_THR_PITCH_DET_1 +15 0x0800 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0400 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x0003 //RX_NS_LVL_CTRL +23 0x9000 //RX_THR_SN_EST +24 0x7CCD //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x65AD //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4E52 //RX_FDEQ_GAIN_0 +40 0x5252 //RX_FDEQ_GAIN_1 +41 0x5252 //RX_FDEQ_GAIN_2 +42 0x5250 //RX_FDEQ_GAIN_3 +43 0x4C46 //RX_FDEQ_GAIN_4 +44 0x4748 //RX_FDEQ_GAIN_5 +45 0x5768 //RX_FDEQ_GAIN_6 +46 0x6162 //RX_FDEQ_GAIN_7 +47 0x5252 //RX_FDEQ_GAIN_8 +48 0x5256 //RX_FDEQ_GAIN_9 +49 0x5248 //RX_FDEQ_GAIN_10 +50 0x3434 //RX_FDEQ_GAIN_11 +51 0x3436 //RX_FDEQ_GAIN_12 +52 0x2A18 //RX_FDEQ_GAIN_13 +53 0x1830 //RX_FDEQ_GAIN_14 +54 0x3648 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x284A //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0002 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x5000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x023E //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x280A //RX_TPKA_FP +127 0x032D //RX_MIN_G_FP +128 0x0A00 //RX_MAX_G_FP +129 0x000B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x5000 //RX_TDDRC_ALPHA_UP_1 +7 0x5000 //RX_TDDRC_ALPHA_UP_2 +8 0x5000 //RX_TDDRC_ALPHA_UP_3 +9 0x2000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7220 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x5000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0214 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x6270 //RX_FDEQ_GAIN_0 +40 0x7A70 //RX_FDEQ_GAIN_1 +41 0x7270 //RX_FDEQ_GAIN_2 +42 0x6A70 //RX_FDEQ_GAIN_3 +43 0x645A //RX_FDEQ_GAIN_4 +44 0x5A5E //RX_FDEQ_GAIN_5 +45 0x6E72 //RX_FDEQ_GAIN_6 +46 0x7268 //RX_FDEQ_GAIN_7 +47 0x665A //RX_FDEQ_GAIN_8 +48 0x5A5A //RX_FDEQ_GAIN_9 +49 0x5A64 //RX_FDEQ_GAIN_10 +50 0x6448 //RX_FDEQ_GAIN_11 +51 0x4949 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x284A //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x000A //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x5000 //RX_TDDRC_ALPHA_UP_1 +7 0x5000 //RX_TDDRC_ALPHA_UP_2 +8 0x5000 //RX_TDDRC_ALPHA_UP_3 +9 0x2000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7220 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x5000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0214 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x6270 //RX_FDEQ_GAIN_0 +40 0x7A70 //RX_FDEQ_GAIN_1 +41 0x7270 //RX_FDEQ_GAIN_2 +42 0x6A70 //RX_FDEQ_GAIN_3 +43 0x645A //RX_FDEQ_GAIN_4 +44 0x5A5E //RX_FDEQ_GAIN_5 +45 0x6E72 //RX_FDEQ_GAIN_6 +46 0x7268 //RX_FDEQ_GAIN_7 +47 0x665A //RX_FDEQ_GAIN_8 +48 0x5A5A //RX_FDEQ_GAIN_9 +49 0x5A64 //RX_FDEQ_GAIN_10 +50 0x6448 //RX_FDEQ_GAIN_11 +51 0x4949 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x284A //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0011 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x5000 //RX_TDDRC_ALPHA_UP_1 +7 0x5000 //RX_TDDRC_ALPHA_UP_2 +8 0x5000 //RX_TDDRC_ALPHA_UP_3 +9 0x2000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7220 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x5000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0214 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x6270 //RX_FDEQ_GAIN_0 +40 0x7A70 //RX_FDEQ_GAIN_1 +41 0x7270 //RX_FDEQ_GAIN_2 +42 0x6A70 //RX_FDEQ_GAIN_3 +43 0x645A //RX_FDEQ_GAIN_4 +44 0x5A5E //RX_FDEQ_GAIN_5 +45 0x6E72 //RX_FDEQ_GAIN_6 +46 0x7268 //RX_FDEQ_GAIN_7 +47 0x665A //RX_FDEQ_GAIN_8 +48 0x5A5A //RX_FDEQ_GAIN_9 +49 0x5A64 //RX_FDEQ_GAIN_10 +50 0x6448 //RX_FDEQ_GAIN_11 +51 0x4949 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x284A //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x001C //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x5000 //RX_TDDRC_ALPHA_UP_1 +7 0x5000 //RX_TDDRC_ALPHA_UP_2 +8 0x5000 //RX_TDDRC_ALPHA_UP_3 +9 0x2000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7220 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x5000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0214 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x6270 //RX_FDEQ_GAIN_0 +40 0x7A70 //RX_FDEQ_GAIN_1 +41 0x7270 //RX_FDEQ_GAIN_2 +42 0x6A70 //RX_FDEQ_GAIN_3 +43 0x645A //RX_FDEQ_GAIN_4 +44 0x5A5E //RX_FDEQ_GAIN_5 +45 0x6E72 //RX_FDEQ_GAIN_6 +46 0x7268 //RX_FDEQ_GAIN_7 +47 0x665A //RX_FDEQ_GAIN_8 +48 0x5A5A //RX_FDEQ_GAIN_9 +49 0x5A64 //RX_FDEQ_GAIN_10 +50 0x6448 //RX_FDEQ_GAIN_11 +51 0x4949 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x284A //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x002F //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x5000 //RX_TDDRC_ALPHA_UP_1 +7 0x5000 //RX_TDDRC_ALPHA_UP_2 +8 0x5000 //RX_TDDRC_ALPHA_UP_3 +9 0x2000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7220 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x5000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0214 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x6270 //RX_FDEQ_GAIN_0 +40 0x7A70 //RX_FDEQ_GAIN_1 +41 0x7270 //RX_FDEQ_GAIN_2 +42 0x6A70 //RX_FDEQ_GAIN_3 +43 0x645A //RX_FDEQ_GAIN_4 +44 0x5A5E //RX_FDEQ_GAIN_5 +45 0x6E72 //RX_FDEQ_GAIN_6 +46 0x7268 //RX_FDEQ_GAIN_7 +47 0x665A //RX_FDEQ_GAIN_8 +48 0x5A5A //RX_FDEQ_GAIN_9 +49 0x5A64 //RX_FDEQ_GAIN_10 +50 0x6448 //RX_FDEQ_GAIN_11 +51 0x4949 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x284A //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x004F //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x5000 //RX_TDDRC_ALPHA_UP_1 +7 0x5000 //RX_TDDRC_ALPHA_UP_2 +8 0x5000 //RX_TDDRC_ALPHA_UP_3 +9 0x2000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7220 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x5000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0214 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x6270 //RX_FDEQ_GAIN_0 +40 0x7A70 //RX_FDEQ_GAIN_1 +41 0x7270 //RX_FDEQ_GAIN_2 +42 0x6A70 //RX_FDEQ_GAIN_3 +43 0x645A //RX_FDEQ_GAIN_4 +44 0x5A5E //RX_FDEQ_GAIN_5 +45 0x6E72 //RX_FDEQ_GAIN_6 +46 0x7268 //RX_FDEQ_GAIN_7 +47 0x665A //RX_FDEQ_GAIN_8 +48 0x5A5A //RX_FDEQ_GAIN_9 +49 0x5A64 //RX_FDEQ_GAIN_10 +50 0x6448 //RX_FDEQ_GAIN_11 +51 0x4949 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x284A //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0086 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x5000 //RX_TDDRC_ALPHA_UP_1 +7 0x5000 //RX_TDDRC_ALPHA_UP_2 +8 0x5000 //RX_TDDRC_ALPHA_UP_3 +9 0x2000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7220 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x5000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0214 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x6270 //RX_FDEQ_GAIN_0 +40 0x7A70 //RX_FDEQ_GAIN_1 +41 0x7270 //RX_FDEQ_GAIN_2 +42 0x6A70 //RX_FDEQ_GAIN_3 +43 0x645A //RX_FDEQ_GAIN_4 +44 0x5A5E //RX_FDEQ_GAIN_5 +45 0x6E72 //RX_FDEQ_GAIN_6 +46 0x7268 //RX_FDEQ_GAIN_7 +47 0x665A //RX_FDEQ_GAIN_8 +48 0x5A5A //RX_FDEQ_GAIN_9 +49 0x5A64 //RX_FDEQ_GAIN_10 +50 0x6448 //RX_FDEQ_GAIN_11 +51 0x4949 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x284A //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x242C //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0003 //RX_SAMPLINGFREQ_SIG +160 0x0003 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x5000 //RX_TDDRC_ALPHA_UP_1 +164 0x5000 //RX_TDDRC_ALPHA_UP_2 +165 0x5000 //RX_TDDRC_ALPHA_UP_3 +166 0x2000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7FFF //RX_A_HP +169 0x0000 //RX_B_PE +170 0x1800 //RX_THR_PITCH_DET_0 +171 0x1000 //RX_THR_PITCH_DET_1 +172 0x0800 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0400 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x0003 //RX_NS_LVL_CTRL +180 0x9000 //RX_THR_SN_EST +181 0x7CCD //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x65AD //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4E52 //RX_FDEQ_GAIN_0 +197 0x5252 //RX_FDEQ_GAIN_1 +198 0x5252 //RX_FDEQ_GAIN_2 +199 0x5250 //RX_FDEQ_GAIN_3 +200 0x4C46 //RX_FDEQ_GAIN_4 +201 0x4748 //RX_FDEQ_GAIN_5 +202 0x5768 //RX_FDEQ_GAIN_6 +203 0x6162 //RX_FDEQ_GAIN_7 +204 0x5252 //RX_FDEQ_GAIN_8 +205 0x5256 //RX_FDEQ_GAIN_9 +206 0x5248 //RX_FDEQ_GAIN_10 +207 0x3434 //RX_FDEQ_GAIN_11 +208 0x3436 //RX_FDEQ_GAIN_12 +209 0x2A18 //RX_FDEQ_GAIN_13 +210 0x1830 //RX_FDEQ_GAIN_14 +211 0x3648 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x284A //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0002 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x5000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x023E //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x280A //RX_TPKA_FP +284 0x032D //RX_MIN_G_FP +285 0x0A00 //RX_MAX_G_FP +286 0x000B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x5000 //RX_TDDRC_ALPHA_UP_1 +164 0x5000 //RX_TDDRC_ALPHA_UP_2 +165 0x5000 //RX_TDDRC_ALPHA_UP_3 +166 0x2000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7220 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x5000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0214 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x6270 //RX_FDEQ_GAIN_0 +197 0x7A70 //RX_FDEQ_GAIN_1 +198 0x7270 //RX_FDEQ_GAIN_2 +199 0x6A70 //RX_FDEQ_GAIN_3 +200 0x645A //RX_FDEQ_GAIN_4 +201 0x5A5E //RX_FDEQ_GAIN_5 +202 0x6E72 //RX_FDEQ_GAIN_6 +203 0x7268 //RX_FDEQ_GAIN_7 +204 0x665A //RX_FDEQ_GAIN_8 +205 0x5A5A //RX_FDEQ_GAIN_9 +206 0x5A64 //RX_FDEQ_GAIN_10 +207 0x6448 //RX_FDEQ_GAIN_11 +208 0x4949 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x284A //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x000A //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x5000 //RX_TDDRC_ALPHA_UP_1 +164 0x5000 //RX_TDDRC_ALPHA_UP_2 +165 0x5000 //RX_TDDRC_ALPHA_UP_3 +166 0x2000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7220 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x5000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0214 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x6270 //RX_FDEQ_GAIN_0 +197 0x7A70 //RX_FDEQ_GAIN_1 +198 0x7270 //RX_FDEQ_GAIN_2 +199 0x6A70 //RX_FDEQ_GAIN_3 +200 0x645A //RX_FDEQ_GAIN_4 +201 0x5A5E //RX_FDEQ_GAIN_5 +202 0x6E72 //RX_FDEQ_GAIN_6 +203 0x7268 //RX_FDEQ_GAIN_7 +204 0x665A //RX_FDEQ_GAIN_8 +205 0x5A5A //RX_FDEQ_GAIN_9 +206 0x5A64 //RX_FDEQ_GAIN_10 +207 0x6448 //RX_FDEQ_GAIN_11 +208 0x4949 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x284A //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0011 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x5000 //RX_TDDRC_ALPHA_UP_1 +164 0x5000 //RX_TDDRC_ALPHA_UP_2 +165 0x5000 //RX_TDDRC_ALPHA_UP_3 +166 0x2000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7220 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x5000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0214 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x6270 //RX_FDEQ_GAIN_0 +197 0x7A70 //RX_FDEQ_GAIN_1 +198 0x7270 //RX_FDEQ_GAIN_2 +199 0x6A70 //RX_FDEQ_GAIN_3 +200 0x645A //RX_FDEQ_GAIN_4 +201 0x5A5E //RX_FDEQ_GAIN_5 +202 0x6E72 //RX_FDEQ_GAIN_6 +203 0x7268 //RX_FDEQ_GAIN_7 +204 0x665A //RX_FDEQ_GAIN_8 +205 0x5A5A //RX_FDEQ_GAIN_9 +206 0x5A64 //RX_FDEQ_GAIN_10 +207 0x6448 //RX_FDEQ_GAIN_11 +208 0x4949 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x284A //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x001C //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x5000 //RX_TDDRC_ALPHA_UP_1 +164 0x5000 //RX_TDDRC_ALPHA_UP_2 +165 0x5000 //RX_TDDRC_ALPHA_UP_3 +166 0x2000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7220 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x5000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0214 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x6270 //RX_FDEQ_GAIN_0 +197 0x7A70 //RX_FDEQ_GAIN_1 +198 0x7270 //RX_FDEQ_GAIN_2 +199 0x6A70 //RX_FDEQ_GAIN_3 +200 0x645A //RX_FDEQ_GAIN_4 +201 0x5A5E //RX_FDEQ_GAIN_5 +202 0x6E72 //RX_FDEQ_GAIN_6 +203 0x7268 //RX_FDEQ_GAIN_7 +204 0x665A //RX_FDEQ_GAIN_8 +205 0x5A5A //RX_FDEQ_GAIN_9 +206 0x5A64 //RX_FDEQ_GAIN_10 +207 0x6448 //RX_FDEQ_GAIN_11 +208 0x4949 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x284A //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x002F //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x5000 //RX_TDDRC_ALPHA_UP_1 +164 0x5000 //RX_TDDRC_ALPHA_UP_2 +165 0x5000 //RX_TDDRC_ALPHA_UP_3 +166 0x2000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7220 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x5000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0214 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x6270 //RX_FDEQ_GAIN_0 +197 0x7A70 //RX_FDEQ_GAIN_1 +198 0x7270 //RX_FDEQ_GAIN_2 +199 0x6A70 //RX_FDEQ_GAIN_3 +200 0x645A //RX_FDEQ_GAIN_4 +201 0x5A5E //RX_FDEQ_GAIN_5 +202 0x6E72 //RX_FDEQ_GAIN_6 +203 0x7268 //RX_FDEQ_GAIN_7 +204 0x665A //RX_FDEQ_GAIN_8 +205 0x5A5A //RX_FDEQ_GAIN_9 +206 0x5A64 //RX_FDEQ_GAIN_10 +207 0x6448 //RX_FDEQ_GAIN_11 +208 0x4949 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x284A //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x004F //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x5000 //RX_TDDRC_ALPHA_UP_1 +164 0x5000 //RX_TDDRC_ALPHA_UP_2 +165 0x5000 //RX_TDDRC_ALPHA_UP_3 +166 0x2000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7220 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x5000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0214 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x6270 //RX_FDEQ_GAIN_0 +197 0x7A70 //RX_FDEQ_GAIN_1 +198 0x7270 //RX_FDEQ_GAIN_2 +199 0x6A70 //RX_FDEQ_GAIN_3 +200 0x645A //RX_FDEQ_GAIN_4 +201 0x5A5E //RX_FDEQ_GAIN_5 +202 0x6E72 //RX_FDEQ_GAIN_6 +203 0x7268 //RX_FDEQ_GAIN_7 +204 0x665A //RX_FDEQ_GAIN_8 +205 0x5A5A //RX_FDEQ_GAIN_9 +206 0x5A64 //RX_FDEQ_GAIN_10 +207 0x6448 //RX_FDEQ_GAIN_11 +208 0x4949 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x284A //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0086 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x5000 //RX_TDDRC_ALPHA_UP_1 +164 0x5000 //RX_TDDRC_ALPHA_UP_2 +165 0x5000 //RX_TDDRC_ALPHA_UP_3 +166 0x2000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7220 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x5000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0214 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x6270 //RX_FDEQ_GAIN_0 +197 0x7A70 //RX_FDEQ_GAIN_1 +198 0x7270 //RX_FDEQ_GAIN_2 +199 0x6A70 //RX_FDEQ_GAIN_3 +200 0x645A //RX_FDEQ_GAIN_4 +201 0x5A5E //RX_FDEQ_GAIN_5 +202 0x6E72 //RX_FDEQ_GAIN_6 +203 0x7268 //RX_FDEQ_GAIN_7 +204 0x665A //RX_FDEQ_GAIN_8 +205 0x5A5A //RX_FDEQ_GAIN_9 +206 0x5A64 //RX_FDEQ_GAIN_10 +207 0x6448 //RX_FDEQ_GAIN_11 +208 0x4949 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x284A //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME HEADSET-USB_BLACKBIRD-VOICE_GENERIC-FB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0009 //TX_OPERATION_MODE_0 +1 0x0009 //TX_OPERATION_MODE_1 +2 0x0020 //TX_PATCH_REG +3 0x6B6A //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0001 //TX_NUM_MIC +6 0x0004 //TX_SAMPLINGFREQ_SIG +7 0x0004 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009B //TX_DIST2REF1 +22 0x0000 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0B4C //TX_PGA_0 +28 0x0800 //TX_PGA_1 +29 0x0000 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0000 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0001 //TX_MIC_DATA_SRC1 +43 0x0002 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3E00 //TX_DIST2REF_11 +73 0x0000 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0200 //TX_MIC_REFBLK_VOLUME +108 0x0800 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0000 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7E56 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x6800 //TX_THR_PITCH_DET_0 +131 0x6000 //TX_THR_PITCH_DET_1 +132 0x5800 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x001E //TX_TAIL_LENGTH +147 0x0200 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x61A8 //TX_EAD_THR +151 0x0400 //TX_THR_RE_EST +152 0x3000 //TX_MIN_EQ_RE_EST_0 +153 0x3000 //TX_MIN_EQ_RE_EST_1 +154 0x4000 //TX_MIN_EQ_RE_EST_2 +155 0x0800 //TX_MIN_EQ_RE_EST_3 +156 0x0800 //TX_MIN_EQ_RE_EST_4 +157 0x0800 //TX_MIN_EQ_RE_EST_5 +158 0x6000 //TX_MIN_EQ_RE_EST_6 +159 0x6000 //TX_MIN_EQ_RE_EST_7 +160 0x6000 //TX_MIN_EQ_RE_EST_8 +161 0x6000 //TX_MIN_EQ_RE_EST_9 +162 0x4000 //TX_MIN_EQ_RE_EST_10 +163 0x4000 //TX_MIN_EQ_RE_EST_11 +164 0x4000 //TX_MIN_EQ_RE_EST_12 +165 0x3000 //TX_LAMBDA_RE_EST +166 0x4000 //TX_LAMBDA_CB_NLE +167 0x3000 //TX_C_POST_FLT +168 0x7FFF //TX_GAIN_NP +169 0x00C8 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x03E8 //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x0800 //TX_DTD_THR1_0 +198 0x0800 //TX_DTD_THR1_1 +199 0x0800 //TX_DTD_THR1_2 +200 0x0800 //TX_DTD_THR1_3 +201 0x0800 //TX_DTD_THR1_4 +202 0x0800 //TX_DTD_THR1_5 +203 0x0800 //TX_DTD_THR1_6 +204 0x0800 //TX_DTD_THR2_0 +205 0x0800 //TX_DTD_THR2_1 +206 0x0800 //TX_DTD_THR2_2 +207 0x0800 //TX_DTD_THR2_3 +208 0x0800 //TX_DTD_THR2_4 +209 0x0100 //TX_DTD_THR2_5 +210 0x0100 //TX_DTD_THR2_6 +211 0x7FFF //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x03E8 //TX_DT_CUT_K +214 0x0CCD //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x0400 //TX_ADPT_STRICT_L +222 0x0200 //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x0800 //TX_B_POST_FILT_ECHO_L +229 0x7FFF //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x7FFF //TX_B_LESSCUT_RTO_ECHO +232 0x00C0 //TX_EPD_OFFSET_00 +233 0x00C0 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x7FFF //TX_DTD_THR1_7 +238 0x7FFF //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xF700 //TX_THR_SN_EST_0 +243 0xFB00 //TX_THR_SN_EST_1 +244 0xFA00 //TX_THR_SN_EST_2 +245 0xF700 //TX_THR_SN_EST_3 +246 0xFA00 //TX_THR_SN_EST_4 +247 0xF600 //TX_THR_SN_EST_5 +248 0xF600 //TX_THR_SN_EST_6 +249 0xF600 //TX_THR_SN_EST_7 +250 0x0200 //TX_DELTA_THR_SN_EST_0 +251 0x0400 //TX_DELTA_THR_SN_EST_1 +252 0x0300 //TX_DELTA_THR_SN_EST_2 +253 0x0600 //TX_DELTA_THR_SN_EST_3 +254 0x0200 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0200 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x4000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x4000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x2000 //TX_B_POST_FLT_0 +280 0x2000 //TX_B_POST_FLT_1 +281 0x0012 //TX_NS_LVL_CTRL_0 +282 0x0020 //TX_NS_LVL_CTRL_1 +283 0x0016 //TX_NS_LVL_CTRL_2 +284 0x0019 //TX_NS_LVL_CTRL_3 +285 0x0010 //TX_NS_LVL_CTRL_4 +286 0x0010 //TX_NS_LVL_CTRL_5 +287 0x0019 //TX_NS_LVL_CTRL_6 +288 0x0010 //TX_NS_LVL_CTRL_7 +289 0x000C //TX_MIN_GAIN_S_0 +290 0x000C //TX_MIN_GAIN_S_1 +291 0x000C //TX_MIN_GAIN_S_2 +292 0x000F //TX_MIN_GAIN_S_3 +293 0x000C //TX_MIN_GAIN_S_4 +294 0x000C //TX_MIN_GAIN_S_5 +295 0x0011 //TX_MIN_GAIN_S_6 +296 0x000C //TX_MIN_GAIN_S_7 +297 0x0800 //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7000 //TX_SNRI_SUP_0 +301 0x1000 //TX_SNRI_SUP_1 +302 0x7000 //TX_SNRI_SUP_2 +303 0x6000 //TX_SNRI_SUP_3 +304 0x7FFF //TX_SNRI_SUP_4 +305 0x7FFF //TX_SNRI_SUP_5 +306 0x6000 //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x0016 //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x6000 //TX_A_POST_FILT_S_0 +315 0x6000 //TX_A_POST_FILT_S_1 +316 0x6000 //TX_A_POST_FILT_S_2 +317 0x6000 //TX_A_POST_FILT_S_3 +318 0x6000 //TX_A_POST_FILT_S_4 +319 0x6000 //TX_A_POST_FILT_S_5 +320 0x6000 //TX_A_POST_FILT_S_6 +321 0x6000 //TX_A_POST_FILT_S_7 +322 0x2000 //TX_B_POST_FILT_0 +323 0x4000 //TX_B_POST_FILT_1 +324 0x2000 //TX_B_POST_FILT_2 +325 0x2000 //TX_B_POST_FILT_3 +326 0x2000 //TX_B_POST_FILT_4 +327 0x2000 //TX_B_POST_FILT_5 +328 0x2000 //TX_B_POST_FILT_6 +329 0x2000 //TX_B_POST_FILT_7 +330 0x7FFF //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x7FFF //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7CCD //TX_LAMBDA_PFILT +339 0x7CCD //TX_LAMBDA_PFILT_S_0 +340 0x7CCD //TX_LAMBDA_PFILT_S_1 +341 0x7CCD //TX_LAMBDA_PFILT_S_2 +342 0x7CCD //TX_LAMBDA_PFILT_S_3 +343 0x7CCD //TX_LAMBDA_PFILT_S_4 +344 0x7CCD //TX_LAMBDA_PFILT_S_5 +345 0x7CCD //TX_LAMBDA_PFILT_S_6 +346 0x7CCD //TX_LAMBDA_PFILT_S_7 +347 0x0200 //TX_K_PEPPER +348 0x0500 //TX_A_PEPPER +349 0x1600 //TX_K_PEPPER_HF +350 0x0400 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0800 //TX_DT_BINVAD_TH_0 +354 0x0800 //TX_DT_BINVAD_TH_1 +355 0x0800 //TX_DT_BINVAD_TH_2 +356 0x0800 //TX_DT_BINVAD_TH_3 +357 0x1D4C //TX_DT_BINVAD_ENDF +358 0x0000 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0190 //TX_NDETCT +367 0x04E8 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x02A6 //TX_NOISE_TH_1 +371 0x07DA //TX_NOISE_TH_2 +372 0x3194 //TX_NOISE_TH_3 +373 0x0960 //TX_NOISE_TH_4 +374 0x5555 //TX_NOISE_TH_5 +375 0x3FF4 //TX_NOISE_TH_5_2 +376 0x0001 //TX_NOISE_TH_5_3 +377 0x0000 //TX_NOISE_TH_5_4 +378 0x02BC //TX_NOISE_TH_6 +379 0x02BC //TX_MINENOISE_TH +380 0xD508 //TX_MORENS_TFMASK_TH +381 0x0001 //TX_DRC_QUIET_FLOOR +382 0x3A98 //TX_RATIODTL_CUT_TH +383 0x1482 //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x0333 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x7FFF //TX_POST_MASK_SUP_HSNE +392 0x1388 //TX_TAIL_DET_TH +393 0x4000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0080 //TX_SUPHIGH_TH +396 0x0000 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x1800 //TX_C_POST_FLT_MASK +399 0x7FFF //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0004 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x04E7 //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x2900 //TX_MIN_G_CTRL_SSNS +409 0x0800 //TX_METAL_RTO_THR +410 0x4848 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x4000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x01E0 //TX_NOR_OFF_THR +498 0x7C00 //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0xD333 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x6000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0xC000 //TX_DEREVERB_LF_MU +515 0xC000 //TX_DEREVERB_HF_MU +516 0xCCCC //TX_DEREVERB_DELAY +517 0xD999 //TX_DEREVERB_COEF_LEN +518 0x1F40 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x7000 //TX_GSC_RTOH_TH +523 0x0064 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0020 //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4848 //TX_FDEQ_GAIN_5 +573 0x4848 //TX_FDEQ_GAIN_6 +574 0x4848 //TX_FDEQ_GAIN_7 +575 0x4848 //TX_FDEQ_GAIN_8 +576 0x4848 //TX_FDEQ_GAIN_9 +577 0x484C //TX_FDEQ_GAIN_10 +578 0x5054 //TX_FDEQ_GAIN_11 +579 0x606C //TX_FDEQ_GAIN_12 +580 0x7890 //TX_FDEQ_GAIN_13 +581 0x9C9C //TX_FDEQ_GAIN_14 +582 0x9C9C //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0304 //TX_FDEQ_BIN_2 +594 0x0405 //TX_FDEQ_BIN_3 +595 0x0607 //TX_FDEQ_BIN_4 +596 0x0809 //TX_FDEQ_BIN_5 +597 0x0A0B //TX_FDEQ_BIN_6 +598 0x0C0D //TX_FDEQ_BIN_7 +599 0x0E0F //TX_FDEQ_BIN_8 +600 0x1011 //TX_FDEQ_BIN_9 +601 0x1214 //TX_FDEQ_BIN_10 +602 0x1618 //TX_FDEQ_BIN_11 +603 0x1C1C //TX_FDEQ_BIN_12 +604 0x2020 //TX_FDEQ_BIN_13 +605 0x2020 //TX_FDEQ_BIN_14 +606 0x2020 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4848 //TX_PREEQ_GAIN_MIC0_8 +626 0x4848 //TX_PREEQ_GAIN_MIC0_9 +627 0x4848 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0E10 //TX_PREEQ_BIN_MIC0_0 +642 0x1010 //TX_PREEQ_BIN_MIC0_1 +643 0x1010 //TX_PREEQ_BIN_MIC0_2 +644 0x1010 //TX_PREEQ_BIN_MIC0_3 +645 0x1010 //TX_PREEQ_BIN_MIC0_4 +646 0x1010 //TX_PREEQ_BIN_MIC0_5 +647 0x1010 //TX_PREEQ_BIN_MIC0_6 +648 0x1010 //TX_PREEQ_BIN_MIC0_7 +649 0x1010 //TX_PREEQ_BIN_MIC0_8 +650 0x1010 //TX_PREEQ_BIN_MIC0_9 +651 0x1010 //TX_PREEQ_BIN_MIC0_10 +652 0x1010 //TX_PREEQ_BIN_MIC0_11 +653 0x1010 //TX_PREEQ_BIN_MIC0_12 +654 0x1010 //TX_PREEQ_BIN_MIC0_13 +655 0x1010 //TX_PREEQ_BIN_MIC0_14 +656 0x0200 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0E10 //TX_PREEQ_BIN_MIC1_0 +691 0x1010 //TX_PREEQ_BIN_MIC1_1 +692 0x1010 //TX_PREEQ_BIN_MIC1_2 +693 0x1010 //TX_PREEQ_BIN_MIC1_3 +694 0x1010 //TX_PREEQ_BIN_MIC1_4 +695 0x1010 //TX_PREEQ_BIN_MIC1_5 +696 0x1010 //TX_PREEQ_BIN_MIC1_6 +697 0x1010 //TX_PREEQ_BIN_MIC1_7 +698 0x1010 //TX_PREEQ_BIN_MIC1_8 +699 0x1010 //TX_PREEQ_BIN_MIC1_9 +700 0x1010 //TX_PREEQ_BIN_MIC1_10 +701 0x1010 //TX_PREEQ_BIN_MIC1_11 +702 0x1010 //TX_PREEQ_BIN_MIC1_12 +703 0x1010 //TX_PREEQ_BIN_MIC1_13 +704 0x1010 //TX_PREEQ_BIN_MIC1_14 +705 0x0200 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0E10 //TX_PREEQ_BIN_MIC2_0 +740 0x1010 //TX_PREEQ_BIN_MIC2_1 +741 0x1010 //TX_PREEQ_BIN_MIC2_2 +742 0x1010 //TX_PREEQ_BIN_MIC2_3 +743 0x1010 //TX_PREEQ_BIN_MIC2_4 +744 0x1010 //TX_PREEQ_BIN_MIC2_5 +745 0x1010 //TX_PREEQ_BIN_MIC2_6 +746 0x1010 //TX_PREEQ_BIN_MIC2_7 +747 0x1010 //TX_PREEQ_BIN_MIC2_8 +748 0x1010 //TX_PREEQ_BIN_MIC2_9 +749 0x1010 //TX_PREEQ_BIN_MIC2_10 +750 0x1010 //TX_PREEQ_BIN_MIC2_11 +751 0x1010 //TX_PREEQ_BIN_MIC2_12 +752 0x1010 //TX_PREEQ_BIN_MIC2_13 +753 0x1010 //TX_PREEQ_BIN_MIC2_14 +754 0x0200 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x2000 //TX_NND_WEIGHT +765 0x0060 //TX_MIC_CALIBRATION_0 +766 0x0060 //TX_MIC_CALIBRATION_1 +767 0x0070 //TX_MIC_CALIBRATION_2 +768 0x0070 //TX_MIC_CALIBRATION_3 +769 0x0050 //TX_MIC_PWR_BIAS_0 +770 0x0040 //TX_MIC_PWR_BIAS_1 +771 0x0040 //TX_MIC_PWR_BIAS_2 +772 0x0040 //TX_MIC_PWR_BIAS_3 +773 0x0009 //TX_GAIN_LIMIT_0 +774 0x000F //TX_GAIN_LIMIT_1 +775 0x000F //TX_GAIN_LIMIT_2 +776 0x000F //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x0C00 //TX_TDDRC_ALPHA_UP_01 +784 0x0C00 //TX_TDDRC_ALPHA_UP_02 +785 0x0C00 //TX_TDDRC_ALPHA_UP_03 +786 0x0C00 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x7FFF //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0000 //TX_DEADMIC_SILENCE_TH +817 0x0000 //TX_MIC_DEGRADE_TH +818 0x0000 //TX_DEADMIC_CNT +819 0x0000 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x4848 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0000 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0002 //TX_FILTINDX +854 0x0001 //TX_TDDRC_THRD_0 +855 0x0001 //TX_TDDRC_THRD_1 +856 0x1900 //TX_TDDRC_THRD_2 +857 0x1900 //TX_TDDRC_THRD_3 +858 0x3000 //TX_TDDRC_SLANT_0 +859 0x7B00 //TX_TDDRC_SLANT_1 +860 0x0C00 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x07F2 //TX_TDDRC_DRC_GAIN +867 0x7FFF //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x0028 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x7000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x2339 //TX_SENDFUNC_REG_MICMUTE +898 0x0021 //TX_SENDFUNC_REG_MICMUTE1 +899 0x02BC //TX_MICMUTE_RATIO_THR +900 0x0140 //TX_MICMUTE_AMP_THR +901 0x0004 //TX_MICMUTE_HPF_IND +902 0x00C0 //TX_MICMUTE_LOG_EYR_TH +903 0x0008 //TX_MICMUTE_CVG_TIME +904 0x0008 //TX_MICMUTE_RELEASE_TIME +905 0x01FE //TX_MIC_VOLUME_MIC0MUTE +906 0x0020 //TX_MICMUTE_EPD_OFFSET_0 +907 0x001E //TX_MICMUTE_FRQ_AEC_L +908 0x7999 //TX_MICMUTE_EAD_THR +909 0x7FFF //TX_MICMUTE_LAMBDA_CB_NLE +910 0x7FFF //TX_MICMUTE_LAMBDA_RE_EST +911 0x4000 //TX_DTD_THR1_MICMUTE_0 +912 0x7000 //TX_DTD_THR1_MICMUTE_1 +913 0x7FFF //TX_DTD_THR1_MICMUTE_2 +914 0x7FFF //TX_DTD_THR1_MICMUTE_3 +915 0x6CCC //TX_DTD_THR2_MICMUTE_0 +916 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x1000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x4000 //TX_MICMUTE_C_POST_FLT +922 0x03E8 //TX_MICMUTE_DT_CUT_K +923 0x0001 //TX_MICMUTE_DT_CUT_THR +924 0x03E8 //TX_MICMUTE_DT_CUT_K2 +925 0x0001 //TX_MICMUTE_DT_CUT_THR2 +926 0x0064 //TX_MICMUTE_DT2_HOLD_N +927 0x1000 //TX_MICMUTE_RATIODTH_THCUT +928 0x1000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x7FFF //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0400 //TX_MICMUTE_C_POST_FLT_MASK +931 0x7999 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0258 //TX_MICMUTE_DT_CUT_K1 +933 0x0800 //TX_MICMUTE_N2_SN_EST +934 0xFC00 //TX_MICMUTE_THR_SN_EST_0 +935 0x001C //TX_MICMUTE_MIN_G_CTRL_0 +936 0x6000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x7000 //TX_MICMUTE_B_POST_FILT_0 +938 0x2710 //TX_MIC1RUB_AMP_THR +939 0x0010 //TX_MIC1MUTE_RATIO_THR +940 0x0450 //TX_MIC1MUTE_AMP_THR +941 0x0008 //TX_MIC1MUTE_CVG_TIME +942 0x0008 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x242C //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0004 //RX_SAMPLINGFREQ_SIG +3 0x0004 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7B02 //RX_A_HP +12 0x4000 //RX_B_PE +13 0x7800 //RX_THR_PITCH_DET_0 +14 0x7000 //RX_THR_PITCH_DET_1 +15 0x6000 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0500 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x000A //RX_NS_LVL_CTRL +23 0xF600 //RX_THR_SN_EST +24 0x7000 //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7220 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4858 //RX_FDEQ_GAIN_0 +40 0x6265 //RX_FDEQ_GAIN_1 +41 0x6568 //RX_FDEQ_GAIN_2 +42 0x5654 //RX_FDEQ_GAIN_3 +43 0x676E //RX_FDEQ_GAIN_4 +44 0x6E6B //RX_FDEQ_GAIN_5 +45 0x5B5F //RX_FDEQ_GAIN_6 +46 0x5864 //RX_FDEQ_GAIN_7 +47 0x6548 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0002 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0231 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x280A //RX_TPKA_FP +127 0x032D //RX_MIN_G_FP +128 0x0A00 //RX_MAX_G_FP +129 0x000B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7220 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0231 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4858 //RX_FDEQ_GAIN_0 +40 0x6265 //RX_FDEQ_GAIN_1 +41 0x6568 //RX_FDEQ_GAIN_2 +42 0x5654 //RX_FDEQ_GAIN_3 +43 0x676E //RX_FDEQ_GAIN_4 +44 0x6E6B //RX_FDEQ_GAIN_5 +45 0x5B5F //RX_FDEQ_GAIN_6 +46 0x5864 //RX_FDEQ_GAIN_7 +47 0x6548 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x000B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7220 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0231 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4858 //RX_FDEQ_GAIN_0 +40 0x6265 //RX_FDEQ_GAIN_1 +41 0x6568 //RX_FDEQ_GAIN_2 +42 0x5654 //RX_FDEQ_GAIN_3 +43 0x676E //RX_FDEQ_GAIN_4 +44 0x6E6B //RX_FDEQ_GAIN_5 +45 0x5B5F //RX_FDEQ_GAIN_6 +46 0x5864 //RX_FDEQ_GAIN_7 +47 0x6548 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0012 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7220 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0231 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4858 //RX_FDEQ_GAIN_0 +40 0x6265 //RX_FDEQ_GAIN_1 +41 0x6568 //RX_FDEQ_GAIN_2 +42 0x5654 //RX_FDEQ_GAIN_3 +43 0x676E //RX_FDEQ_GAIN_4 +44 0x6E6B //RX_FDEQ_GAIN_5 +45 0x5B5F //RX_FDEQ_GAIN_6 +46 0x5864 //RX_FDEQ_GAIN_7 +47 0x6548 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x001F //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7220 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0231 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4858 //RX_FDEQ_GAIN_0 +40 0x6265 //RX_FDEQ_GAIN_1 +41 0x6568 //RX_FDEQ_GAIN_2 +42 0x5654 //RX_FDEQ_GAIN_3 +43 0x676E //RX_FDEQ_GAIN_4 +44 0x6E6B //RX_FDEQ_GAIN_5 +45 0x5B5F //RX_FDEQ_GAIN_6 +46 0x5864 //RX_FDEQ_GAIN_7 +47 0x6548 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0034 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7220 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0231 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4858 //RX_FDEQ_GAIN_0 +40 0x6265 //RX_FDEQ_GAIN_1 +41 0x6568 //RX_FDEQ_GAIN_2 +42 0x5654 //RX_FDEQ_GAIN_3 +43 0x676E //RX_FDEQ_GAIN_4 +44 0x6E6B //RX_FDEQ_GAIN_5 +45 0x5B5F //RX_FDEQ_GAIN_6 +46 0x5864 //RX_FDEQ_GAIN_7 +47 0x6548 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0056 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7220 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0231 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4858 //RX_FDEQ_GAIN_0 +40 0x6265 //RX_FDEQ_GAIN_1 +41 0x6568 //RX_FDEQ_GAIN_2 +42 0x5654 //RX_FDEQ_GAIN_3 +43 0x676E //RX_FDEQ_GAIN_4 +44 0x6E6B //RX_FDEQ_GAIN_5 +45 0x5B5F //RX_FDEQ_GAIN_6 +46 0x5864 //RX_FDEQ_GAIN_7 +47 0x6548 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0090 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7220 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0231 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4858 //RX_FDEQ_GAIN_0 +40 0x6265 //RX_FDEQ_GAIN_1 +41 0x6568 //RX_FDEQ_GAIN_2 +42 0x5654 //RX_FDEQ_GAIN_3 +43 0x676E //RX_FDEQ_GAIN_4 +44 0x6E6B //RX_FDEQ_GAIN_5 +45 0x5B5F //RX_FDEQ_GAIN_6 +46 0x5864 //RX_FDEQ_GAIN_7 +47 0x6548 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x242C //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0004 //RX_SAMPLINGFREQ_SIG +160 0x0004 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7B02 //RX_A_HP +169 0x4000 //RX_B_PE +170 0x7800 //RX_THR_PITCH_DET_0 +171 0x7000 //RX_THR_PITCH_DET_1 +172 0x6000 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0500 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x000A //RX_NS_LVL_CTRL +180 0xF600 //RX_THR_SN_EST +181 0x7000 //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7220 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4858 //RX_FDEQ_GAIN_0 +197 0x6265 //RX_FDEQ_GAIN_1 +198 0x6568 //RX_FDEQ_GAIN_2 +199 0x5654 //RX_FDEQ_GAIN_3 +200 0x676E //RX_FDEQ_GAIN_4 +201 0x6E6B //RX_FDEQ_GAIN_5 +202 0x5B5F //RX_FDEQ_GAIN_6 +203 0x5864 //RX_FDEQ_GAIN_7 +204 0x6548 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0002 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0231 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x280A //RX_TPKA_FP +284 0x032D //RX_MIN_G_FP +285 0x0A00 //RX_MAX_G_FP +286 0x000B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7220 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0231 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4858 //RX_FDEQ_GAIN_0 +197 0x6265 //RX_FDEQ_GAIN_1 +198 0x6568 //RX_FDEQ_GAIN_2 +199 0x5654 //RX_FDEQ_GAIN_3 +200 0x676E //RX_FDEQ_GAIN_4 +201 0x6E6B //RX_FDEQ_GAIN_5 +202 0x5B5F //RX_FDEQ_GAIN_6 +203 0x5864 //RX_FDEQ_GAIN_7 +204 0x6548 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x000B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7220 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0231 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4858 //RX_FDEQ_GAIN_0 +197 0x6265 //RX_FDEQ_GAIN_1 +198 0x6568 //RX_FDEQ_GAIN_2 +199 0x5654 //RX_FDEQ_GAIN_3 +200 0x676E //RX_FDEQ_GAIN_4 +201 0x6E6B //RX_FDEQ_GAIN_5 +202 0x5B5F //RX_FDEQ_GAIN_6 +203 0x5864 //RX_FDEQ_GAIN_7 +204 0x6548 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0012 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7220 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0231 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4858 //RX_FDEQ_GAIN_0 +197 0x6265 //RX_FDEQ_GAIN_1 +198 0x6568 //RX_FDEQ_GAIN_2 +199 0x5654 //RX_FDEQ_GAIN_3 +200 0x676E //RX_FDEQ_GAIN_4 +201 0x6E6B //RX_FDEQ_GAIN_5 +202 0x5B5F //RX_FDEQ_GAIN_6 +203 0x5864 //RX_FDEQ_GAIN_7 +204 0x6548 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x001F //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7220 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0231 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4858 //RX_FDEQ_GAIN_0 +197 0x6265 //RX_FDEQ_GAIN_1 +198 0x6568 //RX_FDEQ_GAIN_2 +199 0x5654 //RX_FDEQ_GAIN_3 +200 0x676E //RX_FDEQ_GAIN_4 +201 0x6E6B //RX_FDEQ_GAIN_5 +202 0x5B5F //RX_FDEQ_GAIN_6 +203 0x5864 //RX_FDEQ_GAIN_7 +204 0x6548 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0034 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7220 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0231 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4858 //RX_FDEQ_GAIN_0 +197 0x6265 //RX_FDEQ_GAIN_1 +198 0x6568 //RX_FDEQ_GAIN_2 +199 0x5654 //RX_FDEQ_GAIN_3 +200 0x676E //RX_FDEQ_GAIN_4 +201 0x6E6B //RX_FDEQ_GAIN_5 +202 0x5B5F //RX_FDEQ_GAIN_6 +203 0x5864 //RX_FDEQ_GAIN_7 +204 0x6548 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0056 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7220 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0231 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4858 //RX_FDEQ_GAIN_0 +197 0x6265 //RX_FDEQ_GAIN_1 +198 0x6568 //RX_FDEQ_GAIN_2 +199 0x5654 //RX_FDEQ_GAIN_3 +200 0x676E //RX_FDEQ_GAIN_4 +201 0x6E6B //RX_FDEQ_GAIN_5 +202 0x5B5F //RX_FDEQ_GAIN_6 +203 0x5864 //RX_FDEQ_GAIN_7 +204 0x6548 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0090 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7220 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0231 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4858 //RX_FDEQ_GAIN_0 +197 0x6265 //RX_FDEQ_GAIN_1 +198 0x6568 //RX_FDEQ_GAIN_2 +199 0x5654 //RX_FDEQ_GAIN_3 +200 0x676E //RX_FDEQ_GAIN_4 +201 0x6E6B //RX_FDEQ_GAIN_5 +202 0x5B5F //RX_FDEQ_GAIN_6 +203 0x5864 //RX_FDEQ_GAIN_7 +204 0x6548 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME HEADSET-GOOGLE_CONDOR-VOICE_GENERIC-NB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0009 //TX_OPERATION_MODE_0 +1 0x0008 //TX_OPERATION_MODE_1 +2 0x0033 //TX_PATCH_REG +3 0x2B68 //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0001 //TX_NUM_MIC +6 0x0000 //TX_SAMPLINGFREQ_SIG +7 0x0000 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009B //TX_DIST2REF1 +22 0x0000 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0B80 //TX_PGA_0 +28 0x0800 //TX_PGA_1 +29 0x0000 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0000 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0001 //TX_MIC_DATA_SRC1 +43 0x0002 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3E00 //TX_DIST2REF_11 +73 0x0000 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0200 //TX_MIC_REFBLK_VOLUME +108 0x0800 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0000 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7646 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x7CCC //TX_THR_PITCH_DET_0 +131 0x7000 //TX_THR_PITCH_DET_1 +132 0x6333 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x001E //TX_TAIL_LENGTH +147 0x0010 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x7000 //TX_EAD_THR +151 0x1000 //TX_THR_RE_EST +152 0x1000 //TX_MIN_EQ_RE_EST_0 +153 0x0800 //TX_MIN_EQ_RE_EST_1 +154 0x0800 //TX_MIN_EQ_RE_EST_2 +155 0x0800 //TX_MIN_EQ_RE_EST_3 +156 0x0800 //TX_MIN_EQ_RE_EST_4 +157 0x0800 //TX_MIN_EQ_RE_EST_5 +158 0x0800 //TX_MIN_EQ_RE_EST_6 +159 0x0800 //TX_MIN_EQ_RE_EST_7 +160 0x0800 //TX_MIN_EQ_RE_EST_8 +161 0x0800 //TX_MIN_EQ_RE_EST_9 +162 0x0800 //TX_MIN_EQ_RE_EST_10 +163 0x0800 //TX_MIN_EQ_RE_EST_11 +164 0x0800 //TX_MIN_EQ_RE_EST_12 +165 0x4000 //TX_LAMBDA_RE_EST +166 0x2000 //TX_LAMBDA_CB_NLE +167 0x2000 //TX_C_POST_FLT +168 0x2000 //TX_GAIN_NP +169 0x00C8 //TX_SE_HOLD_N +170 0x0064 //TX_DT_HOLD_N +171 0x03E8 //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x5000 //TX_DTD_THR1_0 +198 0x7000 //TX_DTD_THR1_1 +199 0x7F00 //TX_DTD_THR1_2 +200 0x7FFF //TX_DTD_THR1_3 +201 0x7FFF //TX_DTD_THR1_4 +202 0x7FFF //TX_DTD_THR1_5 +203 0x7FFF //TX_DTD_THR1_6 +204 0x2000 //TX_DTD_THR2_0 +205 0x2000 //TX_DTD_THR2_1 +206 0x2000 //TX_DTD_THR2_2 +207 0x2000 //TX_DTD_THR2_3 +208 0x2000 //TX_DTD_THR2_4 +209 0x2000 //TX_DTD_THR2_5 +210 0x2000 //TX_DTD_THR2_6 +211 0x4100 //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x03E8 //TX_DT_CUT_K +214 0x1000 //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x0400 //TX_ADPT_STRICT_L +222 0x0200 //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x0800 //TX_B_POST_FILT_ECHO_L +229 0x7FFF //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x1000 //TX_B_LESSCUT_RTO_ECHO +232 0x0010 //TX_EPD_OFFSET_00 +233 0x0010 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x7FFF //TX_DTD_THR1_7 +238 0x7FFF //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xFA00 //TX_THR_SN_EST_0 +243 0xFA00 //TX_THR_SN_EST_1 +244 0xFA00 //TX_THR_SN_EST_2 +245 0xFA00 //TX_THR_SN_EST_3 +246 0xFA00 //TX_THR_SN_EST_4 +247 0xFA00 //TX_THR_SN_EST_5 +248 0xFA00 //TX_THR_SN_EST_6 +249 0xFA00 //TX_THR_SN_EST_7 +250 0x0000 //TX_DELTA_THR_SN_EST_0 +251 0x0000 //TX_DELTA_THR_SN_EST_1 +252 0x0000 //TX_DELTA_THR_SN_EST_2 +253 0x0000 //TX_DELTA_THR_SN_EST_3 +254 0x0000 //TX_DELTA_THR_SN_EST_4 +255 0x0000 //TX_DELTA_THR_SN_EST_5 +256 0x0000 //TX_DELTA_THR_SN_EST_6 +257 0x0000 //TX_DELTA_THR_SN_EST_7 +258 0x4000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x4000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x0400 //TX_B_POST_FLT_0 +280 0x0400 //TX_B_POST_FLT_1 +281 0x0010 //TX_NS_LVL_CTRL_0 +282 0x0010 //TX_NS_LVL_CTRL_1 +283 0x0010 //TX_NS_LVL_CTRL_2 +284 0x0010 //TX_NS_LVL_CTRL_3 +285 0x0010 //TX_NS_LVL_CTRL_4 +286 0x0010 //TX_NS_LVL_CTRL_5 +287 0x0010 //TX_NS_LVL_CTRL_6 +288 0x0010 //TX_NS_LVL_CTRL_7 +289 0x000D //TX_MIN_GAIN_S_0 +290 0x000D //TX_MIN_GAIN_S_1 +291 0x000D //TX_MIN_GAIN_S_2 +292 0x000D //TX_MIN_GAIN_S_3 +293 0x000D //TX_MIN_GAIN_S_4 +294 0x000D //TX_MIN_GAIN_S_5 +295 0x000D //TX_MIN_GAIN_S_6 +296 0x000D //TX_MIN_GAIN_S_7 +297 0x7FFF //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x7FFF //TX_SNRI_SUP_1 +302 0x7FFF //TX_SNRI_SUP_2 +303 0x7FFF //TX_SNRI_SUP_3 +304 0x7FFF //TX_SNRI_SUP_4 +305 0x7FFF //TX_SNRI_SUP_5 +306 0x7FFF //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x0014 //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x4000 //TX_A_POST_FILT_S_0 +315 0x1000 //TX_A_POST_FILT_S_1 +316 0x4000 //TX_A_POST_FILT_S_2 +317 0x4000 //TX_A_POST_FILT_S_3 +318 0x4000 //TX_A_POST_FILT_S_4 +319 0x4000 //TX_A_POST_FILT_S_5 +320 0x4000 //TX_A_POST_FILT_S_6 +321 0x4000 //TX_A_POST_FILT_S_7 +322 0x0400 //TX_B_POST_FILT_0 +323 0x2000 //TX_B_POST_FILT_1 +324 0x2000 //TX_B_POST_FILT_2 +325 0x2000 //TX_B_POST_FILT_3 +326 0x2000 //TX_B_POST_FILT_4 +327 0x2000 //TX_B_POST_FILT_5 +328 0x0400 //TX_B_POST_FILT_6 +329 0x2000 //TX_B_POST_FILT_7 +330 0x7FFF //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x7FFF //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7E14 //TX_LAMBDA_PFILT +339 0x7C29 //TX_LAMBDA_PFILT_S_0 +340 0x7C29 //TX_LAMBDA_PFILT_S_1 +341 0x7C29 //TX_LAMBDA_PFILT_S_2 +342 0x7C29 //TX_LAMBDA_PFILT_S_3 +343 0x7C29 //TX_LAMBDA_PFILT_S_4 +344 0x7C29 //TX_LAMBDA_PFILT_S_5 +345 0x7C29 //TX_LAMBDA_PFILT_S_6 +346 0x7C29 //TX_LAMBDA_PFILT_S_7 +347 0x0200 //TX_K_PEPPER +348 0x0800 //TX_A_PEPPER +349 0x0FA0 //TX_K_PEPPER_HF +350 0x0400 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x4000 //TX_HMNC_BST_THR +353 0x0800 //TX_DT_BINVAD_TH_0 +354 0x0800 //TX_DT_BINVAD_TH_1 +355 0x0800 //TX_DT_BINVAD_TH_2 +356 0x0800 //TX_DT_BINVAD_TH_3 +357 0x1D4C //TX_DT_BINVAD_ENDF +358 0x0000 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0190 //TX_NDETCT +367 0x003B //TX_NOISE_TH_0 +368 0x1B58 //TX_NOISE_TH_0_2 +369 0x2134 //TX_NOISE_TH_0_3 +370 0x02BC //TX_NOISE_TH_1 +371 0x1F40 //TX_NOISE_TH_2 +372 0x4650 //TX_NOISE_TH_3 +373 0x7148 //TX_NOISE_TH_4 +374 0x044C //TX_NOISE_TH_5 +375 0x7FFF //TX_NOISE_TH_5_2 +376 0x0000 //TX_NOISE_TH_5_3 +377 0x0000 //TX_NOISE_TH_5_4 +378 0x0032 //TX_NOISE_TH_6 +379 0x00C8 //TX_MINENOISE_TH +380 0xD508 //TX_MORENS_TFMASK_TH +381 0x0001 //TX_DRC_QUIET_FLOOR +382 0x3A98 //TX_RATIODTL_CUT_TH +383 0x0DAC //TX_DT_CUT_K1 +384 0x00A5 //TX_OUT_ENER_S_TH_CLEAN +385 0x00A5 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x00A5 //TX_OUT_ENER_S_TH_NOISY +387 0x0029 //TX_OUT_ENER_TH_NOISE +388 0x00CE //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x7FFF //TX_POST_MASK_SUP_HSNE +392 0x1388 //TX_TAIL_DET_TH +393 0x4000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0080 //TX_SUPHIGH_TH +396 0x0000 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x1800 //TX_C_POST_FLT_MASK +399 0x7FFF //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0002 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x0032 //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x7FFF //TX_MIN_G_CTRL_SSNS +409 0x0000 //TX_METAL_RTO_THR +410 0x4848 //TX_NS_FP_K_METAL +411 0x7FFF //TX_NOISEDET_BOOST_TH +412 0x0000 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0280 //TX_N_HOLD_HS +416 0x006E //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0333 //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2400 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0640 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x2000 //TX_WTA_EN_RTO_TH +429 0x1400 //TX_TOP_ENER_TH_F +430 0x0064 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x003C //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x0D9A //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x2A3D //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x0230 //TX_NOR_OFF_THR +498 0x0CCD //TX_MORE_ON_700HZ_THR +499 0x0000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0xD333 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x6000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0xC000 //TX_DEREVERB_LF_MU +515 0xC000 //TX_DEREVERB_HF_MU +516 0xCCCC //TX_DEREVERB_DELAY +517 0xD999 //TX_DEREVERB_COEF_LEN +518 0x1F40 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x7000 //TX_GSC_RTOH_TH +523 0x0064 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0014 //TX_FDEQ_SUBNUM +567 0x6048 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4848 //TX_FDEQ_GAIN_5 +573 0x4844 //TX_FDEQ_GAIN_6 +574 0x4444 //TX_FDEQ_GAIN_7 +575 0x4040 //TX_FDEQ_GAIN_8 +576 0x3C3C //TX_FDEQ_GAIN_9 +577 0x4848 //TX_FDEQ_GAIN_10 +578 0x4848 //TX_FDEQ_GAIN_11 +579 0x4848 //TX_FDEQ_GAIN_12 +580 0x4848 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0401 //TX_FDEQ_BIN_0 +592 0x0103 //TX_FDEQ_BIN_1 +593 0x0303 //TX_FDEQ_BIN_2 +594 0x0304 //TX_FDEQ_BIN_3 +595 0x0405 //TX_FDEQ_BIN_4 +596 0x0506 //TX_FDEQ_BIN_5 +597 0x0708 //TX_FDEQ_BIN_6 +598 0x090A //TX_FDEQ_BIN_7 +599 0x0B0C //TX_FDEQ_BIN_8 +600 0x0D0E //TX_FDEQ_BIN_9 +601 0x0000 //TX_FDEQ_BIN_10 +602 0x0000 //TX_FDEQ_BIN_11 +603 0x0000 //TX_FDEQ_BIN_12 +604 0x0000 //TX_FDEQ_BIN_13 +605 0x0000 //TX_FDEQ_BIN_14 +606 0x0000 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0010 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4848 //TX_PREEQ_GAIN_MIC0_8 +626 0x4848 //TX_PREEQ_GAIN_MIC0_9 +627 0x4848 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0608 //TX_PREEQ_BIN_MIC0_0 +642 0x0808 //TX_PREEQ_BIN_MIC0_1 +643 0x0808 //TX_PREEQ_BIN_MIC0_2 +644 0x0808 //TX_PREEQ_BIN_MIC0_3 +645 0x0808 //TX_PREEQ_BIN_MIC0_4 +646 0x0808 //TX_PREEQ_BIN_MIC0_5 +647 0x0808 //TX_PREEQ_BIN_MIC0_6 +648 0x0802 //TX_PREEQ_BIN_MIC0_7 +649 0x0000 //TX_PREEQ_BIN_MIC0_8 +650 0x0000 //TX_PREEQ_BIN_MIC0_9 +651 0x0000 //TX_PREEQ_BIN_MIC0_10 +652 0x0000 //TX_PREEQ_BIN_MIC0_11 +653 0x0000 //TX_PREEQ_BIN_MIC0_12 +654 0x0000 //TX_PREEQ_BIN_MIC0_13 +655 0x0000 //TX_PREEQ_BIN_MIC0_14 +656 0x0000 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0010 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0608 //TX_PREEQ_BIN_MIC1_0 +691 0x0808 //TX_PREEQ_BIN_MIC1_1 +692 0x0808 //TX_PREEQ_BIN_MIC1_2 +693 0x0808 //TX_PREEQ_BIN_MIC1_3 +694 0x0808 //TX_PREEQ_BIN_MIC1_4 +695 0x0808 //TX_PREEQ_BIN_MIC1_5 +696 0x0808 //TX_PREEQ_BIN_MIC1_6 +697 0x0802 //TX_PREEQ_BIN_MIC1_7 +698 0x0000 //TX_PREEQ_BIN_MIC1_8 +699 0x0000 //TX_PREEQ_BIN_MIC1_9 +700 0x0000 //TX_PREEQ_BIN_MIC1_10 +701 0x0000 //TX_PREEQ_BIN_MIC1_11 +702 0x0000 //TX_PREEQ_BIN_MIC1_12 +703 0x0000 //TX_PREEQ_BIN_MIC1_13 +704 0x0000 //TX_PREEQ_BIN_MIC1_14 +705 0x0000 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0010 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0608 //TX_PREEQ_BIN_MIC2_0 +740 0x0808 //TX_PREEQ_BIN_MIC2_1 +741 0x0808 //TX_PREEQ_BIN_MIC2_2 +742 0x0808 //TX_PREEQ_BIN_MIC2_3 +743 0x0808 //TX_PREEQ_BIN_MIC2_4 +744 0x0808 //TX_PREEQ_BIN_MIC2_5 +745 0x0808 //TX_PREEQ_BIN_MIC2_6 +746 0x0802 //TX_PREEQ_BIN_MIC2_7 +747 0x0000 //TX_PREEQ_BIN_MIC2_8 +748 0x0000 //TX_PREEQ_BIN_MIC2_9 +749 0x0000 //TX_PREEQ_BIN_MIC2_10 +750 0x0000 //TX_PREEQ_BIN_MIC2_11 +751 0x0000 //TX_PREEQ_BIN_MIC2_12 +752 0x0000 //TX_PREEQ_BIN_MIC2_13 +753 0x0000 //TX_PREEQ_BIN_MIC2_14 +754 0x0000 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x0800 //TX_NND_WEIGHT +765 0x0065 //TX_MIC_CALIBRATION_0 +766 0x0065 //TX_MIC_CALIBRATION_1 +767 0x0065 //TX_MIC_CALIBRATION_2 +768 0x0065 //TX_MIC_CALIBRATION_3 +769 0x0044 //TX_MIC_PWR_BIAS_0 +770 0x0044 //TX_MIC_PWR_BIAS_1 +771 0x0044 //TX_MIC_PWR_BIAS_2 +772 0x0044 //TX_MIC_PWR_BIAS_3 +773 0x000B //TX_GAIN_LIMIT_0 +774 0x000B //TX_GAIN_LIMIT_1 +775 0x000B //TX_GAIN_LIMIT_2 +776 0x000B //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x1000 //TX_TDDRC_ALPHA_UP_01 +784 0x1000 //TX_TDDRC_ALPHA_UP_02 +785 0x1000 //TX_TDDRC_ALPHA_UP_03 +786 0x1000 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x7FFF //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0000 //TX_DEADMIC_SILENCE_TH +817 0x0000 //TX_MIC_DEGRADE_TH +818 0x0000 //TX_DEADMIC_CNT +819 0x0000 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x4848 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0000 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0001 //TX_FILTINDX +854 0x0000 //TX_TDDRC_THRD_0 +855 0x0000 //TX_TDDRC_THRD_1 +856 0x2000 //TX_TDDRC_THRD_2 +857 0x2000 //TX_TDDRC_THRD_3 +858 0x3000 //TX_TDDRC_SLANT_0 +859 0x6E00 //TX_TDDRC_SLANT_1 +860 0x1000 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x05A0 //TX_TDDRC_DRC_GAIN +867 0x7FFF //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0xF800 //TX_TFMASKLTH_DOA +875 0x0CCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x00C8 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x4000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x2339 //TX_SENDFUNC_REG_MICMUTE +898 0x0021 //TX_SENDFUNC_REG_MICMUTE1 +899 0x02BC //TX_MICMUTE_RATIO_THR +900 0x0140 //TX_MICMUTE_AMP_THR +901 0x0004 //TX_MICMUTE_HPF_IND +902 0x00C0 //TX_MICMUTE_LOG_EYR_TH +903 0x0008 //TX_MICMUTE_CVG_TIME +904 0x0008 //TX_MICMUTE_RELEASE_TIME +905 0x01FE //TX_MIC_VOLUME_MIC0MUTE +906 0x0020 //TX_MICMUTE_EPD_OFFSET_0 +907 0x001E //TX_MICMUTE_FRQ_AEC_L +908 0x7999 //TX_MICMUTE_EAD_THR +909 0x7FFF //TX_MICMUTE_LAMBDA_CB_NLE +910 0x7FFF //TX_MICMUTE_LAMBDA_RE_EST +911 0x4000 //TX_DTD_THR1_MICMUTE_0 +912 0x7000 //TX_DTD_THR1_MICMUTE_1 +913 0x7FFF //TX_DTD_THR1_MICMUTE_2 +914 0x7FFF //TX_DTD_THR1_MICMUTE_3 +915 0x6CCC //TX_DTD_THR2_MICMUTE_0 +916 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x1000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x4000 //TX_MICMUTE_C_POST_FLT +922 0x03E8 //TX_MICMUTE_DT_CUT_K +923 0x0001 //TX_MICMUTE_DT_CUT_THR +924 0x03E8 //TX_MICMUTE_DT_CUT_K2 +925 0x0001 //TX_MICMUTE_DT_CUT_THR2 +926 0x0064 //TX_MICMUTE_DT2_HOLD_N +927 0x1000 //TX_MICMUTE_RATIODTH_THCUT +928 0x1000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x7FFF //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0400 //TX_MICMUTE_C_POST_FLT_MASK +931 0x7999 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0258 //TX_MICMUTE_DT_CUT_K1 +933 0x0800 //TX_MICMUTE_N2_SN_EST +934 0xFC00 //TX_MICMUTE_THR_SN_EST_0 +935 0x001C //TX_MICMUTE_MIN_G_CTRL_0 +936 0x6000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x7000 //TX_MICMUTE_B_POST_FILT_0 +938 0x2710 //TX_MIC1RUB_AMP_THR +939 0x0010 //TX_MIC1MUTE_RATIO_THR +940 0x0450 //TX_MIC1MUTE_AMP_THR +941 0x0008 //TX_MIC1MUTE_CVG_TIME +942 0x0008 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x202C //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0000 //RX_SAMPLINGFREQ_SIG +3 0x0000 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7FFF //RX_A_HP +12 0x0000 //RX_B_PE +13 0x3800 //RX_THR_PITCH_DET_0 +14 0x3000 //RX_THR_PITCH_DET_1 +15 0x2800 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0600 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x0010 //RX_NS_LVL_CTRL +23 0xF800 //RX_THR_SN_EST +24 0x7CCD //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0002 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0200 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x2000 //RX_MIN_G_FP +128 0x0080 //RX_MAX_G_FP +129 0x000B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0200 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x000B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0200 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0013 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0200 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0020 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0200 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0036 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0200 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x005B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0200 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0099 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0200 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x202C //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0000 //RX_SAMPLINGFREQ_SIG +160 0x0000 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7FFF //RX_A_HP +169 0x0000 //RX_B_PE +170 0x3800 //RX_THR_PITCH_DET_0 +171 0x3000 //RX_THR_PITCH_DET_1 +172 0x2800 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0600 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x0010 //RX_NS_LVL_CTRL +180 0xF800 //RX_THR_SN_EST +181 0x7CCD //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0002 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0200 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x2000 //RX_MIN_G_FP +285 0x0080 //RX_MAX_G_FP +286 0x000B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0200 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x000B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0200 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0013 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0200 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0020 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0200 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0036 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0200 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x005B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0200 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0099 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0200 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME HEADSET-GOOGLE_CONDOR-VOICE_GENERIC-WB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0009 //TX_OPERATION_MODE_0 +1 0x0008 //TX_OPERATION_MODE_1 +2 0x0033 //TX_PATCH_REG +3 0x2B68 //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0001 //TX_NUM_MIC +6 0x0001 //TX_SAMPLINGFREQ_SIG +7 0x0001 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009B //TX_DIST2REF1 +22 0x0000 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0B80 //TX_PGA_0 +28 0x0800 //TX_PGA_1 +29 0x0800 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0000 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0001 //TX_MIC_DATA_SRC1 +43 0x0002 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3E00 //TX_DIST2REF_11 +73 0x0000 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0200 //TX_MIC_REFBLK_VOLUME +108 0x0800 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0000 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7D83 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x6800 //TX_THR_PITCH_DET_0 +131 0x6000 //TX_THR_PITCH_DET_1 +132 0x5800 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x001E //TX_TAIL_LENGTH +147 0x0080 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x7000 //TX_EAD_THR +151 0x0800 //TX_THR_RE_EST +152 0x0800 //TX_MIN_EQ_RE_EST_0 +153 0x0800 //TX_MIN_EQ_RE_EST_1 +154 0x0800 //TX_MIN_EQ_RE_EST_2 +155 0x0800 //TX_MIN_EQ_RE_EST_3 +156 0x0800 //TX_MIN_EQ_RE_EST_4 +157 0x0800 //TX_MIN_EQ_RE_EST_5 +158 0x0800 //TX_MIN_EQ_RE_EST_6 +159 0x0800 //TX_MIN_EQ_RE_EST_7 +160 0x0800 //TX_MIN_EQ_RE_EST_8 +161 0x0800 //TX_MIN_EQ_RE_EST_9 +162 0x0800 //TX_MIN_EQ_RE_EST_10 +163 0x0800 //TX_MIN_EQ_RE_EST_11 +164 0x0800 //TX_MIN_EQ_RE_EST_12 +165 0x4000 //TX_LAMBDA_RE_EST +166 0x2000 //TX_LAMBDA_CB_NLE +167 0x6000 //TX_C_POST_FLT +168 0x7000 //TX_GAIN_NP +169 0x00C8 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x03E8 //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x7800 //TX_DTD_THR1_0 +198 0x7000 //TX_DTD_THR1_1 +199 0x7FFF //TX_DTD_THR1_2 +200 0x7FFF //TX_DTD_THR1_3 +201 0x7FFF //TX_DTD_THR1_4 +202 0x7FFF //TX_DTD_THR1_5 +203 0x7FFF //TX_DTD_THR1_6 +204 0x7FFF //TX_DTD_THR2_0 +205 0x7FFF //TX_DTD_THR2_1 +206 0x7FFF //TX_DTD_THR2_2 +207 0x7FFF //TX_DTD_THR2_3 +208 0x7FFF //TX_DTD_THR2_4 +209 0x7FFF //TX_DTD_THR2_5 +210 0x7FFF //TX_DTD_THR2_6 +211 0x1000 //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x0BB8 //TX_DT_CUT_K +214 0x0CCD //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x0400 //TX_ADPT_STRICT_L +222 0x0200 //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x0800 //TX_B_POST_FILT_ECHO_L +229 0x7FFF //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x7FFF //TX_B_LESSCUT_RTO_ECHO +232 0x0019 //TX_EPD_OFFSET_00 +233 0x0019 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x7FFF //TX_DTD_THR1_7 +238 0x7FFF //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xFA00 //TX_THR_SN_EST_0 +243 0xF400 //TX_THR_SN_EST_1 +244 0xF600 //TX_THR_SN_EST_2 +245 0xF400 //TX_THR_SN_EST_3 +246 0xF400 //TX_THR_SN_EST_4 +247 0xF400 //TX_THR_SN_EST_5 +248 0xF400 //TX_THR_SN_EST_6 +249 0xF600 //TX_THR_SN_EST_7 +250 0x0000 //TX_DELTA_THR_SN_EST_0 +251 0x0200 //TX_DELTA_THR_SN_EST_1 +252 0x0200 //TX_DELTA_THR_SN_EST_2 +253 0x0200 //TX_DELTA_THR_SN_EST_3 +254 0x0200 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0000 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x6000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x6000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x1000 //TX_B_POST_FLT_0 +280 0x1000 //TX_B_POST_FLT_1 +281 0x000F //TX_NS_LVL_CTRL_0 +282 0x0011 //TX_NS_LVL_CTRL_1 +283 0x000F //TX_NS_LVL_CTRL_2 +284 0x000F //TX_NS_LVL_CTRL_3 +285 0x000F //TX_NS_LVL_CTRL_4 +286 0x000F //TX_NS_LVL_CTRL_5 +287 0x000F //TX_NS_LVL_CTRL_6 +288 0x0011 //TX_NS_LVL_CTRL_7 +289 0x000C //TX_MIN_GAIN_S_0 +290 0x000F //TX_MIN_GAIN_S_1 +291 0x000C //TX_MIN_GAIN_S_2 +292 0x000C //TX_MIN_GAIN_S_3 +293 0x000C //TX_MIN_GAIN_S_4 +294 0x000C //TX_MIN_GAIN_S_5 +295 0x000C //TX_MIN_GAIN_S_6 +296 0x000F //TX_MIN_GAIN_S_7 +297 0x7FFF //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x7FFF //TX_SNRI_SUP_1 +302 0x7FFF //TX_SNRI_SUP_2 +303 0x7FFF //TX_SNRI_SUP_3 +304 0x7FFF //TX_SNRI_SUP_4 +305 0x7FFF //TX_SNRI_SUP_5 +306 0x7FFF //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x000E //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x4000 //TX_A_POST_FILT_S_0 +315 0x5000 //TX_A_POST_FILT_S_1 +316 0x5000 //TX_A_POST_FILT_S_2 +317 0x5000 //TX_A_POST_FILT_S_3 +318 0x5000 //TX_A_POST_FILT_S_4 +319 0x5000 //TX_A_POST_FILT_S_5 +320 0x4000 //TX_A_POST_FILT_S_6 +321 0x5000 //TX_A_POST_FILT_S_7 +322 0x1000 //TX_B_POST_FILT_0 +323 0x1000 //TX_B_POST_FILT_1 +324 0x1000 //TX_B_POST_FILT_2 +325 0x1000 //TX_B_POST_FILT_3 +326 0x1000 //TX_B_POST_FILT_4 +327 0x1000 //TX_B_POST_FILT_5 +328 0x1000 //TX_B_POST_FILT_6 +329 0x1000 //TX_B_POST_FILT_7 +330 0x7FFF //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x7FFF //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7CCD //TX_LAMBDA_PFILT +339 0x7B00 //TX_LAMBDA_PFILT_S_0 +340 0x7B00 //TX_LAMBDA_PFILT_S_1 +341 0x7B00 //TX_LAMBDA_PFILT_S_2 +342 0x7B00 //TX_LAMBDA_PFILT_S_3 +343 0x7B00 //TX_LAMBDA_PFILT_S_4 +344 0x7B00 //TX_LAMBDA_PFILT_S_5 +345 0x7B00 //TX_LAMBDA_PFILT_S_6 +346 0x7B00 //TX_LAMBDA_PFILT_S_7 +347 0x0200 //TX_K_PEPPER +348 0x0800 //TX_A_PEPPER +349 0x1EAA //TX_K_PEPPER_HF +350 0x0800 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0800 //TX_DT_BINVAD_TH_0 +354 0x0800 //TX_DT_BINVAD_TH_1 +355 0x0800 //TX_DT_BINVAD_TH_2 +356 0x0800 //TX_DT_BINVAD_TH_3 +357 0x1D4C //TX_DT_BINVAD_ENDF +358 0x0000 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0190 //TX_NDETCT +367 0x0102 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x07D0 //TX_NOISE_TH_1 +371 0x00C8 //TX_NOISE_TH_2 +372 0x3A98 //TX_NOISE_TH_3 +373 0x0FA0 //TX_NOISE_TH_4 +374 0x157C //TX_NOISE_TH_5 +375 0x7FFF //TX_NOISE_TH_5_2 +376 0x7FFF //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x044C //TX_NOISE_TH_6 +379 0x00F8 //TX_MINENOISE_TH +380 0xD508 //TX_MORENS_TFMASK_TH +381 0x0001 //TX_DRC_QUIET_FLOOR +382 0x3A98 //TX_RATIODTL_CUT_TH +383 0x0DAC //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x0333 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x7FFF //TX_POST_MASK_SUP_HSNE +392 0x1388 //TX_TAIL_DET_TH +393 0x4000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0080 //TX_SUPHIGH_TH +396 0x0000 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x1800 //TX_C_POST_FLT_MASK +399 0x7FFF //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0002 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x00DC //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x7FFF //TX_MIN_G_CTRL_SSNS +409 0x0000 //TX_METAL_RTO_THR +410 0x0000 //TX_NS_FP_K_METAL +411 0x7FFF //TX_NOISEDET_BOOST_TH +412 0x0000 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x4000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x0230 //TX_NOR_OFF_THR +498 0x0CCD //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0xD333 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x6000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0xC000 //TX_DEREVERB_LF_MU +515 0xC000 //TX_DEREVERB_HF_MU +516 0xCCCC //TX_DEREVERB_DELAY +517 0xD999 //TX_DEREVERB_COEF_LEN +518 0x1F40 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x7000 //TX_GSC_RTOH_TH +523 0x0064 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x001C //TX_FDEQ_SUBNUM +567 0x5850 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4848 //TX_FDEQ_GAIN_5 +573 0x4848 //TX_FDEQ_GAIN_6 +574 0x4848 //TX_FDEQ_GAIN_7 +575 0x4848 //TX_FDEQ_GAIN_8 +576 0x4848 //TX_FDEQ_GAIN_9 +577 0x4848 //TX_FDEQ_GAIN_10 +578 0x4848 //TX_FDEQ_GAIN_11 +579 0x4848 //TX_FDEQ_GAIN_12 +580 0x4848 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0302 //TX_FDEQ_BIN_1 +593 0x0303 //TX_FDEQ_BIN_2 +594 0x0304 //TX_FDEQ_BIN_3 +595 0x0405 //TX_FDEQ_BIN_4 +596 0x0506 //TX_FDEQ_BIN_5 +597 0x0708 //TX_FDEQ_BIN_6 +598 0x090A //TX_FDEQ_BIN_7 +599 0x0B0C //TX_FDEQ_BIN_8 +600 0x0D07 //TX_FDEQ_BIN_9 +601 0x0E0F //TX_FDEQ_BIN_10 +602 0x0F10 //TX_FDEQ_BIN_11 +603 0x1011 //TX_FDEQ_BIN_12 +604 0x1119 //TX_FDEQ_BIN_13 +605 0x0000 //TX_FDEQ_BIN_14 +606 0x0000 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4848 //TX_PREEQ_GAIN_MIC0_8 +626 0x4848 //TX_PREEQ_GAIN_MIC0_9 +627 0x4848 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0608 //TX_PREEQ_BIN_MIC0_0 +642 0x0808 //TX_PREEQ_BIN_MIC0_1 +643 0x0808 //TX_PREEQ_BIN_MIC0_2 +644 0x0808 //TX_PREEQ_BIN_MIC0_3 +645 0x0808 //TX_PREEQ_BIN_MIC0_4 +646 0x0808 //TX_PREEQ_BIN_MIC0_5 +647 0x0808 //TX_PREEQ_BIN_MIC0_6 +648 0x0808 //TX_PREEQ_BIN_MIC0_7 +649 0x0808 //TX_PREEQ_BIN_MIC0_8 +650 0x0808 //TX_PREEQ_BIN_MIC0_9 +651 0x0808 //TX_PREEQ_BIN_MIC0_10 +652 0x0808 //TX_PREEQ_BIN_MIC0_11 +653 0x0808 //TX_PREEQ_BIN_MIC0_12 +654 0x0808 //TX_PREEQ_BIN_MIC0_13 +655 0x0808 //TX_PREEQ_BIN_MIC0_14 +656 0x0200 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0608 //TX_PREEQ_BIN_MIC1_0 +691 0x0808 //TX_PREEQ_BIN_MIC1_1 +692 0x0808 //TX_PREEQ_BIN_MIC1_2 +693 0x0808 //TX_PREEQ_BIN_MIC1_3 +694 0x0808 //TX_PREEQ_BIN_MIC1_4 +695 0x0808 //TX_PREEQ_BIN_MIC1_5 +696 0x0808 //TX_PREEQ_BIN_MIC1_6 +697 0x0808 //TX_PREEQ_BIN_MIC1_7 +698 0x0808 //TX_PREEQ_BIN_MIC1_8 +699 0x0808 //TX_PREEQ_BIN_MIC1_9 +700 0x0808 //TX_PREEQ_BIN_MIC1_10 +701 0x0808 //TX_PREEQ_BIN_MIC1_11 +702 0x0808 //TX_PREEQ_BIN_MIC1_12 +703 0x0808 //TX_PREEQ_BIN_MIC1_13 +704 0x0808 //TX_PREEQ_BIN_MIC1_14 +705 0x0200 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0608 //TX_PREEQ_BIN_MIC2_0 +740 0x0808 //TX_PREEQ_BIN_MIC2_1 +741 0x0808 //TX_PREEQ_BIN_MIC2_2 +742 0x0808 //TX_PREEQ_BIN_MIC2_3 +743 0x0808 //TX_PREEQ_BIN_MIC2_4 +744 0x0808 //TX_PREEQ_BIN_MIC2_5 +745 0x0808 //TX_PREEQ_BIN_MIC2_6 +746 0x0808 //TX_PREEQ_BIN_MIC2_7 +747 0x0808 //TX_PREEQ_BIN_MIC2_8 +748 0x0808 //TX_PREEQ_BIN_MIC2_9 +749 0x0808 //TX_PREEQ_BIN_MIC2_10 +750 0x0808 //TX_PREEQ_BIN_MIC2_11 +751 0x0808 //TX_PREEQ_BIN_MIC2_12 +752 0x0808 //TX_PREEQ_BIN_MIC2_13 +753 0x0808 //TX_PREEQ_BIN_MIC2_14 +754 0x0200 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x0800 //TX_NND_WEIGHT +765 0x0062 //TX_MIC_CALIBRATION_0 +766 0x0062 //TX_MIC_CALIBRATION_1 +767 0x0062 //TX_MIC_CALIBRATION_2 +768 0x0062 //TX_MIC_CALIBRATION_3 +769 0x0046 //TX_MIC_PWR_BIAS_0 +770 0x0046 //TX_MIC_PWR_BIAS_1 +771 0x0046 //TX_MIC_PWR_BIAS_2 +772 0x0046 //TX_MIC_PWR_BIAS_3 +773 0x000C //TX_GAIN_LIMIT_0 +774 0x000C //TX_GAIN_LIMIT_1 +775 0x000C //TX_GAIN_LIMIT_2 +776 0x000C //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x1000 //TX_TDDRC_ALPHA_UP_01 +784 0x1000 //TX_TDDRC_ALPHA_UP_02 +785 0x1000 //TX_TDDRC_ALPHA_UP_03 +786 0x1000 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x7FFF //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0000 //TX_DEADMIC_SILENCE_TH +817 0x0000 //TX_MIC_DEGRADE_TH +818 0x0000 //TX_DEADMIC_CNT +819 0x0000 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x0000 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0000 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0001 //TX_FILTINDX +854 0x0000 //TX_TDDRC_THRD_0 +855 0x0000 //TX_TDDRC_THRD_1 +856 0x2000 //TX_TDDRC_THRD_2 +857 0x2000 //TX_TDDRC_THRD_3 +858 0x3000 //TX_TDDRC_SLANT_0 +859 0x6E00 //TX_TDDRC_SLANT_1 +860 0x1000 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x05A0 //TX_TDDRC_DRC_GAIN +867 0x7FFF //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x00C8 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x4000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x2339 //TX_SENDFUNC_REG_MICMUTE +898 0x0021 //TX_SENDFUNC_REG_MICMUTE1 +899 0x02BC //TX_MICMUTE_RATIO_THR +900 0x0140 //TX_MICMUTE_AMP_THR +901 0x0004 //TX_MICMUTE_HPF_IND +902 0x00C0 //TX_MICMUTE_LOG_EYR_TH +903 0x0008 //TX_MICMUTE_CVG_TIME +904 0x0008 //TX_MICMUTE_RELEASE_TIME +905 0x01FE //TX_MIC_VOLUME_MIC0MUTE +906 0x0020 //TX_MICMUTE_EPD_OFFSET_0 +907 0x001E //TX_MICMUTE_FRQ_AEC_L +908 0x7999 //TX_MICMUTE_EAD_THR +909 0x7FFF //TX_MICMUTE_LAMBDA_CB_NLE +910 0x7FFF //TX_MICMUTE_LAMBDA_RE_EST +911 0x4000 //TX_DTD_THR1_MICMUTE_0 +912 0x7000 //TX_DTD_THR1_MICMUTE_1 +913 0x7FFF //TX_DTD_THR1_MICMUTE_2 +914 0x7FFF //TX_DTD_THR1_MICMUTE_3 +915 0x6CCC //TX_DTD_THR2_MICMUTE_0 +916 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x1000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x4000 //TX_MICMUTE_C_POST_FLT +922 0x03E8 //TX_MICMUTE_DT_CUT_K +923 0x0001 //TX_MICMUTE_DT_CUT_THR +924 0x03E8 //TX_MICMUTE_DT_CUT_K2 +925 0x0001 //TX_MICMUTE_DT_CUT_THR2 +926 0x0064 //TX_MICMUTE_DT2_HOLD_N +927 0x1000 //TX_MICMUTE_RATIODTH_THCUT +928 0x1000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x7FFF //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0400 //TX_MICMUTE_C_POST_FLT_MASK +931 0x7999 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0258 //TX_MICMUTE_DT_CUT_K1 +933 0x0800 //TX_MICMUTE_N2_SN_EST +934 0xFC00 //TX_MICMUTE_THR_SN_EST_0 +935 0x001C //TX_MICMUTE_MIN_G_CTRL_0 +936 0x6000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x7000 //TX_MICMUTE_B_POST_FILT_0 +938 0x2710 //TX_MIC1RUB_AMP_THR +939 0x0010 //TX_MIC1MUTE_RATIO_THR +940 0x0450 //TX_MIC1MUTE_AMP_THR +941 0x0008 //TX_MIC1MUTE_CVG_TIME +942 0x0008 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x202C //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0001 //RX_SAMPLINGFREQ_SIG +3 0x0001 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7FFF //RX_A_HP +12 0x4000 //RX_B_PE +13 0x3800 //RX_THR_PITCH_DET_0 +14 0x3000 //RX_THR_PITCH_DET_1 +15 0x2800 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0600 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x0010 //RX_NS_LVL_CTRL +23 0xF800 //RX_THR_SN_EST +24 0x7CCD //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0002 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0196 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x2000 //RX_MIN_G_FP +128 0x0080 //RX_MAX_G_FP +129 0x000B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0196 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x000B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0196 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0013 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0196 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0020 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0196 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0036 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0196 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x005B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0196 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0099 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0196 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x202C //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0001 //RX_SAMPLINGFREQ_SIG +160 0x0001 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7FFF //RX_A_HP +169 0x4000 //RX_B_PE +170 0x3800 //RX_THR_PITCH_DET_0 +171 0x3000 //RX_THR_PITCH_DET_1 +172 0x2800 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0600 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x0010 //RX_NS_LVL_CTRL +180 0xF800 //RX_THR_SN_EST +181 0x7CCD //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0002 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0196 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x2000 //RX_MIN_G_FP +285 0x0080 //RX_MAX_G_FP +286 0x000B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0196 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x000B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0196 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0013 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0196 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0020 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0196 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0036 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0196 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x005B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0196 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0099 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0196 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME HEADSET-GOOGLE_CONDOR-VOICE_GENERIC-SWB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0009 //TX_OPERATION_MODE_0 +1 0x0001 //TX_OPERATION_MODE_1 +2 0x0033 //TX_PATCH_REG +3 0x2B68 //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0001 //TX_NUM_MIC +6 0x0003 //TX_SAMPLINGFREQ_SIG +7 0x0003 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009B //TX_DIST2REF1 +22 0x0000 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0B80 //TX_PGA_0 +28 0x0800 //TX_PGA_1 +29 0x0800 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0000 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0001 //TX_MIC_DATA_SRC1 +43 0x0002 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3E00 //TX_DIST2REF_11 +73 0x0000 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0200 //TX_MIC_REFBLK_VOLUME +108 0x0800 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0000 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7EFF //TX_A_HP +129 0x4000 //TX_B_PE +130 0x1800 //TX_THR_PITCH_DET_0 +131 0x1000 //TX_THR_PITCH_DET_1 +132 0x0800 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x001E //TX_TAIL_LENGTH +147 0x0080 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x7000 //TX_EAD_THR +151 0x0800 //TX_THR_RE_EST +152 0x0800 //TX_MIN_EQ_RE_EST_0 +153 0x0800 //TX_MIN_EQ_RE_EST_1 +154 0x0800 //TX_MIN_EQ_RE_EST_2 +155 0x0800 //TX_MIN_EQ_RE_EST_3 +156 0x0800 //TX_MIN_EQ_RE_EST_4 +157 0x0800 //TX_MIN_EQ_RE_EST_5 +158 0x0800 //TX_MIN_EQ_RE_EST_6 +159 0x0800 //TX_MIN_EQ_RE_EST_7 +160 0x0800 //TX_MIN_EQ_RE_EST_8 +161 0x0800 //TX_MIN_EQ_RE_EST_9 +162 0x0800 //TX_MIN_EQ_RE_EST_10 +163 0x0800 //TX_MIN_EQ_RE_EST_11 +164 0x0800 //TX_MIN_EQ_RE_EST_12 +165 0x4000 //TX_LAMBDA_RE_EST +166 0x2000 //TX_LAMBDA_CB_NLE +167 0x6000 //TX_C_POST_FLT +168 0x7000 //TX_GAIN_NP +169 0x00C8 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x03E8 //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x7800 //TX_DTD_THR1_0 +198 0x7000 //TX_DTD_THR1_1 +199 0x7FFF //TX_DTD_THR1_2 +200 0x7FFF //TX_DTD_THR1_3 +201 0x7FFF //TX_DTD_THR1_4 +202 0x7FFF //TX_DTD_THR1_5 +203 0x7FFF //TX_DTD_THR1_6 +204 0x7FFF //TX_DTD_THR2_0 +205 0x7FFF //TX_DTD_THR2_1 +206 0x7FFF //TX_DTD_THR2_2 +207 0x7FFF //TX_DTD_THR2_3 +208 0x7FFF //TX_DTD_THR2_4 +209 0x7FFF //TX_DTD_THR2_5 +210 0x7FFF //TX_DTD_THR2_6 +211 0x1000 //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x0BB8 //TX_DT_CUT_K +214 0x0CCD //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x0400 //TX_ADPT_STRICT_L +222 0x0200 //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x0800 //TX_B_POST_FILT_ECHO_L +229 0x7FFF //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x7FFF //TX_B_LESSCUT_RTO_ECHO +232 0x00F0 //TX_EPD_OFFSET_00 +233 0x00F0 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x7FFF //TX_DTD_THR1_7 +238 0x7FFF //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xFA00 //TX_THR_SN_EST_0 +243 0xF400 //TX_THR_SN_EST_1 +244 0xF600 //TX_THR_SN_EST_2 +245 0xF400 //TX_THR_SN_EST_3 +246 0xF400 //TX_THR_SN_EST_4 +247 0xF400 //TX_THR_SN_EST_5 +248 0xF400 //TX_THR_SN_EST_6 +249 0xF600 //TX_THR_SN_EST_7 +250 0x0000 //TX_DELTA_THR_SN_EST_0 +251 0x0200 //TX_DELTA_THR_SN_EST_1 +252 0x0200 //TX_DELTA_THR_SN_EST_2 +253 0x0200 //TX_DELTA_THR_SN_EST_3 +254 0x0200 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0000 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x6000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x6000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x1000 //TX_B_POST_FLT_0 +280 0x1000 //TX_B_POST_FLT_1 +281 0x000B //TX_NS_LVL_CTRL_0 +282 0x0011 //TX_NS_LVL_CTRL_1 +283 0x000F //TX_NS_LVL_CTRL_2 +284 0x000F //TX_NS_LVL_CTRL_3 +285 0x000F //TX_NS_LVL_CTRL_4 +286 0x000F //TX_NS_LVL_CTRL_5 +287 0x000F //TX_NS_LVL_CTRL_6 +288 0x0011 //TX_NS_LVL_CTRL_7 +289 0x000C //TX_MIN_GAIN_S_0 +290 0x000F //TX_MIN_GAIN_S_1 +291 0x000C //TX_MIN_GAIN_S_2 +292 0x000C //TX_MIN_GAIN_S_3 +293 0x000C //TX_MIN_GAIN_S_4 +294 0x000C //TX_MIN_GAIN_S_5 +295 0x000C //TX_MIN_GAIN_S_6 +296 0x000F //TX_MIN_GAIN_S_7 +297 0x7FFF //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x7FFF //TX_SNRI_SUP_1 +302 0x7FFF //TX_SNRI_SUP_2 +303 0x7FFF //TX_SNRI_SUP_3 +304 0x7FFF //TX_SNRI_SUP_4 +305 0x7FFF //TX_SNRI_SUP_5 +306 0x7FFF //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x000E //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x2000 //TX_A_POST_FILT_S_0 +315 0x5000 //TX_A_POST_FILT_S_1 +316 0x5000 //TX_A_POST_FILT_S_2 +317 0x5000 //TX_A_POST_FILT_S_3 +318 0x5000 //TX_A_POST_FILT_S_4 +319 0x5000 //TX_A_POST_FILT_S_5 +320 0x4000 //TX_A_POST_FILT_S_6 +321 0x5000 //TX_A_POST_FILT_S_7 +322 0x1000 //TX_B_POST_FILT_0 +323 0x1000 //TX_B_POST_FILT_1 +324 0x1000 //TX_B_POST_FILT_2 +325 0x1000 //TX_B_POST_FILT_3 +326 0x1000 //TX_B_POST_FILT_4 +327 0x1000 //TX_B_POST_FILT_5 +328 0x1000 //TX_B_POST_FILT_6 +329 0x1000 //TX_B_POST_FILT_7 +330 0x7FFF //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x7FFF //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7900 //TX_LAMBDA_PFILT +339 0x7B00 //TX_LAMBDA_PFILT_S_0 +340 0x7B00 //TX_LAMBDA_PFILT_S_1 +341 0x7B00 //TX_LAMBDA_PFILT_S_2 +342 0x7B00 //TX_LAMBDA_PFILT_S_3 +343 0x7B00 //TX_LAMBDA_PFILT_S_4 +344 0x7B00 //TX_LAMBDA_PFILT_S_5 +345 0x7B00 //TX_LAMBDA_PFILT_S_6 +346 0x7B00 //TX_LAMBDA_PFILT_S_7 +347 0x0000 //TX_K_PEPPER +348 0x0800 //TX_A_PEPPER +349 0x1EAA //TX_K_PEPPER_HF +350 0x0800 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0800 //TX_DT_BINVAD_TH_0 +354 0x0800 //TX_DT_BINVAD_TH_1 +355 0x0800 //TX_DT_BINVAD_TH_2 +356 0x0800 //TX_DT_BINVAD_TH_3 +357 0x1D4C //TX_DT_BINVAD_ENDF +358 0x0000 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0190 //TX_NDETCT +367 0x0383 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x07D0 //TX_NOISE_TH_1 +371 0x00C8 //TX_NOISE_TH_2 +372 0x3A98 //TX_NOISE_TH_3 +373 0x0FA0 //TX_NOISE_TH_4 +374 0x157C //TX_NOISE_TH_5 +375 0x7FFF //TX_NOISE_TH_5_2 +376 0x7FFF //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x044C //TX_NOISE_TH_6 +379 0x044C //TX_MINENOISE_TH +380 0xD508 //TX_MORENS_TFMASK_TH +381 0x0001 //TX_DRC_QUIET_FLOOR +382 0x3A98 //TX_RATIODTL_CUT_TH +383 0x0DAC //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x0333 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x7FFF //TX_POST_MASK_SUP_HSNE +392 0x1388 //TX_TAIL_DET_TH +393 0x4000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0080 //TX_SUPHIGH_TH +396 0x0000 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x1800 //TX_C_POST_FLT_MASK +399 0x7FFF //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0002 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x02F3 //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x2900 //TX_MIN_G_CTRL_SSNS +409 0x0800 //TX_METAL_RTO_THR +410 0x4848 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x4000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x01E0 //TX_NOR_OFF_THR +498 0x7C00 //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0xD333 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x6000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0xC000 //TX_DEREVERB_LF_MU +515 0xC000 //TX_DEREVERB_HF_MU +516 0xCCCC //TX_DEREVERB_DELAY +517 0xD999 //TX_DEREVERB_COEF_LEN +518 0x1F40 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x7000 //TX_GSC_RTOH_TH +523 0x0064 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0020 //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4848 //TX_FDEQ_GAIN_5 +573 0x4848 //TX_FDEQ_GAIN_6 +574 0x4848 //TX_FDEQ_GAIN_7 +575 0x4848 //TX_FDEQ_GAIN_8 +576 0x4848 //TX_FDEQ_GAIN_9 +577 0x4848 //TX_FDEQ_GAIN_10 +578 0x4848 //TX_FDEQ_GAIN_11 +579 0x4848 //TX_FDEQ_GAIN_12 +580 0x4848 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0303 //TX_FDEQ_BIN_2 +594 0x0304 //TX_FDEQ_BIN_3 +595 0x0405 //TX_FDEQ_BIN_4 +596 0x0506 //TX_FDEQ_BIN_5 +597 0x0708 //TX_FDEQ_BIN_6 +598 0x090A //TX_FDEQ_BIN_7 +599 0x0B0C //TX_FDEQ_BIN_8 +600 0x0D0E //TX_FDEQ_BIN_9 +601 0x1013 //TX_FDEQ_BIN_10 +602 0x1719 //TX_FDEQ_BIN_11 +603 0x1B1E //TX_FDEQ_BIN_12 +604 0x1E1E //TX_FDEQ_BIN_13 +605 0x1E28 //TX_FDEQ_BIN_14 +606 0x282C //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4868 //TX_PREEQ_GAIN_MIC0_8 +626 0x6860 //TX_PREEQ_GAIN_MIC0_9 +627 0x6048 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0E10 //TX_PREEQ_BIN_MIC0_0 +642 0x1010 //TX_PREEQ_BIN_MIC0_1 +643 0x1010 //TX_PREEQ_BIN_MIC0_2 +644 0x1010 //TX_PREEQ_BIN_MIC0_3 +645 0x1010 //TX_PREEQ_BIN_MIC0_4 +646 0x1010 //TX_PREEQ_BIN_MIC0_5 +647 0x1010 //TX_PREEQ_BIN_MIC0_6 +648 0x1010 //TX_PREEQ_BIN_MIC0_7 +649 0x1010 //TX_PREEQ_BIN_MIC0_8 +650 0x1010 //TX_PREEQ_BIN_MIC0_9 +651 0x1010 //TX_PREEQ_BIN_MIC0_10 +652 0x1010 //TX_PREEQ_BIN_MIC0_11 +653 0x1010 //TX_PREEQ_BIN_MIC0_12 +654 0x1010 //TX_PREEQ_BIN_MIC0_13 +655 0x1010 //TX_PREEQ_BIN_MIC0_14 +656 0x0200 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0E10 //TX_PREEQ_BIN_MIC1_0 +691 0x1010 //TX_PREEQ_BIN_MIC1_1 +692 0x1010 //TX_PREEQ_BIN_MIC1_2 +693 0x1010 //TX_PREEQ_BIN_MIC1_3 +694 0x1010 //TX_PREEQ_BIN_MIC1_4 +695 0x1010 //TX_PREEQ_BIN_MIC1_5 +696 0x1010 //TX_PREEQ_BIN_MIC1_6 +697 0x1010 //TX_PREEQ_BIN_MIC1_7 +698 0x1010 //TX_PREEQ_BIN_MIC1_8 +699 0x1010 //TX_PREEQ_BIN_MIC1_9 +700 0x1010 //TX_PREEQ_BIN_MIC1_10 +701 0x1010 //TX_PREEQ_BIN_MIC1_11 +702 0x1010 //TX_PREEQ_BIN_MIC1_12 +703 0x1010 //TX_PREEQ_BIN_MIC1_13 +704 0x1010 //TX_PREEQ_BIN_MIC1_14 +705 0x0200 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0E10 //TX_PREEQ_BIN_MIC2_0 +740 0x1010 //TX_PREEQ_BIN_MIC2_1 +741 0x1010 //TX_PREEQ_BIN_MIC2_2 +742 0x1010 //TX_PREEQ_BIN_MIC2_3 +743 0x1010 //TX_PREEQ_BIN_MIC2_4 +744 0x1010 //TX_PREEQ_BIN_MIC2_5 +745 0x1010 //TX_PREEQ_BIN_MIC2_6 +746 0x1010 //TX_PREEQ_BIN_MIC2_7 +747 0x1010 //TX_PREEQ_BIN_MIC2_8 +748 0x1010 //TX_PREEQ_BIN_MIC2_9 +749 0x1010 //TX_PREEQ_BIN_MIC2_10 +750 0x1010 //TX_PREEQ_BIN_MIC2_11 +751 0x1010 //TX_PREEQ_BIN_MIC2_12 +752 0x1010 //TX_PREEQ_BIN_MIC2_13 +753 0x1010 //TX_PREEQ_BIN_MIC2_14 +754 0x0200 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x0800 //TX_NND_WEIGHT +765 0x0062 //TX_MIC_CALIBRATION_0 +766 0x0062 //TX_MIC_CALIBRATION_1 +767 0x0062 //TX_MIC_CALIBRATION_2 +768 0x0062 //TX_MIC_CALIBRATION_3 +769 0x0046 //TX_MIC_PWR_BIAS_0 +770 0x0046 //TX_MIC_PWR_BIAS_1 +771 0x0046 //TX_MIC_PWR_BIAS_2 +772 0x0046 //TX_MIC_PWR_BIAS_3 +773 0x000C //TX_GAIN_LIMIT_0 +774 0x000C //TX_GAIN_LIMIT_1 +775 0x000C //TX_GAIN_LIMIT_2 +776 0x000C //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x3000 //TX_TDDRC_ALPHA_UP_01 +784 0x3000 //TX_TDDRC_ALPHA_UP_02 +785 0x3000 //TX_TDDRC_ALPHA_UP_03 +786 0x3000 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x78D6 //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0000 //TX_DEADMIC_SILENCE_TH +817 0x0000 //TX_MIC_DEGRADE_TH +818 0x0000 //TX_DEADMIC_CNT +819 0x0000 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x4848 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0000 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0000 //TX_FILTINDX +854 0x0000 //TX_TDDRC_THRD_0 +855 0x0000 //TX_TDDRC_THRD_1 +856 0x2000 //TX_TDDRC_THRD_2 +857 0x2000 //TX_TDDRC_THRD_3 +858 0x3000 //TX_TDDRC_SLANT_0 +859 0x6E00 //TX_TDDRC_SLANT_1 +860 0x3000 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x05A0 //TX_TDDRC_DRC_GAIN +867 0x78D6 //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x0028 //TX_FASTNS_ARSPC_TH +889 0x8000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x4000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x2339 //TX_SENDFUNC_REG_MICMUTE +898 0x0021 //TX_SENDFUNC_REG_MICMUTE1 +899 0x02BC //TX_MICMUTE_RATIO_THR +900 0x0140 //TX_MICMUTE_AMP_THR +901 0x0004 //TX_MICMUTE_HPF_IND +902 0x00C0 //TX_MICMUTE_LOG_EYR_TH +903 0x0008 //TX_MICMUTE_CVG_TIME +904 0x0008 //TX_MICMUTE_RELEASE_TIME +905 0x01FE //TX_MIC_VOLUME_MIC0MUTE +906 0x0020 //TX_MICMUTE_EPD_OFFSET_0 +907 0x001E //TX_MICMUTE_FRQ_AEC_L +908 0x7999 //TX_MICMUTE_EAD_THR +909 0x7FFF //TX_MICMUTE_LAMBDA_CB_NLE +910 0x7FFF //TX_MICMUTE_LAMBDA_RE_EST +911 0x4000 //TX_DTD_THR1_MICMUTE_0 +912 0x7000 //TX_DTD_THR1_MICMUTE_1 +913 0x7FFF //TX_DTD_THR1_MICMUTE_2 +914 0x7FFF //TX_DTD_THR1_MICMUTE_3 +915 0x6CCC //TX_DTD_THR2_MICMUTE_0 +916 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x1000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x4000 //TX_MICMUTE_C_POST_FLT +922 0x03E8 //TX_MICMUTE_DT_CUT_K +923 0x0001 //TX_MICMUTE_DT_CUT_THR +924 0x03E8 //TX_MICMUTE_DT_CUT_K2 +925 0x0001 //TX_MICMUTE_DT_CUT_THR2 +926 0x0064 //TX_MICMUTE_DT2_HOLD_N +927 0x1000 //TX_MICMUTE_RATIODTH_THCUT +928 0x1000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x7FFF //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0400 //TX_MICMUTE_C_POST_FLT_MASK +931 0x7999 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0258 //TX_MICMUTE_DT_CUT_K1 +933 0x0800 //TX_MICMUTE_N2_SN_EST +934 0xFC00 //TX_MICMUTE_THR_SN_EST_0 +935 0x001C //TX_MICMUTE_MIN_G_CTRL_0 +936 0x6000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x7000 //TX_MICMUTE_B_POST_FILT_0 +938 0x2710 //TX_MIC1RUB_AMP_THR +939 0x0010 //TX_MIC1MUTE_RATIO_THR +940 0x0450 //TX_MIC1MUTE_AMP_THR +941 0x0008 //TX_MIC1MUTE_CVG_TIME +942 0x0008 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x202C //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0003 //RX_SAMPLINGFREQ_SIG +3 0x0003 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x5000 //RX_TDDRC_ALPHA_UP_1 +7 0x5000 //RX_TDDRC_ALPHA_UP_2 +8 0x5000 //RX_TDDRC_ALPHA_UP_3 +9 0x2000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7FFF //RX_A_HP +12 0x0000 //RX_B_PE +13 0x1800 //RX_THR_PITCH_DET_0 +14 0x1000 //RX_THR_PITCH_DET_1 +15 0x0800 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0400 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x0003 //RX_NS_LVL_CTRL +23 0x9000 //RX_THR_SN_EST +24 0x7CCD //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x65AD //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0002 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x5000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x01C8 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x2000 //RX_MIN_G_FP +128 0x0080 //RX_MAX_G_FP +129 0x000B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x5000 //RX_TDDRC_ALPHA_UP_1 +7 0x5000 //RX_TDDRC_ALPHA_UP_2 +8 0x5000 //RX_TDDRC_ALPHA_UP_3 +9 0x2000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x65AD //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x5000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x01C8 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x000B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x5000 //RX_TDDRC_ALPHA_UP_1 +7 0x5000 //RX_TDDRC_ALPHA_UP_2 +8 0x5000 //RX_TDDRC_ALPHA_UP_3 +9 0x2000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x65AD //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x5000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x01C8 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0013 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x5000 //RX_TDDRC_ALPHA_UP_1 +7 0x5000 //RX_TDDRC_ALPHA_UP_2 +8 0x5000 //RX_TDDRC_ALPHA_UP_3 +9 0x2000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x65AD //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x5000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x01C8 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0020 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x5000 //RX_TDDRC_ALPHA_UP_1 +7 0x5000 //RX_TDDRC_ALPHA_UP_2 +8 0x5000 //RX_TDDRC_ALPHA_UP_3 +9 0x2000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x65AD //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x5000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x01C8 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0036 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x5000 //RX_TDDRC_ALPHA_UP_1 +7 0x5000 //RX_TDDRC_ALPHA_UP_2 +8 0x5000 //RX_TDDRC_ALPHA_UP_3 +9 0x2000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x65AD //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x5000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x01C8 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x005B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x5000 //RX_TDDRC_ALPHA_UP_1 +7 0x5000 //RX_TDDRC_ALPHA_UP_2 +8 0x5000 //RX_TDDRC_ALPHA_UP_3 +9 0x2000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x65AD //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x5000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x01C8 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0099 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x5000 //RX_TDDRC_ALPHA_UP_1 +7 0x5000 //RX_TDDRC_ALPHA_UP_2 +8 0x5000 //RX_TDDRC_ALPHA_UP_3 +9 0x2000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x65AD //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x5000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x01C8 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x202C //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0003 //RX_SAMPLINGFREQ_SIG +160 0x0003 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x5000 //RX_TDDRC_ALPHA_UP_1 +164 0x5000 //RX_TDDRC_ALPHA_UP_2 +165 0x5000 //RX_TDDRC_ALPHA_UP_3 +166 0x2000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7FFF //RX_A_HP +169 0x0000 //RX_B_PE +170 0x1800 //RX_THR_PITCH_DET_0 +171 0x1000 //RX_THR_PITCH_DET_1 +172 0x0800 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0400 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x0003 //RX_NS_LVL_CTRL +180 0x9000 //RX_THR_SN_EST +181 0x7CCD //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x65AD //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0002 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x5000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x01C8 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x2000 //RX_MIN_G_FP +285 0x0080 //RX_MAX_G_FP +286 0x000B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x5000 //RX_TDDRC_ALPHA_UP_1 +164 0x5000 //RX_TDDRC_ALPHA_UP_2 +165 0x5000 //RX_TDDRC_ALPHA_UP_3 +166 0x2000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x65AD //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x5000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x01C8 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x000B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x5000 //RX_TDDRC_ALPHA_UP_1 +164 0x5000 //RX_TDDRC_ALPHA_UP_2 +165 0x5000 //RX_TDDRC_ALPHA_UP_3 +166 0x2000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x65AD //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x5000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x01C8 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0013 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x5000 //RX_TDDRC_ALPHA_UP_1 +164 0x5000 //RX_TDDRC_ALPHA_UP_2 +165 0x5000 //RX_TDDRC_ALPHA_UP_3 +166 0x2000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x65AD //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x5000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x01C8 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0020 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x5000 //RX_TDDRC_ALPHA_UP_1 +164 0x5000 //RX_TDDRC_ALPHA_UP_2 +165 0x5000 //RX_TDDRC_ALPHA_UP_3 +166 0x2000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x65AD //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x5000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x01C8 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0036 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x5000 //RX_TDDRC_ALPHA_UP_1 +164 0x5000 //RX_TDDRC_ALPHA_UP_2 +165 0x5000 //RX_TDDRC_ALPHA_UP_3 +166 0x2000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x65AD //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x5000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x01C8 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x005B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x5000 //RX_TDDRC_ALPHA_UP_1 +164 0x5000 //RX_TDDRC_ALPHA_UP_2 +165 0x5000 //RX_TDDRC_ALPHA_UP_3 +166 0x2000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x65AD //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x5000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x01C8 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0099 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x5000 //RX_TDDRC_ALPHA_UP_1 +164 0x5000 //RX_TDDRC_ALPHA_UP_2 +165 0x5000 //RX_TDDRC_ALPHA_UP_3 +166 0x2000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x65AD //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x5000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x01C8 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME HEADSET-GOOGLE_CONDOR-VOICE_GENERIC-FB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0009 //TX_OPERATION_MODE_0 +1 0x0009 //TX_OPERATION_MODE_1 +2 0x0020 //TX_PATCH_REG +3 0x6B6A //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0001 //TX_NUM_MIC +6 0x0004 //TX_SAMPLINGFREQ_SIG +7 0x0004 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009B //TX_DIST2REF1 +22 0x0000 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0B4C //TX_PGA_0 +28 0x0800 //TX_PGA_1 +29 0x0000 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0000 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0001 //TX_MIC_DATA_SRC1 +43 0x0002 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3E00 //TX_DIST2REF_11 +73 0x0000 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0200 //TX_MIC_REFBLK_VOLUME +108 0x0800 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0000 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7E56 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x6800 //TX_THR_PITCH_DET_0 +131 0x6000 //TX_THR_PITCH_DET_1 +132 0x5800 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x001E //TX_TAIL_LENGTH +147 0x0200 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x61A8 //TX_EAD_THR +151 0x0400 //TX_THR_RE_EST +152 0x3000 //TX_MIN_EQ_RE_EST_0 +153 0x3000 //TX_MIN_EQ_RE_EST_1 +154 0x4000 //TX_MIN_EQ_RE_EST_2 +155 0x0800 //TX_MIN_EQ_RE_EST_3 +156 0x0800 //TX_MIN_EQ_RE_EST_4 +157 0x0800 //TX_MIN_EQ_RE_EST_5 +158 0x6000 //TX_MIN_EQ_RE_EST_6 +159 0x6000 //TX_MIN_EQ_RE_EST_7 +160 0x6000 //TX_MIN_EQ_RE_EST_8 +161 0x6000 //TX_MIN_EQ_RE_EST_9 +162 0x4000 //TX_MIN_EQ_RE_EST_10 +163 0x4000 //TX_MIN_EQ_RE_EST_11 +164 0x4000 //TX_MIN_EQ_RE_EST_12 +165 0x3000 //TX_LAMBDA_RE_EST +166 0x4000 //TX_LAMBDA_CB_NLE +167 0x3000 //TX_C_POST_FLT +168 0x7FFF //TX_GAIN_NP +169 0x00C8 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x03E8 //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x0800 //TX_DTD_THR1_0 +198 0x0800 //TX_DTD_THR1_1 +199 0x0800 //TX_DTD_THR1_2 +200 0x0800 //TX_DTD_THR1_3 +201 0x0800 //TX_DTD_THR1_4 +202 0x0800 //TX_DTD_THR1_5 +203 0x0800 //TX_DTD_THR1_6 +204 0x0800 //TX_DTD_THR2_0 +205 0x0800 //TX_DTD_THR2_1 +206 0x0800 //TX_DTD_THR2_2 +207 0x0800 //TX_DTD_THR2_3 +208 0x0800 //TX_DTD_THR2_4 +209 0x0100 //TX_DTD_THR2_5 +210 0x0100 //TX_DTD_THR2_6 +211 0x7FFF //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x03E8 //TX_DT_CUT_K +214 0x0CCD //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x0400 //TX_ADPT_STRICT_L +222 0x0200 //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x0800 //TX_B_POST_FILT_ECHO_L +229 0x7FFF //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x7FFF //TX_B_LESSCUT_RTO_ECHO +232 0x00C0 //TX_EPD_OFFSET_00 +233 0x00C0 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x7FFF //TX_DTD_THR1_7 +238 0x7FFF //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xF700 //TX_THR_SN_EST_0 +243 0xFB00 //TX_THR_SN_EST_1 +244 0xFA00 //TX_THR_SN_EST_2 +245 0xF700 //TX_THR_SN_EST_3 +246 0xFA00 //TX_THR_SN_EST_4 +247 0xF600 //TX_THR_SN_EST_5 +248 0xF600 //TX_THR_SN_EST_6 +249 0xF600 //TX_THR_SN_EST_7 +250 0x0200 //TX_DELTA_THR_SN_EST_0 +251 0x0400 //TX_DELTA_THR_SN_EST_1 +252 0x0300 //TX_DELTA_THR_SN_EST_2 +253 0x0600 //TX_DELTA_THR_SN_EST_3 +254 0x0200 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0200 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x4000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x4000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x2000 //TX_B_POST_FLT_0 +280 0x2000 //TX_B_POST_FLT_1 +281 0x0012 //TX_NS_LVL_CTRL_0 +282 0x0016 //TX_NS_LVL_CTRL_1 +283 0x0016 //TX_NS_LVL_CTRL_2 +284 0x0019 //TX_NS_LVL_CTRL_3 +285 0x0010 //TX_NS_LVL_CTRL_4 +286 0x0010 //TX_NS_LVL_CTRL_5 +287 0x0019 //TX_NS_LVL_CTRL_6 +288 0x0010 //TX_NS_LVL_CTRL_7 +289 0x000C //TX_MIN_GAIN_S_0 +290 0x000C //TX_MIN_GAIN_S_1 +291 0x000C //TX_MIN_GAIN_S_2 +292 0x000F //TX_MIN_GAIN_S_3 +293 0x000C //TX_MIN_GAIN_S_4 +294 0x000C //TX_MIN_GAIN_S_5 +295 0x0011 //TX_MIN_GAIN_S_6 +296 0x000C //TX_MIN_GAIN_S_7 +297 0x7FFF //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7000 //TX_SNRI_SUP_0 +301 0x7000 //TX_SNRI_SUP_1 +302 0x7000 //TX_SNRI_SUP_2 +303 0x6000 //TX_SNRI_SUP_3 +304 0x7FFF //TX_SNRI_SUP_4 +305 0x7FFF //TX_SNRI_SUP_5 +306 0x6000 //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x0016 //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x6000 //TX_A_POST_FILT_S_0 +315 0x6000 //TX_A_POST_FILT_S_1 +316 0x6000 //TX_A_POST_FILT_S_2 +317 0x6000 //TX_A_POST_FILT_S_3 +318 0x6000 //TX_A_POST_FILT_S_4 +319 0x6000 //TX_A_POST_FILT_S_5 +320 0x6000 //TX_A_POST_FILT_S_6 +321 0x6000 //TX_A_POST_FILT_S_7 +322 0x2000 //TX_B_POST_FILT_0 +323 0x4000 //TX_B_POST_FILT_1 +324 0x2000 //TX_B_POST_FILT_2 +325 0x2000 //TX_B_POST_FILT_3 +326 0x2000 //TX_B_POST_FILT_4 +327 0x2000 //TX_B_POST_FILT_5 +328 0x2000 //TX_B_POST_FILT_6 +329 0x2000 //TX_B_POST_FILT_7 +330 0x7FFF //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x7FFF //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7CCD //TX_LAMBDA_PFILT +339 0x7CCD //TX_LAMBDA_PFILT_S_0 +340 0x7CCD //TX_LAMBDA_PFILT_S_1 +341 0x7CCD //TX_LAMBDA_PFILT_S_2 +342 0x7CCD //TX_LAMBDA_PFILT_S_3 +343 0x7CCD //TX_LAMBDA_PFILT_S_4 +344 0x7CCD //TX_LAMBDA_PFILT_S_5 +345 0x7CCD //TX_LAMBDA_PFILT_S_6 +346 0x7CCD //TX_LAMBDA_PFILT_S_7 +347 0x0200 //TX_K_PEPPER +348 0x0500 //TX_A_PEPPER +349 0x1600 //TX_K_PEPPER_HF +350 0x0400 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0800 //TX_DT_BINVAD_TH_0 +354 0x0800 //TX_DT_BINVAD_TH_1 +355 0x0800 //TX_DT_BINVAD_TH_2 +356 0x0800 //TX_DT_BINVAD_TH_3 +357 0x1D4C //TX_DT_BINVAD_ENDF +358 0x0000 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0190 //TX_NDETCT +367 0x04E8 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x02A6 //TX_NOISE_TH_1 +371 0x04B0 //TX_NOISE_TH_2 +372 0x3194 //TX_NOISE_TH_3 +373 0x0960 //TX_NOISE_TH_4 +374 0x5555 //TX_NOISE_TH_5 +375 0x3FF4 //TX_NOISE_TH_5_2 +376 0x0001 //TX_NOISE_TH_5_3 +377 0x0000 //TX_NOISE_TH_5_4 +378 0x02BC //TX_NOISE_TH_6 +379 0x02BC //TX_MINENOISE_TH +380 0xD508 //TX_MORENS_TFMASK_TH +381 0x0001 //TX_DRC_QUIET_FLOOR +382 0x3A98 //TX_RATIODTL_CUT_TH +383 0x1482 //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x0333 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x7FFF //TX_POST_MASK_SUP_HSNE +392 0x1388 //TX_TAIL_DET_TH +393 0x4000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0080 //TX_SUPHIGH_TH +396 0x0000 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x1800 //TX_C_POST_FLT_MASK +399 0x7FFF //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0004 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x04E7 //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x2900 //TX_MIN_G_CTRL_SSNS +409 0x0800 //TX_METAL_RTO_THR +410 0x4848 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x4000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x01E0 //TX_NOR_OFF_THR +498 0x7C00 //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0xD333 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x6000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0xC000 //TX_DEREVERB_LF_MU +515 0xC000 //TX_DEREVERB_HF_MU +516 0xCCCC //TX_DEREVERB_DELAY +517 0xD999 //TX_DEREVERB_COEF_LEN +518 0x1F40 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x7000 //TX_GSC_RTOH_TH +523 0x0064 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0020 //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4848 //TX_FDEQ_GAIN_5 +573 0x4848 //TX_FDEQ_GAIN_6 +574 0x4848 //TX_FDEQ_GAIN_7 +575 0x4848 //TX_FDEQ_GAIN_8 +576 0x4848 //TX_FDEQ_GAIN_9 +577 0x4848 //TX_FDEQ_GAIN_10 +578 0x4848 //TX_FDEQ_GAIN_11 +579 0x4848 //TX_FDEQ_GAIN_12 +580 0x4848 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0304 //TX_FDEQ_BIN_2 +594 0x0405 //TX_FDEQ_BIN_3 +595 0x0607 //TX_FDEQ_BIN_4 +596 0x0809 //TX_FDEQ_BIN_5 +597 0x0A0B //TX_FDEQ_BIN_6 +598 0x0C0D //TX_FDEQ_BIN_7 +599 0x0E0F //TX_FDEQ_BIN_8 +600 0x1011 //TX_FDEQ_BIN_9 +601 0x1214 //TX_FDEQ_BIN_10 +602 0x1618 //TX_FDEQ_BIN_11 +603 0x1C1C //TX_FDEQ_BIN_12 +604 0x2020 //TX_FDEQ_BIN_13 +605 0x2020 //TX_FDEQ_BIN_14 +606 0x2011 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4848 //TX_PREEQ_GAIN_MIC0_8 +626 0x4848 //TX_PREEQ_GAIN_MIC0_9 +627 0x4848 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0E10 //TX_PREEQ_BIN_MIC0_0 +642 0x1010 //TX_PREEQ_BIN_MIC0_1 +643 0x1010 //TX_PREEQ_BIN_MIC0_2 +644 0x1010 //TX_PREEQ_BIN_MIC0_3 +645 0x1010 //TX_PREEQ_BIN_MIC0_4 +646 0x1010 //TX_PREEQ_BIN_MIC0_5 +647 0x1010 //TX_PREEQ_BIN_MIC0_6 +648 0x1010 //TX_PREEQ_BIN_MIC0_7 +649 0x1010 //TX_PREEQ_BIN_MIC0_8 +650 0x1010 //TX_PREEQ_BIN_MIC0_9 +651 0x1010 //TX_PREEQ_BIN_MIC0_10 +652 0x1010 //TX_PREEQ_BIN_MIC0_11 +653 0x1010 //TX_PREEQ_BIN_MIC0_12 +654 0x1010 //TX_PREEQ_BIN_MIC0_13 +655 0x1010 //TX_PREEQ_BIN_MIC0_14 +656 0x0200 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0E10 //TX_PREEQ_BIN_MIC1_0 +691 0x1010 //TX_PREEQ_BIN_MIC1_1 +692 0x1010 //TX_PREEQ_BIN_MIC1_2 +693 0x1010 //TX_PREEQ_BIN_MIC1_3 +694 0x1010 //TX_PREEQ_BIN_MIC1_4 +695 0x1010 //TX_PREEQ_BIN_MIC1_5 +696 0x1010 //TX_PREEQ_BIN_MIC1_6 +697 0x1010 //TX_PREEQ_BIN_MIC1_7 +698 0x1010 //TX_PREEQ_BIN_MIC1_8 +699 0x1010 //TX_PREEQ_BIN_MIC1_9 +700 0x1010 //TX_PREEQ_BIN_MIC1_10 +701 0x1010 //TX_PREEQ_BIN_MIC1_11 +702 0x1010 //TX_PREEQ_BIN_MIC1_12 +703 0x1010 //TX_PREEQ_BIN_MIC1_13 +704 0x1010 //TX_PREEQ_BIN_MIC1_14 +705 0x0200 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0E10 //TX_PREEQ_BIN_MIC2_0 +740 0x1010 //TX_PREEQ_BIN_MIC2_1 +741 0x1010 //TX_PREEQ_BIN_MIC2_2 +742 0x1010 //TX_PREEQ_BIN_MIC2_3 +743 0x1010 //TX_PREEQ_BIN_MIC2_4 +744 0x1010 //TX_PREEQ_BIN_MIC2_5 +745 0x1010 //TX_PREEQ_BIN_MIC2_6 +746 0x1010 //TX_PREEQ_BIN_MIC2_7 +747 0x1010 //TX_PREEQ_BIN_MIC2_8 +748 0x1010 //TX_PREEQ_BIN_MIC2_9 +749 0x1010 //TX_PREEQ_BIN_MIC2_10 +750 0x1010 //TX_PREEQ_BIN_MIC2_11 +751 0x1010 //TX_PREEQ_BIN_MIC2_12 +752 0x1010 //TX_PREEQ_BIN_MIC2_13 +753 0x1010 //TX_PREEQ_BIN_MIC2_14 +754 0x0200 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x2000 //TX_NND_WEIGHT +765 0x0060 //TX_MIC_CALIBRATION_0 +766 0x0060 //TX_MIC_CALIBRATION_1 +767 0x0070 //TX_MIC_CALIBRATION_2 +768 0x0070 //TX_MIC_CALIBRATION_3 +769 0x0050 //TX_MIC_PWR_BIAS_0 +770 0x0040 //TX_MIC_PWR_BIAS_1 +771 0x0040 //TX_MIC_PWR_BIAS_2 +772 0x0040 //TX_MIC_PWR_BIAS_3 +773 0x0009 //TX_GAIN_LIMIT_0 +774 0x000F //TX_GAIN_LIMIT_1 +775 0x000F //TX_GAIN_LIMIT_2 +776 0x000F //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x0C00 //TX_TDDRC_ALPHA_UP_01 +784 0x0C00 //TX_TDDRC_ALPHA_UP_02 +785 0x0C00 //TX_TDDRC_ALPHA_UP_03 +786 0x0C00 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x7FFF //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0000 //TX_DEADMIC_SILENCE_TH +817 0x0000 //TX_MIC_DEGRADE_TH +818 0x0000 //TX_DEADMIC_CNT +819 0x0000 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x4848 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0000 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0002 //TX_FILTINDX +854 0x0001 //TX_TDDRC_THRD_0 +855 0x0001 //TX_TDDRC_THRD_1 +856 0x1900 //TX_TDDRC_THRD_2 +857 0x1900 //TX_TDDRC_THRD_3 +858 0x3000 //TX_TDDRC_SLANT_0 +859 0x7B00 //TX_TDDRC_SLANT_1 +860 0x0C00 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x07F2 //TX_TDDRC_DRC_GAIN +867 0x7FFF //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x0028 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x7000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x2339 //TX_SENDFUNC_REG_MICMUTE +898 0x0021 //TX_SENDFUNC_REG_MICMUTE1 +899 0x02BC //TX_MICMUTE_RATIO_THR +900 0x0140 //TX_MICMUTE_AMP_THR +901 0x0004 //TX_MICMUTE_HPF_IND +902 0x00C0 //TX_MICMUTE_LOG_EYR_TH +903 0x0008 //TX_MICMUTE_CVG_TIME +904 0x0008 //TX_MICMUTE_RELEASE_TIME +905 0x01FE //TX_MIC_VOLUME_MIC0MUTE +906 0x0020 //TX_MICMUTE_EPD_OFFSET_0 +907 0x001E //TX_MICMUTE_FRQ_AEC_L +908 0x7999 //TX_MICMUTE_EAD_THR +909 0x7FFF //TX_MICMUTE_LAMBDA_CB_NLE +910 0x7FFF //TX_MICMUTE_LAMBDA_RE_EST +911 0x4000 //TX_DTD_THR1_MICMUTE_0 +912 0x7000 //TX_DTD_THR1_MICMUTE_1 +913 0x7FFF //TX_DTD_THR1_MICMUTE_2 +914 0x7FFF //TX_DTD_THR1_MICMUTE_3 +915 0x6CCC //TX_DTD_THR2_MICMUTE_0 +916 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x1000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x4000 //TX_MICMUTE_C_POST_FLT +922 0x03E8 //TX_MICMUTE_DT_CUT_K +923 0x0001 //TX_MICMUTE_DT_CUT_THR +924 0x03E8 //TX_MICMUTE_DT_CUT_K2 +925 0x0001 //TX_MICMUTE_DT_CUT_THR2 +926 0x0064 //TX_MICMUTE_DT2_HOLD_N +927 0x1000 //TX_MICMUTE_RATIODTH_THCUT +928 0x1000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x7FFF //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0400 //TX_MICMUTE_C_POST_FLT_MASK +931 0x7999 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0258 //TX_MICMUTE_DT_CUT_K1 +933 0x0800 //TX_MICMUTE_N2_SN_EST +934 0xFC00 //TX_MICMUTE_THR_SN_EST_0 +935 0x001C //TX_MICMUTE_MIN_G_CTRL_0 +936 0x6000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x7000 //TX_MICMUTE_B_POST_FILT_0 +938 0x2710 //TX_MIC1RUB_AMP_THR +939 0x0010 //TX_MIC1MUTE_RATIO_THR +940 0x0450 //TX_MIC1MUTE_AMP_THR +941 0x0008 //TX_MIC1MUTE_CVG_TIME +942 0x0008 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x202C //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0004 //RX_SAMPLINGFREQ_SIG +3 0x0004 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7B02 //RX_A_HP +12 0x4000 //RX_B_PE +13 0x7800 //RX_THR_PITCH_DET_0 +14 0x7000 //RX_THR_PITCH_DET_1 +15 0x6000 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0500 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x000A //RX_NS_LVL_CTRL +23 0xF600 //RX_THR_SN_EST +24 0x7000 //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0002 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1200 //RX_TDDRC_THRD_2 +115 0x1900 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0240 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x2000 //RX_MIN_G_FP +128 0x0080 //RX_MAX_G_FP +129 0x000B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1200 //RX_TDDRC_THRD_2 +115 0x1900 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0240 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x000B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1200 //RX_TDDRC_THRD_2 +115 0x1900 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0240 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0013 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1200 //RX_TDDRC_THRD_2 +115 0x1900 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0240 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0020 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1200 //RX_TDDRC_THRD_2 +115 0x1900 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0240 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0036 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1200 //RX_TDDRC_THRD_2 +115 0x1900 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0240 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x005B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1200 //RX_TDDRC_THRD_2 +115 0x1900 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0240 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0099 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1200 //RX_TDDRC_THRD_2 +115 0x1900 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0240 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x202C //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0004 //RX_SAMPLINGFREQ_SIG +160 0x0004 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7B02 //RX_A_HP +169 0x4000 //RX_B_PE +170 0x7800 //RX_THR_PITCH_DET_0 +171 0x7000 //RX_THR_PITCH_DET_1 +172 0x6000 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0500 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x000A //RX_NS_LVL_CTRL +180 0xF600 //RX_THR_SN_EST +181 0x7000 //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0002 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1200 //RX_TDDRC_THRD_2 +272 0x1900 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0240 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x2000 //RX_MIN_G_FP +285 0x0080 //RX_MAX_G_FP +286 0x000B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1200 //RX_TDDRC_THRD_2 +272 0x1900 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0240 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x000B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1200 //RX_TDDRC_THRD_2 +272 0x1900 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0240 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0013 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1200 //RX_TDDRC_THRD_2 +272 0x1900 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0240 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0020 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1200 //RX_TDDRC_THRD_2 +272 0x1900 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0240 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0036 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1200 //RX_TDDRC_THRD_2 +272 0x1900 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0240 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x005B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1200 //RX_TDDRC_THRD_2 +272 0x1900 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0240 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0099 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1200 //RX_TDDRC_THRD_2 +272 0x1900 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0240 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME HEADSET-RESERVE1-VOICE_GENERIC-NB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0009 //TX_OPERATION_MODE_0 +1 0x0008 //TX_OPERATION_MODE_1 +2 0x0033 //TX_PATCH_REG +3 0x2B68 //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0001 //TX_NUM_MIC +6 0x0000 //TX_SAMPLINGFREQ_SIG +7 0x0000 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009B //TX_DIST2REF1 +22 0x0000 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0B80 //TX_PGA_0 +28 0x0800 //TX_PGA_1 +29 0x0000 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0000 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0001 //TX_MIC_DATA_SRC1 +43 0x0002 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3E00 //TX_DIST2REF_11 +73 0x0000 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0200 //TX_MIC_REFBLK_VOLUME +108 0x0800 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0000 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7646 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x7CCC //TX_THR_PITCH_DET_0 +131 0x7000 //TX_THR_PITCH_DET_1 +132 0x6333 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x001E //TX_TAIL_LENGTH +147 0x0010 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x7000 //TX_EAD_THR +151 0x1000 //TX_THR_RE_EST +152 0x1000 //TX_MIN_EQ_RE_EST_0 +153 0x0800 //TX_MIN_EQ_RE_EST_1 +154 0x0800 //TX_MIN_EQ_RE_EST_2 +155 0x0800 //TX_MIN_EQ_RE_EST_3 +156 0x0800 //TX_MIN_EQ_RE_EST_4 +157 0x0800 //TX_MIN_EQ_RE_EST_5 +158 0x0800 //TX_MIN_EQ_RE_EST_6 +159 0x0800 //TX_MIN_EQ_RE_EST_7 +160 0x0800 //TX_MIN_EQ_RE_EST_8 +161 0x0800 //TX_MIN_EQ_RE_EST_9 +162 0x0800 //TX_MIN_EQ_RE_EST_10 +163 0x0800 //TX_MIN_EQ_RE_EST_11 +164 0x0800 //TX_MIN_EQ_RE_EST_12 +165 0x4000 //TX_LAMBDA_RE_EST +166 0x2000 //TX_LAMBDA_CB_NLE +167 0x2000 //TX_C_POST_FLT +168 0x2000 //TX_GAIN_NP +169 0x00C8 //TX_SE_HOLD_N +170 0x0064 //TX_DT_HOLD_N +171 0x03E8 //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x5000 //TX_DTD_THR1_0 +198 0x7000 //TX_DTD_THR1_1 +199 0x7F00 //TX_DTD_THR1_2 +200 0x7FFF //TX_DTD_THR1_3 +201 0x7FFF //TX_DTD_THR1_4 +202 0x7FFF //TX_DTD_THR1_5 +203 0x7FFF //TX_DTD_THR1_6 +204 0x2000 //TX_DTD_THR2_0 +205 0x2000 //TX_DTD_THR2_1 +206 0x2000 //TX_DTD_THR2_2 +207 0x2000 //TX_DTD_THR2_3 +208 0x2000 //TX_DTD_THR2_4 +209 0x2000 //TX_DTD_THR2_5 +210 0x2000 //TX_DTD_THR2_6 +211 0x4100 //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x03E8 //TX_DT_CUT_K +214 0x1000 //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x0400 //TX_ADPT_STRICT_L +222 0x0200 //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x0800 //TX_B_POST_FILT_ECHO_L +229 0x7FFF //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x1000 //TX_B_LESSCUT_RTO_ECHO +232 0x0010 //TX_EPD_OFFSET_00 +233 0x0010 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x7FFF //TX_DTD_THR1_7 +238 0x7FFF //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xFA00 //TX_THR_SN_EST_0 +243 0xFA00 //TX_THR_SN_EST_1 +244 0xFA00 //TX_THR_SN_EST_2 +245 0xFA00 //TX_THR_SN_EST_3 +246 0xFA00 //TX_THR_SN_EST_4 +247 0xFA00 //TX_THR_SN_EST_5 +248 0xFA00 //TX_THR_SN_EST_6 +249 0xFA00 //TX_THR_SN_EST_7 +250 0x0000 //TX_DELTA_THR_SN_EST_0 +251 0x0000 //TX_DELTA_THR_SN_EST_1 +252 0x0000 //TX_DELTA_THR_SN_EST_2 +253 0x0000 //TX_DELTA_THR_SN_EST_3 +254 0x0000 //TX_DELTA_THR_SN_EST_4 +255 0x0000 //TX_DELTA_THR_SN_EST_5 +256 0x0000 //TX_DELTA_THR_SN_EST_6 +257 0x0000 //TX_DELTA_THR_SN_EST_7 +258 0x4000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x4000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x0400 //TX_B_POST_FLT_0 +280 0x0400 //TX_B_POST_FLT_1 +281 0x0010 //TX_NS_LVL_CTRL_0 +282 0x0010 //TX_NS_LVL_CTRL_1 +283 0x0010 //TX_NS_LVL_CTRL_2 +284 0x0010 //TX_NS_LVL_CTRL_3 +285 0x0010 //TX_NS_LVL_CTRL_4 +286 0x0010 //TX_NS_LVL_CTRL_5 +287 0x0010 //TX_NS_LVL_CTRL_6 +288 0x0010 //TX_NS_LVL_CTRL_7 +289 0x000D //TX_MIN_GAIN_S_0 +290 0x000D //TX_MIN_GAIN_S_1 +291 0x000D //TX_MIN_GAIN_S_2 +292 0x000D //TX_MIN_GAIN_S_3 +293 0x000D //TX_MIN_GAIN_S_4 +294 0x000D //TX_MIN_GAIN_S_5 +295 0x000D //TX_MIN_GAIN_S_6 +296 0x000D //TX_MIN_GAIN_S_7 +297 0x7FFF //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x7FFF //TX_SNRI_SUP_1 +302 0x7FFF //TX_SNRI_SUP_2 +303 0x7FFF //TX_SNRI_SUP_3 +304 0x7FFF //TX_SNRI_SUP_4 +305 0x7FFF //TX_SNRI_SUP_5 +306 0x7FFF //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x0014 //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x4000 //TX_A_POST_FILT_S_0 +315 0x1000 //TX_A_POST_FILT_S_1 +316 0x4000 //TX_A_POST_FILT_S_2 +317 0x4000 //TX_A_POST_FILT_S_3 +318 0x4000 //TX_A_POST_FILT_S_4 +319 0x4000 //TX_A_POST_FILT_S_5 +320 0x4000 //TX_A_POST_FILT_S_6 +321 0x4000 //TX_A_POST_FILT_S_7 +322 0x0400 //TX_B_POST_FILT_0 +323 0x2000 //TX_B_POST_FILT_1 +324 0x2000 //TX_B_POST_FILT_2 +325 0x2000 //TX_B_POST_FILT_3 +326 0x2000 //TX_B_POST_FILT_4 +327 0x2000 //TX_B_POST_FILT_5 +328 0x0400 //TX_B_POST_FILT_6 +329 0x2000 //TX_B_POST_FILT_7 +330 0x7FFF //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x7FFF //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7E14 //TX_LAMBDA_PFILT +339 0x7C29 //TX_LAMBDA_PFILT_S_0 +340 0x7C29 //TX_LAMBDA_PFILT_S_1 +341 0x7C29 //TX_LAMBDA_PFILT_S_2 +342 0x7C29 //TX_LAMBDA_PFILT_S_3 +343 0x7C29 //TX_LAMBDA_PFILT_S_4 +344 0x7C29 //TX_LAMBDA_PFILT_S_5 +345 0x7C29 //TX_LAMBDA_PFILT_S_6 +346 0x7C29 //TX_LAMBDA_PFILT_S_7 +347 0x0200 //TX_K_PEPPER +348 0x0800 //TX_A_PEPPER +349 0x0FA0 //TX_K_PEPPER_HF +350 0x0400 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x4000 //TX_HMNC_BST_THR +353 0x0800 //TX_DT_BINVAD_TH_0 +354 0x0800 //TX_DT_BINVAD_TH_1 +355 0x0800 //TX_DT_BINVAD_TH_2 +356 0x0800 //TX_DT_BINVAD_TH_3 +357 0x1D4C //TX_DT_BINVAD_ENDF +358 0x0000 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0190 //TX_NDETCT +367 0x003B //TX_NOISE_TH_0 +368 0x1B58 //TX_NOISE_TH_0_2 +369 0x2134 //TX_NOISE_TH_0_3 +370 0x02BC //TX_NOISE_TH_1 +371 0x1F40 //TX_NOISE_TH_2 +372 0x4650 //TX_NOISE_TH_3 +373 0x7148 //TX_NOISE_TH_4 +374 0x044C //TX_NOISE_TH_5 +375 0x7FFF //TX_NOISE_TH_5_2 +376 0x0000 //TX_NOISE_TH_5_3 +377 0x0000 //TX_NOISE_TH_5_4 +378 0x0032 //TX_NOISE_TH_6 +379 0x00C8 //TX_MINENOISE_TH +380 0xD508 //TX_MORENS_TFMASK_TH +381 0x0001 //TX_DRC_QUIET_FLOOR +382 0x3A98 //TX_RATIODTL_CUT_TH +383 0x0DAC //TX_DT_CUT_K1 +384 0x00A5 //TX_OUT_ENER_S_TH_CLEAN +385 0x00A5 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x00A5 //TX_OUT_ENER_S_TH_NOISY +387 0x0029 //TX_OUT_ENER_TH_NOISE +388 0x00CE //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x7FFF //TX_POST_MASK_SUP_HSNE +392 0x1388 //TX_TAIL_DET_TH +393 0x4000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0080 //TX_SUPHIGH_TH +396 0x0000 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x1800 //TX_C_POST_FLT_MASK +399 0x7FFF //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0002 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x0032 //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x7FFF //TX_MIN_G_CTRL_SSNS +409 0x0000 //TX_METAL_RTO_THR +410 0x4848 //TX_NS_FP_K_METAL +411 0x7FFF //TX_NOISEDET_BOOST_TH +412 0x0000 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0280 //TX_N_HOLD_HS +416 0x006E //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0333 //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2400 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0640 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x2000 //TX_WTA_EN_RTO_TH +429 0x1400 //TX_TOP_ENER_TH_F +430 0x0064 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x003C //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x0D9A //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x2A3D //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x0230 //TX_NOR_OFF_THR +498 0x0CCD //TX_MORE_ON_700HZ_THR +499 0x0000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0xD333 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x6000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0xC000 //TX_DEREVERB_LF_MU +515 0xC000 //TX_DEREVERB_HF_MU +516 0xCCCC //TX_DEREVERB_DELAY +517 0xD999 //TX_DEREVERB_COEF_LEN +518 0x1F40 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x7000 //TX_GSC_RTOH_TH +523 0x0064 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0014 //TX_FDEQ_SUBNUM +567 0x6048 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4848 //TX_FDEQ_GAIN_5 +573 0x4844 //TX_FDEQ_GAIN_6 +574 0x4444 //TX_FDEQ_GAIN_7 +575 0x4040 //TX_FDEQ_GAIN_8 +576 0x3C3C //TX_FDEQ_GAIN_9 +577 0x4848 //TX_FDEQ_GAIN_10 +578 0x4848 //TX_FDEQ_GAIN_11 +579 0x4848 //TX_FDEQ_GAIN_12 +580 0x4848 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0401 //TX_FDEQ_BIN_0 +592 0x0103 //TX_FDEQ_BIN_1 +593 0x0303 //TX_FDEQ_BIN_2 +594 0x0304 //TX_FDEQ_BIN_3 +595 0x0405 //TX_FDEQ_BIN_4 +596 0x0506 //TX_FDEQ_BIN_5 +597 0x0708 //TX_FDEQ_BIN_6 +598 0x090A //TX_FDEQ_BIN_7 +599 0x0B0C //TX_FDEQ_BIN_8 +600 0x0D0E //TX_FDEQ_BIN_9 +601 0x0000 //TX_FDEQ_BIN_10 +602 0x0000 //TX_FDEQ_BIN_11 +603 0x0000 //TX_FDEQ_BIN_12 +604 0x0000 //TX_FDEQ_BIN_13 +605 0x0000 //TX_FDEQ_BIN_14 +606 0x0000 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0010 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4848 //TX_PREEQ_GAIN_MIC0_8 +626 0x4848 //TX_PREEQ_GAIN_MIC0_9 +627 0x4848 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0608 //TX_PREEQ_BIN_MIC0_0 +642 0x0808 //TX_PREEQ_BIN_MIC0_1 +643 0x0808 //TX_PREEQ_BIN_MIC0_2 +644 0x0808 //TX_PREEQ_BIN_MIC0_3 +645 0x0808 //TX_PREEQ_BIN_MIC0_4 +646 0x0808 //TX_PREEQ_BIN_MIC0_5 +647 0x0808 //TX_PREEQ_BIN_MIC0_6 +648 0x0802 //TX_PREEQ_BIN_MIC0_7 +649 0x0000 //TX_PREEQ_BIN_MIC0_8 +650 0x0000 //TX_PREEQ_BIN_MIC0_9 +651 0x0000 //TX_PREEQ_BIN_MIC0_10 +652 0x0000 //TX_PREEQ_BIN_MIC0_11 +653 0x0000 //TX_PREEQ_BIN_MIC0_12 +654 0x0000 //TX_PREEQ_BIN_MIC0_13 +655 0x0000 //TX_PREEQ_BIN_MIC0_14 +656 0x0000 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0010 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0608 //TX_PREEQ_BIN_MIC1_0 +691 0x0808 //TX_PREEQ_BIN_MIC1_1 +692 0x0808 //TX_PREEQ_BIN_MIC1_2 +693 0x0808 //TX_PREEQ_BIN_MIC1_3 +694 0x0808 //TX_PREEQ_BIN_MIC1_4 +695 0x0808 //TX_PREEQ_BIN_MIC1_5 +696 0x0808 //TX_PREEQ_BIN_MIC1_6 +697 0x0802 //TX_PREEQ_BIN_MIC1_7 +698 0x0000 //TX_PREEQ_BIN_MIC1_8 +699 0x0000 //TX_PREEQ_BIN_MIC1_9 +700 0x0000 //TX_PREEQ_BIN_MIC1_10 +701 0x0000 //TX_PREEQ_BIN_MIC1_11 +702 0x0000 //TX_PREEQ_BIN_MIC1_12 +703 0x0000 //TX_PREEQ_BIN_MIC1_13 +704 0x0000 //TX_PREEQ_BIN_MIC1_14 +705 0x0000 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0010 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0608 //TX_PREEQ_BIN_MIC2_0 +740 0x0808 //TX_PREEQ_BIN_MIC2_1 +741 0x0808 //TX_PREEQ_BIN_MIC2_2 +742 0x0808 //TX_PREEQ_BIN_MIC2_3 +743 0x0808 //TX_PREEQ_BIN_MIC2_4 +744 0x0808 //TX_PREEQ_BIN_MIC2_5 +745 0x0808 //TX_PREEQ_BIN_MIC2_6 +746 0x0802 //TX_PREEQ_BIN_MIC2_7 +747 0x0000 //TX_PREEQ_BIN_MIC2_8 +748 0x0000 //TX_PREEQ_BIN_MIC2_9 +749 0x0000 //TX_PREEQ_BIN_MIC2_10 +750 0x0000 //TX_PREEQ_BIN_MIC2_11 +751 0x0000 //TX_PREEQ_BIN_MIC2_12 +752 0x0000 //TX_PREEQ_BIN_MIC2_13 +753 0x0000 //TX_PREEQ_BIN_MIC2_14 +754 0x0000 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x0800 //TX_NND_WEIGHT +765 0x0065 //TX_MIC_CALIBRATION_0 +766 0x0065 //TX_MIC_CALIBRATION_1 +767 0x0065 //TX_MIC_CALIBRATION_2 +768 0x0065 //TX_MIC_CALIBRATION_3 +769 0x0044 //TX_MIC_PWR_BIAS_0 +770 0x0044 //TX_MIC_PWR_BIAS_1 +771 0x0044 //TX_MIC_PWR_BIAS_2 +772 0x0044 //TX_MIC_PWR_BIAS_3 +773 0x000B //TX_GAIN_LIMIT_0 +774 0x000B //TX_GAIN_LIMIT_1 +775 0x000B //TX_GAIN_LIMIT_2 +776 0x000B //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x1000 //TX_TDDRC_ALPHA_UP_01 +784 0x1000 //TX_TDDRC_ALPHA_UP_02 +785 0x1000 //TX_TDDRC_ALPHA_UP_03 +786 0x1000 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x7FFF //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0000 //TX_DEADMIC_SILENCE_TH +817 0x0000 //TX_MIC_DEGRADE_TH +818 0x0000 //TX_DEADMIC_CNT +819 0x0000 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x4848 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0000 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0001 //TX_FILTINDX +854 0x0000 //TX_TDDRC_THRD_0 +855 0x0000 //TX_TDDRC_THRD_1 +856 0x2000 //TX_TDDRC_THRD_2 +857 0x2000 //TX_TDDRC_THRD_3 +858 0x3000 //TX_TDDRC_SLANT_0 +859 0x6E00 //TX_TDDRC_SLANT_1 +860 0x1000 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x05A0 //TX_TDDRC_DRC_GAIN +867 0x7FFF //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0xF800 //TX_TFMASKLTH_DOA +875 0x0CCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x00C8 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x4000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x2339 //TX_SENDFUNC_REG_MICMUTE +898 0x0021 //TX_SENDFUNC_REG_MICMUTE1 +899 0x02BC //TX_MICMUTE_RATIO_THR +900 0x0140 //TX_MICMUTE_AMP_THR +901 0x0004 //TX_MICMUTE_HPF_IND +902 0x00C0 //TX_MICMUTE_LOG_EYR_TH +903 0x0008 //TX_MICMUTE_CVG_TIME +904 0x0008 //TX_MICMUTE_RELEASE_TIME +905 0x01FE //TX_MIC_VOLUME_MIC0MUTE +906 0x0020 //TX_MICMUTE_EPD_OFFSET_0 +907 0x001E //TX_MICMUTE_FRQ_AEC_L +908 0x7999 //TX_MICMUTE_EAD_THR +909 0x7FFF //TX_MICMUTE_LAMBDA_CB_NLE +910 0x7FFF //TX_MICMUTE_LAMBDA_RE_EST +911 0x4000 //TX_DTD_THR1_MICMUTE_0 +912 0x7000 //TX_DTD_THR1_MICMUTE_1 +913 0x7FFF //TX_DTD_THR1_MICMUTE_2 +914 0x7FFF //TX_DTD_THR1_MICMUTE_3 +915 0x6CCC //TX_DTD_THR2_MICMUTE_0 +916 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x1000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x4000 //TX_MICMUTE_C_POST_FLT +922 0x03E8 //TX_MICMUTE_DT_CUT_K +923 0x0001 //TX_MICMUTE_DT_CUT_THR +924 0x03E8 //TX_MICMUTE_DT_CUT_K2 +925 0x0001 //TX_MICMUTE_DT_CUT_THR2 +926 0x0064 //TX_MICMUTE_DT2_HOLD_N +927 0x1000 //TX_MICMUTE_RATIODTH_THCUT +928 0x1000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x7FFF //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0400 //TX_MICMUTE_C_POST_FLT_MASK +931 0x7999 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0258 //TX_MICMUTE_DT_CUT_K1 +933 0x0800 //TX_MICMUTE_N2_SN_EST +934 0xFC00 //TX_MICMUTE_THR_SN_EST_0 +935 0x001C //TX_MICMUTE_MIN_G_CTRL_0 +936 0x6000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x7000 //TX_MICMUTE_B_POST_FILT_0 +938 0x2710 //TX_MIC1RUB_AMP_THR +939 0x0010 //TX_MIC1MUTE_RATIO_THR +940 0x0450 //TX_MIC1MUTE_AMP_THR +941 0x0008 //TX_MIC1MUTE_CVG_TIME +942 0x0008 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x202C //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0000 //RX_SAMPLINGFREQ_SIG +3 0x0000 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7FFF //RX_A_HP +12 0x0000 //RX_B_PE +13 0x3800 //RX_THR_PITCH_DET_0 +14 0x3000 //RX_THR_PITCH_DET_1 +15 0x2800 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0600 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x0010 //RX_NS_LVL_CTRL +23 0xF800 //RX_THR_SN_EST +24 0x7CCD //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0002 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0200 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x2000 //RX_MIN_G_FP +128 0x0080 //RX_MAX_G_FP +129 0x000B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0200 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x000B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0200 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0013 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0200 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0020 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0200 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0036 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0200 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x005B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0200 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0099 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0200 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x202C //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0000 //RX_SAMPLINGFREQ_SIG +160 0x0000 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7FFF //RX_A_HP +169 0x0000 //RX_B_PE +170 0x3800 //RX_THR_PITCH_DET_0 +171 0x3000 //RX_THR_PITCH_DET_1 +172 0x2800 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0600 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x0010 //RX_NS_LVL_CTRL +180 0xF800 //RX_THR_SN_EST +181 0x7CCD //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0002 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0200 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x2000 //RX_MIN_G_FP +285 0x0080 //RX_MAX_G_FP +286 0x000B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0200 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x000B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0200 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0013 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0200 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0020 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0200 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0036 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0200 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x005B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0200 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0099 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0200 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME HEADSET-RESERVE1-VOICE_GENERIC-WB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0009 //TX_OPERATION_MODE_0 +1 0x0008 //TX_OPERATION_MODE_1 +2 0x0033 //TX_PATCH_REG +3 0x2B68 //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0001 //TX_NUM_MIC +6 0x0001 //TX_SAMPLINGFREQ_SIG +7 0x0001 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009B //TX_DIST2REF1 +22 0x0000 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0B80 //TX_PGA_0 +28 0x0800 //TX_PGA_1 +29 0x0800 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0000 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0001 //TX_MIC_DATA_SRC1 +43 0x0002 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3E00 //TX_DIST2REF_11 +73 0x0000 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0200 //TX_MIC_REFBLK_VOLUME +108 0x0800 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0000 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7D83 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x6800 //TX_THR_PITCH_DET_0 +131 0x6000 //TX_THR_PITCH_DET_1 +132 0x5800 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x001E //TX_TAIL_LENGTH +147 0x0080 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x7000 //TX_EAD_THR +151 0x0800 //TX_THR_RE_EST +152 0x0800 //TX_MIN_EQ_RE_EST_0 +153 0x0800 //TX_MIN_EQ_RE_EST_1 +154 0x0800 //TX_MIN_EQ_RE_EST_2 +155 0x0800 //TX_MIN_EQ_RE_EST_3 +156 0x0800 //TX_MIN_EQ_RE_EST_4 +157 0x0800 //TX_MIN_EQ_RE_EST_5 +158 0x0800 //TX_MIN_EQ_RE_EST_6 +159 0x0800 //TX_MIN_EQ_RE_EST_7 +160 0x0800 //TX_MIN_EQ_RE_EST_8 +161 0x0800 //TX_MIN_EQ_RE_EST_9 +162 0x0800 //TX_MIN_EQ_RE_EST_10 +163 0x0800 //TX_MIN_EQ_RE_EST_11 +164 0x0800 //TX_MIN_EQ_RE_EST_12 +165 0x4000 //TX_LAMBDA_RE_EST +166 0x2000 //TX_LAMBDA_CB_NLE +167 0x6000 //TX_C_POST_FLT +168 0x7000 //TX_GAIN_NP +169 0x00C8 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x03E8 //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x7800 //TX_DTD_THR1_0 +198 0x7000 //TX_DTD_THR1_1 +199 0x7FFF //TX_DTD_THR1_2 +200 0x7FFF //TX_DTD_THR1_3 +201 0x7FFF //TX_DTD_THR1_4 +202 0x7FFF //TX_DTD_THR1_5 +203 0x7FFF //TX_DTD_THR1_6 +204 0x7FFF //TX_DTD_THR2_0 +205 0x7FFF //TX_DTD_THR2_1 +206 0x7FFF //TX_DTD_THR2_2 +207 0x7FFF //TX_DTD_THR2_3 +208 0x7FFF //TX_DTD_THR2_4 +209 0x7FFF //TX_DTD_THR2_5 +210 0x7FFF //TX_DTD_THR2_6 +211 0x1000 //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x0BB8 //TX_DT_CUT_K +214 0x0CCD //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x0400 //TX_ADPT_STRICT_L +222 0x0200 //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x0800 //TX_B_POST_FILT_ECHO_L +229 0x7FFF //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x7FFF //TX_B_LESSCUT_RTO_ECHO +232 0x0019 //TX_EPD_OFFSET_00 +233 0x0019 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x7FFF //TX_DTD_THR1_7 +238 0x7FFF //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xFA00 //TX_THR_SN_EST_0 +243 0xF400 //TX_THR_SN_EST_1 +244 0xF600 //TX_THR_SN_EST_2 +245 0xF400 //TX_THR_SN_EST_3 +246 0xF400 //TX_THR_SN_EST_4 +247 0xF400 //TX_THR_SN_EST_5 +248 0xF400 //TX_THR_SN_EST_6 +249 0xF600 //TX_THR_SN_EST_7 +250 0x0000 //TX_DELTA_THR_SN_EST_0 +251 0x0200 //TX_DELTA_THR_SN_EST_1 +252 0x0200 //TX_DELTA_THR_SN_EST_2 +253 0x0200 //TX_DELTA_THR_SN_EST_3 +254 0x0200 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0000 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x6000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x6000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x1000 //TX_B_POST_FLT_0 +280 0x1000 //TX_B_POST_FLT_1 +281 0x000F //TX_NS_LVL_CTRL_0 +282 0x0011 //TX_NS_LVL_CTRL_1 +283 0x000F //TX_NS_LVL_CTRL_2 +284 0x000F //TX_NS_LVL_CTRL_3 +285 0x000F //TX_NS_LVL_CTRL_4 +286 0x000F //TX_NS_LVL_CTRL_5 +287 0x000F //TX_NS_LVL_CTRL_6 +288 0x0011 //TX_NS_LVL_CTRL_7 +289 0x000C //TX_MIN_GAIN_S_0 +290 0x000F //TX_MIN_GAIN_S_1 +291 0x000C //TX_MIN_GAIN_S_2 +292 0x000C //TX_MIN_GAIN_S_3 +293 0x000C //TX_MIN_GAIN_S_4 +294 0x000C //TX_MIN_GAIN_S_5 +295 0x000C //TX_MIN_GAIN_S_6 +296 0x000F //TX_MIN_GAIN_S_7 +297 0x7FFF //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x7FFF //TX_SNRI_SUP_1 +302 0x7FFF //TX_SNRI_SUP_2 +303 0x7FFF //TX_SNRI_SUP_3 +304 0x7FFF //TX_SNRI_SUP_4 +305 0x7FFF //TX_SNRI_SUP_5 +306 0x7FFF //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x000E //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x4000 //TX_A_POST_FILT_S_0 +315 0x5000 //TX_A_POST_FILT_S_1 +316 0x5000 //TX_A_POST_FILT_S_2 +317 0x5000 //TX_A_POST_FILT_S_3 +318 0x5000 //TX_A_POST_FILT_S_4 +319 0x5000 //TX_A_POST_FILT_S_5 +320 0x4000 //TX_A_POST_FILT_S_6 +321 0x5000 //TX_A_POST_FILT_S_7 +322 0x1000 //TX_B_POST_FILT_0 +323 0x1000 //TX_B_POST_FILT_1 +324 0x1000 //TX_B_POST_FILT_2 +325 0x1000 //TX_B_POST_FILT_3 +326 0x1000 //TX_B_POST_FILT_4 +327 0x1000 //TX_B_POST_FILT_5 +328 0x1000 //TX_B_POST_FILT_6 +329 0x1000 //TX_B_POST_FILT_7 +330 0x7FFF //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x7FFF //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7CCD //TX_LAMBDA_PFILT +339 0x7B00 //TX_LAMBDA_PFILT_S_0 +340 0x7B00 //TX_LAMBDA_PFILT_S_1 +341 0x7B00 //TX_LAMBDA_PFILT_S_2 +342 0x7B00 //TX_LAMBDA_PFILT_S_3 +343 0x7B00 //TX_LAMBDA_PFILT_S_4 +344 0x7B00 //TX_LAMBDA_PFILT_S_5 +345 0x7B00 //TX_LAMBDA_PFILT_S_6 +346 0x7B00 //TX_LAMBDA_PFILT_S_7 +347 0x0200 //TX_K_PEPPER +348 0x0800 //TX_A_PEPPER +349 0x1EAA //TX_K_PEPPER_HF +350 0x0800 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0800 //TX_DT_BINVAD_TH_0 +354 0x0800 //TX_DT_BINVAD_TH_1 +355 0x0800 //TX_DT_BINVAD_TH_2 +356 0x0800 //TX_DT_BINVAD_TH_3 +357 0x1D4C //TX_DT_BINVAD_ENDF +358 0x0000 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0190 //TX_NDETCT +367 0x0102 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x07D0 //TX_NOISE_TH_1 +371 0x00C8 //TX_NOISE_TH_2 +372 0x3A98 //TX_NOISE_TH_3 +373 0x0FA0 //TX_NOISE_TH_4 +374 0x157C //TX_NOISE_TH_5 +375 0x7FFF //TX_NOISE_TH_5_2 +376 0x7FFF //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x044C //TX_NOISE_TH_6 +379 0x00F8 //TX_MINENOISE_TH +380 0xD508 //TX_MORENS_TFMASK_TH +381 0x0001 //TX_DRC_QUIET_FLOOR +382 0x3A98 //TX_RATIODTL_CUT_TH +383 0x0DAC //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x0333 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x7FFF //TX_POST_MASK_SUP_HSNE +392 0x1388 //TX_TAIL_DET_TH +393 0x4000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0080 //TX_SUPHIGH_TH +396 0x0000 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x1800 //TX_C_POST_FLT_MASK +399 0x7FFF //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0002 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x00DC //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x7FFF //TX_MIN_G_CTRL_SSNS +409 0x0000 //TX_METAL_RTO_THR +410 0x0000 //TX_NS_FP_K_METAL +411 0x7FFF //TX_NOISEDET_BOOST_TH +412 0x0000 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x4000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x0230 //TX_NOR_OFF_THR +498 0x0CCD //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0xD333 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x6000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0xC000 //TX_DEREVERB_LF_MU +515 0xC000 //TX_DEREVERB_HF_MU +516 0xCCCC //TX_DEREVERB_DELAY +517 0xD999 //TX_DEREVERB_COEF_LEN +518 0x1F40 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x7000 //TX_GSC_RTOH_TH +523 0x0064 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x001C //TX_FDEQ_SUBNUM +567 0x5850 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4848 //TX_FDEQ_GAIN_5 +573 0x4848 //TX_FDEQ_GAIN_6 +574 0x4848 //TX_FDEQ_GAIN_7 +575 0x4848 //TX_FDEQ_GAIN_8 +576 0x4848 //TX_FDEQ_GAIN_9 +577 0x4848 //TX_FDEQ_GAIN_10 +578 0x4848 //TX_FDEQ_GAIN_11 +579 0x4848 //TX_FDEQ_GAIN_12 +580 0x4848 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0302 //TX_FDEQ_BIN_1 +593 0x0303 //TX_FDEQ_BIN_2 +594 0x0304 //TX_FDEQ_BIN_3 +595 0x0405 //TX_FDEQ_BIN_4 +596 0x0506 //TX_FDEQ_BIN_5 +597 0x0708 //TX_FDEQ_BIN_6 +598 0x090A //TX_FDEQ_BIN_7 +599 0x0B0C //TX_FDEQ_BIN_8 +600 0x0D07 //TX_FDEQ_BIN_9 +601 0x0E0F //TX_FDEQ_BIN_10 +602 0x0F10 //TX_FDEQ_BIN_11 +603 0x1011 //TX_FDEQ_BIN_12 +604 0x1119 //TX_FDEQ_BIN_13 +605 0x0000 //TX_FDEQ_BIN_14 +606 0x0000 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4848 //TX_PREEQ_GAIN_MIC0_8 +626 0x4848 //TX_PREEQ_GAIN_MIC0_9 +627 0x4848 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0608 //TX_PREEQ_BIN_MIC0_0 +642 0x0808 //TX_PREEQ_BIN_MIC0_1 +643 0x0808 //TX_PREEQ_BIN_MIC0_2 +644 0x0808 //TX_PREEQ_BIN_MIC0_3 +645 0x0808 //TX_PREEQ_BIN_MIC0_4 +646 0x0808 //TX_PREEQ_BIN_MIC0_5 +647 0x0808 //TX_PREEQ_BIN_MIC0_6 +648 0x0808 //TX_PREEQ_BIN_MIC0_7 +649 0x0808 //TX_PREEQ_BIN_MIC0_8 +650 0x0808 //TX_PREEQ_BIN_MIC0_9 +651 0x0808 //TX_PREEQ_BIN_MIC0_10 +652 0x0808 //TX_PREEQ_BIN_MIC0_11 +653 0x0808 //TX_PREEQ_BIN_MIC0_12 +654 0x0808 //TX_PREEQ_BIN_MIC0_13 +655 0x0808 //TX_PREEQ_BIN_MIC0_14 +656 0x0200 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0608 //TX_PREEQ_BIN_MIC1_0 +691 0x0808 //TX_PREEQ_BIN_MIC1_1 +692 0x0808 //TX_PREEQ_BIN_MIC1_2 +693 0x0808 //TX_PREEQ_BIN_MIC1_3 +694 0x0808 //TX_PREEQ_BIN_MIC1_4 +695 0x0808 //TX_PREEQ_BIN_MIC1_5 +696 0x0808 //TX_PREEQ_BIN_MIC1_6 +697 0x0808 //TX_PREEQ_BIN_MIC1_7 +698 0x0808 //TX_PREEQ_BIN_MIC1_8 +699 0x0808 //TX_PREEQ_BIN_MIC1_9 +700 0x0808 //TX_PREEQ_BIN_MIC1_10 +701 0x0808 //TX_PREEQ_BIN_MIC1_11 +702 0x0808 //TX_PREEQ_BIN_MIC1_12 +703 0x0808 //TX_PREEQ_BIN_MIC1_13 +704 0x0808 //TX_PREEQ_BIN_MIC1_14 +705 0x0200 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0608 //TX_PREEQ_BIN_MIC2_0 +740 0x0808 //TX_PREEQ_BIN_MIC2_1 +741 0x0808 //TX_PREEQ_BIN_MIC2_2 +742 0x0808 //TX_PREEQ_BIN_MIC2_3 +743 0x0808 //TX_PREEQ_BIN_MIC2_4 +744 0x0808 //TX_PREEQ_BIN_MIC2_5 +745 0x0808 //TX_PREEQ_BIN_MIC2_6 +746 0x0808 //TX_PREEQ_BIN_MIC2_7 +747 0x0808 //TX_PREEQ_BIN_MIC2_8 +748 0x0808 //TX_PREEQ_BIN_MIC2_9 +749 0x0808 //TX_PREEQ_BIN_MIC2_10 +750 0x0808 //TX_PREEQ_BIN_MIC2_11 +751 0x0808 //TX_PREEQ_BIN_MIC2_12 +752 0x0808 //TX_PREEQ_BIN_MIC2_13 +753 0x0808 //TX_PREEQ_BIN_MIC2_14 +754 0x0200 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x0800 //TX_NND_WEIGHT +765 0x0062 //TX_MIC_CALIBRATION_0 +766 0x0062 //TX_MIC_CALIBRATION_1 +767 0x0062 //TX_MIC_CALIBRATION_2 +768 0x0062 //TX_MIC_CALIBRATION_3 +769 0x0046 //TX_MIC_PWR_BIAS_0 +770 0x0046 //TX_MIC_PWR_BIAS_1 +771 0x0046 //TX_MIC_PWR_BIAS_2 +772 0x0046 //TX_MIC_PWR_BIAS_3 +773 0x000C //TX_GAIN_LIMIT_0 +774 0x000C //TX_GAIN_LIMIT_1 +775 0x000C //TX_GAIN_LIMIT_2 +776 0x000C //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x1000 //TX_TDDRC_ALPHA_UP_01 +784 0x1000 //TX_TDDRC_ALPHA_UP_02 +785 0x1000 //TX_TDDRC_ALPHA_UP_03 +786 0x1000 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x7FFF //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0000 //TX_DEADMIC_SILENCE_TH +817 0x0000 //TX_MIC_DEGRADE_TH +818 0x0000 //TX_DEADMIC_CNT +819 0x0000 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x0000 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0000 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0001 //TX_FILTINDX +854 0x0000 //TX_TDDRC_THRD_0 +855 0x0000 //TX_TDDRC_THRD_1 +856 0x2000 //TX_TDDRC_THRD_2 +857 0x2000 //TX_TDDRC_THRD_3 +858 0x3000 //TX_TDDRC_SLANT_0 +859 0x6E00 //TX_TDDRC_SLANT_1 +860 0x1000 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x05A0 //TX_TDDRC_DRC_GAIN +867 0x7FFF //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x00C8 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x4000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x2339 //TX_SENDFUNC_REG_MICMUTE +898 0x0021 //TX_SENDFUNC_REG_MICMUTE1 +899 0x02BC //TX_MICMUTE_RATIO_THR +900 0x0140 //TX_MICMUTE_AMP_THR +901 0x0004 //TX_MICMUTE_HPF_IND +902 0x00C0 //TX_MICMUTE_LOG_EYR_TH +903 0x0008 //TX_MICMUTE_CVG_TIME +904 0x0008 //TX_MICMUTE_RELEASE_TIME +905 0x01FE //TX_MIC_VOLUME_MIC0MUTE +906 0x0020 //TX_MICMUTE_EPD_OFFSET_0 +907 0x001E //TX_MICMUTE_FRQ_AEC_L +908 0x7999 //TX_MICMUTE_EAD_THR +909 0x7FFF //TX_MICMUTE_LAMBDA_CB_NLE +910 0x7FFF //TX_MICMUTE_LAMBDA_RE_EST +911 0x4000 //TX_DTD_THR1_MICMUTE_0 +912 0x7000 //TX_DTD_THR1_MICMUTE_1 +913 0x7FFF //TX_DTD_THR1_MICMUTE_2 +914 0x7FFF //TX_DTD_THR1_MICMUTE_3 +915 0x6CCC //TX_DTD_THR2_MICMUTE_0 +916 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x1000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x4000 //TX_MICMUTE_C_POST_FLT +922 0x03E8 //TX_MICMUTE_DT_CUT_K +923 0x0001 //TX_MICMUTE_DT_CUT_THR +924 0x03E8 //TX_MICMUTE_DT_CUT_K2 +925 0x0001 //TX_MICMUTE_DT_CUT_THR2 +926 0x0064 //TX_MICMUTE_DT2_HOLD_N +927 0x1000 //TX_MICMUTE_RATIODTH_THCUT +928 0x1000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x7FFF //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0400 //TX_MICMUTE_C_POST_FLT_MASK +931 0x7999 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0258 //TX_MICMUTE_DT_CUT_K1 +933 0x0800 //TX_MICMUTE_N2_SN_EST +934 0xFC00 //TX_MICMUTE_THR_SN_EST_0 +935 0x001C //TX_MICMUTE_MIN_G_CTRL_0 +936 0x6000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x7000 //TX_MICMUTE_B_POST_FILT_0 +938 0x2710 //TX_MIC1RUB_AMP_THR +939 0x0010 //TX_MIC1MUTE_RATIO_THR +940 0x0450 //TX_MIC1MUTE_AMP_THR +941 0x0008 //TX_MIC1MUTE_CVG_TIME +942 0x0008 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x202C //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0001 //RX_SAMPLINGFREQ_SIG +3 0x0001 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7FFF //RX_A_HP +12 0x4000 //RX_B_PE +13 0x3800 //RX_THR_PITCH_DET_0 +14 0x3000 //RX_THR_PITCH_DET_1 +15 0x2800 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0600 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x0010 //RX_NS_LVL_CTRL +23 0xF800 //RX_THR_SN_EST +24 0x7CCD //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0002 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0196 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x2000 //RX_MIN_G_FP +128 0x0080 //RX_MAX_G_FP +129 0x000B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0196 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x000B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0196 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0013 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0196 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0020 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0196 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0036 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0196 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x005B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0196 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0099 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0196 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x202C //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0001 //RX_SAMPLINGFREQ_SIG +160 0x0001 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7FFF //RX_A_HP +169 0x4000 //RX_B_PE +170 0x3800 //RX_THR_PITCH_DET_0 +171 0x3000 //RX_THR_PITCH_DET_1 +172 0x2800 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0600 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x0010 //RX_NS_LVL_CTRL +180 0xF800 //RX_THR_SN_EST +181 0x7CCD //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0002 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0196 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x2000 //RX_MIN_G_FP +285 0x0080 //RX_MAX_G_FP +286 0x000B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0196 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x000B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0196 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0013 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0196 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0020 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0196 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0036 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0196 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x005B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0196 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0099 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0196 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME HEADSET-RESERVE1-VOICE_GENERIC-SWB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0009 //TX_OPERATION_MODE_0 +1 0x0001 //TX_OPERATION_MODE_1 +2 0x0033 //TX_PATCH_REG +3 0x2B68 //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0001 //TX_NUM_MIC +6 0x0003 //TX_SAMPLINGFREQ_SIG +7 0x0003 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009B //TX_DIST2REF1 +22 0x0000 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0B80 //TX_PGA_0 +28 0x0800 //TX_PGA_1 +29 0x0800 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0000 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0001 //TX_MIC_DATA_SRC1 +43 0x0002 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3E00 //TX_DIST2REF_11 +73 0x0000 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0200 //TX_MIC_REFBLK_VOLUME +108 0x0800 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0000 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7EFF //TX_A_HP +129 0x4000 //TX_B_PE +130 0x1800 //TX_THR_PITCH_DET_0 +131 0x1000 //TX_THR_PITCH_DET_1 +132 0x0800 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x001E //TX_TAIL_LENGTH +147 0x0080 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x7000 //TX_EAD_THR +151 0x0800 //TX_THR_RE_EST +152 0x0800 //TX_MIN_EQ_RE_EST_0 +153 0x0800 //TX_MIN_EQ_RE_EST_1 +154 0x0800 //TX_MIN_EQ_RE_EST_2 +155 0x0800 //TX_MIN_EQ_RE_EST_3 +156 0x0800 //TX_MIN_EQ_RE_EST_4 +157 0x0800 //TX_MIN_EQ_RE_EST_5 +158 0x0800 //TX_MIN_EQ_RE_EST_6 +159 0x0800 //TX_MIN_EQ_RE_EST_7 +160 0x0800 //TX_MIN_EQ_RE_EST_8 +161 0x0800 //TX_MIN_EQ_RE_EST_9 +162 0x0800 //TX_MIN_EQ_RE_EST_10 +163 0x0800 //TX_MIN_EQ_RE_EST_11 +164 0x0800 //TX_MIN_EQ_RE_EST_12 +165 0x4000 //TX_LAMBDA_RE_EST +166 0x2000 //TX_LAMBDA_CB_NLE +167 0x6000 //TX_C_POST_FLT +168 0x7000 //TX_GAIN_NP +169 0x00C8 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x03E8 //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x7800 //TX_DTD_THR1_0 +198 0x7000 //TX_DTD_THR1_1 +199 0x7FFF //TX_DTD_THR1_2 +200 0x7FFF //TX_DTD_THR1_3 +201 0x7FFF //TX_DTD_THR1_4 +202 0x7FFF //TX_DTD_THR1_5 +203 0x7FFF //TX_DTD_THR1_6 +204 0x7FFF //TX_DTD_THR2_0 +205 0x7FFF //TX_DTD_THR2_1 +206 0x7FFF //TX_DTD_THR2_2 +207 0x7FFF //TX_DTD_THR2_3 +208 0x7FFF //TX_DTD_THR2_4 +209 0x7FFF //TX_DTD_THR2_5 +210 0x7FFF //TX_DTD_THR2_6 +211 0x1000 //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x0BB8 //TX_DT_CUT_K +214 0x0CCD //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x0400 //TX_ADPT_STRICT_L +222 0x0200 //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x0800 //TX_B_POST_FILT_ECHO_L +229 0x7FFF //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x7FFF //TX_B_LESSCUT_RTO_ECHO +232 0x00F0 //TX_EPD_OFFSET_00 +233 0x00F0 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x7FFF //TX_DTD_THR1_7 +238 0x7FFF //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xFA00 //TX_THR_SN_EST_0 +243 0xF400 //TX_THR_SN_EST_1 +244 0xF600 //TX_THR_SN_EST_2 +245 0xF400 //TX_THR_SN_EST_3 +246 0xF400 //TX_THR_SN_EST_4 +247 0xF400 //TX_THR_SN_EST_5 +248 0xF400 //TX_THR_SN_EST_6 +249 0xF600 //TX_THR_SN_EST_7 +250 0x0000 //TX_DELTA_THR_SN_EST_0 +251 0x0200 //TX_DELTA_THR_SN_EST_1 +252 0x0200 //TX_DELTA_THR_SN_EST_2 +253 0x0200 //TX_DELTA_THR_SN_EST_3 +254 0x0200 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0000 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x6000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x6000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x1000 //TX_B_POST_FLT_0 +280 0x1000 //TX_B_POST_FLT_1 +281 0x000B //TX_NS_LVL_CTRL_0 +282 0x0011 //TX_NS_LVL_CTRL_1 +283 0x000F //TX_NS_LVL_CTRL_2 +284 0x000F //TX_NS_LVL_CTRL_3 +285 0x000F //TX_NS_LVL_CTRL_4 +286 0x000F //TX_NS_LVL_CTRL_5 +287 0x000F //TX_NS_LVL_CTRL_6 +288 0x0011 //TX_NS_LVL_CTRL_7 +289 0x000C //TX_MIN_GAIN_S_0 +290 0x000F //TX_MIN_GAIN_S_1 +291 0x000C //TX_MIN_GAIN_S_2 +292 0x000C //TX_MIN_GAIN_S_3 +293 0x000C //TX_MIN_GAIN_S_4 +294 0x000C //TX_MIN_GAIN_S_5 +295 0x000C //TX_MIN_GAIN_S_6 +296 0x000F //TX_MIN_GAIN_S_7 +297 0x7FFF //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x7FFF //TX_SNRI_SUP_1 +302 0x7FFF //TX_SNRI_SUP_2 +303 0x7FFF //TX_SNRI_SUP_3 +304 0x7FFF //TX_SNRI_SUP_4 +305 0x7FFF //TX_SNRI_SUP_5 +306 0x7FFF //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x000E //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x2000 //TX_A_POST_FILT_S_0 +315 0x5000 //TX_A_POST_FILT_S_1 +316 0x5000 //TX_A_POST_FILT_S_2 +317 0x5000 //TX_A_POST_FILT_S_3 +318 0x5000 //TX_A_POST_FILT_S_4 +319 0x5000 //TX_A_POST_FILT_S_5 +320 0x4000 //TX_A_POST_FILT_S_6 +321 0x5000 //TX_A_POST_FILT_S_7 +322 0x1000 //TX_B_POST_FILT_0 +323 0x1000 //TX_B_POST_FILT_1 +324 0x1000 //TX_B_POST_FILT_2 +325 0x1000 //TX_B_POST_FILT_3 +326 0x1000 //TX_B_POST_FILT_4 +327 0x1000 //TX_B_POST_FILT_5 +328 0x1000 //TX_B_POST_FILT_6 +329 0x1000 //TX_B_POST_FILT_7 +330 0x7FFF //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x7FFF //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7900 //TX_LAMBDA_PFILT +339 0x7B00 //TX_LAMBDA_PFILT_S_0 +340 0x7B00 //TX_LAMBDA_PFILT_S_1 +341 0x7B00 //TX_LAMBDA_PFILT_S_2 +342 0x7B00 //TX_LAMBDA_PFILT_S_3 +343 0x7B00 //TX_LAMBDA_PFILT_S_4 +344 0x7B00 //TX_LAMBDA_PFILT_S_5 +345 0x7B00 //TX_LAMBDA_PFILT_S_6 +346 0x7B00 //TX_LAMBDA_PFILT_S_7 +347 0x0000 //TX_K_PEPPER +348 0x0800 //TX_A_PEPPER +349 0x1EAA //TX_K_PEPPER_HF +350 0x0800 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0800 //TX_DT_BINVAD_TH_0 +354 0x0800 //TX_DT_BINVAD_TH_1 +355 0x0800 //TX_DT_BINVAD_TH_2 +356 0x0800 //TX_DT_BINVAD_TH_3 +357 0x1D4C //TX_DT_BINVAD_ENDF +358 0x0000 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0190 //TX_NDETCT +367 0x0383 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x07D0 //TX_NOISE_TH_1 +371 0x00C8 //TX_NOISE_TH_2 +372 0x3A98 //TX_NOISE_TH_3 +373 0x0FA0 //TX_NOISE_TH_4 +374 0x157C //TX_NOISE_TH_5 +375 0x7FFF //TX_NOISE_TH_5_2 +376 0x7FFF //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x044C //TX_NOISE_TH_6 +379 0x044C //TX_MINENOISE_TH +380 0xD508 //TX_MORENS_TFMASK_TH +381 0x0001 //TX_DRC_QUIET_FLOOR +382 0x3A98 //TX_RATIODTL_CUT_TH +383 0x0DAC //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x0333 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x7FFF //TX_POST_MASK_SUP_HSNE +392 0x1388 //TX_TAIL_DET_TH +393 0x4000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0080 //TX_SUPHIGH_TH +396 0x0000 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x1800 //TX_C_POST_FLT_MASK +399 0x7FFF //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0002 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x02F3 //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x2900 //TX_MIN_G_CTRL_SSNS +409 0x0800 //TX_METAL_RTO_THR +410 0x4848 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x4000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x01E0 //TX_NOR_OFF_THR +498 0x7C00 //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0xD333 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x6000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0xC000 //TX_DEREVERB_LF_MU +515 0xC000 //TX_DEREVERB_HF_MU +516 0xCCCC //TX_DEREVERB_DELAY +517 0xD999 //TX_DEREVERB_COEF_LEN +518 0x1F40 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x7000 //TX_GSC_RTOH_TH +523 0x0064 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0020 //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4848 //TX_FDEQ_GAIN_5 +573 0x4848 //TX_FDEQ_GAIN_6 +574 0x4848 //TX_FDEQ_GAIN_7 +575 0x4848 //TX_FDEQ_GAIN_8 +576 0x4848 //TX_FDEQ_GAIN_9 +577 0x4848 //TX_FDEQ_GAIN_10 +578 0x4848 //TX_FDEQ_GAIN_11 +579 0x4848 //TX_FDEQ_GAIN_12 +580 0x4848 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0303 //TX_FDEQ_BIN_2 +594 0x0304 //TX_FDEQ_BIN_3 +595 0x0405 //TX_FDEQ_BIN_4 +596 0x0506 //TX_FDEQ_BIN_5 +597 0x0708 //TX_FDEQ_BIN_6 +598 0x090A //TX_FDEQ_BIN_7 +599 0x0B0C //TX_FDEQ_BIN_8 +600 0x0D0E //TX_FDEQ_BIN_9 +601 0x1013 //TX_FDEQ_BIN_10 +602 0x1719 //TX_FDEQ_BIN_11 +603 0x1B1E //TX_FDEQ_BIN_12 +604 0x1E1E //TX_FDEQ_BIN_13 +605 0x1E28 //TX_FDEQ_BIN_14 +606 0x282C //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4868 //TX_PREEQ_GAIN_MIC0_8 +626 0x6860 //TX_PREEQ_GAIN_MIC0_9 +627 0x6048 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0E10 //TX_PREEQ_BIN_MIC0_0 +642 0x1010 //TX_PREEQ_BIN_MIC0_1 +643 0x1010 //TX_PREEQ_BIN_MIC0_2 +644 0x1010 //TX_PREEQ_BIN_MIC0_3 +645 0x1010 //TX_PREEQ_BIN_MIC0_4 +646 0x1010 //TX_PREEQ_BIN_MIC0_5 +647 0x1010 //TX_PREEQ_BIN_MIC0_6 +648 0x1010 //TX_PREEQ_BIN_MIC0_7 +649 0x1010 //TX_PREEQ_BIN_MIC0_8 +650 0x1010 //TX_PREEQ_BIN_MIC0_9 +651 0x1010 //TX_PREEQ_BIN_MIC0_10 +652 0x1010 //TX_PREEQ_BIN_MIC0_11 +653 0x1010 //TX_PREEQ_BIN_MIC0_12 +654 0x1010 //TX_PREEQ_BIN_MIC0_13 +655 0x1010 //TX_PREEQ_BIN_MIC0_14 +656 0x0200 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0E10 //TX_PREEQ_BIN_MIC1_0 +691 0x1010 //TX_PREEQ_BIN_MIC1_1 +692 0x1010 //TX_PREEQ_BIN_MIC1_2 +693 0x1010 //TX_PREEQ_BIN_MIC1_3 +694 0x1010 //TX_PREEQ_BIN_MIC1_4 +695 0x1010 //TX_PREEQ_BIN_MIC1_5 +696 0x1010 //TX_PREEQ_BIN_MIC1_6 +697 0x1010 //TX_PREEQ_BIN_MIC1_7 +698 0x1010 //TX_PREEQ_BIN_MIC1_8 +699 0x1010 //TX_PREEQ_BIN_MIC1_9 +700 0x1010 //TX_PREEQ_BIN_MIC1_10 +701 0x1010 //TX_PREEQ_BIN_MIC1_11 +702 0x1010 //TX_PREEQ_BIN_MIC1_12 +703 0x1010 //TX_PREEQ_BIN_MIC1_13 +704 0x1010 //TX_PREEQ_BIN_MIC1_14 +705 0x0200 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0E10 //TX_PREEQ_BIN_MIC2_0 +740 0x1010 //TX_PREEQ_BIN_MIC2_1 +741 0x1010 //TX_PREEQ_BIN_MIC2_2 +742 0x1010 //TX_PREEQ_BIN_MIC2_3 +743 0x1010 //TX_PREEQ_BIN_MIC2_4 +744 0x1010 //TX_PREEQ_BIN_MIC2_5 +745 0x1010 //TX_PREEQ_BIN_MIC2_6 +746 0x1010 //TX_PREEQ_BIN_MIC2_7 +747 0x1010 //TX_PREEQ_BIN_MIC2_8 +748 0x1010 //TX_PREEQ_BIN_MIC2_9 +749 0x1010 //TX_PREEQ_BIN_MIC2_10 +750 0x1010 //TX_PREEQ_BIN_MIC2_11 +751 0x1010 //TX_PREEQ_BIN_MIC2_12 +752 0x1010 //TX_PREEQ_BIN_MIC2_13 +753 0x1010 //TX_PREEQ_BIN_MIC2_14 +754 0x0200 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x0800 //TX_NND_WEIGHT +765 0x0062 //TX_MIC_CALIBRATION_0 +766 0x0062 //TX_MIC_CALIBRATION_1 +767 0x0062 //TX_MIC_CALIBRATION_2 +768 0x0062 //TX_MIC_CALIBRATION_3 +769 0x0046 //TX_MIC_PWR_BIAS_0 +770 0x0046 //TX_MIC_PWR_BIAS_1 +771 0x0046 //TX_MIC_PWR_BIAS_2 +772 0x0046 //TX_MIC_PWR_BIAS_3 +773 0x000C //TX_GAIN_LIMIT_0 +774 0x000C //TX_GAIN_LIMIT_1 +775 0x000C //TX_GAIN_LIMIT_2 +776 0x000C //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x3000 //TX_TDDRC_ALPHA_UP_01 +784 0x3000 //TX_TDDRC_ALPHA_UP_02 +785 0x3000 //TX_TDDRC_ALPHA_UP_03 +786 0x3000 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x78D6 //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0000 //TX_DEADMIC_SILENCE_TH +817 0x0000 //TX_MIC_DEGRADE_TH +818 0x0000 //TX_DEADMIC_CNT +819 0x0000 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x4848 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0000 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0000 //TX_FILTINDX +854 0x0000 //TX_TDDRC_THRD_0 +855 0x0000 //TX_TDDRC_THRD_1 +856 0x2000 //TX_TDDRC_THRD_2 +857 0x2000 //TX_TDDRC_THRD_3 +858 0x3000 //TX_TDDRC_SLANT_0 +859 0x6E00 //TX_TDDRC_SLANT_1 +860 0x3000 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x05A0 //TX_TDDRC_DRC_GAIN +867 0x78D6 //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x0028 //TX_FASTNS_ARSPC_TH +889 0x8000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x4000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x2339 //TX_SENDFUNC_REG_MICMUTE +898 0x0021 //TX_SENDFUNC_REG_MICMUTE1 +899 0x02BC //TX_MICMUTE_RATIO_THR +900 0x0140 //TX_MICMUTE_AMP_THR +901 0x0004 //TX_MICMUTE_HPF_IND +902 0x00C0 //TX_MICMUTE_LOG_EYR_TH +903 0x0008 //TX_MICMUTE_CVG_TIME +904 0x0008 //TX_MICMUTE_RELEASE_TIME +905 0x01FE //TX_MIC_VOLUME_MIC0MUTE +906 0x0020 //TX_MICMUTE_EPD_OFFSET_0 +907 0x001E //TX_MICMUTE_FRQ_AEC_L +908 0x7999 //TX_MICMUTE_EAD_THR +909 0x7FFF //TX_MICMUTE_LAMBDA_CB_NLE +910 0x7FFF //TX_MICMUTE_LAMBDA_RE_EST +911 0x4000 //TX_DTD_THR1_MICMUTE_0 +912 0x7000 //TX_DTD_THR1_MICMUTE_1 +913 0x7FFF //TX_DTD_THR1_MICMUTE_2 +914 0x7FFF //TX_DTD_THR1_MICMUTE_3 +915 0x6CCC //TX_DTD_THR2_MICMUTE_0 +916 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x1000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x4000 //TX_MICMUTE_C_POST_FLT +922 0x03E8 //TX_MICMUTE_DT_CUT_K +923 0x0001 //TX_MICMUTE_DT_CUT_THR +924 0x03E8 //TX_MICMUTE_DT_CUT_K2 +925 0x0001 //TX_MICMUTE_DT_CUT_THR2 +926 0x0064 //TX_MICMUTE_DT2_HOLD_N +927 0x1000 //TX_MICMUTE_RATIODTH_THCUT +928 0x1000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x7FFF //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0400 //TX_MICMUTE_C_POST_FLT_MASK +931 0x7999 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0258 //TX_MICMUTE_DT_CUT_K1 +933 0x0800 //TX_MICMUTE_N2_SN_EST +934 0xFC00 //TX_MICMUTE_THR_SN_EST_0 +935 0x001C //TX_MICMUTE_MIN_G_CTRL_0 +936 0x6000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x7000 //TX_MICMUTE_B_POST_FILT_0 +938 0x2710 //TX_MIC1RUB_AMP_THR +939 0x0010 //TX_MIC1MUTE_RATIO_THR +940 0x0450 //TX_MIC1MUTE_AMP_THR +941 0x0008 //TX_MIC1MUTE_CVG_TIME +942 0x0008 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x202C //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0003 //RX_SAMPLINGFREQ_SIG +3 0x0003 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x5000 //RX_TDDRC_ALPHA_UP_1 +7 0x5000 //RX_TDDRC_ALPHA_UP_2 +8 0x5000 //RX_TDDRC_ALPHA_UP_3 +9 0x2000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7FFF //RX_A_HP +12 0x0000 //RX_B_PE +13 0x1800 //RX_THR_PITCH_DET_0 +14 0x1000 //RX_THR_PITCH_DET_1 +15 0x0800 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0400 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x0003 //RX_NS_LVL_CTRL +23 0x9000 //RX_THR_SN_EST +24 0x7CCD //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x65AD //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0002 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x5000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x01C8 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x2000 //RX_MIN_G_FP +128 0x0080 //RX_MAX_G_FP +129 0x000B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x5000 //RX_TDDRC_ALPHA_UP_1 +7 0x5000 //RX_TDDRC_ALPHA_UP_2 +8 0x5000 //RX_TDDRC_ALPHA_UP_3 +9 0x2000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x65AD //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x5000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x01C8 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x000B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x5000 //RX_TDDRC_ALPHA_UP_1 +7 0x5000 //RX_TDDRC_ALPHA_UP_2 +8 0x5000 //RX_TDDRC_ALPHA_UP_3 +9 0x2000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x65AD //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x5000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x01C8 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0013 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x5000 //RX_TDDRC_ALPHA_UP_1 +7 0x5000 //RX_TDDRC_ALPHA_UP_2 +8 0x5000 //RX_TDDRC_ALPHA_UP_3 +9 0x2000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x65AD //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x5000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x01C8 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0020 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x5000 //RX_TDDRC_ALPHA_UP_1 +7 0x5000 //RX_TDDRC_ALPHA_UP_2 +8 0x5000 //RX_TDDRC_ALPHA_UP_3 +9 0x2000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x65AD //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x5000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x01C8 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0036 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x5000 //RX_TDDRC_ALPHA_UP_1 +7 0x5000 //RX_TDDRC_ALPHA_UP_2 +8 0x5000 //RX_TDDRC_ALPHA_UP_3 +9 0x2000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x65AD //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x5000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x01C8 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x005B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x5000 //RX_TDDRC_ALPHA_UP_1 +7 0x5000 //RX_TDDRC_ALPHA_UP_2 +8 0x5000 //RX_TDDRC_ALPHA_UP_3 +9 0x2000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x65AD //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x5000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x01C8 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0099 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x5000 //RX_TDDRC_ALPHA_UP_1 +7 0x5000 //RX_TDDRC_ALPHA_UP_2 +8 0x5000 //RX_TDDRC_ALPHA_UP_3 +9 0x2000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x65AD //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x5000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x01C8 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x202C //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0003 //RX_SAMPLINGFREQ_SIG +160 0x0003 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x5000 //RX_TDDRC_ALPHA_UP_1 +164 0x5000 //RX_TDDRC_ALPHA_UP_2 +165 0x5000 //RX_TDDRC_ALPHA_UP_3 +166 0x2000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7FFF //RX_A_HP +169 0x0000 //RX_B_PE +170 0x1800 //RX_THR_PITCH_DET_0 +171 0x1000 //RX_THR_PITCH_DET_1 +172 0x0800 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0400 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x0003 //RX_NS_LVL_CTRL +180 0x9000 //RX_THR_SN_EST +181 0x7CCD //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x65AD //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0002 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x5000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x01C8 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x2000 //RX_MIN_G_FP +285 0x0080 //RX_MAX_G_FP +286 0x000B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x5000 //RX_TDDRC_ALPHA_UP_1 +164 0x5000 //RX_TDDRC_ALPHA_UP_2 +165 0x5000 //RX_TDDRC_ALPHA_UP_3 +166 0x2000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x65AD //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x5000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x01C8 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x000B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x5000 //RX_TDDRC_ALPHA_UP_1 +164 0x5000 //RX_TDDRC_ALPHA_UP_2 +165 0x5000 //RX_TDDRC_ALPHA_UP_3 +166 0x2000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x65AD //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x5000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x01C8 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0013 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x5000 //RX_TDDRC_ALPHA_UP_1 +164 0x5000 //RX_TDDRC_ALPHA_UP_2 +165 0x5000 //RX_TDDRC_ALPHA_UP_3 +166 0x2000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x65AD //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x5000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x01C8 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0020 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x5000 //RX_TDDRC_ALPHA_UP_1 +164 0x5000 //RX_TDDRC_ALPHA_UP_2 +165 0x5000 //RX_TDDRC_ALPHA_UP_3 +166 0x2000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x65AD //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x5000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x01C8 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0036 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x5000 //RX_TDDRC_ALPHA_UP_1 +164 0x5000 //RX_TDDRC_ALPHA_UP_2 +165 0x5000 //RX_TDDRC_ALPHA_UP_3 +166 0x2000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x65AD //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x5000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x01C8 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x005B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x5000 //RX_TDDRC_ALPHA_UP_1 +164 0x5000 //RX_TDDRC_ALPHA_UP_2 +165 0x5000 //RX_TDDRC_ALPHA_UP_3 +166 0x2000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x65AD //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x5000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x01C8 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0099 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x5000 //RX_TDDRC_ALPHA_UP_1 +164 0x5000 //RX_TDDRC_ALPHA_UP_2 +165 0x5000 //RX_TDDRC_ALPHA_UP_3 +166 0x2000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x65AD //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x5000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x01C8 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME HEADSET-RESERVE1-VOICE_GENERIC-FB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0009 //TX_OPERATION_MODE_0 +1 0x0009 //TX_OPERATION_MODE_1 +2 0x0020 //TX_PATCH_REG +3 0x6B6A //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0001 //TX_NUM_MIC +6 0x0004 //TX_SAMPLINGFREQ_SIG +7 0x0004 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009B //TX_DIST2REF1 +22 0x0000 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0B4C //TX_PGA_0 +28 0x0800 //TX_PGA_1 +29 0x0000 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0000 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0001 //TX_MIC_DATA_SRC1 +43 0x0002 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3E00 //TX_DIST2REF_11 +73 0x0000 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0200 //TX_MIC_REFBLK_VOLUME +108 0x0800 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0000 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7E56 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x6800 //TX_THR_PITCH_DET_0 +131 0x6000 //TX_THR_PITCH_DET_1 +132 0x5800 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x001E //TX_TAIL_LENGTH +147 0x0200 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x61A8 //TX_EAD_THR +151 0x0400 //TX_THR_RE_EST +152 0x3000 //TX_MIN_EQ_RE_EST_0 +153 0x3000 //TX_MIN_EQ_RE_EST_1 +154 0x4000 //TX_MIN_EQ_RE_EST_2 +155 0x0800 //TX_MIN_EQ_RE_EST_3 +156 0x0800 //TX_MIN_EQ_RE_EST_4 +157 0x0800 //TX_MIN_EQ_RE_EST_5 +158 0x6000 //TX_MIN_EQ_RE_EST_6 +159 0x6000 //TX_MIN_EQ_RE_EST_7 +160 0x6000 //TX_MIN_EQ_RE_EST_8 +161 0x6000 //TX_MIN_EQ_RE_EST_9 +162 0x4000 //TX_MIN_EQ_RE_EST_10 +163 0x4000 //TX_MIN_EQ_RE_EST_11 +164 0x4000 //TX_MIN_EQ_RE_EST_12 +165 0x3000 //TX_LAMBDA_RE_EST +166 0x4000 //TX_LAMBDA_CB_NLE +167 0x3000 //TX_C_POST_FLT +168 0x7FFF //TX_GAIN_NP +169 0x00C8 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x03E8 //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x0800 //TX_DTD_THR1_0 +198 0x0800 //TX_DTD_THR1_1 +199 0x0800 //TX_DTD_THR1_2 +200 0x0800 //TX_DTD_THR1_3 +201 0x0800 //TX_DTD_THR1_4 +202 0x0800 //TX_DTD_THR1_5 +203 0x0800 //TX_DTD_THR1_6 +204 0x0800 //TX_DTD_THR2_0 +205 0x0800 //TX_DTD_THR2_1 +206 0x0800 //TX_DTD_THR2_2 +207 0x0800 //TX_DTD_THR2_3 +208 0x0800 //TX_DTD_THR2_4 +209 0x0100 //TX_DTD_THR2_5 +210 0x0100 //TX_DTD_THR2_6 +211 0x7FFF //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x03E8 //TX_DT_CUT_K +214 0x0CCD //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x0400 //TX_ADPT_STRICT_L +222 0x0200 //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x0800 //TX_B_POST_FILT_ECHO_L +229 0x7FFF //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x7FFF //TX_B_LESSCUT_RTO_ECHO +232 0x00C0 //TX_EPD_OFFSET_00 +233 0x00C0 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x7FFF //TX_DTD_THR1_7 +238 0x7FFF //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xF700 //TX_THR_SN_EST_0 +243 0xFB00 //TX_THR_SN_EST_1 +244 0xFA00 //TX_THR_SN_EST_2 +245 0xF700 //TX_THR_SN_EST_3 +246 0xFA00 //TX_THR_SN_EST_4 +247 0xF600 //TX_THR_SN_EST_5 +248 0xF600 //TX_THR_SN_EST_6 +249 0xF600 //TX_THR_SN_EST_7 +250 0x0200 //TX_DELTA_THR_SN_EST_0 +251 0x0400 //TX_DELTA_THR_SN_EST_1 +252 0x0300 //TX_DELTA_THR_SN_EST_2 +253 0x0600 //TX_DELTA_THR_SN_EST_3 +254 0x0200 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0200 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x4000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x4000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x2000 //TX_B_POST_FLT_0 +280 0x2000 //TX_B_POST_FLT_1 +281 0x0012 //TX_NS_LVL_CTRL_0 +282 0x0016 //TX_NS_LVL_CTRL_1 +283 0x0016 //TX_NS_LVL_CTRL_2 +284 0x0019 //TX_NS_LVL_CTRL_3 +285 0x0010 //TX_NS_LVL_CTRL_4 +286 0x0010 //TX_NS_LVL_CTRL_5 +287 0x0019 //TX_NS_LVL_CTRL_6 +288 0x0010 //TX_NS_LVL_CTRL_7 +289 0x000C //TX_MIN_GAIN_S_0 +290 0x000C //TX_MIN_GAIN_S_1 +291 0x000C //TX_MIN_GAIN_S_2 +292 0x000F //TX_MIN_GAIN_S_3 +293 0x000C //TX_MIN_GAIN_S_4 +294 0x000C //TX_MIN_GAIN_S_5 +295 0x0011 //TX_MIN_GAIN_S_6 +296 0x000C //TX_MIN_GAIN_S_7 +297 0x7FFF //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7000 //TX_SNRI_SUP_0 +301 0x7000 //TX_SNRI_SUP_1 +302 0x7000 //TX_SNRI_SUP_2 +303 0x6000 //TX_SNRI_SUP_3 +304 0x7FFF //TX_SNRI_SUP_4 +305 0x7FFF //TX_SNRI_SUP_5 +306 0x6000 //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x0016 //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x6000 //TX_A_POST_FILT_S_0 +315 0x6000 //TX_A_POST_FILT_S_1 +316 0x6000 //TX_A_POST_FILT_S_2 +317 0x6000 //TX_A_POST_FILT_S_3 +318 0x6000 //TX_A_POST_FILT_S_4 +319 0x6000 //TX_A_POST_FILT_S_5 +320 0x6000 //TX_A_POST_FILT_S_6 +321 0x6000 //TX_A_POST_FILT_S_7 +322 0x2000 //TX_B_POST_FILT_0 +323 0x4000 //TX_B_POST_FILT_1 +324 0x2000 //TX_B_POST_FILT_2 +325 0x2000 //TX_B_POST_FILT_3 +326 0x2000 //TX_B_POST_FILT_4 +327 0x2000 //TX_B_POST_FILT_5 +328 0x2000 //TX_B_POST_FILT_6 +329 0x2000 //TX_B_POST_FILT_7 +330 0x7FFF //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x7FFF //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7CCD //TX_LAMBDA_PFILT +339 0x7CCD //TX_LAMBDA_PFILT_S_0 +340 0x7CCD //TX_LAMBDA_PFILT_S_1 +341 0x7CCD //TX_LAMBDA_PFILT_S_2 +342 0x7CCD //TX_LAMBDA_PFILT_S_3 +343 0x7CCD //TX_LAMBDA_PFILT_S_4 +344 0x7CCD //TX_LAMBDA_PFILT_S_5 +345 0x7CCD //TX_LAMBDA_PFILT_S_6 +346 0x7CCD //TX_LAMBDA_PFILT_S_7 +347 0x0200 //TX_K_PEPPER +348 0x0500 //TX_A_PEPPER +349 0x1600 //TX_K_PEPPER_HF +350 0x0400 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0800 //TX_DT_BINVAD_TH_0 +354 0x0800 //TX_DT_BINVAD_TH_1 +355 0x0800 //TX_DT_BINVAD_TH_2 +356 0x0800 //TX_DT_BINVAD_TH_3 +357 0x1D4C //TX_DT_BINVAD_ENDF +358 0x0000 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0190 //TX_NDETCT +367 0x04E8 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x02A6 //TX_NOISE_TH_1 +371 0x04B0 //TX_NOISE_TH_2 +372 0x3194 //TX_NOISE_TH_3 +373 0x0960 //TX_NOISE_TH_4 +374 0x5555 //TX_NOISE_TH_5 +375 0x3FF4 //TX_NOISE_TH_5_2 +376 0x0001 //TX_NOISE_TH_5_3 +377 0x0000 //TX_NOISE_TH_5_4 +378 0x02BC //TX_NOISE_TH_6 +379 0x02BC //TX_MINENOISE_TH +380 0xD508 //TX_MORENS_TFMASK_TH +381 0x0001 //TX_DRC_QUIET_FLOOR +382 0x3A98 //TX_RATIODTL_CUT_TH +383 0x1482 //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x0333 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x7FFF //TX_POST_MASK_SUP_HSNE +392 0x1388 //TX_TAIL_DET_TH +393 0x4000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0080 //TX_SUPHIGH_TH +396 0x0000 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x1800 //TX_C_POST_FLT_MASK +399 0x7FFF //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0004 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x04E7 //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x2900 //TX_MIN_G_CTRL_SSNS +409 0x0800 //TX_METAL_RTO_THR +410 0x4848 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x4000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x01E0 //TX_NOR_OFF_THR +498 0x7C00 //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0xD333 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x6000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0xC000 //TX_DEREVERB_LF_MU +515 0xC000 //TX_DEREVERB_HF_MU +516 0xCCCC //TX_DEREVERB_DELAY +517 0xD999 //TX_DEREVERB_COEF_LEN +518 0x1F40 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x7000 //TX_GSC_RTOH_TH +523 0x0064 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0020 //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4848 //TX_FDEQ_GAIN_5 +573 0x4848 //TX_FDEQ_GAIN_6 +574 0x4848 //TX_FDEQ_GAIN_7 +575 0x4848 //TX_FDEQ_GAIN_8 +576 0x4848 //TX_FDEQ_GAIN_9 +577 0x4848 //TX_FDEQ_GAIN_10 +578 0x4848 //TX_FDEQ_GAIN_11 +579 0x4848 //TX_FDEQ_GAIN_12 +580 0x4848 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0304 //TX_FDEQ_BIN_2 +594 0x0405 //TX_FDEQ_BIN_3 +595 0x0607 //TX_FDEQ_BIN_4 +596 0x0809 //TX_FDEQ_BIN_5 +597 0x0A0B //TX_FDEQ_BIN_6 +598 0x0C0D //TX_FDEQ_BIN_7 +599 0x0E0F //TX_FDEQ_BIN_8 +600 0x1011 //TX_FDEQ_BIN_9 +601 0x1214 //TX_FDEQ_BIN_10 +602 0x1618 //TX_FDEQ_BIN_11 +603 0x1C1C //TX_FDEQ_BIN_12 +604 0x2020 //TX_FDEQ_BIN_13 +605 0x2020 //TX_FDEQ_BIN_14 +606 0x2011 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4848 //TX_PREEQ_GAIN_MIC0_8 +626 0x4848 //TX_PREEQ_GAIN_MIC0_9 +627 0x4848 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0E10 //TX_PREEQ_BIN_MIC0_0 +642 0x1010 //TX_PREEQ_BIN_MIC0_1 +643 0x1010 //TX_PREEQ_BIN_MIC0_2 +644 0x1010 //TX_PREEQ_BIN_MIC0_3 +645 0x1010 //TX_PREEQ_BIN_MIC0_4 +646 0x1010 //TX_PREEQ_BIN_MIC0_5 +647 0x1010 //TX_PREEQ_BIN_MIC0_6 +648 0x1010 //TX_PREEQ_BIN_MIC0_7 +649 0x1010 //TX_PREEQ_BIN_MIC0_8 +650 0x1010 //TX_PREEQ_BIN_MIC0_9 +651 0x1010 //TX_PREEQ_BIN_MIC0_10 +652 0x1010 //TX_PREEQ_BIN_MIC0_11 +653 0x1010 //TX_PREEQ_BIN_MIC0_12 +654 0x1010 //TX_PREEQ_BIN_MIC0_13 +655 0x1010 //TX_PREEQ_BIN_MIC0_14 +656 0x0200 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0E10 //TX_PREEQ_BIN_MIC1_0 +691 0x1010 //TX_PREEQ_BIN_MIC1_1 +692 0x1010 //TX_PREEQ_BIN_MIC1_2 +693 0x1010 //TX_PREEQ_BIN_MIC1_3 +694 0x1010 //TX_PREEQ_BIN_MIC1_4 +695 0x1010 //TX_PREEQ_BIN_MIC1_5 +696 0x1010 //TX_PREEQ_BIN_MIC1_6 +697 0x1010 //TX_PREEQ_BIN_MIC1_7 +698 0x1010 //TX_PREEQ_BIN_MIC1_8 +699 0x1010 //TX_PREEQ_BIN_MIC1_9 +700 0x1010 //TX_PREEQ_BIN_MIC1_10 +701 0x1010 //TX_PREEQ_BIN_MIC1_11 +702 0x1010 //TX_PREEQ_BIN_MIC1_12 +703 0x1010 //TX_PREEQ_BIN_MIC1_13 +704 0x1010 //TX_PREEQ_BIN_MIC1_14 +705 0x0200 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0E10 //TX_PREEQ_BIN_MIC2_0 +740 0x1010 //TX_PREEQ_BIN_MIC2_1 +741 0x1010 //TX_PREEQ_BIN_MIC2_2 +742 0x1010 //TX_PREEQ_BIN_MIC2_3 +743 0x1010 //TX_PREEQ_BIN_MIC2_4 +744 0x1010 //TX_PREEQ_BIN_MIC2_5 +745 0x1010 //TX_PREEQ_BIN_MIC2_6 +746 0x1010 //TX_PREEQ_BIN_MIC2_7 +747 0x1010 //TX_PREEQ_BIN_MIC2_8 +748 0x1010 //TX_PREEQ_BIN_MIC2_9 +749 0x1010 //TX_PREEQ_BIN_MIC2_10 +750 0x1010 //TX_PREEQ_BIN_MIC2_11 +751 0x1010 //TX_PREEQ_BIN_MIC2_12 +752 0x1010 //TX_PREEQ_BIN_MIC2_13 +753 0x1010 //TX_PREEQ_BIN_MIC2_14 +754 0x0200 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x2000 //TX_NND_WEIGHT +765 0x0060 //TX_MIC_CALIBRATION_0 +766 0x0060 //TX_MIC_CALIBRATION_1 +767 0x0070 //TX_MIC_CALIBRATION_2 +768 0x0070 //TX_MIC_CALIBRATION_3 +769 0x0050 //TX_MIC_PWR_BIAS_0 +770 0x0040 //TX_MIC_PWR_BIAS_1 +771 0x0040 //TX_MIC_PWR_BIAS_2 +772 0x0040 //TX_MIC_PWR_BIAS_3 +773 0x0009 //TX_GAIN_LIMIT_0 +774 0x000F //TX_GAIN_LIMIT_1 +775 0x000F //TX_GAIN_LIMIT_2 +776 0x000F //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x0C00 //TX_TDDRC_ALPHA_UP_01 +784 0x0C00 //TX_TDDRC_ALPHA_UP_02 +785 0x0C00 //TX_TDDRC_ALPHA_UP_03 +786 0x0C00 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x7FFF //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0000 //TX_DEADMIC_SILENCE_TH +817 0x0000 //TX_MIC_DEGRADE_TH +818 0x0000 //TX_DEADMIC_CNT +819 0x0000 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x4848 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0000 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0002 //TX_FILTINDX +854 0x0001 //TX_TDDRC_THRD_0 +855 0x0001 //TX_TDDRC_THRD_1 +856 0x1900 //TX_TDDRC_THRD_2 +857 0x1900 //TX_TDDRC_THRD_3 +858 0x3000 //TX_TDDRC_SLANT_0 +859 0x7B00 //TX_TDDRC_SLANT_1 +860 0x0C00 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x07F2 //TX_TDDRC_DRC_GAIN +867 0x7FFF //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x0028 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x7000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x2339 //TX_SENDFUNC_REG_MICMUTE +898 0x0021 //TX_SENDFUNC_REG_MICMUTE1 +899 0x02BC //TX_MICMUTE_RATIO_THR +900 0x0140 //TX_MICMUTE_AMP_THR +901 0x0004 //TX_MICMUTE_HPF_IND +902 0x00C0 //TX_MICMUTE_LOG_EYR_TH +903 0x0008 //TX_MICMUTE_CVG_TIME +904 0x0008 //TX_MICMUTE_RELEASE_TIME +905 0x01FE //TX_MIC_VOLUME_MIC0MUTE +906 0x0020 //TX_MICMUTE_EPD_OFFSET_0 +907 0x001E //TX_MICMUTE_FRQ_AEC_L +908 0x7999 //TX_MICMUTE_EAD_THR +909 0x7FFF //TX_MICMUTE_LAMBDA_CB_NLE +910 0x7FFF //TX_MICMUTE_LAMBDA_RE_EST +911 0x4000 //TX_DTD_THR1_MICMUTE_0 +912 0x7000 //TX_DTD_THR1_MICMUTE_1 +913 0x7FFF //TX_DTD_THR1_MICMUTE_2 +914 0x7FFF //TX_DTD_THR1_MICMUTE_3 +915 0x6CCC //TX_DTD_THR2_MICMUTE_0 +916 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x1000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x4000 //TX_MICMUTE_C_POST_FLT +922 0x03E8 //TX_MICMUTE_DT_CUT_K +923 0x0001 //TX_MICMUTE_DT_CUT_THR +924 0x03E8 //TX_MICMUTE_DT_CUT_K2 +925 0x0001 //TX_MICMUTE_DT_CUT_THR2 +926 0x0064 //TX_MICMUTE_DT2_HOLD_N +927 0x1000 //TX_MICMUTE_RATIODTH_THCUT +928 0x1000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x7FFF //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0400 //TX_MICMUTE_C_POST_FLT_MASK +931 0x7999 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0258 //TX_MICMUTE_DT_CUT_K1 +933 0x0800 //TX_MICMUTE_N2_SN_EST +934 0xFC00 //TX_MICMUTE_THR_SN_EST_0 +935 0x001C //TX_MICMUTE_MIN_G_CTRL_0 +936 0x6000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x7000 //TX_MICMUTE_B_POST_FILT_0 +938 0x2710 //TX_MIC1RUB_AMP_THR +939 0x0010 //TX_MIC1MUTE_RATIO_THR +940 0x0450 //TX_MIC1MUTE_AMP_THR +941 0x0008 //TX_MIC1MUTE_CVG_TIME +942 0x0008 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x202C //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0004 //RX_SAMPLINGFREQ_SIG +3 0x0004 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7B02 //RX_A_HP +12 0x4000 //RX_B_PE +13 0x7800 //RX_THR_PITCH_DET_0 +14 0x7000 //RX_THR_PITCH_DET_1 +15 0x6000 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0500 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x000A //RX_NS_LVL_CTRL +23 0xF600 //RX_THR_SN_EST +24 0x7000 //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0002 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1200 //RX_TDDRC_THRD_2 +115 0x1900 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0240 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x2000 //RX_MIN_G_FP +128 0x0080 //RX_MAX_G_FP +129 0x000B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1200 //RX_TDDRC_THRD_2 +115 0x1900 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0240 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x000B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1200 //RX_TDDRC_THRD_2 +115 0x1900 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0240 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0013 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1200 //RX_TDDRC_THRD_2 +115 0x1900 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0240 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0020 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1200 //RX_TDDRC_THRD_2 +115 0x1900 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0240 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0036 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1200 //RX_TDDRC_THRD_2 +115 0x1900 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0240 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x005B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1200 //RX_TDDRC_THRD_2 +115 0x1900 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0240 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0099 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1200 //RX_TDDRC_THRD_2 +115 0x1900 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0240 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x202C //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0004 //RX_SAMPLINGFREQ_SIG +160 0x0004 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7B02 //RX_A_HP +169 0x4000 //RX_B_PE +170 0x7800 //RX_THR_PITCH_DET_0 +171 0x7000 //RX_THR_PITCH_DET_1 +172 0x6000 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0500 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x000A //RX_NS_LVL_CTRL +180 0xF600 //RX_THR_SN_EST +181 0x7000 //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0002 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1200 //RX_TDDRC_THRD_2 +272 0x1900 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0240 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x2000 //RX_MIN_G_FP +285 0x0080 //RX_MAX_G_FP +286 0x000B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1200 //RX_TDDRC_THRD_2 +272 0x1900 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0240 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x000B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1200 //RX_TDDRC_THRD_2 +272 0x1900 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0240 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0013 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1200 //RX_TDDRC_THRD_2 +272 0x1900 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0240 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0020 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1200 //RX_TDDRC_THRD_2 +272 0x1900 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0240 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0036 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1200 //RX_TDDRC_THRD_2 +272 0x1900 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0240 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x005B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1200 //RX_TDDRC_THRD_2 +272 0x1900 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0240 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0099 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1200 //RX_TDDRC_THRD_2 +272 0x1900 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0240 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME HEADSET-GOOGLE_CONDOR_HEADPHONE-VOICE_GENERIC-NB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0001 //TX_OPERATION_MODE_0 +1 0x0001 //TX_OPERATION_MODE_1 +2 0x0033 //TX_PATCH_REG +3 0x6F7C //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0002 //TX_NUM_MIC +6 0x0000 //TX_SAMPLINGFREQ_SIG +7 0x0000 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009D //TX_DIST2REF1 +22 0x0010 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x1000 //TX_PGA_0 +28 0x1000 //TX_PGA_1 +29 0x1000 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0001 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0002 //TX_MIC_DATA_SRC0 +42 0x0000 //TX_MIC_DATA_SRC1 +43 0x0001 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3A66 //TX_DIST2REF_11 +73 0x053D //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0200 //TX_MIC_REFBLK_VOLUME +108 0x0CAE //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0000 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7646 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x5000 //TX_THR_PITCH_DET_0 +131 0x4800 //TX_THR_PITCH_DET_1 +132 0x4000 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x0028 //TX_TAIL_LENGTH +147 0x0100 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x7500 //TX_EAD_THR +151 0x1000 //TX_THR_RE_EST +152 0x0200 //TX_MIN_EQ_RE_EST_0 +153 0x0200 //TX_MIN_EQ_RE_EST_1 +154 0x0200 //TX_MIN_EQ_RE_EST_2 +155 0x0200 //TX_MIN_EQ_RE_EST_3 +156 0x0200 //TX_MIN_EQ_RE_EST_4 +157 0x0200 //TX_MIN_EQ_RE_EST_5 +158 0x0200 //TX_MIN_EQ_RE_EST_6 +159 0x1800 //TX_MIN_EQ_RE_EST_7 +160 0x1800 //TX_MIN_EQ_RE_EST_8 +161 0x3000 //TX_MIN_EQ_RE_EST_9 +162 0x4000 //TX_MIN_EQ_RE_EST_10 +163 0x6000 //TX_MIN_EQ_RE_EST_11 +164 0x7FFF //TX_MIN_EQ_RE_EST_12 +165 0x2000 //TX_LAMBDA_RE_EST +166 0x0000 //TX_LAMBDA_CB_NLE +167 0x4000 //TX_C_POST_FLT +168 0x2000 //TX_GAIN_NP +169 0x0180 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x05DC //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x7FF0 //TX_DTD_THR1_0 +198 0x7FF0 //TX_DTD_THR1_1 +199 0x7FF0 //TX_DTD_THR1_2 +200 0x7FF0 //TX_DTD_THR1_3 +201 0x7FF0 //TX_DTD_THR1_4 +202 0x7FF0 //TX_DTD_THR1_5 +203 0x7FF0 //TX_DTD_THR1_6 +204 0x7E00 //TX_DTD_THR2_0 +205 0x0CCD //TX_DTD_THR2_1 +206 0x0CCD //TX_DTD_THR2_2 +207 0x0CCD //TX_DTD_THR2_3 +208 0x0CCD //TX_DTD_THR2_4 +209 0x0CCD //TX_DTD_THR2_5 +210 0x0CCD //TX_DTD_THR2_6 +211 0x7FFF //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x1F40 //TX_DT_CUT_K +214 0x0100 //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x1000 //TX_ADPT_STRICT_L +222 0x1000 //TX_ADPT_STRICT_H +223 0x0001 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x0640 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x0001 //TX_RATIO_DT_L0_TH +228 0x7FFF //TX_B_POST_FILT_ECHO_L +229 0x2000 //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x1000 //TX_B_LESSCUT_RTO_ECHO +232 0x0000 //TX_EPD_OFFSET_00 +233 0x0000 //TX_EPD_OFFST_01 +234 0x05DC //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x0000 //TX_DTD_THR1_7 +238 0x0000 //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xFA00 //TX_THR_SN_EST_0 +243 0xFA00 //TX_THR_SN_EST_1 +244 0xFA00 //TX_THR_SN_EST_2 +245 0xF900 //TX_THR_SN_EST_3 +246 0xFA00 //TX_THR_SN_EST_4 +247 0xFA00 //TX_THR_SN_EST_5 +248 0xF800 //TX_THR_SN_EST_6 +249 0xF800 //TX_THR_SN_EST_7 +250 0x0050 //TX_DELTA_THR_SN_EST_0 +251 0x0200 //TX_DELTA_THR_SN_EST_1 +252 0x0200 //TX_DELTA_THR_SN_EST_2 +253 0x0100 //TX_DELTA_THR_SN_EST_3 +254 0x0200 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x01A0 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x4000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x4000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x7F00 //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0800 //TX_MAINREFRTO_TH_EQ +279 0x1000 //TX_B_POST_FLT_0 +280 0x1000 //TX_B_POST_FLT_1 +281 0x0010 //TX_NS_LVL_CTRL_0 +282 0x0012 //TX_NS_LVL_CTRL_1 +283 0x0015 //TX_NS_LVL_CTRL_2 +284 0x0012 //TX_NS_LVL_CTRL_3 +285 0x0012 //TX_NS_LVL_CTRL_4 +286 0x0011 //TX_NS_LVL_CTRL_5 +287 0x0012 //TX_NS_LVL_CTRL_6 +288 0x0011 //TX_NS_LVL_CTRL_7 +289 0x000F //TX_MIN_GAIN_S_0 +290 0x000D //TX_MIN_GAIN_S_1 +291 0x000F //TX_MIN_GAIN_S_2 +292 0x000F //TX_MIN_GAIN_S_3 +293 0x000F //TX_MIN_GAIN_S_4 +294 0x0010 //TX_MIN_GAIN_S_5 +295 0x000F //TX_MIN_GAIN_S_6 +296 0x000F //TX_MIN_GAIN_S_7 +297 0x4000 //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x3000 //TX_SNRI_SUP_1 +302 0x4000 //TX_SNRI_SUP_2 +303 0x2400 //TX_SNRI_SUP_3 +304 0x4000 //TX_SNRI_SUP_4 +305 0x4000 //TX_SNRI_SUP_5 +306 0x4000 //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x0018 //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x4000 //TX_A_POST_FILT_S_0 +315 0x2000 //TX_A_POST_FILT_S_1 +316 0x4000 //TX_A_POST_FILT_S_2 +317 0x1000 //TX_A_POST_FILT_S_3 +318 0x3000 //TX_A_POST_FILT_S_4 +319 0x5000 //TX_A_POST_FILT_S_5 +320 0x5000 //TX_A_POST_FILT_S_6 +321 0x7000 //TX_A_POST_FILT_S_7 +322 0x1000 //TX_B_POST_FILT_0 +323 0x1000 //TX_B_POST_FILT_1 +324 0x1000 //TX_B_POST_FILT_2 +325 0x5000 //TX_B_POST_FILT_3 +326 0x3000 //TX_B_POST_FILT_4 +327 0x1000 //TX_B_POST_FILT_5 +328 0x1000 //TX_B_POST_FILT_6 +329 0x2000 //TX_B_POST_FILT_7 +330 0x4000 //TX_B_LESSCUT_RTO_S_0 +331 0x6000 //TX_B_LESSCUT_RTO_S_1 +332 0x6000 //TX_B_LESSCUT_RTO_S_2 +333 0x6000 //TX_B_LESSCUT_RTO_S_3 +334 0x6000 //TX_B_LESSCUT_RTO_S_4 +335 0x6000 //TX_B_LESSCUT_RTO_S_5 +336 0x6000 //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7E00 //TX_LAMBDA_PFILT +339 0x7D00 //TX_LAMBDA_PFILT_S_0 +340 0x7C00 //TX_LAMBDA_PFILT_S_1 +341 0x7900 //TX_LAMBDA_PFILT_S_2 +342 0x7000 //TX_LAMBDA_PFILT_S_3 +343 0x7D00 //TX_LAMBDA_PFILT_S_4 +344 0x7D00 //TX_LAMBDA_PFILT_S_5 +345 0x7900 //TX_LAMBDA_PFILT_S_6 +346 0x7D00 //TX_LAMBDA_PFILT_S_7 +347 0x0200 //TX_K_PEPPER +348 0x0800 //TX_A_PEPPER +349 0x1EAA //TX_K_PEPPER_HF +350 0x0600 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0800 //TX_DT_BINVAD_TH_0 +354 0x0100 //TX_DT_BINVAD_TH_1 +355 0x0100 //TX_DT_BINVAD_TH_2 +356 0x0800 //TX_DT_BINVAD_TH_3 +357 0x0FA0 //TX_DT_BINVAD_ENDF +358 0x7000 //TX_C_POST_FLT_DT +359 0x4000 //TX_NS_B_POST_FLT_LESSCUT +360 0x01B0 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0064 //TX_NDETCT +367 0x003B //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x07D0 //TX_NOISE_TH_1 +371 0x03ED //TX_NOISE_TH_2 +372 0x2EE0 //TX_NOISE_TH_3 +373 0x5528 //TX_NOISE_TH_4 +374 0x7FFF //TX_NOISE_TH_5 +375 0x7FFF //TX_NOISE_TH_5_2 +376 0x0000 //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x0FA0 //TX_NOISE_TH_6 +379 0x00C8 //TX_MINENOISE_TH +380 0xD508 //TX_MORENS_TFMASK_TH +381 0x0001 //TX_DRC_QUIET_FLOOR +382 0x3A98 //TX_RATIODTL_CUT_TH +383 0x0DAC //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x1000 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x7FFF //TX_POST_MASK_SUP_HSNE +392 0x1388 //TX_TAIL_DET_TH +393 0x4000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0080 //TX_SUPHIGH_TH +396 0x0000 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x1800 //TX_C_POST_FLT_MASK +399 0x7FFF //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0004 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x0032 //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x7FFF //TX_MIN_G_CTRL_SSNS +409 0x0000 //TX_METAL_RTO_THR +410 0x4848 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x007A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x5000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x01E0 //TX_NOR_OFF_THR +498 0x7C00 //TX_MORE_ON_700HZ_THR +499 0x0000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0xD333 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x7FFF //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0xC000 //TX_DEREVERB_LF_MU +515 0xC000 //TX_DEREVERB_HF_MU +516 0xCCCC //TX_DEREVERB_DELAY +517 0xD999 //TX_DEREVERB_COEF_LEN +518 0x1F40 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x7000 //TX_GSC_RTOH_TH +523 0x0064 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0014 //TX_FDEQ_SUBNUM +567 0x5050 //TX_FDEQ_GAIN_0 +568 0x5048 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x483C //TX_FDEQ_GAIN_3 +571 0x3034 //TX_FDEQ_GAIN_4 +572 0x3048 //TX_FDEQ_GAIN_5 +573 0x4840 //TX_FDEQ_GAIN_6 +574 0x403C //TX_FDEQ_GAIN_7 +575 0x262C //TX_FDEQ_GAIN_8 +576 0x3A3C //TX_FDEQ_GAIN_9 +577 0x4848 //TX_FDEQ_GAIN_10 +578 0x4848 //TX_FDEQ_GAIN_11 +579 0x4848 //TX_FDEQ_GAIN_12 +580 0x4848 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0303 //TX_FDEQ_BIN_2 +594 0x0304 //TX_FDEQ_BIN_3 +595 0x0405 //TX_FDEQ_BIN_4 +596 0x0506 //TX_FDEQ_BIN_5 +597 0x0708 //TX_FDEQ_BIN_6 +598 0x090A //TX_FDEQ_BIN_7 +599 0x0B0C //TX_FDEQ_BIN_8 +600 0x0D0E //TX_FDEQ_BIN_9 +601 0x0000 //TX_FDEQ_BIN_10 +602 0x0000 //TX_FDEQ_BIN_11 +603 0x0000 //TX_FDEQ_BIN_12 +604 0x0000 //TX_FDEQ_BIN_13 +605 0x0000 //TX_FDEQ_BIN_14 +606 0x0000 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0014 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4A4C //TX_PREEQ_GAIN_MIC0_8 +626 0x4E50 //TX_PREEQ_GAIN_MIC0_9 +627 0x4848 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0202 //TX_PREEQ_BIN_MIC0_0 +642 0x0203 //TX_PREEQ_BIN_MIC0_1 +643 0x0303 //TX_PREEQ_BIN_MIC0_2 +644 0x0304 //TX_PREEQ_BIN_MIC0_3 +645 0x0405 //TX_PREEQ_BIN_MIC0_4 +646 0x0506 //TX_PREEQ_BIN_MIC0_5 +647 0x0708 //TX_PREEQ_BIN_MIC0_6 +648 0x090A //TX_PREEQ_BIN_MIC0_7 +649 0x0B0C //TX_PREEQ_BIN_MIC0_8 +650 0x0D0E //TX_PREEQ_BIN_MIC0_9 +651 0x0000 //TX_PREEQ_BIN_MIC0_10 +652 0x0000 //TX_PREEQ_BIN_MIC0_11 +653 0x0000 //TX_PREEQ_BIN_MIC0_12 +654 0x0000 //TX_PREEQ_BIN_MIC0_13 +655 0x0000 //TX_PREEQ_BIN_MIC0_14 +656 0x0000 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4846 //TX_PREEQ_GAIN_MIC1_7 +674 0x4544 //TX_PREEQ_GAIN_MIC1_8 +675 0x4241 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0202 //TX_PREEQ_BIN_MIC1_0 +691 0x0203 //TX_PREEQ_BIN_MIC1_1 +692 0x0303 //TX_PREEQ_BIN_MIC1_2 +693 0x0304 //TX_PREEQ_BIN_MIC1_3 +694 0x0405 //TX_PREEQ_BIN_MIC1_4 +695 0x0506 //TX_PREEQ_BIN_MIC1_5 +696 0x0708 //TX_PREEQ_BIN_MIC1_6 +697 0x090A //TX_PREEQ_BIN_MIC1_7 +698 0x0B0C //TX_PREEQ_BIN_MIC1_8 +699 0x0D0E //TX_PREEQ_BIN_MIC1_9 +700 0x0000 //TX_PREEQ_BIN_MIC1_10 +701 0x0000 //TX_PREEQ_BIN_MIC1_11 +702 0x0000 //TX_PREEQ_BIN_MIC1_12 +703 0x0000 //TX_PREEQ_BIN_MIC1_13 +704 0x0000 //TX_PREEQ_BIN_MIC1_14 +705 0x0000 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0000 //TX_PREEQ_BIN_MIC2_0 +740 0x0000 //TX_PREEQ_BIN_MIC2_1 +741 0x0000 //TX_PREEQ_BIN_MIC2_2 +742 0x0000 //TX_PREEQ_BIN_MIC2_3 +743 0x0000 //TX_PREEQ_BIN_MIC2_4 +744 0x0000 //TX_PREEQ_BIN_MIC2_5 +745 0x0000 //TX_PREEQ_BIN_MIC2_6 +746 0x0000 //TX_PREEQ_BIN_MIC2_7 +747 0x0000 //TX_PREEQ_BIN_MIC2_8 +748 0x0000 //TX_PREEQ_BIN_MIC2_9 +749 0x0000 //TX_PREEQ_BIN_MIC2_10 +750 0x0000 //TX_PREEQ_BIN_MIC2_11 +751 0x0000 //TX_PREEQ_BIN_MIC2_12 +752 0x0000 //TX_PREEQ_BIN_MIC2_13 +753 0x0000 //TX_PREEQ_BIN_MIC2_14 +754 0x0000 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x0800 //TX_NND_WEIGHT +765 0x0065 //TX_MIC_CALIBRATION_0 +766 0x0065 //TX_MIC_CALIBRATION_1 +767 0x0065 //TX_MIC_CALIBRATION_2 +768 0x0065 //TX_MIC_CALIBRATION_3 +769 0x0044 //TX_MIC_PWR_BIAS_0 +770 0x0044 //TX_MIC_PWR_BIAS_1 +771 0x0044 //TX_MIC_PWR_BIAS_2 +772 0x0044 //TX_MIC_PWR_BIAS_3 +773 0x0009 //TX_GAIN_LIMIT_0 +774 0x000F //TX_GAIN_LIMIT_1 +775 0x000F //TX_GAIN_LIMIT_2 +776 0x000F //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x4000 //TX_TDDRC_ALPHA_UP_01 +784 0x4000 //TX_TDDRC_ALPHA_UP_02 +785 0x4000 //TX_TDDRC_ALPHA_UP_03 +786 0x4000 //TX_TDDRC_ALPHA_UP_04 +787 0x6000 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x7214 //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0010 //TX_DEADMIC_SILENCE_TH +817 0x0600 //TX_MIC_DEGRADE_TH +818 0x0078 //TX_DEADMIC_CNT +819 0x0078 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x4848 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0096 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0002 //TX_FILTINDX +854 0x0004 //TX_TDDRC_THRD_0 +855 0x0010 //TX_TDDRC_THRD_1 +856 0x1800 //TX_TDDRC_THRD_2 +857 0x1800 //TX_TDDRC_THRD_3 +858 0x7FFF //TX_TDDRC_SLANT_0 +859 0x7FFF //TX_TDDRC_SLANT_1 +860 0x4000 //TX_TDDRC_ALPHA_UP_00 +861 0x6000 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x0A00 //TX_TDDRC_DRC_GAIN +867 0x7FFF //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x0028 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x4000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x2339 //TX_SENDFUNC_REG_MICMUTE +898 0x0021 //TX_SENDFUNC_REG_MICMUTE1 +899 0x02BC //TX_MICMUTE_RATIO_THR +900 0x0140 //TX_MICMUTE_AMP_THR +901 0x0004 //TX_MICMUTE_HPF_IND +902 0x00C0 //TX_MICMUTE_LOG_EYR_TH +903 0x0008 //TX_MICMUTE_CVG_TIME +904 0x0008 //TX_MICMUTE_RELEASE_TIME +905 0x01FE //TX_MIC_VOLUME_MIC0MUTE +906 0x0020 //TX_MICMUTE_EPD_OFFSET_0 +907 0x001E //TX_MICMUTE_FRQ_AEC_L +908 0x7999 //TX_MICMUTE_EAD_THR +909 0x7FFF //TX_MICMUTE_LAMBDA_CB_NLE +910 0x7FFF //TX_MICMUTE_LAMBDA_RE_EST +911 0x4000 //TX_DTD_THR1_MICMUTE_0 +912 0x7000 //TX_DTD_THR1_MICMUTE_1 +913 0x7FFF //TX_DTD_THR1_MICMUTE_2 +914 0x7FFF //TX_DTD_THR1_MICMUTE_3 +915 0x6CCC //TX_DTD_THR2_MICMUTE_0 +916 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x1000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x4000 //TX_MICMUTE_C_POST_FLT +922 0x03E8 //TX_MICMUTE_DT_CUT_K +923 0x0001 //TX_MICMUTE_DT_CUT_THR +924 0x03E8 //TX_MICMUTE_DT_CUT_K2 +925 0x0001 //TX_MICMUTE_DT_CUT_THR2 +926 0x0064 //TX_MICMUTE_DT2_HOLD_N +927 0x1000 //TX_MICMUTE_RATIODTH_THCUT +928 0x1000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x7FFF //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0400 //TX_MICMUTE_C_POST_FLT_MASK +931 0x7999 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0258 //TX_MICMUTE_DT_CUT_K1 +933 0x0800 //TX_MICMUTE_N2_SN_EST +934 0xFC00 //TX_MICMUTE_THR_SN_EST_0 +935 0x001C //TX_MICMUTE_MIN_G_CTRL_0 +936 0x6000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x7000 //TX_MICMUTE_B_POST_FILT_0 +938 0x2710 //TX_MIC1RUB_AMP_THR +939 0x0010 //TX_MIC1MUTE_RATIO_THR +940 0x0450 //TX_MIC1MUTE_AMP_THR +941 0x0008 //TX_MIC1MUTE_CVG_TIME +942 0x0008 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x202C //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0000 //RX_SAMPLINGFREQ_SIG +3 0x0000 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7FFF //RX_A_HP +12 0x0000 //RX_B_PE +13 0x3800 //RX_THR_PITCH_DET_0 +14 0x3000 //RX_THR_PITCH_DET_1 +15 0x2800 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0600 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x0010 //RX_NS_LVL_CTRL +23 0xF800 //RX_THR_SN_EST +24 0x7CCD //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0002 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0200 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x2000 //RX_MIN_G_FP +128 0x0080 //RX_MAX_G_FP +129 0x000B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0200 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x000B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0200 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0013 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0200 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0020 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0200 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0036 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0200 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x005B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0200 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0099 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0200 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x202C //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0000 //RX_SAMPLINGFREQ_SIG +160 0x0000 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7FFF //RX_A_HP +169 0x0000 //RX_B_PE +170 0x3800 //RX_THR_PITCH_DET_0 +171 0x3000 //RX_THR_PITCH_DET_1 +172 0x2800 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0600 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x0010 //RX_NS_LVL_CTRL +180 0xF800 //RX_THR_SN_EST +181 0x7CCD //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0002 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0200 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x2000 //RX_MIN_G_FP +285 0x0080 //RX_MAX_G_FP +286 0x000B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0200 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x000B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0200 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0013 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0200 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0020 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0200 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0036 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0200 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x005B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0200 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0099 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0200 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME HEADSET-GOOGLE_CONDOR_HEADPHONE-VOICE_GENERIC-WB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0001 //TX_OPERATION_MODE_0 +1 0x0001 //TX_OPERATION_MODE_1 +2 0x0033 //TX_PATCH_REG +3 0x6F7C //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0002 //TX_NUM_MIC +6 0x0001 //TX_SAMPLINGFREQ_SIG +7 0x0001 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009D //TX_DIST2REF1 +22 0x0010 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x1000 //TX_PGA_0 +28 0x1000 //TX_PGA_1 +29 0x1000 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0001 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0002 //TX_MIC_DATA_SRC0 +42 0x0000 //TX_MIC_DATA_SRC1 +43 0x0001 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3A66 //TX_DIST2REF_11 +73 0x053D //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0800 //TX_MIC_REFBLK_VOLUME +108 0x0C00 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0004 //TX_MAINMIC_BLKFACTOR +114 0x0004 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0000 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7B02 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x5000 //TX_THR_PITCH_DET_0 +131 0x4800 //TX_THR_PITCH_DET_1 +132 0x4000 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x0028 //TX_TAIL_LENGTH +147 0x0300 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x6800 //TX_EAD_THR +151 0x1000 //TX_THR_RE_EST +152 0x3000 //TX_MIN_EQ_RE_EST_0 +153 0x0100 //TX_MIN_EQ_RE_EST_1 +154 0x0200 //TX_MIN_EQ_RE_EST_2 +155 0x0200 //TX_MIN_EQ_RE_EST_3 +156 0x0200 //TX_MIN_EQ_RE_EST_4 +157 0x0200 //TX_MIN_EQ_RE_EST_5 +158 0x0200 //TX_MIN_EQ_RE_EST_6 +159 0x1000 //TX_MIN_EQ_RE_EST_7 +160 0x1000 //TX_MIN_EQ_RE_EST_8 +161 0x1000 //TX_MIN_EQ_RE_EST_9 +162 0x1000 //TX_MIN_EQ_RE_EST_10 +163 0x1000 //TX_MIN_EQ_RE_EST_11 +164 0x1000 //TX_MIN_EQ_RE_EST_12 +165 0x1B00 //TX_LAMBDA_RE_EST +166 0x4000 //TX_LAMBDA_CB_NLE +167 0x7FFF //TX_C_POST_FLT +168 0x5000 //TX_GAIN_NP +169 0x0180 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x0020 //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x76D0 //TX_DTD_THR1_0 +198 0x76D0 //TX_DTD_THR1_1 +199 0x76D0 //TX_DTD_THR1_2 +200 0x7FF0 //TX_DTD_THR1_3 +201 0x7FF0 //TX_DTD_THR1_4 +202 0x7FF0 //TX_DTD_THR1_5 +203 0x7FF0 //TX_DTD_THR1_6 +204 0x7E00 //TX_DTD_THR2_0 +205 0x7E00 //TX_DTD_THR2_1 +206 0x5000 //TX_DTD_THR2_2 +207 0x5000 //TX_DTD_THR2_3 +208 0x5000 //TX_DTD_THR2_4 +209 0x5000 //TX_DTD_THR2_5 +210 0x5000 //TX_DTD_THR2_6 +211 0x7FFF //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x03E8 //TX_DT_CUT_K +214 0x0010 //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x023E //TX_ADPT_STRICT_L +222 0x023E //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x044C //TX_RATIO_DT_L_TH_HIGH +226 0x7800 //TX_RATIO_DT_H_TH_HIGH +227 0x0001 //TX_RATIO_DT_L0_TH +228 0x7FFF //TX_B_POST_FILT_ECHO_L +229 0x7FFF //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x1000 //TX_B_LESSCUT_RTO_ECHO +232 0x0000 //TX_EPD_OFFSET_00 +233 0x0000 //TX_EPD_OFFST_01 +234 0x03E8 //TX_RATIO_DT_L0_TH_HIGH +235 0x7FFF //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x0000 //TX_DTD_THR1_7 +238 0x0000 //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xFA00 //TX_THR_SN_EST_0 +243 0xFA00 //TX_THR_SN_EST_1 +244 0xFA00 //TX_THR_SN_EST_2 +245 0xFB00 //TX_THR_SN_EST_3 +246 0xFA00 //TX_THR_SN_EST_4 +247 0xFA00 //TX_THR_SN_EST_5 +248 0xF800 //TX_THR_SN_EST_6 +249 0xF800 //TX_THR_SN_EST_7 +250 0x0100 //TX_DELTA_THR_SN_EST_0 +251 0x0100 //TX_DELTA_THR_SN_EST_1 +252 0x0200 //TX_DELTA_THR_SN_EST_2 +253 0x0100 //TX_DELTA_THR_SN_EST_3 +254 0x0100 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0200 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x4000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x4000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x2000 //TX_B_POST_FLT_0 +280 0x1000 //TX_B_POST_FLT_1 +281 0x0010 //TX_NS_LVL_CTRL_0 +282 0x0014 //TX_NS_LVL_CTRL_1 +283 0x0018 //TX_NS_LVL_CTRL_2 +284 0x0016 //TX_NS_LVL_CTRL_3 +285 0x0014 //TX_NS_LVL_CTRL_4 +286 0x0011 //TX_NS_LVL_CTRL_5 +287 0x0014 //TX_NS_LVL_CTRL_6 +288 0x0011 //TX_NS_LVL_CTRL_7 +289 0x000F //TX_MIN_GAIN_S_0 +290 0x0010 //TX_MIN_GAIN_S_1 +291 0x0010 //TX_MIN_GAIN_S_2 +292 0x0010 //TX_MIN_GAIN_S_3 +293 0x0010 //TX_MIN_GAIN_S_4 +294 0x0010 //TX_MIN_GAIN_S_5 +295 0x0010 //TX_MIN_GAIN_S_6 +296 0x000F //TX_MIN_GAIN_S_7 +297 0x6000 //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x4000 //TX_SNRI_SUP_1 +302 0x4000 //TX_SNRI_SUP_2 +303 0x4000 //TX_SNRI_SUP_3 +304 0x4000 //TX_SNRI_SUP_4 +305 0x50C0 //TX_SNRI_SUP_5 +306 0x4000 //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x0018 //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x5000 //TX_A_POST_FILT_S_0 +315 0x4C00 //TX_A_POST_FILT_S_1 +316 0x4000 //TX_A_POST_FILT_S_2 +317 0x6000 //TX_A_POST_FILT_S_3 +318 0x4000 //TX_A_POST_FILT_S_4 +319 0x5000 //TX_A_POST_FILT_S_5 +320 0x6000 //TX_A_POST_FILT_S_6 +321 0x7000 //TX_A_POST_FILT_S_7 +322 0x2000 //TX_B_POST_FILT_0 +323 0x2000 //TX_B_POST_FILT_1 +324 0x2000 //TX_B_POST_FILT_2 +325 0x4000 //TX_B_POST_FILT_3 +326 0x4000 //TX_B_POST_FILT_4 +327 0x1000 //TX_B_POST_FILT_5 +328 0x1000 //TX_B_POST_FILT_6 +329 0x2000 //TX_B_POST_FILT_7 +330 0x4000 //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x6000 //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7C00 //TX_LAMBDA_PFILT +339 0x7C00 //TX_LAMBDA_PFILT_S_0 +340 0x7C00 //TX_LAMBDA_PFILT_S_1 +341 0x7A00 //TX_LAMBDA_PFILT_S_2 +342 0x7C00 //TX_LAMBDA_PFILT_S_3 +343 0x7C00 //TX_LAMBDA_PFILT_S_4 +344 0x7C00 //TX_LAMBDA_PFILT_S_5 +345 0x7C00 //TX_LAMBDA_PFILT_S_6 +346 0x7C00 //TX_LAMBDA_PFILT_S_7 +347 0x0200 //TX_K_PEPPER +348 0x0800 //TX_A_PEPPER +349 0x1EAA //TX_K_PEPPER_HF +350 0x0600 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0800 //TX_DT_BINVAD_TH_0 +354 0x0800 //TX_DT_BINVAD_TH_1 +355 0x0800 //TX_DT_BINVAD_TH_2 +356 0x0800 //TX_DT_BINVAD_TH_3 +357 0x1D4C //TX_DT_BINVAD_ENDF +358 0x0800 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0140 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0064 //TX_NDETCT +367 0x0102 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x017E //TX_NOISE_TH_1 +371 0x0230 //TX_NOISE_TH_2 +372 0x3492 //TX_NOISE_TH_3 +373 0x4E20 //TX_NOISE_TH_4 +374 0x55B8 //TX_NOISE_TH_5 +375 0x49E6 //TX_NOISE_TH_5_2 +376 0x0001 //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x0F0A //TX_NOISE_TH_6 +379 0x00F8 //TX_MINENOISE_TH +380 0xD508 //TX_MORENS_TFMASK_TH +381 0x0001 //TX_DRC_QUIET_FLOOR +382 0x3A98 //TX_RATIODTL_CUT_TH +383 0x0DAC //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x0333 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x7FFF //TX_POST_MASK_SUP_HSNE +392 0x1388 //TX_TAIL_DET_TH +393 0x4000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0080 //TX_SUPHIGH_TH +396 0x0000 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x1800 //TX_C_POST_FLT_MASK +399 0x7FFF //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0004 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x00DC //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x7FFF //TX_MIN_G_CTRL_SSNS +409 0x0000 //TX_METAL_RTO_THR +410 0x4848 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x4000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x01E0 //TX_NOR_OFF_THR +498 0x7C00 //TX_MORE_ON_700HZ_THR +499 0x0000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0xD333 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x4000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0xC000 //TX_DEREVERB_LF_MU +515 0xC000 //TX_DEREVERB_HF_MU +516 0xCCCC //TX_DEREVERB_DELAY +517 0xD999 //TX_DEREVERB_COEF_LEN +518 0x1F40 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x7000 //TX_GSC_RTOH_TH +523 0x0064 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0020 //TX_FDEQ_SUBNUM +567 0x5454 //TX_FDEQ_GAIN_0 +568 0x5448 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4850 //TX_FDEQ_GAIN_5 +573 0x5050 //TX_FDEQ_GAIN_6 +574 0x5448 //TX_FDEQ_GAIN_7 +575 0x464C //TX_FDEQ_GAIN_8 +576 0x5050 //TX_FDEQ_GAIN_9 +577 0x4848 //TX_FDEQ_GAIN_10 +578 0x4848 //TX_FDEQ_GAIN_11 +579 0x4848 //TX_FDEQ_GAIN_12 +580 0x4848 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0303 //TX_FDEQ_BIN_2 +594 0x0304 //TX_FDEQ_BIN_3 +595 0x0405 //TX_FDEQ_BIN_4 +596 0x0506 //TX_FDEQ_BIN_5 +597 0x0708 //TX_FDEQ_BIN_6 +598 0x090A //TX_FDEQ_BIN_7 +599 0x0B0C //TX_FDEQ_BIN_8 +600 0x0D0E //TX_FDEQ_BIN_9 +601 0x0F10 //TX_FDEQ_BIN_10 +602 0x1011 //TX_FDEQ_BIN_11 +603 0x1112 //TX_FDEQ_BIN_12 +604 0x120B //TX_FDEQ_BIN_13 +605 0x0000 //TX_FDEQ_BIN_14 +606 0x0000 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x484A //TX_PREEQ_GAIN_MIC0_8 +626 0x4B4C //TX_PREEQ_GAIN_MIC0_9 +627 0x4B4A //TX_PREEQ_GAIN_MIC0_10 +628 0x4A48 //TX_PREEQ_GAIN_MIC0_11 +629 0x4C4C //TX_PREEQ_GAIN_MIC0_12 +630 0x4C4C //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0202 //TX_PREEQ_BIN_MIC0_0 +642 0x0203 //TX_PREEQ_BIN_MIC0_1 +643 0x0303 //TX_PREEQ_BIN_MIC0_2 +644 0x0304 //TX_PREEQ_BIN_MIC0_3 +645 0x0405 //TX_PREEQ_BIN_MIC0_4 +646 0x0506 //TX_PREEQ_BIN_MIC0_5 +647 0x0708 //TX_PREEQ_BIN_MIC0_6 +648 0x090A //TX_PREEQ_BIN_MIC0_7 +649 0x0B0C //TX_PREEQ_BIN_MIC0_8 +650 0x0D0E //TX_PREEQ_BIN_MIC0_9 +651 0x0F10 //TX_PREEQ_BIN_MIC0_10 +652 0x1011 //TX_PREEQ_BIN_MIC0_11 +653 0x1112 //TX_PREEQ_BIN_MIC0_12 +654 0x120B //TX_PREEQ_BIN_MIC0_13 +655 0x0000 //TX_PREEQ_BIN_MIC0_14 +656 0x0000 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4846 //TX_PREEQ_GAIN_MIC1_7 +674 0x4544 //TX_PREEQ_GAIN_MIC1_8 +675 0x4241 //TX_PREEQ_GAIN_MIC1_9 +676 0x403E //TX_PREEQ_GAIN_MIC1_10 +677 0x3D3C //TX_PREEQ_GAIN_MIC1_11 +678 0x3C3C //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0202 //TX_PREEQ_BIN_MIC1_0 +691 0x0203 //TX_PREEQ_BIN_MIC1_1 +692 0x0303 //TX_PREEQ_BIN_MIC1_2 +693 0x0304 //TX_PREEQ_BIN_MIC1_3 +694 0x0405 //TX_PREEQ_BIN_MIC1_4 +695 0x0506 //TX_PREEQ_BIN_MIC1_5 +696 0x0708 //TX_PREEQ_BIN_MIC1_6 +697 0x090A //TX_PREEQ_BIN_MIC1_7 +698 0x0B0C //TX_PREEQ_BIN_MIC1_8 +699 0x0F10 //TX_PREEQ_BIN_MIC1_9 +700 0x1011 //TX_PREEQ_BIN_MIC1_10 +701 0x1112 //TX_PREEQ_BIN_MIC1_11 +702 0x1208 //TX_PREEQ_BIN_MIC1_12 +703 0x0000 //TX_PREEQ_BIN_MIC1_13 +704 0x0000 //TX_PREEQ_BIN_MIC1_14 +705 0x0000 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0608 //TX_PREEQ_BIN_MIC2_0 +740 0x0808 //TX_PREEQ_BIN_MIC2_1 +741 0x0808 //TX_PREEQ_BIN_MIC2_2 +742 0x0808 //TX_PREEQ_BIN_MIC2_3 +743 0x0808 //TX_PREEQ_BIN_MIC2_4 +744 0x0808 //TX_PREEQ_BIN_MIC2_5 +745 0x0808 //TX_PREEQ_BIN_MIC2_6 +746 0x0808 //TX_PREEQ_BIN_MIC2_7 +747 0x0808 //TX_PREEQ_BIN_MIC2_8 +748 0x0808 //TX_PREEQ_BIN_MIC2_9 +749 0x0808 //TX_PREEQ_BIN_MIC2_10 +750 0x0808 //TX_PREEQ_BIN_MIC2_11 +751 0x0808 //TX_PREEQ_BIN_MIC2_12 +752 0x0808 //TX_PREEQ_BIN_MIC2_13 +753 0x0808 //TX_PREEQ_BIN_MIC2_14 +754 0x0200 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x0800 //TX_NND_WEIGHT +765 0x0062 //TX_MIC_CALIBRATION_0 +766 0x0062 //TX_MIC_CALIBRATION_1 +767 0x0062 //TX_MIC_CALIBRATION_2 +768 0x0062 //TX_MIC_CALIBRATION_3 +769 0x0046 //TX_MIC_PWR_BIAS_0 +770 0x0046 //TX_MIC_PWR_BIAS_1 +771 0x0046 //TX_MIC_PWR_BIAS_2 +772 0x0046 //TX_MIC_PWR_BIAS_3 +773 0x0009 //TX_GAIN_LIMIT_0 +774 0x000F //TX_GAIN_LIMIT_1 +775 0x000F //TX_GAIN_LIMIT_2 +776 0x000F //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x0800 //TX_TDDRC_ALPHA_UP_01 +784 0x0800 //TX_TDDRC_ALPHA_UP_02 +785 0x0800 //TX_TDDRC_ALPHA_UP_03 +786 0x0800 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x7214 //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0010 //TX_DEADMIC_SILENCE_TH +817 0x0600 //TX_MIC_DEGRADE_TH +818 0x0078 //TX_DEADMIC_CNT +819 0x0078 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x4848 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0096 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0002 //TX_FILTINDX +854 0x0001 //TX_TDDRC_THRD_0 +855 0x0002 //TX_TDDRC_THRD_1 +856 0x1800 //TX_TDDRC_THRD_2 +857 0x1800 //TX_TDDRC_THRD_3 +858 0x7FFF //TX_TDDRC_SLANT_0 +859 0x7FFF //TX_TDDRC_SLANT_1 +860 0x0800 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x0C97 //TX_TDDRC_DRC_GAIN +867 0x7FFF //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x0028 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x4000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x2339 //TX_SENDFUNC_REG_MICMUTE +898 0x0021 //TX_SENDFUNC_REG_MICMUTE1 +899 0x02BC //TX_MICMUTE_RATIO_THR +900 0x0140 //TX_MICMUTE_AMP_THR +901 0x0004 //TX_MICMUTE_HPF_IND +902 0x00C0 //TX_MICMUTE_LOG_EYR_TH +903 0x0008 //TX_MICMUTE_CVG_TIME +904 0x0008 //TX_MICMUTE_RELEASE_TIME +905 0x01FE //TX_MIC_VOLUME_MIC0MUTE +906 0x0020 //TX_MICMUTE_EPD_OFFSET_0 +907 0x001E //TX_MICMUTE_FRQ_AEC_L +908 0x7999 //TX_MICMUTE_EAD_THR +909 0x7FFF //TX_MICMUTE_LAMBDA_CB_NLE +910 0x7FFF //TX_MICMUTE_LAMBDA_RE_EST +911 0x4000 //TX_DTD_THR1_MICMUTE_0 +912 0x7000 //TX_DTD_THR1_MICMUTE_1 +913 0x7FFF //TX_DTD_THR1_MICMUTE_2 +914 0x7FFF //TX_DTD_THR1_MICMUTE_3 +915 0x6CCC //TX_DTD_THR2_MICMUTE_0 +916 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x1000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x4000 //TX_MICMUTE_C_POST_FLT +922 0x03E8 //TX_MICMUTE_DT_CUT_K +923 0x0001 //TX_MICMUTE_DT_CUT_THR +924 0x03E8 //TX_MICMUTE_DT_CUT_K2 +925 0x0001 //TX_MICMUTE_DT_CUT_THR2 +926 0x0064 //TX_MICMUTE_DT2_HOLD_N +927 0x1000 //TX_MICMUTE_RATIODTH_THCUT +928 0x1000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x7FFF //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0400 //TX_MICMUTE_C_POST_FLT_MASK +931 0x7999 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0258 //TX_MICMUTE_DT_CUT_K1 +933 0x0800 //TX_MICMUTE_N2_SN_EST +934 0xFC00 //TX_MICMUTE_THR_SN_EST_0 +935 0x001C //TX_MICMUTE_MIN_G_CTRL_0 +936 0x6000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x7000 //TX_MICMUTE_B_POST_FILT_0 +938 0x2710 //TX_MIC1RUB_AMP_THR +939 0x0010 //TX_MIC1MUTE_RATIO_THR +940 0x0450 //TX_MIC1MUTE_AMP_THR +941 0x0008 //TX_MIC1MUTE_CVG_TIME +942 0x0008 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x202C //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0001 //RX_SAMPLINGFREQ_SIG +3 0x0001 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7FFF //RX_A_HP +12 0x4000 //RX_B_PE +13 0x3800 //RX_THR_PITCH_DET_0 +14 0x3000 //RX_THR_PITCH_DET_1 +15 0x2800 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0600 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x0010 //RX_NS_LVL_CTRL +23 0xF800 //RX_THR_SN_EST +24 0x7CCD //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0002 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0196 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x2000 //RX_MIN_G_FP +128 0x0080 //RX_MAX_G_FP +129 0x000B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0196 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x000B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0196 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0013 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0196 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0020 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0196 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0036 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0196 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x005B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0196 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0099 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0196 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x202C //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0001 //RX_SAMPLINGFREQ_SIG +160 0x0001 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7FFF //RX_A_HP +169 0x4000 //RX_B_PE +170 0x3800 //RX_THR_PITCH_DET_0 +171 0x3000 //RX_THR_PITCH_DET_1 +172 0x2800 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0600 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x0010 //RX_NS_LVL_CTRL +180 0xF800 //RX_THR_SN_EST +181 0x7CCD //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0002 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0196 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x2000 //RX_MIN_G_FP +285 0x0080 //RX_MAX_G_FP +286 0x000B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0196 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x000B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0196 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0013 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0196 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0020 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0196 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0036 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0196 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x005B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0196 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0099 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0196 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME HEADSET-GOOGLE_CONDOR_HEADPHONE-VOICE_GENERIC-SWB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0001 //TX_OPERATION_MODE_0 +1 0x0001 //TX_OPERATION_MODE_1 +2 0x0033 //TX_PATCH_REG +3 0x6F7C //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0002 //TX_NUM_MIC +6 0x0003 //TX_SAMPLINGFREQ_SIG +7 0x0003 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009D //TX_DIST2REF1 +22 0x0010 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x1000 //TX_PGA_0 +28 0x1000 //TX_PGA_1 +29 0x1000 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0001 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0002 //TX_MIC_DATA_SRC0 +42 0x0000 //TX_MIC_DATA_SRC1 +43 0x0001 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3B33 //TX_DIST2REF_11 +73 0x0A70 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0800 //TX_MIC_REFBLK_VOLUME +108 0x0CAE //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0015 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7D83 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x5000 //TX_THR_PITCH_DET_0 +131 0x4800 //TX_THR_PITCH_DET_1 +132 0x4000 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x0028 //TX_TAIL_LENGTH +147 0x0400 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x7600 //TX_EAD_THR +151 0x1000 //TX_THR_RE_EST +152 0x2000 //TX_MIN_EQ_RE_EST_0 +153 0x0600 //TX_MIN_EQ_RE_EST_1 +154 0x3000 //TX_MIN_EQ_RE_EST_2 +155 0x3000 //TX_MIN_EQ_RE_EST_3 +156 0x3000 //TX_MIN_EQ_RE_EST_4 +157 0x3000 //TX_MIN_EQ_RE_EST_5 +158 0x3000 //TX_MIN_EQ_RE_EST_6 +159 0x1000 //TX_MIN_EQ_RE_EST_7 +160 0x7800 //TX_MIN_EQ_RE_EST_8 +161 0x7800 //TX_MIN_EQ_RE_EST_9 +162 0x7800 //TX_MIN_EQ_RE_EST_10 +163 0x7800 //TX_MIN_EQ_RE_EST_11 +164 0x7800 //TX_MIN_EQ_RE_EST_12 +165 0x0880 //TX_LAMBDA_RE_EST +166 0x7FFF //TX_LAMBDA_CB_NLE +167 0x7FFF //TX_C_POST_FLT +168 0x4000 //TX_GAIN_NP +169 0x0180 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x05DC //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x7FF0 //TX_DTD_THR1_0 +198 0x7FF0 //TX_DTD_THR1_1 +199 0x7FF0 //TX_DTD_THR1_2 +200 0x7FF0 //TX_DTD_THR1_3 +201 0x7FF0 //TX_DTD_THR1_4 +202 0x7FF0 //TX_DTD_THR1_5 +203 0x7FF0 //TX_DTD_THR1_6 +204 0x7E00 //TX_DTD_THR2_0 +205 0x7E00 //TX_DTD_THR2_1 +206 0x5000 //TX_DTD_THR2_2 +207 0x5000 //TX_DTD_THR2_3 +208 0x5000 //TX_DTD_THR2_4 +209 0x5000 //TX_DTD_THR2_5 +210 0x5000 //TX_DTD_THR2_6 +211 0x7FFF //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x36B0 //TX_DT_CUT_K +214 0x0100 //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x7FFF //TX_DTD_MIC_BLK +221 0x023E //TX_ADPT_STRICT_L +222 0x023E //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x733C //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x7FFF //TX_B_POST_FILT_ECHO_L +229 0x7FFF //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x1000 //TX_B_LESSCUT_RTO_ECHO +232 0x0000 //TX_EPD_OFFSET_00 +233 0x0000 //TX_EPD_OFFST_01 +234 0x3A98 //TX_RATIO_DT_L0_TH_HIGH +235 0x7FFF //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x0000 //TX_DTD_THR1_7 +238 0x0000 //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xFA00 //TX_THR_SN_EST_0 +243 0xFA00 //TX_THR_SN_EST_1 +244 0xFA00 //TX_THR_SN_EST_2 +245 0xFA00 //TX_THR_SN_EST_3 +246 0xF800 //TX_THR_SN_EST_4 +247 0xFA00 //TX_THR_SN_EST_5 +248 0xF800 //TX_THR_SN_EST_6 +249 0xF800 //TX_THR_SN_EST_7 +250 0x0100 //TX_DELTA_THR_SN_EST_0 +251 0x0100 //TX_DELTA_THR_SN_EST_1 +252 0x0100 //TX_DELTA_THR_SN_EST_2 +253 0x0000 //TX_DELTA_THR_SN_EST_3 +254 0x0100 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0100 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x4000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x4000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x2000 //TX_B_POST_FLT_0 +280 0x1000 //TX_B_POST_FLT_1 +281 0x0010 //TX_NS_LVL_CTRL_0 +282 0x003C //TX_NS_LVL_CTRL_1 +283 0x0024 //TX_NS_LVL_CTRL_2 +284 0x003C //TX_NS_LVL_CTRL_3 +285 0x0014 //TX_NS_LVL_CTRL_4 +286 0x0011 //TX_NS_LVL_CTRL_5 +287 0x003C //TX_NS_LVL_CTRL_6 +288 0x0011 //TX_NS_LVL_CTRL_7 +289 0x000F //TX_MIN_GAIN_S_0 +290 0x0010 //TX_MIN_GAIN_S_1 +291 0x0010 //TX_MIN_GAIN_S_2 +292 0x0010 //TX_MIN_GAIN_S_3 +293 0x0010 //TX_MIN_GAIN_S_4 +294 0x0010 //TX_MIN_GAIN_S_5 +295 0x0010 //TX_MIN_GAIN_S_6 +296 0x000F //TX_MIN_GAIN_S_7 +297 0x6000 //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x1400 //TX_SNRI_SUP_1 +302 0x1400 //TX_SNRI_SUP_2 +303 0x4000 //TX_SNRI_SUP_3 +304 0x4000 //TX_SNRI_SUP_4 +305 0x50C0 //TX_SNRI_SUP_5 +306 0x1400 //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x0018 //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x5000 //TX_A_POST_FILT_S_0 +315 0x4C00 //TX_A_POST_FILT_S_1 +316 0x4000 //TX_A_POST_FILT_S_2 +317 0x6000 //TX_A_POST_FILT_S_3 +318 0x4000 //TX_A_POST_FILT_S_4 +319 0x5000 //TX_A_POST_FILT_S_5 +320 0x7C00 //TX_A_POST_FILT_S_6 +321 0x7000 //TX_A_POST_FILT_S_7 +322 0x2000 //TX_B_POST_FILT_0 +323 0x6000 //TX_B_POST_FILT_1 +324 0x6000 //TX_B_POST_FILT_2 +325 0x6000 //TX_B_POST_FILT_3 +326 0x4000 //TX_B_POST_FILT_4 +327 0x1000 //TX_B_POST_FILT_5 +328 0x1000 //TX_B_POST_FILT_6 +329 0x2000 //TX_B_POST_FILT_7 +330 0x4000 //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x6000 //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7C00 //TX_LAMBDA_PFILT +339 0x7D00 //TX_LAMBDA_PFILT_S_0 +340 0x7D00 //TX_LAMBDA_PFILT_S_1 +341 0x7D00 //TX_LAMBDA_PFILT_S_2 +342 0x7D00 //TX_LAMBDA_PFILT_S_3 +343 0x7D00 //TX_LAMBDA_PFILT_S_4 +344 0x7D00 //TX_LAMBDA_PFILT_S_5 +345 0x7D00 //TX_LAMBDA_PFILT_S_6 +346 0x7D00 //TX_LAMBDA_PFILT_S_7 +347 0x0200 //TX_K_PEPPER +348 0x0400 //TX_A_PEPPER +349 0x1EAA //TX_K_PEPPER_HF +350 0x0600 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0040 //TX_DT_BINVAD_TH_0 +354 0x0040 //TX_DT_BINVAD_TH_1 +355 0x0100 //TX_DT_BINVAD_TH_2 +356 0x0100 //TX_DT_BINVAD_TH_3 +357 0x36B0 //TX_DT_BINVAD_ENDF +358 0x0200 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0140 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0064 //TX_NDETCT +367 0x0383 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x07D0 //TX_NOISE_TH_1 +371 0x01F4 //TX_NOISE_TH_2 +372 0x36B0 //TX_NOISE_TH_3 +373 0x2710 //TX_NOISE_TH_4 +374 0x2CEC //TX_NOISE_TH_5 +375 0x7FFF //TX_NOISE_TH_5_2 +376 0x0000 //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x0DAC //TX_NOISE_TH_6 +379 0x044C //TX_MINENOISE_TH +380 0xD508 //TX_MORENS_TFMASK_TH +381 0x0001 //TX_DRC_QUIET_FLOOR +382 0x3A98 //TX_RATIODTL_CUT_TH +383 0x0DAC //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x0333 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x7FFF //TX_POST_MASK_SUP_HSNE +392 0x1388 //TX_TAIL_DET_TH +393 0x4000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0080 //TX_SUPHIGH_TH +396 0x0000 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x1800 //TX_C_POST_FLT_MASK +399 0x7FFF //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0004 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x02F3 //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x4000 //TX_MIN_G_CTRL_SSNS +409 0x0000 //TX_METAL_RTO_THR +410 0x4848 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x4000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x0230 //TX_NOR_OFF_THR +498 0x0CCD //TX_MORE_ON_700HZ_THR +499 0x0000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x2000 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0x4650 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x4000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0xC000 //TX_DEREVERB_LF_MU +515 0xC000 //TX_DEREVERB_HF_MU +516 0xCCCC //TX_DEREVERB_DELAY +517 0xD999 //TX_DEREVERB_COEF_LEN +518 0x1F40 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x7000 //TX_GSC_RTOH_TH +523 0x0064 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0020 //TX_FDEQ_SUBNUM +567 0x5450 //TX_FDEQ_GAIN_0 +568 0x4C48 //TX_FDEQ_GAIN_1 +569 0x4850 //TX_FDEQ_GAIN_2 +570 0x5050 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x484E //TX_FDEQ_GAIN_5 +573 0x4E5E //TX_FDEQ_GAIN_6 +574 0x584E //TX_FDEQ_GAIN_7 +575 0x4C4E //TX_FDEQ_GAIN_8 +576 0x564E //TX_FDEQ_GAIN_9 +577 0x5058 //TX_FDEQ_GAIN_10 +578 0x625C //TX_FDEQ_GAIN_11 +579 0x6C6C //TX_FDEQ_GAIN_12 +580 0x7086 //TX_FDEQ_GAIN_13 +581 0x869C //TX_FDEQ_GAIN_14 +582 0xB0B0 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0303 //TX_FDEQ_BIN_2 +594 0x0304 //TX_FDEQ_BIN_3 +595 0x0405 //TX_FDEQ_BIN_4 +596 0x0506 //TX_FDEQ_BIN_5 +597 0x0708 //TX_FDEQ_BIN_6 +598 0x090A //TX_FDEQ_BIN_7 +599 0x0B0C //TX_FDEQ_BIN_8 +600 0x0D0E //TX_FDEQ_BIN_9 +601 0x1013 //TX_FDEQ_BIN_10 +602 0x1719 //TX_FDEQ_BIN_11 +603 0x1B1E //TX_FDEQ_BIN_12 +604 0x1E1E //TX_FDEQ_BIN_13 +605 0x1E28 //TX_FDEQ_BIN_14 +606 0x284A //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x494A //TX_PREEQ_GAIN_MIC0_8 +626 0x4B4C //TX_PREEQ_GAIN_MIC0_9 +627 0x4B4A //TX_PREEQ_GAIN_MIC0_10 +628 0x484B //TX_PREEQ_GAIN_MIC0_11 +629 0x4C4C //TX_PREEQ_GAIN_MIC0_12 +630 0x4B48 //TX_PREEQ_GAIN_MIC0_13 +631 0x3838 //TX_PREEQ_GAIN_MIC0_14 +632 0x3835 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0202 //TX_PREEQ_BIN_MIC0_0 +642 0x0203 //TX_PREEQ_BIN_MIC0_1 +643 0x0303 //TX_PREEQ_BIN_MIC0_2 +644 0x0304 //TX_PREEQ_BIN_MIC0_3 +645 0x0405 //TX_PREEQ_BIN_MIC0_4 +646 0x0506 //TX_PREEQ_BIN_MIC0_5 +647 0x0708 //TX_PREEQ_BIN_MIC0_6 +648 0x090A //TX_PREEQ_BIN_MIC0_7 +649 0x0B0C //TX_PREEQ_BIN_MIC0_8 +650 0x0D0E //TX_PREEQ_BIN_MIC0_9 +651 0x1013 //TX_PREEQ_BIN_MIC0_10 +652 0x1719 //TX_PREEQ_BIN_MIC0_11 +653 0x1B1E //TX_PREEQ_BIN_MIC0_12 +654 0x1E1E //TX_PREEQ_BIN_MIC0_13 +655 0x1E28 //TX_PREEQ_BIN_MIC0_14 +656 0x282C //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4846 //TX_PREEQ_GAIN_MIC1_7 +674 0x4544 //TX_PREEQ_GAIN_MIC1_8 +675 0x4241 //TX_PREEQ_GAIN_MIC1_9 +676 0x403E //TX_PREEQ_GAIN_MIC1_10 +677 0x3D3C //TX_PREEQ_GAIN_MIC1_11 +678 0x3C3C //TX_PREEQ_GAIN_MIC1_12 +679 0x3C39 //TX_PREEQ_GAIN_MIC1_13 +680 0x3838 //TX_PREEQ_GAIN_MIC1_14 +681 0x3A3C //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0202 //TX_PREEQ_BIN_MIC1_0 +691 0x0203 //TX_PREEQ_BIN_MIC1_1 +692 0x0303 //TX_PREEQ_BIN_MIC1_2 +693 0x0304 //TX_PREEQ_BIN_MIC1_3 +694 0x0405 //TX_PREEQ_BIN_MIC1_4 +695 0x0506 //TX_PREEQ_BIN_MIC1_5 +696 0x0708 //TX_PREEQ_BIN_MIC1_6 +697 0x090A //TX_PREEQ_BIN_MIC1_7 +698 0x0B0C //TX_PREEQ_BIN_MIC1_8 +699 0x0D0E //TX_PREEQ_BIN_MIC1_9 +700 0x1013 //TX_PREEQ_BIN_MIC1_10 +701 0x1719 //TX_PREEQ_BIN_MIC1_11 +702 0x1B1E //TX_PREEQ_BIN_MIC1_12 +703 0x1E1E //TX_PREEQ_BIN_MIC1_13 +704 0x1E28 //TX_PREEQ_BIN_MIC1_14 +705 0x282C //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0608 //TX_PREEQ_BIN_MIC2_0 +740 0x0808 //TX_PREEQ_BIN_MIC2_1 +741 0x0808 //TX_PREEQ_BIN_MIC2_2 +742 0x0808 //TX_PREEQ_BIN_MIC2_3 +743 0x0808 //TX_PREEQ_BIN_MIC2_4 +744 0x0808 //TX_PREEQ_BIN_MIC2_5 +745 0x0808 //TX_PREEQ_BIN_MIC2_6 +746 0x0808 //TX_PREEQ_BIN_MIC2_7 +747 0x0808 //TX_PREEQ_BIN_MIC2_8 +748 0x0808 //TX_PREEQ_BIN_MIC2_9 +749 0x0808 //TX_PREEQ_BIN_MIC2_10 +750 0x0808 //TX_PREEQ_BIN_MIC2_11 +751 0x0808 //TX_PREEQ_BIN_MIC2_12 +752 0x0808 //TX_PREEQ_BIN_MIC2_13 +753 0x0808 //TX_PREEQ_BIN_MIC2_14 +754 0xF200 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x0800 //TX_NND_WEIGHT +765 0x0050 //TX_MIC_CALIBRATION_0 +766 0x0065 //TX_MIC_CALIBRATION_1 +767 0x0050 //TX_MIC_CALIBRATION_2 +768 0x0050 //TX_MIC_CALIBRATION_3 +769 0x0046 //TX_MIC_PWR_BIAS_0 +770 0x0040 //TX_MIC_PWR_BIAS_1 +771 0x0046 //TX_MIC_PWR_BIAS_2 +772 0x0046 //TX_MIC_PWR_BIAS_3 +773 0x0000 //TX_GAIN_LIMIT_0 +774 0x000F //TX_GAIN_LIMIT_1 +775 0x0000 //TX_GAIN_LIMIT_2 +776 0x0000 //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x0800 //TX_TDDRC_ALPHA_UP_01 +784 0x0800 //TX_TDDRC_ALPHA_UP_02 +785 0x0800 //TX_TDDRC_ALPHA_UP_03 +786 0x0800 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x7214 //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0010 //TX_DEADMIC_SILENCE_TH +817 0x0600 //TX_MIC_DEGRADE_TH +818 0x0078 //TX_DEADMIC_CNT +819 0x0078 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x4848 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0096 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0002 //TX_FILTINDX +854 0x0003 //TX_TDDRC_THRD_0 +855 0x0004 //TX_TDDRC_THRD_1 +856 0x1800 //TX_TDDRC_THRD_2 +857 0x1800 //TX_TDDRC_THRD_3 +858 0x7FFF //TX_TDDRC_SLANT_0 +859 0x7FFF //TX_TDDRC_SLANT_1 +860 0x0800 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x0E21 //TX_TDDRC_DRC_GAIN +867 0x7FFF //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x00C8 //TX_FASTNS_ARSPC_TH +889 0x8000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x4000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x2339 //TX_SENDFUNC_REG_MICMUTE +898 0x0021 //TX_SENDFUNC_REG_MICMUTE1 +899 0x02BC //TX_MICMUTE_RATIO_THR +900 0x0140 //TX_MICMUTE_AMP_THR +901 0x0004 //TX_MICMUTE_HPF_IND +902 0x00C0 //TX_MICMUTE_LOG_EYR_TH +903 0x0008 //TX_MICMUTE_CVG_TIME +904 0x0008 //TX_MICMUTE_RELEASE_TIME +905 0x01FE //TX_MIC_VOLUME_MIC0MUTE +906 0x0020 //TX_MICMUTE_EPD_OFFSET_0 +907 0x001E //TX_MICMUTE_FRQ_AEC_L +908 0x7999 //TX_MICMUTE_EAD_THR +909 0x7FFF //TX_MICMUTE_LAMBDA_CB_NLE +910 0x7FFF //TX_MICMUTE_LAMBDA_RE_EST +911 0x4000 //TX_DTD_THR1_MICMUTE_0 +912 0x7000 //TX_DTD_THR1_MICMUTE_1 +913 0x7FFF //TX_DTD_THR1_MICMUTE_2 +914 0x7FFF //TX_DTD_THR1_MICMUTE_3 +915 0x6CCC //TX_DTD_THR2_MICMUTE_0 +916 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x1000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x4000 //TX_MICMUTE_C_POST_FLT +922 0x03E8 //TX_MICMUTE_DT_CUT_K +923 0x0001 //TX_MICMUTE_DT_CUT_THR +924 0x03E8 //TX_MICMUTE_DT_CUT_K2 +925 0x0001 //TX_MICMUTE_DT_CUT_THR2 +926 0x0064 //TX_MICMUTE_DT2_HOLD_N +927 0x1000 //TX_MICMUTE_RATIODTH_THCUT +928 0x1000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x7FFF //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0400 //TX_MICMUTE_C_POST_FLT_MASK +931 0x7999 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0258 //TX_MICMUTE_DT_CUT_K1 +933 0x0800 //TX_MICMUTE_N2_SN_EST +934 0xFC00 //TX_MICMUTE_THR_SN_EST_0 +935 0x001C //TX_MICMUTE_MIN_G_CTRL_0 +936 0x6000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x7000 //TX_MICMUTE_B_POST_FILT_0 +938 0x2710 //TX_MIC1RUB_AMP_THR +939 0x0010 //TX_MIC1MUTE_RATIO_THR +940 0x0450 //TX_MIC1MUTE_AMP_THR +941 0x0008 //TX_MIC1MUTE_CVG_TIME +942 0x0008 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x202C //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0003 //RX_SAMPLINGFREQ_SIG +3 0x0003 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x5000 //RX_TDDRC_ALPHA_UP_1 +7 0x5000 //RX_TDDRC_ALPHA_UP_2 +8 0x5000 //RX_TDDRC_ALPHA_UP_3 +9 0x2000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7FFF //RX_A_HP +12 0x0000 //RX_B_PE +13 0x1800 //RX_THR_PITCH_DET_0 +14 0x1000 //RX_THR_PITCH_DET_1 +15 0x0800 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0400 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x0003 //RX_NS_LVL_CTRL +23 0x9000 //RX_THR_SN_EST +24 0x7CCD //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x65AD //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0002 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x5000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x01C8 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x2000 //RX_MIN_G_FP +128 0x0080 //RX_MAX_G_FP +129 0x000B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x5000 //RX_TDDRC_ALPHA_UP_1 +7 0x5000 //RX_TDDRC_ALPHA_UP_2 +8 0x5000 //RX_TDDRC_ALPHA_UP_3 +9 0x2000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x65AD //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x5000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x01C8 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x000B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x5000 //RX_TDDRC_ALPHA_UP_1 +7 0x5000 //RX_TDDRC_ALPHA_UP_2 +8 0x5000 //RX_TDDRC_ALPHA_UP_3 +9 0x2000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x65AD //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x5000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x01C8 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0013 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x5000 //RX_TDDRC_ALPHA_UP_1 +7 0x5000 //RX_TDDRC_ALPHA_UP_2 +8 0x5000 //RX_TDDRC_ALPHA_UP_3 +9 0x2000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x65AD //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x5000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x01C8 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0020 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x5000 //RX_TDDRC_ALPHA_UP_1 +7 0x5000 //RX_TDDRC_ALPHA_UP_2 +8 0x5000 //RX_TDDRC_ALPHA_UP_3 +9 0x2000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x65AD //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x5000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x01C8 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0036 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x5000 //RX_TDDRC_ALPHA_UP_1 +7 0x5000 //RX_TDDRC_ALPHA_UP_2 +8 0x5000 //RX_TDDRC_ALPHA_UP_3 +9 0x2000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x65AD //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x5000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x01C8 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x005B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x5000 //RX_TDDRC_ALPHA_UP_1 +7 0x5000 //RX_TDDRC_ALPHA_UP_2 +8 0x5000 //RX_TDDRC_ALPHA_UP_3 +9 0x2000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x65AD //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x5000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x01C8 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0099 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x5000 //RX_TDDRC_ALPHA_UP_1 +7 0x5000 //RX_TDDRC_ALPHA_UP_2 +8 0x5000 //RX_TDDRC_ALPHA_UP_3 +9 0x2000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x65AD //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x5000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x01C8 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x202C //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0003 //RX_SAMPLINGFREQ_SIG +160 0x0003 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x5000 //RX_TDDRC_ALPHA_UP_1 +164 0x5000 //RX_TDDRC_ALPHA_UP_2 +165 0x5000 //RX_TDDRC_ALPHA_UP_3 +166 0x2000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7FFF //RX_A_HP +169 0x0000 //RX_B_PE +170 0x1800 //RX_THR_PITCH_DET_0 +171 0x1000 //RX_THR_PITCH_DET_1 +172 0x0800 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0400 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x0003 //RX_NS_LVL_CTRL +180 0x9000 //RX_THR_SN_EST +181 0x7CCD //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x65AD //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0002 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x5000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x01C8 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x2000 //RX_MIN_G_FP +285 0x0080 //RX_MAX_G_FP +286 0x000B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x5000 //RX_TDDRC_ALPHA_UP_1 +164 0x5000 //RX_TDDRC_ALPHA_UP_2 +165 0x5000 //RX_TDDRC_ALPHA_UP_3 +166 0x2000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x65AD //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x5000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x01C8 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x000B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x5000 //RX_TDDRC_ALPHA_UP_1 +164 0x5000 //RX_TDDRC_ALPHA_UP_2 +165 0x5000 //RX_TDDRC_ALPHA_UP_3 +166 0x2000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x65AD //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x5000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x01C8 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0013 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x5000 //RX_TDDRC_ALPHA_UP_1 +164 0x5000 //RX_TDDRC_ALPHA_UP_2 +165 0x5000 //RX_TDDRC_ALPHA_UP_3 +166 0x2000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x65AD //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x5000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x01C8 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0020 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x5000 //RX_TDDRC_ALPHA_UP_1 +164 0x5000 //RX_TDDRC_ALPHA_UP_2 +165 0x5000 //RX_TDDRC_ALPHA_UP_3 +166 0x2000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x65AD //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x5000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x01C8 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0036 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x5000 //RX_TDDRC_ALPHA_UP_1 +164 0x5000 //RX_TDDRC_ALPHA_UP_2 +165 0x5000 //RX_TDDRC_ALPHA_UP_3 +166 0x2000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x65AD //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x5000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x01C8 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x005B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x5000 //RX_TDDRC_ALPHA_UP_1 +164 0x5000 //RX_TDDRC_ALPHA_UP_2 +165 0x5000 //RX_TDDRC_ALPHA_UP_3 +166 0x2000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x65AD //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x5000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x01C8 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0099 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x5000 //RX_TDDRC_ALPHA_UP_1 +164 0x5000 //RX_TDDRC_ALPHA_UP_2 +165 0x5000 //RX_TDDRC_ALPHA_UP_3 +166 0x2000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x65AD //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x5000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x01C8 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME HEADSET-GOOGLE_CONDOR_HEADPHONE-VOICE_GENERIC-FB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0001 //TX_OPERATION_MODE_0 +1 0x0001 //TX_OPERATION_MODE_1 +2 0x0033 //TX_PATCH_REG +3 0x6B7C //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0002 //TX_NUM_MIC +6 0x0004 //TX_SAMPLINGFREQ_SIG +7 0x0004 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009D //TX_DIST2REF1 +22 0x0010 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x1000 //TX_PGA_0 +28 0x1000 //TX_PGA_1 +29 0x1000 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0001 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0002 //TX_MIC_DATA_SRC0 +42 0x0000 //TX_MIC_DATA_SRC1 +43 0x0001 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3B33 //TX_DIST2REF_11 +73 0x0A70 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0800 //TX_MIC_REFBLK_VOLUME +108 0x0CAE //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0015 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7E56 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x1800 //TX_THR_PITCH_DET_0 +131 0x1000 //TX_THR_PITCH_DET_1 +132 0x0800 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x0028 //TX_TAIL_LENGTH +147 0x0300 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x7A00 //TX_EAD_THR +151 0x1000 //TX_THR_RE_EST +152 0x0800 //TX_MIN_EQ_RE_EST_0 +153 0x2000 //TX_MIN_EQ_RE_EST_1 +154 0x2000 //TX_MIN_EQ_RE_EST_2 +155 0x4000 //TX_MIN_EQ_RE_EST_3 +156 0x4000 //TX_MIN_EQ_RE_EST_4 +157 0x7FFF //TX_MIN_EQ_RE_EST_5 +158 0x7FFF //TX_MIN_EQ_RE_EST_6 +159 0x7FFF //TX_MIN_EQ_RE_EST_7 +160 0x7FFF //TX_MIN_EQ_RE_EST_8 +161 0x7FFF //TX_MIN_EQ_RE_EST_9 +162 0x7FFF //TX_MIN_EQ_RE_EST_10 +163 0x7FFF //TX_MIN_EQ_RE_EST_11 +164 0x7FFF //TX_MIN_EQ_RE_EST_12 +165 0x0700 //TX_LAMBDA_RE_EST +166 0x0CCD //TX_LAMBDA_CB_NLE +167 0x2000 //TX_C_POST_FLT +168 0x7FFF //TX_GAIN_NP +169 0x0180 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x09C4 //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x7D00 //TX_DTD_THR1_0 +198 0x7FF0 //TX_DTD_THR1_1 +199 0x7FF0 //TX_DTD_THR1_2 +200 0x7FF0 //TX_DTD_THR1_3 +201 0x7FF0 //TX_DTD_THR1_4 +202 0x7FF0 //TX_DTD_THR1_5 +203 0x7FF0 //TX_DTD_THR1_6 +204 0x0CCD //TX_DTD_THR2_0 +205 0x0CCD //TX_DTD_THR2_1 +206 0x0CCD //TX_DTD_THR2_2 +207 0x0CCD //TX_DTD_THR2_3 +208 0x0CCD //TX_DTD_THR2_4 +209 0x0CCD //TX_DTD_THR2_5 +210 0x0CCD //TX_DTD_THR2_6 +211 0x7FFF //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x0DAC //TX_DT_CUT_K +214 0x0020 //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x7FFF //TX_DTD_MIC_BLK +221 0x023E //TX_ADPT_STRICT_L +222 0x023E //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1194 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x7FFF //TX_B_POST_FILT_ECHO_L +229 0x2000 //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x1000 //TX_B_LESSCUT_RTO_ECHO +232 0x0063 //TX_EPD_OFFSET_00 +233 0x0000 //TX_EPD_OFFST_01 +234 0x0A28 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x0000 //TX_DTD_THR1_7 +238 0x0000 //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xF700 //TX_THR_SN_EST_0 +243 0xFA00 //TX_THR_SN_EST_1 +244 0xFA00 //TX_THR_SN_EST_2 +245 0xFB00 //TX_THR_SN_EST_3 +246 0xFA00 //TX_THR_SN_EST_4 +247 0xFA00 //TX_THR_SN_EST_5 +248 0xF800 //TX_THR_SN_EST_6 +249 0xF800 //TX_THR_SN_EST_7 +250 0x0100 //TX_DELTA_THR_SN_EST_0 +251 0x0100 //TX_DELTA_THR_SN_EST_1 +252 0x0200 //TX_DELTA_THR_SN_EST_2 +253 0x0100 //TX_DELTA_THR_SN_EST_3 +254 0x0100 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0200 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x4000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x4000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x2000 //TX_B_POST_FLT_0 +280 0x1000 //TX_B_POST_FLT_1 +281 0x0010 //TX_NS_LVL_CTRL_0 +282 0x0014 //TX_NS_LVL_CTRL_1 +283 0x0018 //TX_NS_LVL_CTRL_2 +284 0x0016 //TX_NS_LVL_CTRL_3 +285 0x0014 //TX_NS_LVL_CTRL_4 +286 0x0011 //TX_NS_LVL_CTRL_5 +287 0x0014 //TX_NS_LVL_CTRL_6 +288 0x0011 //TX_NS_LVL_CTRL_7 +289 0x000F //TX_MIN_GAIN_S_0 +290 0x0010 //TX_MIN_GAIN_S_1 +291 0x0010 //TX_MIN_GAIN_S_2 +292 0x0010 //TX_MIN_GAIN_S_3 +293 0x0010 //TX_MIN_GAIN_S_4 +294 0x0010 //TX_MIN_GAIN_S_5 +295 0x0010 //TX_MIN_GAIN_S_6 +296 0x000F //TX_MIN_GAIN_S_7 +297 0x6000 //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x4000 //TX_SNRI_SUP_1 +302 0x4000 //TX_SNRI_SUP_2 +303 0x4000 //TX_SNRI_SUP_3 +304 0x4000 //TX_SNRI_SUP_4 +305 0x50C0 //TX_SNRI_SUP_5 +306 0x4000 //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x0018 //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x5000 //TX_A_POST_FILT_S_0 +315 0x4C00 //TX_A_POST_FILT_S_1 +316 0x4000 //TX_A_POST_FILT_S_2 +317 0x6000 //TX_A_POST_FILT_S_3 +318 0x4000 //TX_A_POST_FILT_S_4 +319 0x5000 //TX_A_POST_FILT_S_5 +320 0x6000 //TX_A_POST_FILT_S_6 +321 0x7000 //TX_A_POST_FILT_S_7 +322 0x2000 //TX_B_POST_FILT_0 +323 0x2000 //TX_B_POST_FILT_1 +324 0x2000 //TX_B_POST_FILT_2 +325 0x4000 //TX_B_POST_FILT_3 +326 0x4000 //TX_B_POST_FILT_4 +327 0x1000 //TX_B_POST_FILT_5 +328 0x1000 //TX_B_POST_FILT_6 +329 0x2000 //TX_B_POST_FILT_7 +330 0x4000 //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x6000 //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7C00 //TX_LAMBDA_PFILT +339 0x7C00 //TX_LAMBDA_PFILT_S_0 +340 0x7C00 //TX_LAMBDA_PFILT_S_1 +341 0x7A00 //TX_LAMBDA_PFILT_S_2 +342 0x7C00 //TX_LAMBDA_PFILT_S_3 +343 0x7C00 //TX_LAMBDA_PFILT_S_4 +344 0x7C00 //TX_LAMBDA_PFILT_S_5 +345 0x7C00 //TX_LAMBDA_PFILT_S_6 +346 0x7C00 //TX_LAMBDA_PFILT_S_7 +347 0x0180 //TX_K_PEPPER +348 0x0800 //TX_A_PEPPER +349 0x1EAA //TX_K_PEPPER_HF +350 0x0600 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x2000 //TX_DT_BINVAD_TH_0 +354 0x0800 //TX_DT_BINVAD_TH_1 +355 0x0200 //TX_DT_BINVAD_TH_2 +356 0x0200 //TX_DT_BINVAD_TH_3 +357 0x1F40 //TX_DT_BINVAD_ENDF +358 0x0100 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0064 //TX_NDETCT +367 0x04E8 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x07D0 //TX_NOISE_TH_1 +371 0x0DAC //TX_NOISE_TH_2 +372 0x4E20 //TX_NOISE_TH_3 +373 0x4E20 //TX_NOISE_TH_4 +374 0x59D8 //TX_NOISE_TH_5 +375 0x7FFF //TX_NOISE_TH_5_2 +376 0x0000 //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x2710 //TX_NOISE_TH_6 +379 0x02BC //TX_MINENOISE_TH +380 0xD508 //TX_MORENS_TFMASK_TH +381 0x0001 //TX_DRC_QUIET_FLOOR +382 0x3A98 //TX_RATIODTL_CUT_TH +383 0x1482 //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x0333 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x7FFF //TX_POST_MASK_SUP_HSNE +392 0x1388 //TX_TAIL_DET_TH +393 0x4000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0080 //TX_SUPHIGH_TH +396 0x0000 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x1800 //TX_C_POST_FLT_MASK +399 0x7FFF //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0004 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x04E7 //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x7FFF //TX_MIN_G_CTRL_SSNS +409 0x0000 //TX_METAL_RTO_THR +410 0x4848 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x4000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x0230 //TX_NOR_OFF_THR +498 0x0CCD //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x2000 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0x4650 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x7FFF //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0xC000 //TX_DEREVERB_LF_MU +515 0xC000 //TX_DEREVERB_HF_MU +516 0xCCCC //TX_DEREVERB_DELAY +517 0xD999 //TX_DEREVERB_COEF_LEN +518 0x1F40 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x7000 //TX_GSC_RTOH_TH +523 0x0064 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0020 //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x484C //TX_FDEQ_GAIN_3 +571 0x4C4C //TX_FDEQ_GAIN_4 +572 0x544C //TX_FDEQ_GAIN_5 +573 0x5454 //TX_FDEQ_GAIN_6 +574 0x5454 //TX_FDEQ_GAIN_7 +575 0x585A //TX_FDEQ_GAIN_8 +576 0x5C5C //TX_FDEQ_GAIN_9 +577 0x6068 //TX_FDEQ_GAIN_10 +578 0x8894 //TX_FDEQ_GAIN_11 +579 0x94B4 //TX_FDEQ_GAIN_12 +580 0xB4C7 //TX_FDEQ_GAIN_13 +581 0xC7C6 //TX_FDEQ_GAIN_14 +582 0xC6C6 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0304 //TX_FDEQ_BIN_2 +594 0x0405 //TX_FDEQ_BIN_3 +595 0x0607 //TX_FDEQ_BIN_4 +596 0x0809 //TX_FDEQ_BIN_5 +597 0x0A0B //TX_FDEQ_BIN_6 +598 0x0C0D //TX_FDEQ_BIN_7 +599 0x0E0F //TX_FDEQ_BIN_8 +600 0x1011 //TX_FDEQ_BIN_9 +601 0x1214 //TX_FDEQ_BIN_10 +602 0x1618 //TX_FDEQ_BIN_11 +603 0x1C1C //TX_FDEQ_BIN_12 +604 0x2020 //TX_FDEQ_BIN_13 +605 0x2020 //TX_FDEQ_BIN_14 +606 0x2011 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0030 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4849 //TX_PREEQ_GAIN_MIC0_6 +624 0x4A4B //TX_PREEQ_GAIN_MIC0_7 +625 0x4C4B //TX_PREEQ_GAIN_MIC0_8 +626 0x4A48 //TX_PREEQ_GAIN_MIC0_9 +627 0x4B4C //TX_PREEQ_GAIN_MIC0_10 +628 0x4C4B //TX_PREEQ_GAIN_MIC0_11 +629 0x4838 //TX_PREEQ_GAIN_MIC0_12 +630 0x3858 //TX_PREEQ_GAIN_MIC0_13 +631 0x7060 //TX_PREEQ_GAIN_MIC0_14 +632 0x9870 //TX_PREEQ_GAIN_MIC0_15 +633 0x5848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0202 //TX_PREEQ_BIN_MIC0_0 +642 0x0203 //TX_PREEQ_BIN_MIC0_1 +643 0x0303 //TX_PREEQ_BIN_MIC0_2 +644 0x0304 //TX_PREEQ_BIN_MIC0_3 +645 0x0405 //TX_PREEQ_BIN_MIC0_4 +646 0x0506 //TX_PREEQ_BIN_MIC0_5 +647 0x0808 //TX_PREEQ_BIN_MIC0_6 +648 0x0809 //TX_PREEQ_BIN_MIC0_7 +649 0x0A0A //TX_PREEQ_BIN_MIC0_8 +650 0x0C10 //TX_PREEQ_BIN_MIC0_9 +651 0x1013 //TX_PREEQ_BIN_MIC0_10 +652 0x1414 //TX_PREEQ_BIN_MIC0_11 +653 0x261E //TX_PREEQ_BIN_MIC0_12 +654 0x1E14 //TX_PREEQ_BIN_MIC0_13 +655 0x1414 //TX_PREEQ_BIN_MIC0_14 +656 0x2814 //TX_PREEQ_BIN_MIC0_15 +657 0x4000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0030 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4645 //TX_PREEQ_GAIN_MIC1_6 +673 0x4442 //TX_PREEQ_GAIN_MIC1_7 +674 0x4140 //TX_PREEQ_GAIN_MIC1_8 +675 0x3E3D //TX_PREEQ_GAIN_MIC1_9 +676 0x3C3C //TX_PREEQ_GAIN_MIC1_10 +677 0x3C3C //TX_PREEQ_GAIN_MIC1_11 +678 0x3938 //TX_PREEQ_GAIN_MIC1_12 +679 0x3A3C //TX_PREEQ_GAIN_MIC1_13 +680 0x3C3E //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0202 //TX_PREEQ_BIN_MIC1_0 +691 0x0203 //TX_PREEQ_BIN_MIC1_1 +692 0x0303 //TX_PREEQ_BIN_MIC1_2 +693 0x0304 //TX_PREEQ_BIN_MIC1_3 +694 0x0405 //TX_PREEQ_BIN_MIC1_4 +695 0x0506 //TX_PREEQ_BIN_MIC1_5 +696 0x0808 //TX_PREEQ_BIN_MIC1_6 +697 0x0809 //TX_PREEQ_BIN_MIC1_7 +698 0x0A0A //TX_PREEQ_BIN_MIC1_8 +699 0x0C10 //TX_PREEQ_BIN_MIC1_9 +700 0x1013 //TX_PREEQ_BIN_MIC1_10 +701 0x1414 //TX_PREEQ_BIN_MIC1_11 +702 0x261E //TX_PREEQ_BIN_MIC1_12 +703 0x1E14 //TX_PREEQ_BIN_MIC1_13 +704 0x1414 //TX_PREEQ_BIN_MIC1_14 +705 0x2814 //TX_PREEQ_BIN_MIC1_15 +706 0x4000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0E10 //TX_PREEQ_BIN_MIC2_0 +740 0x1010 //TX_PREEQ_BIN_MIC2_1 +741 0x1010 //TX_PREEQ_BIN_MIC2_2 +742 0x1010 //TX_PREEQ_BIN_MIC2_3 +743 0x1010 //TX_PREEQ_BIN_MIC2_4 +744 0x1010 //TX_PREEQ_BIN_MIC2_5 +745 0x1010 //TX_PREEQ_BIN_MIC2_6 +746 0x1010 //TX_PREEQ_BIN_MIC2_7 +747 0x1010 //TX_PREEQ_BIN_MIC2_8 +748 0x1010 //TX_PREEQ_BIN_MIC2_9 +749 0x1010 //TX_PREEQ_BIN_MIC2_10 +750 0x1010 //TX_PREEQ_BIN_MIC2_11 +751 0x1010 //TX_PREEQ_BIN_MIC2_12 +752 0x1010 //TX_PREEQ_BIN_MIC2_13 +753 0x1010 //TX_PREEQ_BIN_MIC2_14 +754 0x0200 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x2000 //TX_NND_WEIGHT +765 0x0060 //TX_MIC_CALIBRATION_0 +766 0x0060 //TX_MIC_CALIBRATION_1 +767 0x0070 //TX_MIC_CALIBRATION_2 +768 0x0070 //TX_MIC_CALIBRATION_3 +769 0x0050 //TX_MIC_PWR_BIAS_0 +770 0x0040 //TX_MIC_PWR_BIAS_1 +771 0x0040 //TX_MIC_PWR_BIAS_2 +772 0x0040 //TX_MIC_PWR_BIAS_3 +773 0x0009 //TX_GAIN_LIMIT_0 +774 0x000F //TX_GAIN_LIMIT_1 +775 0x000F //TX_GAIN_LIMIT_2 +776 0x000F //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x0C00 //TX_TDDRC_ALPHA_UP_01 +784 0x0C00 //TX_TDDRC_ALPHA_UP_02 +785 0x0C00 //TX_TDDRC_ALPHA_UP_03 +786 0x0C00 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x7214 //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0010 //TX_DEADMIC_SILENCE_TH +817 0x0600 //TX_MIC_DEGRADE_TH +818 0x0078 //TX_DEADMIC_CNT +819 0x0078 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x4848 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0096 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0002 //TX_FILTINDX +854 0x0004 //TX_TDDRC_THRD_0 +855 0x0016 //TX_TDDRC_THRD_1 +856 0x1800 //TX_TDDRC_THRD_2 +857 0x1800 //TX_TDDRC_THRD_3 +858 0x7FFF //TX_TDDRC_SLANT_0 +859 0x7FFF //TX_TDDRC_SLANT_1 +860 0x0C00 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x0B39 //TX_TDDRC_DRC_GAIN +867 0x7FFF //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x0028 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x7000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x2339 //TX_SENDFUNC_REG_MICMUTE +898 0x0021 //TX_SENDFUNC_REG_MICMUTE1 +899 0x02BC //TX_MICMUTE_RATIO_THR +900 0x0140 //TX_MICMUTE_AMP_THR +901 0x0004 //TX_MICMUTE_HPF_IND +902 0x00C0 //TX_MICMUTE_LOG_EYR_TH +903 0x0008 //TX_MICMUTE_CVG_TIME +904 0x0008 //TX_MICMUTE_RELEASE_TIME +905 0x01FE //TX_MIC_VOLUME_MIC0MUTE +906 0x0020 //TX_MICMUTE_EPD_OFFSET_0 +907 0x001E //TX_MICMUTE_FRQ_AEC_L +908 0x7999 //TX_MICMUTE_EAD_THR +909 0x7FFF //TX_MICMUTE_LAMBDA_CB_NLE +910 0x7FFF //TX_MICMUTE_LAMBDA_RE_EST +911 0x4000 //TX_DTD_THR1_MICMUTE_0 +912 0x7000 //TX_DTD_THR1_MICMUTE_1 +913 0x7FFF //TX_DTD_THR1_MICMUTE_2 +914 0x7FFF //TX_DTD_THR1_MICMUTE_3 +915 0x6CCC //TX_DTD_THR2_MICMUTE_0 +916 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x1000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x4000 //TX_MICMUTE_C_POST_FLT +922 0x03E8 //TX_MICMUTE_DT_CUT_K +923 0x0001 //TX_MICMUTE_DT_CUT_THR +924 0x03E8 //TX_MICMUTE_DT_CUT_K2 +925 0x0001 //TX_MICMUTE_DT_CUT_THR2 +926 0x0064 //TX_MICMUTE_DT2_HOLD_N +927 0x1000 //TX_MICMUTE_RATIODTH_THCUT +928 0x1000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x7FFF //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0400 //TX_MICMUTE_C_POST_FLT_MASK +931 0x7999 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0258 //TX_MICMUTE_DT_CUT_K1 +933 0x0800 //TX_MICMUTE_N2_SN_EST +934 0xFC00 //TX_MICMUTE_THR_SN_EST_0 +935 0x001C //TX_MICMUTE_MIN_G_CTRL_0 +936 0x6000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x7000 //TX_MICMUTE_B_POST_FILT_0 +938 0x2710 //TX_MIC1RUB_AMP_THR +939 0x0010 //TX_MIC1MUTE_RATIO_THR +940 0x0450 //TX_MIC1MUTE_AMP_THR +941 0x0008 //TX_MIC1MUTE_CVG_TIME +942 0x0008 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x202C //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0004 //RX_SAMPLINGFREQ_SIG +3 0x0004 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7B02 //RX_A_HP +12 0x4000 //RX_B_PE +13 0x7800 //RX_THR_PITCH_DET_0 +14 0x7000 //RX_THR_PITCH_DET_1 +15 0x6000 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0500 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x000A //RX_NS_LVL_CTRL +23 0xF600 //RX_THR_SN_EST +24 0x7000 //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0002 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1200 //RX_TDDRC_THRD_2 +115 0x1900 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0240 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x2000 //RX_MIN_G_FP +128 0x0080 //RX_MAX_G_FP +129 0x000B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1200 //RX_TDDRC_THRD_2 +115 0x1900 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0240 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x000B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1200 //RX_TDDRC_THRD_2 +115 0x1900 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0240 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0013 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1200 //RX_TDDRC_THRD_2 +115 0x1900 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0240 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0020 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1200 //RX_TDDRC_THRD_2 +115 0x1900 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0240 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0036 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1200 //RX_TDDRC_THRD_2 +115 0x1900 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0240 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x005B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1200 //RX_TDDRC_THRD_2 +115 0x1900 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0240 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0099 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1200 //RX_TDDRC_THRD_2 +115 0x1900 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0240 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x202C //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0004 //RX_SAMPLINGFREQ_SIG +160 0x0004 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7B02 //RX_A_HP +169 0x4000 //RX_B_PE +170 0x7800 //RX_THR_PITCH_DET_0 +171 0x7000 //RX_THR_PITCH_DET_1 +172 0x6000 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0500 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x000A //RX_NS_LVL_CTRL +180 0xF600 //RX_THR_SN_EST +181 0x7000 //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0002 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1200 //RX_TDDRC_THRD_2 +272 0x1900 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0240 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x2000 //RX_MIN_G_FP +285 0x0080 //RX_MAX_G_FP +286 0x000B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1200 //RX_TDDRC_THRD_2 +272 0x1900 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0240 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x000B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1200 //RX_TDDRC_THRD_2 +272 0x1900 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0240 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0013 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1200 //RX_TDDRC_THRD_2 +272 0x1900 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0240 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0020 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1200 //RX_TDDRC_THRD_2 +272 0x1900 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0240 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0036 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1200 //RX_TDDRC_THRD_2 +272 0x1900 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0240 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x005B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1200 //RX_TDDRC_THRD_2 +272 0x1900 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0240 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0099 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1200 //RX_TDDRC_THRD_2 +272 0x1900 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0240 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME HEADSET-GOOGLE_CONDOR_CERTIFICATION1-VOICE_GENERIC-NB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0009 //TX_OPERATION_MODE_0 +1 0x0008 //TX_OPERATION_MODE_1 +2 0x0033 //TX_PATCH_REG +3 0x2B68 //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0001 //TX_NUM_MIC +6 0x0000 //TX_SAMPLINGFREQ_SIG +7 0x0000 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009B //TX_DIST2REF1 +22 0x0000 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0B80 //TX_PGA_0 +28 0x0800 //TX_PGA_1 +29 0x0000 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0000 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0001 //TX_MIC_DATA_SRC1 +43 0x0002 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3E00 //TX_DIST2REF_11 +73 0x0000 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0200 //TX_MIC_REFBLK_VOLUME +108 0x0800 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0000 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7646 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x7CCC //TX_THR_PITCH_DET_0 +131 0x7000 //TX_THR_PITCH_DET_1 +132 0x6333 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x001E //TX_TAIL_LENGTH +147 0x0010 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x7000 //TX_EAD_THR +151 0x1000 //TX_THR_RE_EST +152 0x1000 //TX_MIN_EQ_RE_EST_0 +153 0x0800 //TX_MIN_EQ_RE_EST_1 +154 0x0800 //TX_MIN_EQ_RE_EST_2 +155 0x0800 //TX_MIN_EQ_RE_EST_3 +156 0x0800 //TX_MIN_EQ_RE_EST_4 +157 0x0800 //TX_MIN_EQ_RE_EST_5 +158 0x0800 //TX_MIN_EQ_RE_EST_6 +159 0x0800 //TX_MIN_EQ_RE_EST_7 +160 0x0800 //TX_MIN_EQ_RE_EST_8 +161 0x0800 //TX_MIN_EQ_RE_EST_9 +162 0x0800 //TX_MIN_EQ_RE_EST_10 +163 0x0800 //TX_MIN_EQ_RE_EST_11 +164 0x0800 //TX_MIN_EQ_RE_EST_12 +165 0x4000 //TX_LAMBDA_RE_EST +166 0x2000 //TX_LAMBDA_CB_NLE +167 0x2000 //TX_C_POST_FLT +168 0x2000 //TX_GAIN_NP +169 0x00C8 //TX_SE_HOLD_N +170 0x0064 //TX_DT_HOLD_N +171 0x03E8 //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x5000 //TX_DTD_THR1_0 +198 0x7000 //TX_DTD_THR1_1 +199 0x7F00 //TX_DTD_THR1_2 +200 0x7FFF //TX_DTD_THR1_3 +201 0x7FFF //TX_DTD_THR1_4 +202 0x7FFF //TX_DTD_THR1_5 +203 0x7FFF //TX_DTD_THR1_6 +204 0x2000 //TX_DTD_THR2_0 +205 0x2000 //TX_DTD_THR2_1 +206 0x2000 //TX_DTD_THR2_2 +207 0x2000 //TX_DTD_THR2_3 +208 0x2000 //TX_DTD_THR2_4 +209 0x2000 //TX_DTD_THR2_5 +210 0x2000 //TX_DTD_THR2_6 +211 0x4100 //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x03E8 //TX_DT_CUT_K +214 0x1000 //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x0400 //TX_ADPT_STRICT_L +222 0x0200 //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x0800 //TX_B_POST_FILT_ECHO_L +229 0x7FFF //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x1000 //TX_B_LESSCUT_RTO_ECHO +232 0x0010 //TX_EPD_OFFSET_00 +233 0x0010 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x7FFF //TX_DTD_THR1_7 +238 0x7FFF //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xFA00 //TX_THR_SN_EST_0 +243 0xFA00 //TX_THR_SN_EST_1 +244 0xFA00 //TX_THR_SN_EST_2 +245 0xFA00 //TX_THR_SN_EST_3 +246 0xFA00 //TX_THR_SN_EST_4 +247 0xFA00 //TX_THR_SN_EST_5 +248 0xFA00 //TX_THR_SN_EST_6 +249 0xFA00 //TX_THR_SN_EST_7 +250 0x0000 //TX_DELTA_THR_SN_EST_0 +251 0x0000 //TX_DELTA_THR_SN_EST_1 +252 0x0000 //TX_DELTA_THR_SN_EST_2 +253 0x0000 //TX_DELTA_THR_SN_EST_3 +254 0x0000 //TX_DELTA_THR_SN_EST_4 +255 0x0000 //TX_DELTA_THR_SN_EST_5 +256 0x0000 //TX_DELTA_THR_SN_EST_6 +257 0x0000 //TX_DELTA_THR_SN_EST_7 +258 0x4000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x4000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x0400 //TX_B_POST_FLT_0 +280 0x0400 //TX_B_POST_FLT_1 +281 0x0010 //TX_NS_LVL_CTRL_0 +282 0x0010 //TX_NS_LVL_CTRL_1 +283 0x0010 //TX_NS_LVL_CTRL_2 +284 0x0010 //TX_NS_LVL_CTRL_3 +285 0x0010 //TX_NS_LVL_CTRL_4 +286 0x0010 //TX_NS_LVL_CTRL_5 +287 0x0010 //TX_NS_LVL_CTRL_6 +288 0x0010 //TX_NS_LVL_CTRL_7 +289 0x000D //TX_MIN_GAIN_S_0 +290 0x000D //TX_MIN_GAIN_S_1 +291 0x000D //TX_MIN_GAIN_S_2 +292 0x000D //TX_MIN_GAIN_S_3 +293 0x000D //TX_MIN_GAIN_S_4 +294 0x000D //TX_MIN_GAIN_S_5 +295 0x000D //TX_MIN_GAIN_S_6 +296 0x000D //TX_MIN_GAIN_S_7 +297 0x7FFF //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x7FFF //TX_SNRI_SUP_1 +302 0x7FFF //TX_SNRI_SUP_2 +303 0x7FFF //TX_SNRI_SUP_3 +304 0x7FFF //TX_SNRI_SUP_4 +305 0x7FFF //TX_SNRI_SUP_5 +306 0x7FFF //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x0014 //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x4000 //TX_A_POST_FILT_S_0 +315 0x1000 //TX_A_POST_FILT_S_1 +316 0x4000 //TX_A_POST_FILT_S_2 +317 0x4000 //TX_A_POST_FILT_S_3 +318 0x4000 //TX_A_POST_FILT_S_4 +319 0x4000 //TX_A_POST_FILT_S_5 +320 0x4000 //TX_A_POST_FILT_S_6 +321 0x4000 //TX_A_POST_FILT_S_7 +322 0x0400 //TX_B_POST_FILT_0 +323 0x2000 //TX_B_POST_FILT_1 +324 0x2000 //TX_B_POST_FILT_2 +325 0x2000 //TX_B_POST_FILT_3 +326 0x2000 //TX_B_POST_FILT_4 +327 0x2000 //TX_B_POST_FILT_5 +328 0x0400 //TX_B_POST_FILT_6 +329 0x2000 //TX_B_POST_FILT_7 +330 0x7FFF //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x7FFF //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7E14 //TX_LAMBDA_PFILT +339 0x7C29 //TX_LAMBDA_PFILT_S_0 +340 0x7C29 //TX_LAMBDA_PFILT_S_1 +341 0x7C29 //TX_LAMBDA_PFILT_S_2 +342 0x7C29 //TX_LAMBDA_PFILT_S_3 +343 0x7C29 //TX_LAMBDA_PFILT_S_4 +344 0x7C29 //TX_LAMBDA_PFILT_S_5 +345 0x7C29 //TX_LAMBDA_PFILT_S_6 +346 0x7C29 //TX_LAMBDA_PFILT_S_7 +347 0x0200 //TX_K_PEPPER +348 0x0800 //TX_A_PEPPER +349 0x0FA0 //TX_K_PEPPER_HF +350 0x0400 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x4000 //TX_HMNC_BST_THR +353 0x0800 //TX_DT_BINVAD_TH_0 +354 0x0800 //TX_DT_BINVAD_TH_1 +355 0x0800 //TX_DT_BINVAD_TH_2 +356 0x0800 //TX_DT_BINVAD_TH_3 +357 0x1D4C //TX_DT_BINVAD_ENDF +358 0x0000 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0190 //TX_NDETCT +367 0x003B //TX_NOISE_TH_0 +368 0x1B58 //TX_NOISE_TH_0_2 +369 0x2134 //TX_NOISE_TH_0_3 +370 0x02BC //TX_NOISE_TH_1 +371 0x1F40 //TX_NOISE_TH_2 +372 0x4650 //TX_NOISE_TH_3 +373 0x7148 //TX_NOISE_TH_4 +374 0x044C //TX_NOISE_TH_5 +375 0x7FFF //TX_NOISE_TH_5_2 +376 0x0000 //TX_NOISE_TH_5_3 +377 0x0000 //TX_NOISE_TH_5_4 +378 0x0032 //TX_NOISE_TH_6 +379 0x00C8 //TX_MINENOISE_TH +380 0xD508 //TX_MORENS_TFMASK_TH +381 0x0001 //TX_DRC_QUIET_FLOOR +382 0x3A98 //TX_RATIODTL_CUT_TH +383 0x0DAC //TX_DT_CUT_K1 +384 0x00A5 //TX_OUT_ENER_S_TH_CLEAN +385 0x00A5 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x00A5 //TX_OUT_ENER_S_TH_NOISY +387 0x0029 //TX_OUT_ENER_TH_NOISE +388 0x00CE //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x7FFF //TX_POST_MASK_SUP_HSNE +392 0x1388 //TX_TAIL_DET_TH +393 0x4000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0080 //TX_SUPHIGH_TH +396 0x0000 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x1800 //TX_C_POST_FLT_MASK +399 0x7FFF //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0002 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x0032 //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x7FFF //TX_MIN_G_CTRL_SSNS +409 0x0000 //TX_METAL_RTO_THR +410 0x4848 //TX_NS_FP_K_METAL +411 0x7FFF //TX_NOISEDET_BOOST_TH +412 0x0000 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0280 //TX_N_HOLD_HS +416 0x006E //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0333 //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2400 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0640 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x2000 //TX_WTA_EN_RTO_TH +429 0x1400 //TX_TOP_ENER_TH_F +430 0x0064 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x003C //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x0D9A //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x2A3D //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x0230 //TX_NOR_OFF_THR +498 0x0CCD //TX_MORE_ON_700HZ_THR +499 0x0000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0xD333 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x6000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0xC000 //TX_DEREVERB_LF_MU +515 0xC000 //TX_DEREVERB_HF_MU +516 0xCCCC //TX_DEREVERB_DELAY +517 0xD999 //TX_DEREVERB_COEF_LEN +518 0x1F40 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x7000 //TX_GSC_RTOH_TH +523 0x0064 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0014 //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4848 //TX_FDEQ_GAIN_5 +573 0x4848 //TX_FDEQ_GAIN_6 +574 0x4848 //TX_FDEQ_GAIN_7 +575 0x4848 //TX_FDEQ_GAIN_8 +576 0x4848 //TX_FDEQ_GAIN_9 +577 0x4848 //TX_FDEQ_GAIN_10 +578 0x4848 //TX_FDEQ_GAIN_11 +579 0x4848 //TX_FDEQ_GAIN_12 +580 0x4848 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0303 //TX_FDEQ_BIN_2 +594 0x0304 //TX_FDEQ_BIN_3 +595 0x0405 //TX_FDEQ_BIN_4 +596 0x0506 //TX_FDEQ_BIN_5 +597 0x0708 //TX_FDEQ_BIN_6 +598 0x090A //TX_FDEQ_BIN_7 +599 0x0B0C //TX_FDEQ_BIN_8 +600 0x0D08 //TX_FDEQ_BIN_9 +601 0x0000 //TX_FDEQ_BIN_10 +602 0x0000 //TX_FDEQ_BIN_11 +603 0x0000 //TX_FDEQ_BIN_12 +604 0x0000 //TX_FDEQ_BIN_13 +605 0x0000 //TX_FDEQ_BIN_14 +606 0x0000 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0010 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4848 //TX_PREEQ_GAIN_MIC0_8 +626 0x4848 //TX_PREEQ_GAIN_MIC0_9 +627 0x4848 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0608 //TX_PREEQ_BIN_MIC0_0 +642 0x0808 //TX_PREEQ_BIN_MIC0_1 +643 0x0808 //TX_PREEQ_BIN_MIC0_2 +644 0x0808 //TX_PREEQ_BIN_MIC0_3 +645 0x0808 //TX_PREEQ_BIN_MIC0_4 +646 0x0808 //TX_PREEQ_BIN_MIC0_5 +647 0x0808 //TX_PREEQ_BIN_MIC0_6 +648 0x0802 //TX_PREEQ_BIN_MIC0_7 +649 0x0000 //TX_PREEQ_BIN_MIC0_8 +650 0x0000 //TX_PREEQ_BIN_MIC0_9 +651 0x0000 //TX_PREEQ_BIN_MIC0_10 +652 0x0000 //TX_PREEQ_BIN_MIC0_11 +653 0x0000 //TX_PREEQ_BIN_MIC0_12 +654 0x0000 //TX_PREEQ_BIN_MIC0_13 +655 0x0000 //TX_PREEQ_BIN_MIC0_14 +656 0x0000 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0010 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0608 //TX_PREEQ_BIN_MIC1_0 +691 0x0808 //TX_PREEQ_BIN_MIC1_1 +692 0x0808 //TX_PREEQ_BIN_MIC1_2 +693 0x0808 //TX_PREEQ_BIN_MIC1_3 +694 0x0808 //TX_PREEQ_BIN_MIC1_4 +695 0x0808 //TX_PREEQ_BIN_MIC1_5 +696 0x0808 //TX_PREEQ_BIN_MIC1_6 +697 0x0802 //TX_PREEQ_BIN_MIC1_7 +698 0x0000 //TX_PREEQ_BIN_MIC1_8 +699 0x0000 //TX_PREEQ_BIN_MIC1_9 +700 0x0000 //TX_PREEQ_BIN_MIC1_10 +701 0x0000 //TX_PREEQ_BIN_MIC1_11 +702 0x0000 //TX_PREEQ_BIN_MIC1_12 +703 0x0000 //TX_PREEQ_BIN_MIC1_13 +704 0x0000 //TX_PREEQ_BIN_MIC1_14 +705 0x0000 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0010 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0608 //TX_PREEQ_BIN_MIC2_0 +740 0x0808 //TX_PREEQ_BIN_MIC2_1 +741 0x0808 //TX_PREEQ_BIN_MIC2_2 +742 0x0808 //TX_PREEQ_BIN_MIC2_3 +743 0x0808 //TX_PREEQ_BIN_MIC2_4 +744 0x0808 //TX_PREEQ_BIN_MIC2_5 +745 0x0808 //TX_PREEQ_BIN_MIC2_6 +746 0x0802 //TX_PREEQ_BIN_MIC2_7 +747 0x0000 //TX_PREEQ_BIN_MIC2_8 +748 0x0000 //TX_PREEQ_BIN_MIC2_9 +749 0x0000 //TX_PREEQ_BIN_MIC2_10 +750 0x0000 //TX_PREEQ_BIN_MIC2_11 +751 0x0000 //TX_PREEQ_BIN_MIC2_12 +752 0x0000 //TX_PREEQ_BIN_MIC2_13 +753 0x0000 //TX_PREEQ_BIN_MIC2_14 +754 0x0000 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x0800 //TX_NND_WEIGHT +765 0x0065 //TX_MIC_CALIBRATION_0 +766 0x0065 //TX_MIC_CALIBRATION_1 +767 0x0065 //TX_MIC_CALIBRATION_2 +768 0x0065 //TX_MIC_CALIBRATION_3 +769 0x0044 //TX_MIC_PWR_BIAS_0 +770 0x0044 //TX_MIC_PWR_BIAS_1 +771 0x0044 //TX_MIC_PWR_BIAS_2 +772 0x0044 //TX_MIC_PWR_BIAS_3 +773 0x000B //TX_GAIN_LIMIT_0 +774 0x000B //TX_GAIN_LIMIT_1 +775 0x000B //TX_GAIN_LIMIT_2 +776 0x000B //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x1000 //TX_TDDRC_ALPHA_UP_01 +784 0x1000 //TX_TDDRC_ALPHA_UP_02 +785 0x1000 //TX_TDDRC_ALPHA_UP_03 +786 0x1000 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x7FFF //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0000 //TX_DEADMIC_SILENCE_TH +817 0x0000 //TX_MIC_DEGRADE_TH +818 0x0000 //TX_DEADMIC_CNT +819 0x0000 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x4848 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0000 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0001 //TX_FILTINDX +854 0x0000 //TX_TDDRC_THRD_0 +855 0x0000 //TX_TDDRC_THRD_1 +856 0x2000 //TX_TDDRC_THRD_2 +857 0x2000 //TX_TDDRC_THRD_3 +858 0x3000 //TX_TDDRC_SLANT_0 +859 0x6E00 //TX_TDDRC_SLANT_1 +860 0x1000 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x05A0 //TX_TDDRC_DRC_GAIN +867 0x7FFF //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0xF800 //TX_TFMASKLTH_DOA +875 0x0CCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x00C8 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x4000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x2339 //TX_SENDFUNC_REG_MICMUTE +898 0x0021 //TX_SENDFUNC_REG_MICMUTE1 +899 0x02BC //TX_MICMUTE_RATIO_THR +900 0x0140 //TX_MICMUTE_AMP_THR +901 0x0004 //TX_MICMUTE_HPF_IND +902 0x00C0 //TX_MICMUTE_LOG_EYR_TH +903 0x0008 //TX_MICMUTE_CVG_TIME +904 0x0008 //TX_MICMUTE_RELEASE_TIME +905 0x01FE //TX_MIC_VOLUME_MIC0MUTE +906 0x0020 //TX_MICMUTE_EPD_OFFSET_0 +907 0x001E //TX_MICMUTE_FRQ_AEC_L +908 0x7999 //TX_MICMUTE_EAD_THR +909 0x7FFF //TX_MICMUTE_LAMBDA_CB_NLE +910 0x7FFF //TX_MICMUTE_LAMBDA_RE_EST +911 0x4000 //TX_DTD_THR1_MICMUTE_0 +912 0x7000 //TX_DTD_THR1_MICMUTE_1 +913 0x7FFF //TX_DTD_THR1_MICMUTE_2 +914 0x7FFF //TX_DTD_THR1_MICMUTE_3 +915 0x6CCC //TX_DTD_THR2_MICMUTE_0 +916 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x1000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x4000 //TX_MICMUTE_C_POST_FLT +922 0x03E8 //TX_MICMUTE_DT_CUT_K +923 0x0001 //TX_MICMUTE_DT_CUT_THR +924 0x03E8 //TX_MICMUTE_DT_CUT_K2 +925 0x0001 //TX_MICMUTE_DT_CUT_THR2 +926 0x0064 //TX_MICMUTE_DT2_HOLD_N +927 0x1000 //TX_MICMUTE_RATIODTH_THCUT +928 0x1000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x7FFF //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0400 //TX_MICMUTE_C_POST_FLT_MASK +931 0x7999 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0258 //TX_MICMUTE_DT_CUT_K1 +933 0x0800 //TX_MICMUTE_N2_SN_EST +934 0xFC00 //TX_MICMUTE_THR_SN_EST_0 +935 0x001C //TX_MICMUTE_MIN_G_CTRL_0 +936 0x6000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x7000 //TX_MICMUTE_B_POST_FILT_0 +938 0x2710 //TX_MIC1RUB_AMP_THR +939 0x0010 //TX_MIC1MUTE_RATIO_THR +940 0x0450 //TX_MIC1MUTE_AMP_THR +941 0x0008 //TX_MIC1MUTE_CVG_TIME +942 0x0008 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x2024 //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0000 //RX_SAMPLINGFREQ_SIG +3 0x0000 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7FFF //RX_A_HP +12 0x0000 //RX_B_PE +13 0x3800 //RX_THR_PITCH_DET_0 +14 0x3000 //RX_THR_PITCH_DET_1 +15 0x2800 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0600 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x0010 //RX_NS_LVL_CTRL +23 0xF800 //RX_THR_SN_EST +24 0x7CCD //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0002 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2030 //RX_TDDRC_THRD_2 +115 0x2030 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0478 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x2000 //RX_MIN_G_FP +128 0x0080 //RX_MAX_G_FP +129 0x000C //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2030 //RX_TDDRC_THRD_2 +115 0x2030 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0478 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x000C //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2030 //RX_TDDRC_THRD_2 +115 0x2030 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0478 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0014 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2030 //RX_TDDRC_THRD_2 +115 0x2030 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0478 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0021 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2030 //RX_TDDRC_THRD_2 +115 0x2030 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0478 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0037 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2030 //RX_TDDRC_THRD_2 +115 0x2030 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0478 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x005B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2030 //RX_TDDRC_THRD_2 +115 0x2030 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0478 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0099 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2030 //RX_TDDRC_THRD_2 +115 0x2030 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0478 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x2024 //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0000 //RX_SAMPLINGFREQ_SIG +160 0x0000 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7FFF //RX_A_HP +169 0x0000 //RX_B_PE +170 0x3800 //RX_THR_PITCH_DET_0 +171 0x3000 //RX_THR_PITCH_DET_1 +172 0x2800 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0600 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x0010 //RX_NS_LVL_CTRL +180 0xF800 //RX_THR_SN_EST +181 0x7CCD //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0002 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2030 //RX_TDDRC_THRD_2 +272 0x2030 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0478 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x2000 //RX_MIN_G_FP +285 0x0080 //RX_MAX_G_FP +286 0x000C //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2030 //RX_TDDRC_THRD_2 +272 0x2030 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0478 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x000C //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2030 //RX_TDDRC_THRD_2 +272 0x2030 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0478 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0014 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2030 //RX_TDDRC_THRD_2 +272 0x2030 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0478 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0021 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2030 //RX_TDDRC_THRD_2 +272 0x2030 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0478 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0037 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2030 //RX_TDDRC_THRD_2 +272 0x2030 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0478 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x005B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2030 //RX_TDDRC_THRD_2 +272 0x2030 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0478 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0099 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2030 //RX_TDDRC_THRD_2 +272 0x2030 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0478 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME HEADSET-GOOGLE_CONDOR_CERTIFICATION1-VOICE_GENERIC-WB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0009 //TX_OPERATION_MODE_0 +1 0x0008 //TX_OPERATION_MODE_1 +2 0x0033 //TX_PATCH_REG +3 0x2B68 //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0001 //TX_NUM_MIC +6 0x0001 //TX_SAMPLINGFREQ_SIG +7 0x0001 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009B //TX_DIST2REF1 +22 0x0000 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0B80 //TX_PGA_0 +28 0x0800 //TX_PGA_1 +29 0x0800 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0000 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0001 //TX_MIC_DATA_SRC1 +43 0x0002 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3E00 //TX_DIST2REF_11 +73 0x0000 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0200 //TX_MIC_REFBLK_VOLUME +108 0x0800 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0000 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7D83 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x6800 //TX_THR_PITCH_DET_0 +131 0x6000 //TX_THR_PITCH_DET_1 +132 0x5800 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x001E //TX_TAIL_LENGTH +147 0x0080 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x7000 //TX_EAD_THR +151 0x0800 //TX_THR_RE_EST +152 0x0800 //TX_MIN_EQ_RE_EST_0 +153 0x0800 //TX_MIN_EQ_RE_EST_1 +154 0x0800 //TX_MIN_EQ_RE_EST_2 +155 0x0800 //TX_MIN_EQ_RE_EST_3 +156 0x0800 //TX_MIN_EQ_RE_EST_4 +157 0x0800 //TX_MIN_EQ_RE_EST_5 +158 0x0800 //TX_MIN_EQ_RE_EST_6 +159 0x0800 //TX_MIN_EQ_RE_EST_7 +160 0x0800 //TX_MIN_EQ_RE_EST_8 +161 0x0800 //TX_MIN_EQ_RE_EST_9 +162 0x0800 //TX_MIN_EQ_RE_EST_10 +163 0x0800 //TX_MIN_EQ_RE_EST_11 +164 0x0800 //TX_MIN_EQ_RE_EST_12 +165 0x4000 //TX_LAMBDA_RE_EST +166 0x2000 //TX_LAMBDA_CB_NLE +167 0x6000 //TX_C_POST_FLT +168 0x7000 //TX_GAIN_NP +169 0x00C8 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x03E8 //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x7800 //TX_DTD_THR1_0 +198 0x7000 //TX_DTD_THR1_1 +199 0x7FFF //TX_DTD_THR1_2 +200 0x7FFF //TX_DTD_THR1_3 +201 0x7FFF //TX_DTD_THR1_4 +202 0x7FFF //TX_DTD_THR1_5 +203 0x7FFF //TX_DTD_THR1_6 +204 0x7FFF //TX_DTD_THR2_0 +205 0x7FFF //TX_DTD_THR2_1 +206 0x7FFF //TX_DTD_THR2_2 +207 0x7FFF //TX_DTD_THR2_3 +208 0x7FFF //TX_DTD_THR2_4 +209 0x7FFF //TX_DTD_THR2_5 +210 0x7FFF //TX_DTD_THR2_6 +211 0x1000 //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x0BB8 //TX_DT_CUT_K +214 0x0CCD //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x0400 //TX_ADPT_STRICT_L +222 0x0200 //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x0800 //TX_B_POST_FILT_ECHO_L +229 0x7FFF //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x7FFF //TX_B_LESSCUT_RTO_ECHO +232 0x0019 //TX_EPD_OFFSET_00 +233 0x0019 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x7FFF //TX_DTD_THR1_7 +238 0x7FFF //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xFA00 //TX_THR_SN_EST_0 +243 0xF400 //TX_THR_SN_EST_1 +244 0xF600 //TX_THR_SN_EST_2 +245 0xF400 //TX_THR_SN_EST_3 +246 0xF400 //TX_THR_SN_EST_4 +247 0xF400 //TX_THR_SN_EST_5 +248 0xF400 //TX_THR_SN_EST_6 +249 0xF600 //TX_THR_SN_EST_7 +250 0x0000 //TX_DELTA_THR_SN_EST_0 +251 0x0200 //TX_DELTA_THR_SN_EST_1 +252 0x0200 //TX_DELTA_THR_SN_EST_2 +253 0x0200 //TX_DELTA_THR_SN_EST_3 +254 0x0200 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0000 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x6000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x6000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x1000 //TX_B_POST_FLT_0 +280 0x1000 //TX_B_POST_FLT_1 +281 0x000F //TX_NS_LVL_CTRL_0 +282 0x0011 //TX_NS_LVL_CTRL_1 +283 0x000F //TX_NS_LVL_CTRL_2 +284 0x000F //TX_NS_LVL_CTRL_3 +285 0x000F //TX_NS_LVL_CTRL_4 +286 0x000F //TX_NS_LVL_CTRL_5 +287 0x000F //TX_NS_LVL_CTRL_6 +288 0x0011 //TX_NS_LVL_CTRL_7 +289 0x000C //TX_MIN_GAIN_S_0 +290 0x000F //TX_MIN_GAIN_S_1 +291 0x000C //TX_MIN_GAIN_S_2 +292 0x000C //TX_MIN_GAIN_S_3 +293 0x000C //TX_MIN_GAIN_S_4 +294 0x000C //TX_MIN_GAIN_S_5 +295 0x000C //TX_MIN_GAIN_S_6 +296 0x000F //TX_MIN_GAIN_S_7 +297 0x7FFF //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x7FFF //TX_SNRI_SUP_1 +302 0x7FFF //TX_SNRI_SUP_2 +303 0x7FFF //TX_SNRI_SUP_3 +304 0x7FFF //TX_SNRI_SUP_4 +305 0x7FFF //TX_SNRI_SUP_5 +306 0x7FFF //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x000E //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x4000 //TX_A_POST_FILT_S_0 +315 0x5000 //TX_A_POST_FILT_S_1 +316 0x5000 //TX_A_POST_FILT_S_2 +317 0x5000 //TX_A_POST_FILT_S_3 +318 0x5000 //TX_A_POST_FILT_S_4 +319 0x5000 //TX_A_POST_FILT_S_5 +320 0x4000 //TX_A_POST_FILT_S_6 +321 0x5000 //TX_A_POST_FILT_S_7 +322 0x1000 //TX_B_POST_FILT_0 +323 0x1000 //TX_B_POST_FILT_1 +324 0x1000 //TX_B_POST_FILT_2 +325 0x1000 //TX_B_POST_FILT_3 +326 0x1000 //TX_B_POST_FILT_4 +327 0x1000 //TX_B_POST_FILT_5 +328 0x1000 //TX_B_POST_FILT_6 +329 0x1000 //TX_B_POST_FILT_7 +330 0x7FFF //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x7FFF //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7CCD //TX_LAMBDA_PFILT +339 0x7B00 //TX_LAMBDA_PFILT_S_0 +340 0x7B00 //TX_LAMBDA_PFILT_S_1 +341 0x7B00 //TX_LAMBDA_PFILT_S_2 +342 0x7B00 //TX_LAMBDA_PFILT_S_3 +343 0x7B00 //TX_LAMBDA_PFILT_S_4 +344 0x7B00 //TX_LAMBDA_PFILT_S_5 +345 0x7B00 //TX_LAMBDA_PFILT_S_6 +346 0x7B00 //TX_LAMBDA_PFILT_S_7 +347 0x0200 //TX_K_PEPPER +348 0x0800 //TX_A_PEPPER +349 0x1EAA //TX_K_PEPPER_HF +350 0x0800 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0800 //TX_DT_BINVAD_TH_0 +354 0x0800 //TX_DT_BINVAD_TH_1 +355 0x0800 //TX_DT_BINVAD_TH_2 +356 0x0800 //TX_DT_BINVAD_TH_3 +357 0x1D4C //TX_DT_BINVAD_ENDF +358 0x0000 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0190 //TX_NDETCT +367 0x0102 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x07D0 //TX_NOISE_TH_1 +371 0x00C8 //TX_NOISE_TH_2 +372 0x3A98 //TX_NOISE_TH_3 +373 0x0FA0 //TX_NOISE_TH_4 +374 0x157C //TX_NOISE_TH_5 +375 0x7FFF //TX_NOISE_TH_5_2 +376 0x7FFF //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x044C //TX_NOISE_TH_6 +379 0x00F8 //TX_MINENOISE_TH +380 0xD508 //TX_MORENS_TFMASK_TH +381 0x0001 //TX_DRC_QUIET_FLOOR +382 0x3A98 //TX_RATIODTL_CUT_TH +383 0x0DAC //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x0333 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x7FFF //TX_POST_MASK_SUP_HSNE +392 0x1388 //TX_TAIL_DET_TH +393 0x4000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0080 //TX_SUPHIGH_TH +396 0x0000 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x1800 //TX_C_POST_FLT_MASK +399 0x7FFF //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0002 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x00DC //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x7FFF //TX_MIN_G_CTRL_SSNS +409 0x0000 //TX_METAL_RTO_THR +410 0x0000 //TX_NS_FP_K_METAL +411 0x7FFF //TX_NOISEDET_BOOST_TH +412 0x0000 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x4000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x0230 //TX_NOR_OFF_THR +498 0x0CCD //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0xD333 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x6000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0xC000 //TX_DEREVERB_LF_MU +515 0xC000 //TX_DEREVERB_HF_MU +516 0xCCCC //TX_DEREVERB_DELAY +517 0xD999 //TX_DEREVERB_COEF_LEN +518 0x1F40 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x7000 //TX_GSC_RTOH_TH +523 0x0064 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x001C //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4848 //TX_FDEQ_GAIN_5 +573 0x4848 //TX_FDEQ_GAIN_6 +574 0x4848 //TX_FDEQ_GAIN_7 +575 0x4848 //TX_FDEQ_GAIN_8 +576 0x4848 //TX_FDEQ_GAIN_9 +577 0x4848 //TX_FDEQ_GAIN_10 +578 0x4848 //TX_FDEQ_GAIN_11 +579 0x4848 //TX_FDEQ_GAIN_12 +580 0x4848 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0303 //TX_FDEQ_BIN_2 +594 0x0304 //TX_FDEQ_BIN_3 +595 0x0405 //TX_FDEQ_BIN_4 +596 0x0506 //TX_FDEQ_BIN_5 +597 0x0708 //TX_FDEQ_BIN_6 +598 0x090A //TX_FDEQ_BIN_7 +599 0x0B0C //TX_FDEQ_BIN_8 +600 0x0D0E //TX_FDEQ_BIN_9 +601 0x0E0F //TX_FDEQ_BIN_10 +602 0x0F10 //TX_FDEQ_BIN_11 +603 0x1011 //TX_FDEQ_BIN_12 +604 0x1104 //TX_FDEQ_BIN_13 +605 0x0000 //TX_FDEQ_BIN_14 +606 0x0000 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4848 //TX_PREEQ_GAIN_MIC0_8 +626 0x4848 //TX_PREEQ_GAIN_MIC0_9 +627 0x4848 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0608 //TX_PREEQ_BIN_MIC0_0 +642 0x0808 //TX_PREEQ_BIN_MIC0_1 +643 0x0808 //TX_PREEQ_BIN_MIC0_2 +644 0x0808 //TX_PREEQ_BIN_MIC0_3 +645 0x0808 //TX_PREEQ_BIN_MIC0_4 +646 0x0808 //TX_PREEQ_BIN_MIC0_5 +647 0x0808 //TX_PREEQ_BIN_MIC0_6 +648 0x0808 //TX_PREEQ_BIN_MIC0_7 +649 0x0808 //TX_PREEQ_BIN_MIC0_8 +650 0x0808 //TX_PREEQ_BIN_MIC0_9 +651 0x0808 //TX_PREEQ_BIN_MIC0_10 +652 0x0808 //TX_PREEQ_BIN_MIC0_11 +653 0x0808 //TX_PREEQ_BIN_MIC0_12 +654 0x0808 //TX_PREEQ_BIN_MIC0_13 +655 0x0808 //TX_PREEQ_BIN_MIC0_14 +656 0x0200 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0608 //TX_PREEQ_BIN_MIC1_0 +691 0x0808 //TX_PREEQ_BIN_MIC1_1 +692 0x0808 //TX_PREEQ_BIN_MIC1_2 +693 0x0808 //TX_PREEQ_BIN_MIC1_3 +694 0x0808 //TX_PREEQ_BIN_MIC1_4 +695 0x0808 //TX_PREEQ_BIN_MIC1_5 +696 0x0808 //TX_PREEQ_BIN_MIC1_6 +697 0x0808 //TX_PREEQ_BIN_MIC1_7 +698 0x0808 //TX_PREEQ_BIN_MIC1_8 +699 0x0808 //TX_PREEQ_BIN_MIC1_9 +700 0x0808 //TX_PREEQ_BIN_MIC1_10 +701 0x0808 //TX_PREEQ_BIN_MIC1_11 +702 0x0808 //TX_PREEQ_BIN_MIC1_12 +703 0x0808 //TX_PREEQ_BIN_MIC1_13 +704 0x0808 //TX_PREEQ_BIN_MIC1_14 +705 0x0200 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0608 //TX_PREEQ_BIN_MIC2_0 +740 0x0808 //TX_PREEQ_BIN_MIC2_1 +741 0x0808 //TX_PREEQ_BIN_MIC2_2 +742 0x0808 //TX_PREEQ_BIN_MIC2_3 +743 0x0808 //TX_PREEQ_BIN_MIC2_4 +744 0x0808 //TX_PREEQ_BIN_MIC2_5 +745 0x0808 //TX_PREEQ_BIN_MIC2_6 +746 0x0808 //TX_PREEQ_BIN_MIC2_7 +747 0x0808 //TX_PREEQ_BIN_MIC2_8 +748 0x0808 //TX_PREEQ_BIN_MIC2_9 +749 0x0808 //TX_PREEQ_BIN_MIC2_10 +750 0x0808 //TX_PREEQ_BIN_MIC2_11 +751 0x0808 //TX_PREEQ_BIN_MIC2_12 +752 0x0808 //TX_PREEQ_BIN_MIC2_13 +753 0x0808 //TX_PREEQ_BIN_MIC2_14 +754 0x0200 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x0800 //TX_NND_WEIGHT +765 0x0062 //TX_MIC_CALIBRATION_0 +766 0x0062 //TX_MIC_CALIBRATION_1 +767 0x0062 //TX_MIC_CALIBRATION_2 +768 0x0062 //TX_MIC_CALIBRATION_3 +769 0x0046 //TX_MIC_PWR_BIAS_0 +770 0x0046 //TX_MIC_PWR_BIAS_1 +771 0x0046 //TX_MIC_PWR_BIAS_2 +772 0x0046 //TX_MIC_PWR_BIAS_3 +773 0x000C //TX_GAIN_LIMIT_0 +774 0x000C //TX_GAIN_LIMIT_1 +775 0x000C //TX_GAIN_LIMIT_2 +776 0x000C //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x1000 //TX_TDDRC_ALPHA_UP_01 +784 0x1000 //TX_TDDRC_ALPHA_UP_02 +785 0x1000 //TX_TDDRC_ALPHA_UP_03 +786 0x1000 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x7FFF //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0000 //TX_DEADMIC_SILENCE_TH +817 0x0000 //TX_MIC_DEGRADE_TH +818 0x0000 //TX_DEADMIC_CNT +819 0x0000 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x0000 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0000 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0001 //TX_FILTINDX +854 0x0000 //TX_TDDRC_THRD_0 +855 0x0000 //TX_TDDRC_THRD_1 +856 0x2000 //TX_TDDRC_THRD_2 +857 0x2000 //TX_TDDRC_THRD_3 +858 0x3000 //TX_TDDRC_SLANT_0 +859 0x6E00 //TX_TDDRC_SLANT_1 +860 0x1000 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x05A0 //TX_TDDRC_DRC_GAIN +867 0x7FFF //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x00C8 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x4000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x2339 //TX_SENDFUNC_REG_MICMUTE +898 0x0021 //TX_SENDFUNC_REG_MICMUTE1 +899 0x02BC //TX_MICMUTE_RATIO_THR +900 0x0140 //TX_MICMUTE_AMP_THR +901 0x0004 //TX_MICMUTE_HPF_IND +902 0x00C0 //TX_MICMUTE_LOG_EYR_TH +903 0x0008 //TX_MICMUTE_CVG_TIME +904 0x0008 //TX_MICMUTE_RELEASE_TIME +905 0x01FE //TX_MIC_VOLUME_MIC0MUTE +906 0x0020 //TX_MICMUTE_EPD_OFFSET_0 +907 0x001E //TX_MICMUTE_FRQ_AEC_L +908 0x7999 //TX_MICMUTE_EAD_THR +909 0x7FFF //TX_MICMUTE_LAMBDA_CB_NLE +910 0x7FFF //TX_MICMUTE_LAMBDA_RE_EST +911 0x4000 //TX_DTD_THR1_MICMUTE_0 +912 0x7000 //TX_DTD_THR1_MICMUTE_1 +913 0x7FFF //TX_DTD_THR1_MICMUTE_2 +914 0x7FFF //TX_DTD_THR1_MICMUTE_3 +915 0x6CCC //TX_DTD_THR2_MICMUTE_0 +916 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x1000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x4000 //TX_MICMUTE_C_POST_FLT +922 0x03E8 //TX_MICMUTE_DT_CUT_K +923 0x0001 //TX_MICMUTE_DT_CUT_THR +924 0x03E8 //TX_MICMUTE_DT_CUT_K2 +925 0x0001 //TX_MICMUTE_DT_CUT_THR2 +926 0x0064 //TX_MICMUTE_DT2_HOLD_N +927 0x1000 //TX_MICMUTE_RATIODTH_THCUT +928 0x1000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x7FFF //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0400 //TX_MICMUTE_C_POST_FLT_MASK +931 0x7999 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0258 //TX_MICMUTE_DT_CUT_K1 +933 0x0800 //TX_MICMUTE_N2_SN_EST +934 0xFC00 //TX_MICMUTE_THR_SN_EST_0 +935 0x001C //TX_MICMUTE_MIN_G_CTRL_0 +936 0x6000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x7000 //TX_MICMUTE_B_POST_FILT_0 +938 0x2710 //TX_MIC1RUB_AMP_THR +939 0x0010 //TX_MIC1MUTE_RATIO_THR +940 0x0450 //TX_MIC1MUTE_AMP_THR +941 0x0008 //TX_MIC1MUTE_CVG_TIME +942 0x0008 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x2024 //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0001 //RX_SAMPLINGFREQ_SIG +3 0x0001 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7FFF //RX_A_HP +12 0x4000 //RX_B_PE +13 0x3800 //RX_THR_PITCH_DET_0 +14 0x3000 //RX_THR_PITCH_DET_1 +15 0x2800 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0600 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x0010 //RX_NS_LVL_CTRL +23 0xF800 //RX_THR_SN_EST +24 0x7CCD //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0002 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0196 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x2000 //RX_MIN_G_FP +128 0x0080 //RX_MAX_G_FP +129 0x000C //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0196 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x000C //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0196 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0014 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0196 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0021 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0196 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0037 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0196 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x005B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0196 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0099 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x2000 //RX_TDDRC_THRD_2 +115 0x3000 //RX_TDDRC_THRD_3 +116 0x0800 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0196 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x2024 //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0001 //RX_SAMPLINGFREQ_SIG +160 0x0001 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7FFF //RX_A_HP +169 0x4000 //RX_B_PE +170 0x3800 //RX_THR_PITCH_DET_0 +171 0x3000 //RX_THR_PITCH_DET_1 +172 0x2800 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0600 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x0010 //RX_NS_LVL_CTRL +180 0xF800 //RX_THR_SN_EST +181 0x7CCD //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0002 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0196 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x2000 //RX_MIN_G_FP +285 0x0080 //RX_MAX_G_FP +286 0x000C //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0196 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x000C //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0196 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0014 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0196 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0021 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0196 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0037 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0196 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x005B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0196 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0099 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x2000 //RX_TDDRC_THRD_2 +272 0x3000 //RX_TDDRC_THRD_3 +273 0x0800 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0196 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME HEADSET-GOOGLE_CONDOR_CERTIFICATION1-VOICE_GENERIC-SWB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0009 //TX_OPERATION_MODE_0 +1 0x0001 //TX_OPERATION_MODE_1 +2 0x0033 //TX_PATCH_REG +3 0x2B68 //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0001 //TX_NUM_MIC +6 0x0003 //TX_SAMPLINGFREQ_SIG +7 0x0003 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009B //TX_DIST2REF1 +22 0x0000 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0B80 //TX_PGA_0 +28 0x0800 //TX_PGA_1 +29 0x0800 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0000 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0001 //TX_MIC_DATA_SRC1 +43 0x0002 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3E00 //TX_DIST2REF_11 +73 0x0000 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0200 //TX_MIC_REFBLK_VOLUME +108 0x0800 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0000 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7EFF //TX_A_HP +129 0x4000 //TX_B_PE +130 0x1800 //TX_THR_PITCH_DET_0 +131 0x1000 //TX_THR_PITCH_DET_1 +132 0x0800 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x001E //TX_TAIL_LENGTH +147 0x0080 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x7000 //TX_EAD_THR +151 0x0800 //TX_THR_RE_EST +152 0x0800 //TX_MIN_EQ_RE_EST_0 +153 0x0800 //TX_MIN_EQ_RE_EST_1 +154 0x0800 //TX_MIN_EQ_RE_EST_2 +155 0x0800 //TX_MIN_EQ_RE_EST_3 +156 0x0800 //TX_MIN_EQ_RE_EST_4 +157 0x0800 //TX_MIN_EQ_RE_EST_5 +158 0x0800 //TX_MIN_EQ_RE_EST_6 +159 0x0800 //TX_MIN_EQ_RE_EST_7 +160 0x0800 //TX_MIN_EQ_RE_EST_8 +161 0x0800 //TX_MIN_EQ_RE_EST_9 +162 0x0800 //TX_MIN_EQ_RE_EST_10 +163 0x0800 //TX_MIN_EQ_RE_EST_11 +164 0x0800 //TX_MIN_EQ_RE_EST_12 +165 0x4000 //TX_LAMBDA_RE_EST +166 0x2000 //TX_LAMBDA_CB_NLE +167 0x6000 //TX_C_POST_FLT +168 0x7000 //TX_GAIN_NP +169 0x00C8 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x03E8 //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x7800 //TX_DTD_THR1_0 +198 0x7000 //TX_DTD_THR1_1 +199 0x7FFF //TX_DTD_THR1_2 +200 0x7FFF //TX_DTD_THR1_3 +201 0x7FFF //TX_DTD_THR1_4 +202 0x7FFF //TX_DTD_THR1_5 +203 0x7FFF //TX_DTD_THR1_6 +204 0x7FFF //TX_DTD_THR2_0 +205 0x7FFF //TX_DTD_THR2_1 +206 0x7FFF //TX_DTD_THR2_2 +207 0x7FFF //TX_DTD_THR2_3 +208 0x7FFF //TX_DTD_THR2_4 +209 0x7FFF //TX_DTD_THR2_5 +210 0x7FFF //TX_DTD_THR2_6 +211 0x1000 //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x0BB8 //TX_DT_CUT_K +214 0x0CCD //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x0400 //TX_ADPT_STRICT_L +222 0x0200 //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x0800 //TX_B_POST_FILT_ECHO_L +229 0x7FFF //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x7FFF //TX_B_LESSCUT_RTO_ECHO +232 0x00F0 //TX_EPD_OFFSET_00 +233 0x00F0 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x7FFF //TX_DTD_THR1_7 +238 0x7FFF //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xFA00 //TX_THR_SN_EST_0 +243 0xF400 //TX_THR_SN_EST_1 +244 0xF600 //TX_THR_SN_EST_2 +245 0xF400 //TX_THR_SN_EST_3 +246 0xF400 //TX_THR_SN_EST_4 +247 0xF400 //TX_THR_SN_EST_5 +248 0xF400 //TX_THR_SN_EST_6 +249 0xF600 //TX_THR_SN_EST_7 +250 0x0000 //TX_DELTA_THR_SN_EST_0 +251 0x0200 //TX_DELTA_THR_SN_EST_1 +252 0x0200 //TX_DELTA_THR_SN_EST_2 +253 0x0200 //TX_DELTA_THR_SN_EST_3 +254 0x0200 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0000 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x6000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x6000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x1000 //TX_B_POST_FLT_0 +280 0x1000 //TX_B_POST_FLT_1 +281 0x000B //TX_NS_LVL_CTRL_0 +282 0x0011 //TX_NS_LVL_CTRL_1 +283 0x000F //TX_NS_LVL_CTRL_2 +284 0x000F //TX_NS_LVL_CTRL_3 +285 0x000F //TX_NS_LVL_CTRL_4 +286 0x000F //TX_NS_LVL_CTRL_5 +287 0x000F //TX_NS_LVL_CTRL_6 +288 0x0011 //TX_NS_LVL_CTRL_7 +289 0x000C //TX_MIN_GAIN_S_0 +290 0x000F //TX_MIN_GAIN_S_1 +291 0x000C //TX_MIN_GAIN_S_2 +292 0x000C //TX_MIN_GAIN_S_3 +293 0x000C //TX_MIN_GAIN_S_4 +294 0x000C //TX_MIN_GAIN_S_5 +295 0x000C //TX_MIN_GAIN_S_6 +296 0x000F //TX_MIN_GAIN_S_7 +297 0x7FFF //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x7FFF //TX_SNRI_SUP_1 +302 0x7FFF //TX_SNRI_SUP_2 +303 0x7FFF //TX_SNRI_SUP_3 +304 0x7FFF //TX_SNRI_SUP_4 +305 0x7FFF //TX_SNRI_SUP_5 +306 0x7FFF //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x000E //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x2000 //TX_A_POST_FILT_S_0 +315 0x5000 //TX_A_POST_FILT_S_1 +316 0x5000 //TX_A_POST_FILT_S_2 +317 0x5000 //TX_A_POST_FILT_S_3 +318 0x5000 //TX_A_POST_FILT_S_4 +319 0x5000 //TX_A_POST_FILT_S_5 +320 0x4000 //TX_A_POST_FILT_S_6 +321 0x5000 //TX_A_POST_FILT_S_7 +322 0x1000 //TX_B_POST_FILT_0 +323 0x1000 //TX_B_POST_FILT_1 +324 0x1000 //TX_B_POST_FILT_2 +325 0x1000 //TX_B_POST_FILT_3 +326 0x1000 //TX_B_POST_FILT_4 +327 0x1000 //TX_B_POST_FILT_5 +328 0x1000 //TX_B_POST_FILT_6 +329 0x1000 //TX_B_POST_FILT_7 +330 0x7FFF //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x7FFF //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7900 //TX_LAMBDA_PFILT +339 0x7B00 //TX_LAMBDA_PFILT_S_0 +340 0x7B00 //TX_LAMBDA_PFILT_S_1 +341 0x7B00 //TX_LAMBDA_PFILT_S_2 +342 0x7B00 //TX_LAMBDA_PFILT_S_3 +343 0x7B00 //TX_LAMBDA_PFILT_S_4 +344 0x7B00 //TX_LAMBDA_PFILT_S_5 +345 0x7B00 //TX_LAMBDA_PFILT_S_6 +346 0x7B00 //TX_LAMBDA_PFILT_S_7 +347 0x0000 //TX_K_PEPPER +348 0x0800 //TX_A_PEPPER +349 0x1EAA //TX_K_PEPPER_HF +350 0x0800 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0800 //TX_DT_BINVAD_TH_0 +354 0x0800 //TX_DT_BINVAD_TH_1 +355 0x0800 //TX_DT_BINVAD_TH_2 +356 0x0800 //TX_DT_BINVAD_TH_3 +357 0x1D4C //TX_DT_BINVAD_ENDF +358 0x0000 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0190 //TX_NDETCT +367 0x0383 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x07D0 //TX_NOISE_TH_1 +371 0x00C8 //TX_NOISE_TH_2 +372 0x3A98 //TX_NOISE_TH_3 +373 0x0FA0 //TX_NOISE_TH_4 +374 0x157C //TX_NOISE_TH_5 +375 0x7FFF //TX_NOISE_TH_5_2 +376 0x7FFF //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x044C //TX_NOISE_TH_6 +379 0x044C //TX_MINENOISE_TH +380 0xD508 //TX_MORENS_TFMASK_TH +381 0x0001 //TX_DRC_QUIET_FLOOR +382 0x3A98 //TX_RATIODTL_CUT_TH +383 0x0DAC //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x0333 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x7FFF //TX_POST_MASK_SUP_HSNE +392 0x1388 //TX_TAIL_DET_TH +393 0x4000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0080 //TX_SUPHIGH_TH +396 0x0000 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x1800 //TX_C_POST_FLT_MASK +399 0x7FFF //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0002 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x02F3 //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x2900 //TX_MIN_G_CTRL_SSNS +409 0x0800 //TX_METAL_RTO_THR +410 0x4848 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x4000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x01E0 //TX_NOR_OFF_THR +498 0x7C00 //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0xD333 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x6000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0xC000 //TX_DEREVERB_LF_MU +515 0xC000 //TX_DEREVERB_HF_MU +516 0xCCCC //TX_DEREVERB_DELAY +517 0xD999 //TX_DEREVERB_COEF_LEN +518 0x1F40 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x7000 //TX_GSC_RTOH_TH +523 0x0064 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0020 //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4848 //TX_FDEQ_GAIN_5 +573 0x4848 //TX_FDEQ_GAIN_6 +574 0x4848 //TX_FDEQ_GAIN_7 +575 0x4848 //TX_FDEQ_GAIN_8 +576 0x4848 //TX_FDEQ_GAIN_9 +577 0x4848 //TX_FDEQ_GAIN_10 +578 0x4848 //TX_FDEQ_GAIN_11 +579 0x4848 //TX_FDEQ_GAIN_12 +580 0x4848 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0303 //TX_FDEQ_BIN_2 +594 0x0304 //TX_FDEQ_BIN_3 +595 0x0405 //TX_FDEQ_BIN_4 +596 0x0506 //TX_FDEQ_BIN_5 +597 0x0708 //TX_FDEQ_BIN_6 +598 0x090A //TX_FDEQ_BIN_7 +599 0x0B0C //TX_FDEQ_BIN_8 +600 0x0D0E //TX_FDEQ_BIN_9 +601 0x1013 //TX_FDEQ_BIN_10 +602 0x1719 //TX_FDEQ_BIN_11 +603 0x1B1E //TX_FDEQ_BIN_12 +604 0x1E1E //TX_FDEQ_BIN_13 +605 0x1E28 //TX_FDEQ_BIN_14 +606 0x282C //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4868 //TX_PREEQ_GAIN_MIC0_8 +626 0x6860 //TX_PREEQ_GAIN_MIC0_9 +627 0x6048 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0E10 //TX_PREEQ_BIN_MIC0_0 +642 0x1010 //TX_PREEQ_BIN_MIC0_1 +643 0x1010 //TX_PREEQ_BIN_MIC0_2 +644 0x1010 //TX_PREEQ_BIN_MIC0_3 +645 0x1010 //TX_PREEQ_BIN_MIC0_4 +646 0x1010 //TX_PREEQ_BIN_MIC0_5 +647 0x1010 //TX_PREEQ_BIN_MIC0_6 +648 0x1010 //TX_PREEQ_BIN_MIC0_7 +649 0x1010 //TX_PREEQ_BIN_MIC0_8 +650 0x1010 //TX_PREEQ_BIN_MIC0_9 +651 0x1010 //TX_PREEQ_BIN_MIC0_10 +652 0x1010 //TX_PREEQ_BIN_MIC0_11 +653 0x1010 //TX_PREEQ_BIN_MIC0_12 +654 0x1010 //TX_PREEQ_BIN_MIC0_13 +655 0x1010 //TX_PREEQ_BIN_MIC0_14 +656 0x0200 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0E10 //TX_PREEQ_BIN_MIC1_0 +691 0x1010 //TX_PREEQ_BIN_MIC1_1 +692 0x1010 //TX_PREEQ_BIN_MIC1_2 +693 0x1010 //TX_PREEQ_BIN_MIC1_3 +694 0x1010 //TX_PREEQ_BIN_MIC1_4 +695 0x1010 //TX_PREEQ_BIN_MIC1_5 +696 0x1010 //TX_PREEQ_BIN_MIC1_6 +697 0x1010 //TX_PREEQ_BIN_MIC1_7 +698 0x1010 //TX_PREEQ_BIN_MIC1_8 +699 0x1010 //TX_PREEQ_BIN_MIC1_9 +700 0x1010 //TX_PREEQ_BIN_MIC1_10 +701 0x1010 //TX_PREEQ_BIN_MIC1_11 +702 0x1010 //TX_PREEQ_BIN_MIC1_12 +703 0x1010 //TX_PREEQ_BIN_MIC1_13 +704 0x1010 //TX_PREEQ_BIN_MIC1_14 +705 0x0200 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0E10 //TX_PREEQ_BIN_MIC2_0 +740 0x1010 //TX_PREEQ_BIN_MIC2_1 +741 0x1010 //TX_PREEQ_BIN_MIC2_2 +742 0x1010 //TX_PREEQ_BIN_MIC2_3 +743 0x1010 //TX_PREEQ_BIN_MIC2_4 +744 0x1010 //TX_PREEQ_BIN_MIC2_5 +745 0x1010 //TX_PREEQ_BIN_MIC2_6 +746 0x1010 //TX_PREEQ_BIN_MIC2_7 +747 0x1010 //TX_PREEQ_BIN_MIC2_8 +748 0x1010 //TX_PREEQ_BIN_MIC2_9 +749 0x1010 //TX_PREEQ_BIN_MIC2_10 +750 0x1010 //TX_PREEQ_BIN_MIC2_11 +751 0x1010 //TX_PREEQ_BIN_MIC2_12 +752 0x1010 //TX_PREEQ_BIN_MIC2_13 +753 0x1010 //TX_PREEQ_BIN_MIC2_14 +754 0x0200 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x0800 //TX_NND_WEIGHT +765 0x0062 //TX_MIC_CALIBRATION_0 +766 0x0062 //TX_MIC_CALIBRATION_1 +767 0x0062 //TX_MIC_CALIBRATION_2 +768 0x0062 //TX_MIC_CALIBRATION_3 +769 0x0046 //TX_MIC_PWR_BIAS_0 +770 0x0046 //TX_MIC_PWR_BIAS_1 +771 0x0046 //TX_MIC_PWR_BIAS_2 +772 0x0046 //TX_MIC_PWR_BIAS_3 +773 0x000C //TX_GAIN_LIMIT_0 +774 0x000C //TX_GAIN_LIMIT_1 +775 0x000C //TX_GAIN_LIMIT_2 +776 0x000C //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x3000 //TX_TDDRC_ALPHA_UP_01 +784 0x3000 //TX_TDDRC_ALPHA_UP_02 +785 0x3000 //TX_TDDRC_ALPHA_UP_03 +786 0x3000 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x78D6 //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0000 //TX_DEADMIC_SILENCE_TH +817 0x0000 //TX_MIC_DEGRADE_TH +818 0x0000 //TX_DEADMIC_CNT +819 0x0000 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x4848 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0000 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0000 //TX_FILTINDX +854 0x0000 //TX_TDDRC_THRD_0 +855 0x0000 //TX_TDDRC_THRD_1 +856 0x2000 //TX_TDDRC_THRD_2 +857 0x2000 //TX_TDDRC_THRD_3 +858 0x3000 //TX_TDDRC_SLANT_0 +859 0x6E00 //TX_TDDRC_SLANT_1 +860 0x3000 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x05A0 //TX_TDDRC_DRC_GAIN +867 0x78D6 //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x0028 //TX_FASTNS_ARSPC_TH +889 0x8000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x4000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x2339 //TX_SENDFUNC_REG_MICMUTE +898 0x0021 //TX_SENDFUNC_REG_MICMUTE1 +899 0x02BC //TX_MICMUTE_RATIO_THR +900 0x0140 //TX_MICMUTE_AMP_THR +901 0x0004 //TX_MICMUTE_HPF_IND +902 0x00C0 //TX_MICMUTE_LOG_EYR_TH +903 0x0008 //TX_MICMUTE_CVG_TIME +904 0x0008 //TX_MICMUTE_RELEASE_TIME +905 0x01FE //TX_MIC_VOLUME_MIC0MUTE +906 0x0020 //TX_MICMUTE_EPD_OFFSET_0 +907 0x001E //TX_MICMUTE_FRQ_AEC_L +908 0x7999 //TX_MICMUTE_EAD_THR +909 0x7FFF //TX_MICMUTE_LAMBDA_CB_NLE +910 0x7FFF //TX_MICMUTE_LAMBDA_RE_EST +911 0x4000 //TX_DTD_THR1_MICMUTE_0 +912 0x7000 //TX_DTD_THR1_MICMUTE_1 +913 0x7FFF //TX_DTD_THR1_MICMUTE_2 +914 0x7FFF //TX_DTD_THR1_MICMUTE_3 +915 0x6CCC //TX_DTD_THR2_MICMUTE_0 +916 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x1000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x4000 //TX_MICMUTE_C_POST_FLT +922 0x03E8 //TX_MICMUTE_DT_CUT_K +923 0x0001 //TX_MICMUTE_DT_CUT_THR +924 0x03E8 //TX_MICMUTE_DT_CUT_K2 +925 0x0001 //TX_MICMUTE_DT_CUT_THR2 +926 0x0064 //TX_MICMUTE_DT2_HOLD_N +927 0x1000 //TX_MICMUTE_RATIODTH_THCUT +928 0x1000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x7FFF //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0400 //TX_MICMUTE_C_POST_FLT_MASK +931 0x7999 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0258 //TX_MICMUTE_DT_CUT_K1 +933 0x0800 //TX_MICMUTE_N2_SN_EST +934 0xFC00 //TX_MICMUTE_THR_SN_EST_0 +935 0x001C //TX_MICMUTE_MIN_G_CTRL_0 +936 0x6000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x7000 //TX_MICMUTE_B_POST_FILT_0 +938 0x2710 //TX_MIC1RUB_AMP_THR +939 0x0010 //TX_MIC1MUTE_RATIO_THR +940 0x0450 //TX_MIC1MUTE_AMP_THR +941 0x0008 //TX_MIC1MUTE_CVG_TIME +942 0x0008 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x2024 //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0003 //RX_SAMPLINGFREQ_SIG +3 0x0003 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x5000 //RX_TDDRC_ALPHA_UP_1 +7 0x5000 //RX_TDDRC_ALPHA_UP_2 +8 0x5000 //RX_TDDRC_ALPHA_UP_3 +9 0x2000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7FFF //RX_A_HP +12 0x0000 //RX_B_PE +13 0x1800 //RX_THR_PITCH_DET_0 +14 0x1000 //RX_THR_PITCH_DET_1 +15 0x0800 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0400 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x0003 //RX_NS_LVL_CTRL +23 0x9000 //RX_THR_SN_EST +24 0x7CCD //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x65AD //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0002 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x5000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x01C8 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x2000 //RX_MIN_G_FP +128 0x0080 //RX_MAX_G_FP +129 0x000C //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x5000 //RX_TDDRC_ALPHA_UP_1 +7 0x5000 //RX_TDDRC_ALPHA_UP_2 +8 0x5000 //RX_TDDRC_ALPHA_UP_3 +9 0x2000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x65AD //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x5000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x01C8 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x000C //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x5000 //RX_TDDRC_ALPHA_UP_1 +7 0x5000 //RX_TDDRC_ALPHA_UP_2 +8 0x5000 //RX_TDDRC_ALPHA_UP_3 +9 0x2000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x65AD //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x5000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x01C8 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0014 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x5000 //RX_TDDRC_ALPHA_UP_1 +7 0x5000 //RX_TDDRC_ALPHA_UP_2 +8 0x5000 //RX_TDDRC_ALPHA_UP_3 +9 0x2000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x65AD //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x5000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x01C8 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0021 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x5000 //RX_TDDRC_ALPHA_UP_1 +7 0x5000 //RX_TDDRC_ALPHA_UP_2 +8 0x5000 //RX_TDDRC_ALPHA_UP_3 +9 0x2000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x65AD //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x5000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x01C8 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0037 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x5000 //RX_TDDRC_ALPHA_UP_1 +7 0x5000 //RX_TDDRC_ALPHA_UP_2 +8 0x5000 //RX_TDDRC_ALPHA_UP_3 +9 0x2000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x65AD //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x5000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x01C8 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x005B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x5000 //RX_TDDRC_ALPHA_UP_1 +7 0x5000 //RX_TDDRC_ALPHA_UP_2 +8 0x5000 //RX_TDDRC_ALPHA_UP_3 +9 0x2000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x65AD //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x5000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x01C8 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0099 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x5000 //RX_TDDRC_ALPHA_UP_1 +7 0x5000 //RX_TDDRC_ALPHA_UP_2 +8 0x5000 //RX_TDDRC_ALPHA_UP_3 +9 0x2000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x65AD //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x7EB8 //RX_TDDRC_SLANT_1 +118 0x5000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x01C8 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0405 //RX_FDEQ_BIN_4 +68 0x0506 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x2024 //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0003 //RX_SAMPLINGFREQ_SIG +160 0x0003 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x5000 //RX_TDDRC_ALPHA_UP_1 +164 0x5000 //RX_TDDRC_ALPHA_UP_2 +165 0x5000 //RX_TDDRC_ALPHA_UP_3 +166 0x2000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7FFF //RX_A_HP +169 0x0000 //RX_B_PE +170 0x1800 //RX_THR_PITCH_DET_0 +171 0x1000 //RX_THR_PITCH_DET_1 +172 0x0800 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0400 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x0003 //RX_NS_LVL_CTRL +180 0x9000 //RX_THR_SN_EST +181 0x7CCD //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x65AD //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0002 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x5000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x01C8 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x2000 //RX_MIN_G_FP +285 0x0080 //RX_MAX_G_FP +286 0x000C //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x5000 //RX_TDDRC_ALPHA_UP_1 +164 0x5000 //RX_TDDRC_ALPHA_UP_2 +165 0x5000 //RX_TDDRC_ALPHA_UP_3 +166 0x2000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x65AD //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x5000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x01C8 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x000C //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x5000 //RX_TDDRC_ALPHA_UP_1 +164 0x5000 //RX_TDDRC_ALPHA_UP_2 +165 0x5000 //RX_TDDRC_ALPHA_UP_3 +166 0x2000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x65AD //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x5000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x01C8 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0014 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x5000 //RX_TDDRC_ALPHA_UP_1 +164 0x5000 //RX_TDDRC_ALPHA_UP_2 +165 0x5000 //RX_TDDRC_ALPHA_UP_3 +166 0x2000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x65AD //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x5000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x01C8 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0021 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x5000 //RX_TDDRC_ALPHA_UP_1 +164 0x5000 //RX_TDDRC_ALPHA_UP_2 +165 0x5000 //RX_TDDRC_ALPHA_UP_3 +166 0x2000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x65AD //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x5000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x01C8 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0037 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x5000 //RX_TDDRC_ALPHA_UP_1 +164 0x5000 //RX_TDDRC_ALPHA_UP_2 +165 0x5000 //RX_TDDRC_ALPHA_UP_3 +166 0x2000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x65AD //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x5000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x01C8 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x005B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x5000 //RX_TDDRC_ALPHA_UP_1 +164 0x5000 //RX_TDDRC_ALPHA_UP_2 +165 0x5000 //RX_TDDRC_ALPHA_UP_3 +166 0x2000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x65AD //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x5000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x01C8 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0099 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x5000 //RX_TDDRC_ALPHA_UP_1 +164 0x5000 //RX_TDDRC_ALPHA_UP_2 +165 0x5000 //RX_TDDRC_ALPHA_UP_3 +166 0x2000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x65AD //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x7EB8 //RX_TDDRC_SLANT_1 +275 0x5000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x01C8 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0405 //RX_FDEQ_BIN_4 +225 0x0506 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME HEADSET-GOOGLE_CONDOR_CERTIFICATION1-VOICE_GENERIC-FB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0009 //TX_OPERATION_MODE_0 +1 0x0009 //TX_OPERATION_MODE_1 +2 0x0020 //TX_PATCH_REG +3 0x6B6A //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0001 //TX_NUM_MIC +6 0x0004 //TX_SAMPLINGFREQ_SIG +7 0x0004 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009B //TX_DIST2REF1 +22 0x0000 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0B4C //TX_PGA_0 +28 0x0800 //TX_PGA_1 +29 0x0000 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0000 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0001 //TX_MIC_DATA_SRC1 +43 0x0002 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3E00 //TX_DIST2REF_11 +73 0x0000 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0200 //TX_MIC_REFBLK_VOLUME +108 0x0800 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0000 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7E56 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x6800 //TX_THR_PITCH_DET_0 +131 0x6000 //TX_THR_PITCH_DET_1 +132 0x5800 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x001E //TX_TAIL_LENGTH +147 0x0200 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x61A8 //TX_EAD_THR +151 0x0400 //TX_THR_RE_EST +152 0x3000 //TX_MIN_EQ_RE_EST_0 +153 0x3000 //TX_MIN_EQ_RE_EST_1 +154 0x4000 //TX_MIN_EQ_RE_EST_2 +155 0x0800 //TX_MIN_EQ_RE_EST_3 +156 0x0800 //TX_MIN_EQ_RE_EST_4 +157 0x0800 //TX_MIN_EQ_RE_EST_5 +158 0x6000 //TX_MIN_EQ_RE_EST_6 +159 0x6000 //TX_MIN_EQ_RE_EST_7 +160 0x6000 //TX_MIN_EQ_RE_EST_8 +161 0x6000 //TX_MIN_EQ_RE_EST_9 +162 0x4000 //TX_MIN_EQ_RE_EST_10 +163 0x4000 //TX_MIN_EQ_RE_EST_11 +164 0x4000 //TX_MIN_EQ_RE_EST_12 +165 0x3000 //TX_LAMBDA_RE_EST +166 0x4000 //TX_LAMBDA_CB_NLE +167 0x3000 //TX_C_POST_FLT +168 0x7FFF //TX_GAIN_NP +169 0x00C8 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x03E8 //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x0800 //TX_DTD_THR1_0 +198 0x0800 //TX_DTD_THR1_1 +199 0x0800 //TX_DTD_THR1_2 +200 0x0800 //TX_DTD_THR1_3 +201 0x0800 //TX_DTD_THR1_4 +202 0x0800 //TX_DTD_THR1_5 +203 0x0800 //TX_DTD_THR1_6 +204 0x0800 //TX_DTD_THR2_0 +205 0x0800 //TX_DTD_THR2_1 +206 0x0800 //TX_DTD_THR2_2 +207 0x0800 //TX_DTD_THR2_3 +208 0x0800 //TX_DTD_THR2_4 +209 0x0100 //TX_DTD_THR2_5 +210 0x0100 //TX_DTD_THR2_6 +211 0x7FFF //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x03E8 //TX_DT_CUT_K +214 0x0CCD //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x0400 //TX_ADPT_STRICT_L +222 0x0200 //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x0800 //TX_B_POST_FILT_ECHO_L +229 0x7FFF //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x7FFF //TX_B_LESSCUT_RTO_ECHO +232 0x00C0 //TX_EPD_OFFSET_00 +233 0x00C0 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x7FFF //TX_DTD_THR1_7 +238 0x7FFF //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xF700 //TX_THR_SN_EST_0 +243 0xFB00 //TX_THR_SN_EST_1 +244 0xFA00 //TX_THR_SN_EST_2 +245 0xF700 //TX_THR_SN_EST_3 +246 0xFA00 //TX_THR_SN_EST_4 +247 0xF600 //TX_THR_SN_EST_5 +248 0xF600 //TX_THR_SN_EST_6 +249 0xF600 //TX_THR_SN_EST_7 +250 0x0200 //TX_DELTA_THR_SN_EST_0 +251 0x0400 //TX_DELTA_THR_SN_EST_1 +252 0x0300 //TX_DELTA_THR_SN_EST_2 +253 0x0600 //TX_DELTA_THR_SN_EST_3 +254 0x0200 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0200 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x4000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x4000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x2000 //TX_B_POST_FLT_0 +280 0x2000 //TX_B_POST_FLT_1 +281 0x0012 //TX_NS_LVL_CTRL_0 +282 0x0016 //TX_NS_LVL_CTRL_1 +283 0x0016 //TX_NS_LVL_CTRL_2 +284 0x0019 //TX_NS_LVL_CTRL_3 +285 0x0010 //TX_NS_LVL_CTRL_4 +286 0x0010 //TX_NS_LVL_CTRL_5 +287 0x0019 //TX_NS_LVL_CTRL_6 +288 0x0010 //TX_NS_LVL_CTRL_7 +289 0x000C //TX_MIN_GAIN_S_0 +290 0x000C //TX_MIN_GAIN_S_1 +291 0x000C //TX_MIN_GAIN_S_2 +292 0x000F //TX_MIN_GAIN_S_3 +293 0x000C //TX_MIN_GAIN_S_4 +294 0x000C //TX_MIN_GAIN_S_5 +295 0x0011 //TX_MIN_GAIN_S_6 +296 0x000C //TX_MIN_GAIN_S_7 +297 0x7FFF //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7000 //TX_SNRI_SUP_0 +301 0x7000 //TX_SNRI_SUP_1 +302 0x7000 //TX_SNRI_SUP_2 +303 0x6000 //TX_SNRI_SUP_3 +304 0x7FFF //TX_SNRI_SUP_4 +305 0x7FFF //TX_SNRI_SUP_5 +306 0x6000 //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x0016 //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x6000 //TX_A_POST_FILT_S_0 +315 0x6000 //TX_A_POST_FILT_S_1 +316 0x6000 //TX_A_POST_FILT_S_2 +317 0x6000 //TX_A_POST_FILT_S_3 +318 0x6000 //TX_A_POST_FILT_S_4 +319 0x6000 //TX_A_POST_FILT_S_5 +320 0x6000 //TX_A_POST_FILT_S_6 +321 0x6000 //TX_A_POST_FILT_S_7 +322 0x2000 //TX_B_POST_FILT_0 +323 0x4000 //TX_B_POST_FILT_1 +324 0x2000 //TX_B_POST_FILT_2 +325 0x2000 //TX_B_POST_FILT_3 +326 0x2000 //TX_B_POST_FILT_4 +327 0x2000 //TX_B_POST_FILT_5 +328 0x2000 //TX_B_POST_FILT_6 +329 0x2000 //TX_B_POST_FILT_7 +330 0x7FFF //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x7FFF //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7CCD //TX_LAMBDA_PFILT +339 0x7CCD //TX_LAMBDA_PFILT_S_0 +340 0x7CCD //TX_LAMBDA_PFILT_S_1 +341 0x7CCD //TX_LAMBDA_PFILT_S_2 +342 0x7CCD //TX_LAMBDA_PFILT_S_3 +343 0x7CCD //TX_LAMBDA_PFILT_S_4 +344 0x7CCD //TX_LAMBDA_PFILT_S_5 +345 0x7CCD //TX_LAMBDA_PFILT_S_6 +346 0x7CCD //TX_LAMBDA_PFILT_S_7 +347 0x0200 //TX_K_PEPPER +348 0x0500 //TX_A_PEPPER +349 0x1600 //TX_K_PEPPER_HF +350 0x0400 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0800 //TX_DT_BINVAD_TH_0 +354 0x0800 //TX_DT_BINVAD_TH_1 +355 0x0800 //TX_DT_BINVAD_TH_2 +356 0x0800 //TX_DT_BINVAD_TH_3 +357 0x1D4C //TX_DT_BINVAD_ENDF +358 0x0000 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0190 //TX_NDETCT +367 0x04E8 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x02A6 //TX_NOISE_TH_1 +371 0x04B0 //TX_NOISE_TH_2 +372 0x3194 //TX_NOISE_TH_3 +373 0x0960 //TX_NOISE_TH_4 +374 0x5555 //TX_NOISE_TH_5 +375 0x3FF4 //TX_NOISE_TH_5_2 +376 0x0001 //TX_NOISE_TH_5_3 +377 0x0000 //TX_NOISE_TH_5_4 +378 0x02BC //TX_NOISE_TH_6 +379 0x02BC //TX_MINENOISE_TH +380 0xD508 //TX_MORENS_TFMASK_TH +381 0x0001 //TX_DRC_QUIET_FLOOR +382 0x3A98 //TX_RATIODTL_CUT_TH +383 0x1482 //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x0333 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x7FFF //TX_POST_MASK_SUP_HSNE +392 0x1388 //TX_TAIL_DET_TH +393 0x4000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0080 //TX_SUPHIGH_TH +396 0x0000 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x1800 //TX_C_POST_FLT_MASK +399 0x7FFF //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0004 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x04E7 //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x2900 //TX_MIN_G_CTRL_SSNS +409 0x0800 //TX_METAL_RTO_THR +410 0x4848 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x4000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x01E0 //TX_NOR_OFF_THR +498 0x7C00 //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0xD333 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x6000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0xC000 //TX_DEREVERB_LF_MU +515 0xC000 //TX_DEREVERB_HF_MU +516 0xCCCC //TX_DEREVERB_DELAY +517 0xD999 //TX_DEREVERB_COEF_LEN +518 0x1F40 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x7000 //TX_GSC_RTOH_TH +523 0x0064 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0020 //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4848 //TX_FDEQ_GAIN_5 +573 0x4848 //TX_FDEQ_GAIN_6 +574 0x4848 //TX_FDEQ_GAIN_7 +575 0x4848 //TX_FDEQ_GAIN_8 +576 0x4848 //TX_FDEQ_GAIN_9 +577 0x4848 //TX_FDEQ_GAIN_10 +578 0x4848 //TX_FDEQ_GAIN_11 +579 0x4848 //TX_FDEQ_GAIN_12 +580 0x4848 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0304 //TX_FDEQ_BIN_2 +594 0x0405 //TX_FDEQ_BIN_3 +595 0x0607 //TX_FDEQ_BIN_4 +596 0x0809 //TX_FDEQ_BIN_5 +597 0x0A0B //TX_FDEQ_BIN_6 +598 0x0C0D //TX_FDEQ_BIN_7 +599 0x0E0F //TX_FDEQ_BIN_8 +600 0x1011 //TX_FDEQ_BIN_9 +601 0x1214 //TX_FDEQ_BIN_10 +602 0x1618 //TX_FDEQ_BIN_11 +603 0x1C1C //TX_FDEQ_BIN_12 +604 0x2020 //TX_FDEQ_BIN_13 +605 0x2020 //TX_FDEQ_BIN_14 +606 0x2011 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4848 //TX_PREEQ_GAIN_MIC0_8 +626 0x4848 //TX_PREEQ_GAIN_MIC0_9 +627 0x4848 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0E10 //TX_PREEQ_BIN_MIC0_0 +642 0x1010 //TX_PREEQ_BIN_MIC0_1 +643 0x1010 //TX_PREEQ_BIN_MIC0_2 +644 0x1010 //TX_PREEQ_BIN_MIC0_3 +645 0x1010 //TX_PREEQ_BIN_MIC0_4 +646 0x1010 //TX_PREEQ_BIN_MIC0_5 +647 0x1010 //TX_PREEQ_BIN_MIC0_6 +648 0x1010 //TX_PREEQ_BIN_MIC0_7 +649 0x1010 //TX_PREEQ_BIN_MIC0_8 +650 0x1010 //TX_PREEQ_BIN_MIC0_9 +651 0x1010 //TX_PREEQ_BIN_MIC0_10 +652 0x1010 //TX_PREEQ_BIN_MIC0_11 +653 0x1010 //TX_PREEQ_BIN_MIC0_12 +654 0x1010 //TX_PREEQ_BIN_MIC0_13 +655 0x1010 //TX_PREEQ_BIN_MIC0_14 +656 0x0200 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0E10 //TX_PREEQ_BIN_MIC1_0 +691 0x1010 //TX_PREEQ_BIN_MIC1_1 +692 0x1010 //TX_PREEQ_BIN_MIC1_2 +693 0x1010 //TX_PREEQ_BIN_MIC1_3 +694 0x1010 //TX_PREEQ_BIN_MIC1_4 +695 0x1010 //TX_PREEQ_BIN_MIC1_5 +696 0x1010 //TX_PREEQ_BIN_MIC1_6 +697 0x1010 //TX_PREEQ_BIN_MIC1_7 +698 0x1010 //TX_PREEQ_BIN_MIC1_8 +699 0x1010 //TX_PREEQ_BIN_MIC1_9 +700 0x1010 //TX_PREEQ_BIN_MIC1_10 +701 0x1010 //TX_PREEQ_BIN_MIC1_11 +702 0x1010 //TX_PREEQ_BIN_MIC1_12 +703 0x1010 //TX_PREEQ_BIN_MIC1_13 +704 0x1010 //TX_PREEQ_BIN_MIC1_14 +705 0x0200 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0E10 //TX_PREEQ_BIN_MIC2_0 +740 0x1010 //TX_PREEQ_BIN_MIC2_1 +741 0x1010 //TX_PREEQ_BIN_MIC2_2 +742 0x1010 //TX_PREEQ_BIN_MIC2_3 +743 0x1010 //TX_PREEQ_BIN_MIC2_4 +744 0x1010 //TX_PREEQ_BIN_MIC2_5 +745 0x1010 //TX_PREEQ_BIN_MIC2_6 +746 0x1010 //TX_PREEQ_BIN_MIC2_7 +747 0x1010 //TX_PREEQ_BIN_MIC2_8 +748 0x1010 //TX_PREEQ_BIN_MIC2_9 +749 0x1010 //TX_PREEQ_BIN_MIC2_10 +750 0x1010 //TX_PREEQ_BIN_MIC2_11 +751 0x1010 //TX_PREEQ_BIN_MIC2_12 +752 0x1010 //TX_PREEQ_BIN_MIC2_13 +753 0x1010 //TX_PREEQ_BIN_MIC2_14 +754 0x0200 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x2000 //TX_NND_WEIGHT +765 0x0060 //TX_MIC_CALIBRATION_0 +766 0x0060 //TX_MIC_CALIBRATION_1 +767 0x0070 //TX_MIC_CALIBRATION_2 +768 0x0070 //TX_MIC_CALIBRATION_3 +769 0x0050 //TX_MIC_PWR_BIAS_0 +770 0x0040 //TX_MIC_PWR_BIAS_1 +771 0x0040 //TX_MIC_PWR_BIAS_2 +772 0x0040 //TX_MIC_PWR_BIAS_3 +773 0x0009 //TX_GAIN_LIMIT_0 +774 0x000F //TX_GAIN_LIMIT_1 +775 0x000F //TX_GAIN_LIMIT_2 +776 0x000F //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x0C00 //TX_TDDRC_ALPHA_UP_01 +784 0x0C00 //TX_TDDRC_ALPHA_UP_02 +785 0x0C00 //TX_TDDRC_ALPHA_UP_03 +786 0x0C00 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x7FFF //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0000 //TX_DEADMIC_SILENCE_TH +817 0x0000 //TX_MIC_DEGRADE_TH +818 0x0000 //TX_DEADMIC_CNT +819 0x0000 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x4848 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0000 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0002 //TX_FILTINDX +854 0x0001 //TX_TDDRC_THRD_0 +855 0x0001 //TX_TDDRC_THRD_1 +856 0x1900 //TX_TDDRC_THRD_2 +857 0x1900 //TX_TDDRC_THRD_3 +858 0x3000 //TX_TDDRC_SLANT_0 +859 0x7B00 //TX_TDDRC_SLANT_1 +860 0x0C00 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x07F2 //TX_TDDRC_DRC_GAIN +867 0x7FFF //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x0028 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x7000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x2339 //TX_SENDFUNC_REG_MICMUTE +898 0x0021 //TX_SENDFUNC_REG_MICMUTE1 +899 0x02BC //TX_MICMUTE_RATIO_THR +900 0x0140 //TX_MICMUTE_AMP_THR +901 0x0004 //TX_MICMUTE_HPF_IND +902 0x00C0 //TX_MICMUTE_LOG_EYR_TH +903 0x0008 //TX_MICMUTE_CVG_TIME +904 0x0008 //TX_MICMUTE_RELEASE_TIME +905 0x01FE //TX_MIC_VOLUME_MIC0MUTE +906 0x0020 //TX_MICMUTE_EPD_OFFSET_0 +907 0x001E //TX_MICMUTE_FRQ_AEC_L +908 0x7999 //TX_MICMUTE_EAD_THR +909 0x7FFF //TX_MICMUTE_LAMBDA_CB_NLE +910 0x7FFF //TX_MICMUTE_LAMBDA_RE_EST +911 0x4000 //TX_DTD_THR1_MICMUTE_0 +912 0x7000 //TX_DTD_THR1_MICMUTE_1 +913 0x7FFF //TX_DTD_THR1_MICMUTE_2 +914 0x7FFF //TX_DTD_THR1_MICMUTE_3 +915 0x6CCC //TX_DTD_THR2_MICMUTE_0 +916 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x1000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x4000 //TX_MICMUTE_C_POST_FLT +922 0x03E8 //TX_MICMUTE_DT_CUT_K +923 0x0001 //TX_MICMUTE_DT_CUT_THR +924 0x03E8 //TX_MICMUTE_DT_CUT_K2 +925 0x0001 //TX_MICMUTE_DT_CUT_THR2 +926 0x0064 //TX_MICMUTE_DT2_HOLD_N +927 0x1000 //TX_MICMUTE_RATIODTH_THCUT +928 0x1000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x7FFF //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0400 //TX_MICMUTE_C_POST_FLT_MASK +931 0x7999 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0258 //TX_MICMUTE_DT_CUT_K1 +933 0x0800 //TX_MICMUTE_N2_SN_EST +934 0xFC00 //TX_MICMUTE_THR_SN_EST_0 +935 0x001C //TX_MICMUTE_MIN_G_CTRL_0 +936 0x6000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x7000 //TX_MICMUTE_B_POST_FILT_0 +938 0x2710 //TX_MIC1RUB_AMP_THR +939 0x0010 //TX_MIC1MUTE_RATIO_THR +940 0x0450 //TX_MIC1MUTE_AMP_THR +941 0x0008 //TX_MIC1MUTE_CVG_TIME +942 0x0008 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x202C //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0004 //RX_SAMPLINGFREQ_SIG +3 0x0004 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +10 0x0800 //RX_PGA +11 0x7B02 //RX_A_HP +12 0x4000 //RX_B_PE +13 0x7800 //RX_THR_PITCH_DET_0 +14 0x7000 //RX_THR_PITCH_DET_1 +15 0x6000 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0500 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x000A //RX_NS_LVL_CTRL +23 0xF600 //RX_THR_SN_EST +24 0x7000 //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0002 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1200 //RX_TDDRC_THRD_2 +115 0x1900 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0240 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x2000 //RX_MIN_G_FP +128 0x0080 //RX_MAX_G_FP +129 0x000B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1200 //RX_TDDRC_THRD_2 +115 0x1900 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0240 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x000B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1200 //RX_TDDRC_THRD_2 +115 0x1900 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0240 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0013 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1200 //RX_TDDRC_THRD_2 +115 0x1900 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0240 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0020 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1200 //RX_TDDRC_THRD_2 +115 0x1900 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0240 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0036 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1200 //RX_TDDRC_THRD_2 +115 0x1900 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0240 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x005B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1200 //RX_TDDRC_THRD_2 +115 0x1900 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0240 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0099 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7FFF //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x1200 //RX_TDDRC_THRD_2 +115 0x1900 //RX_TDDRC_THRD_3 +116 0x3000 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0240 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0304 //RX_FDEQ_BIN_2 +66 0x0405 //RX_FDEQ_BIN_3 +67 0x0607 //RX_FDEQ_BIN_4 +68 0x0809 //RX_FDEQ_BIN_5 +69 0x0A0B //RX_FDEQ_BIN_6 +70 0x0C0D //RX_FDEQ_BIN_7 +71 0x0E0F //RX_FDEQ_BIN_8 +72 0x1011 //RX_FDEQ_BIN_9 +73 0x1214 //RX_FDEQ_BIN_10 +74 0x1618 //RX_FDEQ_BIN_11 +75 0x1C1C //RX_FDEQ_BIN_12 +76 0x2020 //RX_FDEQ_BIN_13 +77 0x2020 //RX_FDEQ_BIN_14 +78 0x2011 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0007 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x5333 //RX_FDDRC_SLANT_1_0 +107 0x5333 //RX_FDDRC_SLANT_1_1 +108 0x5333 //RX_FDDRC_SLANT_1_2 +109 0x5333 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x202C //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0004 //RX_SAMPLINGFREQ_SIG +160 0x0004 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +167 0x0800 //RX_PGA +168 0x7B02 //RX_A_HP +169 0x4000 //RX_B_PE +170 0x7800 //RX_THR_PITCH_DET_0 +171 0x7000 //RX_THR_PITCH_DET_1 +172 0x6000 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0500 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x000A //RX_NS_LVL_CTRL +180 0xF600 //RX_THR_SN_EST +181 0x7000 //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0002 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1200 //RX_TDDRC_THRD_2 +272 0x1900 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0240 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x2000 //RX_MIN_G_FP +285 0x0080 //RX_MAX_G_FP +286 0x000B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1200 //RX_TDDRC_THRD_2 +272 0x1900 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0240 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x000B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1200 //RX_TDDRC_THRD_2 +272 0x1900 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0240 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0013 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1200 //RX_TDDRC_THRD_2 +272 0x1900 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0240 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0020 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1200 //RX_TDDRC_THRD_2 +272 0x1900 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0240 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0036 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1200 //RX_TDDRC_THRD_2 +272 0x1900 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0240 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x005B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1200 //RX_TDDRC_THRD_2 +272 0x1900 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0240 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0099 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7FFF //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x1200 //RX_TDDRC_THRD_2 +272 0x1900 //RX_TDDRC_THRD_3 +273 0x3000 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0240 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0304 //RX_FDEQ_BIN_2 +223 0x0405 //RX_FDEQ_BIN_3 +224 0x0607 //RX_FDEQ_BIN_4 +225 0x0809 //RX_FDEQ_BIN_5 +226 0x0A0B //RX_FDEQ_BIN_6 +227 0x0C0D //RX_FDEQ_BIN_7 +228 0x0E0F //RX_FDEQ_BIN_8 +229 0x1011 //RX_FDEQ_BIN_9 +230 0x1214 //RX_FDEQ_BIN_10 +231 0x1618 //RX_FDEQ_BIN_11 +232 0x1C1C //RX_FDEQ_BIN_12 +233 0x2020 //RX_FDEQ_BIN_13 +234 0x2020 //RX_FDEQ_BIN_14 +235 0x2011 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0007 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x5333 //RX_FDDRC_SLANT_1_0 +264 0x5333 //RX_FDDRC_SLANT_1_1 +265 0x5333 //RX_FDDRC_SLANT_1_2 +266 0x5333 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME HEADSET-TTY_HCO-VOICE_GENERIC-NB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0001 //TX_OPERATION_MODE_0 +1 0x0000 //TX_OPERATION_MODE_1 +2 0x0000 //TX_PATCH_REG +3 0x0200 //TX_SENDFUNC_MODE_0 +4 0x0000 //TX_SENDFUNC_MODE_1 +5 0x0001 //TX_NUM_MIC +6 0x0000 //TX_SAMPLINGFREQ_SIG +7 0x0000 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x0078 //TX_DIST2REF1 +22 0x0000 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0302 //TX_PGA_0 +28 0x0800 //TX_PGA_1 +29 0x0800 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0000 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0000 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0000 //TX_MICS_OF_PAIR0 +38 0x0000 //TX_MICS_OF_PAIR1 +39 0x0000 //TX_MICS_OF_PAIR2 +40 0x0000 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0001 //TX_MIC_DATA_SRC1 +43 0x0002 //TX_MIC_DATA_SRC2 +44 0x0003 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x0000 //TX_HD_BIN_MASK +53 0x0000 //TX_HD_SUBAND_MASK +54 0x0000 //TX_HD_FRAME_AVG_MASK +55 0x0000 //TX_HD_MIN_FRQ +56 0x0000 //TX_HD_ALPHA_PSD +57 0x0000 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0x0000 //TX_T_PSDVAT +63 0x0000 //TX_CNT +64 0x0000 //TX_ANTI_HOWL_GAIN +65 0x0000 //TX_MICFORBFMARK_0 +66 0x0000 //TX_MICFORBFMARK_1 +67 0x0000 //TX_MICFORBFMARK_2 +68 0x0000 //TX_MICFORBFMARK_3 +69 0x0000 //TX_MICFORBFMARK_4 +70 0x0000 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x0000 //TX_DIST2REF_11 +73 0x0000 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0800 //TX_MIC_REFBLK_VOLUME +108 0x0800 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x0000 //TX_ADCS_GAIN +112 0x0000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x7FFF //TX_BLMIC_BLKFACTOR +116 0x7FFF //TX_BRMIC_BLKFACTOR +117 0x000A //TX_MICBLK_START_BIN +118 0x0041 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0015 //TX_FENE_HOLD +123 0x0000 //TX_FE_ENER_TH_MTS +124 0x0000 //TX_FE_ENER_TH_EXP +125 0x0000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x0000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0020 //TX_MIC_BLOCK_N +128 0x7652 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x7800 //TX_THR_PITCH_DET_0 +131 0x7000 //TX_THR_PITCH_DET_1 +132 0x6000 //TX_THR_PITCH_DET_2 +133 0x0000 //TX_PITCH_BFR_LEN +134 0x0000 //TX_SBD_PITCH_DET +135 0x0000 //TX_TD_AEC_L +136 0x0000 //TX_MU0_UNP_TD_AEC +137 0x0000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x0028 //TX_TAIL_LENGTH +147 0x2000 //TX_AEC_REF_GAIN_0 +148 0x2000 //TX_AEC_REF_GAIN_1 +149 0x2000 //TX_AEC_REF_GAIN_2 +150 0x4000 //TX_EAD_THR +151 0x0200 //TX_THR_RE_EST +152 0x0100 //TX_MIN_EQ_RE_EST_0 +153 0x0100 //TX_MIN_EQ_RE_EST_1 +154 0x0100 //TX_MIN_EQ_RE_EST_2 +155 0x0100 //TX_MIN_EQ_RE_EST_3 +156 0x0100 //TX_MIN_EQ_RE_EST_4 +157 0x0100 //TX_MIN_EQ_RE_EST_5 +158 0x0100 //TX_MIN_EQ_RE_EST_6 +159 0x0100 //TX_MIN_EQ_RE_EST_7 +160 0x0100 //TX_MIN_EQ_RE_EST_8 +161 0x0100 //TX_MIN_EQ_RE_EST_9 +162 0x0100 //TX_MIN_EQ_RE_EST_10 +163 0x0100 //TX_MIN_EQ_RE_EST_11 +164 0x0100 //TX_MIN_EQ_RE_EST_12 +165 0x4000 //TX_LAMBDA_RE_EST +166 0x0000 //TX_LAMBDA_CB_NLE +167 0x0000 //TX_C_POST_FLT +168 0x4000 //TX_GAIN_NP +169 0x0008 //TX_SE_HOLD_N +170 0x0050 //TX_DT_HOLD_N +171 0x03E8 //TX_DT2_HOLD_N +172 0x0000 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x0000 //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0000 //TX_FRQ_LIN_LEN +184 0x0000 //TX_FRQ_AEC_LEN_RHO +185 0x0000 //TX_MU0_UNP_FRQ_AEC +186 0x0000 //TX_MU0_PTD_FRQ_AEC +187 0x0000 //TX_MINENOISETH +188 0x0000 //TX_MU0_RE_EST +189 0x0000 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x0000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x7333 //TX_DTD_THR1_0 +198 0x7333 //TX_DTD_THR1_1 +199 0x7333 //TX_DTD_THR1_2 +200 0x7333 //TX_DTD_THR1_3 +201 0x7333 //TX_DTD_THR1_4 +202 0x7333 //TX_DTD_THR1_5 +203 0x7333 //TX_DTD_THR1_6 +204 0x0CCD //TX_DTD_THR2_0 +205 0x0CCD //TX_DTD_THR2_1 +206 0x0CCD //TX_DTD_THR2_2 +207 0x0CCD //TX_DTD_THR2_3 +208 0x0CCD //TX_DTD_THR2_4 +209 0x0CCD //TX_DTD_THR2_5 +210 0x0CCD //TX_DTD_THR2_6 +211 0x7FFF //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x0400 //TX_DT_CUT_K +214 0x0000 //TX_DT_CUT_THR +215 0x0000 //TX_COMFORT_G +216 0x0000 //TX_POWER_YOUT_TH +217 0x0000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x0400 //TX_ADPT_STRICT_L +222 0x0200 //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x0800 //TX_B_POST_FILT_ECHO_L +229 0x0800 //TX_B_POST_FILT_ECHO_H +230 0x0000 //TX_MIN_G_CTRL_ECHO +231 0x7FFF //TX_B_LESSCUT_RTO_ECHO +232 0x0000 //TX_EPD_OFFSET_00 +233 0x0000 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x0000 //TX_MIN_EQ_RE_EST_13 +237 0x0000 //TX_DTD_THR1_7 +238 0x0000 //TX_DTD_THR2_7 +239 0x0000 //TX_DT_RESRV_7 +240 0x0000 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xFA00 //TX_THR_SN_EST_0 +243 0xF400 //TX_THR_SN_EST_1 +244 0xF800 //TX_THR_SN_EST_2 +245 0xF600 //TX_THR_SN_EST_3 +246 0xF800 //TX_THR_SN_EST_4 +247 0xF800 //TX_THR_SN_EST_5 +248 0xF800 //TX_THR_SN_EST_6 +249 0xF800 //TX_THR_SN_EST_7 +250 0x0100 //TX_DELTA_THR_SN_EST_0 +251 0x0100 //TX_DELTA_THR_SN_EST_1 +252 0x0100 //TX_DELTA_THR_SN_EST_2 +253 0x0200 //TX_DELTA_THR_SN_EST_3 +254 0x0200 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0000 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x4000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x4000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0A00 //TX_N_SN_EST +267 0x0000 //TX_INBEAM_T +268 0x0000 //TX_INBEAMHOLDT +269 0x1FFF //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x1000 //TX_NE_RTO_TH_L +274 0x1000 //TX_MAINREFRTOH_TH_H +275 0x1000 //TX_MAINREFRTOH_TH_L +276 0x2000 //TX_MAINREFRTO_TH_H +277 0x1400 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x0000 //TX_B_POST_FLT_0 +280 0x0000 //TX_B_POST_FLT_1 +281 0x001A //TX_NS_LVL_CTRL_0 +282 0x0014 //TX_NS_LVL_CTRL_1 +283 0x0014 //TX_NS_LVL_CTRL_2 +284 0x000C //TX_NS_LVL_CTRL_3 +285 0x000C //TX_NS_LVL_CTRL_4 +286 0x000C //TX_NS_LVL_CTRL_5 +287 0x001A //TX_NS_LVL_CTRL_6 +288 0x000C //TX_NS_LVL_CTRL_7 +289 0x000E //TX_MIN_GAIN_S_0 +290 0x0014 //TX_MIN_GAIN_S_1 +291 0x0014 //TX_MIN_GAIN_S_2 +292 0x0014 //TX_MIN_GAIN_S_3 +293 0x0014 //TX_MIN_GAIN_S_4 +294 0x0014 //TX_MIN_GAIN_S_5 +295 0x0014 //TX_MIN_GAIN_S_6 +296 0x0014 //TX_MIN_GAIN_S_7 +297 0x0000 //TX_NMOS_SUP +298 0x0064 //TX_NS_MAX_PRI_SNR_TH +299 0x7FFF //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x7FFF //TX_SNRI_SUP_1 +302 0x7FFF //TX_SNRI_SUP_2 +303 0x4000 //TX_SNRI_SUP_3 +304 0x4000 //TX_SNRI_SUP_4 +305 0x4000 //TX_SNRI_SUP_5 +306 0x7FFF //TX_SNRI_SUP_6 +307 0x4000 //TX_SNRI_SUP_7 +308 0x1200 //TX_THR_LFNS +309 0x0147 //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x7FFF //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x7FFF //TX_A_POST_FILT_1 +314 0x4000 //TX_A_POST_FILT_S_0 +315 0x1000 //TX_A_POST_FILT_S_1 +316 0x1000 //TX_A_POST_FILT_S_2 +317 0x6666 //TX_A_POST_FILT_S_3 +318 0x6666 //TX_A_POST_FILT_S_4 +319 0x6666 //TX_A_POST_FILT_S_5 +320 0x199A //TX_A_POST_FILT_S_6 +321 0x6666 //TX_A_POST_FILT_S_7 +322 0x2000 //TX_B_POST_FILT_0 +323 0x2000 //TX_B_POST_FILT_1 +324 0x2000 //TX_B_POST_FILT_2 +325 0x2000 //TX_B_POST_FILT_3 +326 0x2000 //TX_B_POST_FILT_4 +327 0x2000 //TX_B_POST_FILT_5 +328 0x2000 //TX_B_POST_FILT_6 +329 0x2000 //TX_B_POST_FILT_7 +330 0x7FFF //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x7FFF //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7E00 //TX_LAMBDA_PFILT +339 0x7E00 //TX_LAMBDA_PFILT_S_0 +340 0x7E00 //TX_LAMBDA_PFILT_S_1 +341 0x7E00 //TX_LAMBDA_PFILT_S_2 +342 0x7E00 //TX_LAMBDA_PFILT_S_3 +343 0x7E00 //TX_LAMBDA_PFILT_S_4 +344 0x7E00 //TX_LAMBDA_PFILT_S_5 +345 0x7E00 //TX_LAMBDA_PFILT_S_6 +346 0x7E00 //TX_LAMBDA_PFILT_S_7 +347 0x0010 //TX_K_PEPPER +348 0x0400 //TX_A_PEPPER +349 0x0000 //TX_K_PEPPER_HF +350 0x0000 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x4000 //TX_HMNC_BST_THR +353 0x0000 //TX_DT_BINVAD_TH_0 +354 0x0000 //TX_DT_BINVAD_TH_1 +355 0x0000 //TX_DT_BINVAD_TH_2 +356 0x0000 //TX_DT_BINVAD_TH_3 +357 0x0000 //TX_DT_BINVAD_ENDF +358 0x0000 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0001 //TX_BF_SGRAD_FLG +362 0x0000 //TX_BF_DVG_TH +363 0x0000 //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x05A0 //TX_NDETCT +367 0x003B //TX_NOISE_TH_0 +368 0x1388 //TX_NOISE_TH_0_2 +369 0x3A98 //TX_NOISE_TH_0_3 +370 0x0C80 //TX_NOISE_TH_1 +371 0x0032 //TX_NOISE_TH_2 +372 0x3D54 //TX_NOISE_TH_3 +373 0x012C //TX_NOISE_TH_4 +374 0x07D0 //TX_NOISE_TH_5 +375 0x6590 //TX_NOISE_TH_5_2 +376 0x7FFF //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x00C8 //TX_NOISE_TH_6 +379 0x00C8 //TX_MINENOISE_TH +380 0xD508 //TX_MORENS_TFMASK_TH +381 0x0001 //TX_DRC_QUIET_FLOOR +382 0x3A98 //TX_RATIODTL_CUT_TH +383 0x0DAC //TX_DT_CUT_K1 +384 0x6400 //TX_OUT_ENER_S_TH_CLEAN +385 0x6400 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x6400 //TX_OUT_ENER_S_TH_NOISY +387 0x6400 //TX_OUT_ENER_TH_NOISE +388 0x7D00 //TX_OUT_ENER_TH_SPEECH +389 0x0000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x7FFF //TX_POST_MASK_SUP_HSNE +392 0x1388 //TX_TAIL_DET_TH +393 0x4000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0080 //TX_SUPHIGH_TH +396 0x0000 //TX_MASK_G_R +397 0x0000 //TX_EXTRA_NS_L +398 0x1800 //TX_C_POST_FLT_MASK +399 0x7FFF //TX_A_POST_FLT_WNS +400 0x0000 //TX_MIN_G_LOW300HZ +401 0x0010 //TX_MAXLEVEL_CNG +402 0x0000 //TX_STN_NOISE_TH +403 0x0000 //TX_POST_MASK_SUP +404 0x0000 //TX_POST_MASK_ADJUST +405 0x0014 //TX_NS_ENOISE_MIC0_TH +406 0x0032 //TX_MINENOISE_MIC0_TH +407 0x0226 //TX_MINENOISE_MIC0_S_TH +408 0x2879 //TX_MIN_G_CTRL_SSNS +409 0x0400 //TX_METAL_RTO_THR +410 0x0080 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x2000 //TX_RHO_UPB +415 0x0020 //TX_N_HOLD_HS +416 0x0009 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0000 //TX_EXTRA_GAIN_MICBLOCK +419 0x0333 //TX_THR_STD_NSR +420 0x0219 //TX_THR_STD_PLH +421 0x09C4 //TX_N_HOLD_STD +422 0x0166 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0800 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x0000 //TX_SB_RTO_MEAN_TH_RUB +428 0x2000 //TX_WTA_EN_RTO_TH +429 0x1400 //TX_TOP_ENER_TH_F +430 0x0064 //TX_DESIRED_TALK_HOLDT +431 0x1000 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0000 //TX_HS_VAD_BIN +435 0x0000 //TX_THR_VAD_HS +436 0x0000 //TX_MEAN_RTO_MIN_TH2 +437 0x0000 //TX_SILENCE_T +438 0x4000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x099A //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x001E //TX_DOA_VAD_THR_1 +445 0x001E //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x00B4 //TX_SRC_DOA_RNG_HIGH_0B +453 0x005A //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x00B4 //TX_SRC_DOA_RNG_HIGH_0C +456 0x005A //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x00B4 //TX_SRC_DOA_RNG_HIGH_0D +459 0x005A //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0172 //TX_BF_HOLDOFF_T +473 0x8000 //TX_DOA_COST_FACTOR +474 0x0D9A //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x071C //TX_DOA_TRACK_HT +477 0x0280 //TX_N1_HOLD_HF +478 0x0140 //TX_N2_HOLD_HF +479 0x2AAB //TX_BF_RESET_THR_HF +480 0x4000 //TX_DOA_SMOOTH +481 0x0000 //TX_MU_BF +482 0x0200 //TX_BF_MU_LF_B2 +483 0x0000 //TX_BF_FC_END_BIN_B2 +484 0x0000 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0000 //TX_N_DOA_SEED +488 0x0000 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x0000 //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x0000 //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x0000 //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x0168 //TX_NOR_OFF_THR +498 0x0CCD //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0004 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0230 //TX_NOR_OFF_TH1 +503 0xD333 //TX_WIDE_MASK_TH +504 0x4650 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x6000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x000A //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x6666 //TX_MICTOBFGAIN0 +513 0x0014 //TX_FASTMUE_TH +514 0xC000 //TX_DEREVERB_LF_MU +515 0xC000 //TX_DEREVERB_HF_MU +516 0xCCCC //TX_DEREVERB_DELAY +517 0xD999 //TX_DEREVERB_COEF_LEN +518 0x1F40 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x7000 //TX_GSC_RTOH_TH +523 0x0064 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x0000 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0028 //TX_SNR_THR +531 0x03E8 //TX_ENGY_THR +532 0x0000 //TX_CORR_HIGH_TH +533 0x0000 //TX_ENGY_THR_2 +534 0x0000 //TX_MEAN_RTO_THR +535 0x0000 //TX_WNS_ENOISE_MIC0_TH +536 0x0000 //TX_RATIOMICL_TH +537 0x0000 //TX_CALIG_HS +538 0x000A //TX_LVL_CTRL +539 0x0000 //TX_WIND_SUPRTO +540 0x0000 //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x0000 //TX_RATIOMICH_TH +543 0x0000 //TX_WIND_INBEAM_L_TH +544 0x0000 //TX_WIND_INBEAM_H_TH +545 0x0000 //TX_WNS_RESRV_0 +546 0x0000 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0000 //TX_BF_LESSCUT_BBIN +554 0x0000 //TX_BF_LESSCUT_EBIN +555 0x0000 //TX_POSTBFB0 +556 0x0000 //TX_POSTBFB +557 0x0000 //TX_POSTBFE +558 0x0000 //TX_SPEECH_SNR_TH +559 0x0000 //TX_PB_MAX_PRI_SNR_TH +560 0x0000 //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0020 //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4848 //TX_FDEQ_GAIN_5 +573 0x4848 //TX_FDEQ_GAIN_6 +574 0x4848 //TX_FDEQ_GAIN_7 +575 0x4848 //TX_FDEQ_GAIN_8 +576 0x4848 //TX_FDEQ_GAIN_9 +577 0x4848 //TX_FDEQ_GAIN_10 +578 0x4848 //TX_FDEQ_GAIN_11 +579 0x4848 //TX_FDEQ_GAIN_12 +580 0x4848 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0000 //TX_FDEQ_BIN_0 +592 0x0000 //TX_FDEQ_BIN_1 +593 0x0000 //TX_FDEQ_BIN_2 +594 0x0000 //TX_FDEQ_BIN_3 +595 0x0000 //TX_FDEQ_BIN_4 +596 0x0000 //TX_FDEQ_BIN_5 +597 0x0000 //TX_FDEQ_BIN_6 +598 0x0000 //TX_FDEQ_BIN_7 +599 0x0000 //TX_FDEQ_BIN_8 +600 0x0000 //TX_FDEQ_BIN_9 +601 0x0000 //TX_FDEQ_BIN_10 +602 0x0000 //TX_FDEQ_BIN_11 +603 0x0000 //TX_FDEQ_BIN_12 +604 0x0000 //TX_FDEQ_BIN_13 +605 0x0000 //TX_FDEQ_BIN_14 +606 0x0000 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4848 //TX_PREEQ_GAIN_MIC0_8 +626 0x4848 //TX_PREEQ_GAIN_MIC0_9 +627 0x4848 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0000 //TX_PREEQ_BIN_MIC0_0 +642 0x0000 //TX_PREEQ_BIN_MIC0_1 +643 0x0000 //TX_PREEQ_BIN_MIC0_2 +644 0x0000 //TX_PREEQ_BIN_MIC0_3 +645 0x0000 //TX_PREEQ_BIN_MIC0_4 +646 0x0000 //TX_PREEQ_BIN_MIC0_5 +647 0x0000 //TX_PREEQ_BIN_MIC0_6 +648 0x0000 //TX_PREEQ_BIN_MIC0_7 +649 0x0000 //TX_PREEQ_BIN_MIC0_8 +650 0x0000 //TX_PREEQ_BIN_MIC0_9 +651 0x0000 //TX_PREEQ_BIN_MIC0_10 +652 0x0000 //TX_PREEQ_BIN_MIC0_11 +653 0x0000 //TX_PREEQ_BIN_MIC0_12 +654 0x0000 //TX_PREEQ_BIN_MIC0_13 +655 0x0000 //TX_PREEQ_BIN_MIC0_14 +656 0x0000 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0000 //TX_PREEQ_BIN_MIC1_0 +691 0x0000 //TX_PREEQ_BIN_MIC1_1 +692 0x0000 //TX_PREEQ_BIN_MIC1_2 +693 0x0000 //TX_PREEQ_BIN_MIC1_3 +694 0x0000 //TX_PREEQ_BIN_MIC1_4 +695 0x0000 //TX_PREEQ_BIN_MIC1_5 +696 0x0000 //TX_PREEQ_BIN_MIC1_6 +697 0x0000 //TX_PREEQ_BIN_MIC1_7 +698 0x0000 //TX_PREEQ_BIN_MIC1_8 +699 0x0000 //TX_PREEQ_BIN_MIC1_9 +700 0x0000 //TX_PREEQ_BIN_MIC1_10 +701 0x0000 //TX_PREEQ_BIN_MIC1_11 +702 0x0000 //TX_PREEQ_BIN_MIC1_12 +703 0x0000 //TX_PREEQ_BIN_MIC1_13 +704 0x0000 //TX_PREEQ_BIN_MIC1_14 +705 0x0000 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0000 //TX_PREEQ_BIN_MIC2_0 +740 0x0000 //TX_PREEQ_BIN_MIC2_1 +741 0x0000 //TX_PREEQ_BIN_MIC2_2 +742 0x0000 //TX_PREEQ_BIN_MIC2_3 +743 0x0000 //TX_PREEQ_BIN_MIC2_4 +744 0x0000 //TX_PREEQ_BIN_MIC2_5 +745 0x0000 //TX_PREEQ_BIN_MIC2_6 +746 0x0000 //TX_PREEQ_BIN_MIC2_7 +747 0x0000 //TX_PREEQ_BIN_MIC2_8 +748 0x0000 //TX_PREEQ_BIN_MIC2_9 +749 0x0000 //TX_PREEQ_BIN_MIC2_10 +750 0x0000 //TX_PREEQ_BIN_MIC2_11 +751 0x0000 //TX_PREEQ_BIN_MIC2_12 +752 0x0000 //TX_PREEQ_BIN_MIC2_13 +753 0x0000 //TX_PREEQ_BIN_MIC2_14 +754 0x0000 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x2000 //TX_NND_WEIGHT +765 0x0064 //TX_MIC_CALIBRATION_0 +766 0x006A //TX_MIC_CALIBRATION_1 +767 0x006A //TX_MIC_CALIBRATION_2 +768 0x006B //TX_MIC_CALIBRATION_3 +769 0x0048 //TX_MIC_PWR_BIAS_0 +770 0x003C //TX_MIC_PWR_BIAS_1 +771 0x003C //TX_MIC_PWR_BIAS_2 +772 0x003C //TX_MIC_PWR_BIAS_3 +773 0x0000 //TX_GAIN_LIMIT_0 +774 0x0009 //TX_GAIN_LIMIT_1 +775 0x000C //TX_GAIN_LIMIT_2 +776 0x000F //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F3D //TX_BVE_NOVAD0_ALPHAUP +783 0x3000 //TX_TDDRC_ALPHA_UP_01 +784 0x3000 //TX_TDDRC_ALPHA_UP_02 +785 0x3000 //TX_TDDRC_ALPHA_UP_03 +786 0x3000 //TX_TDDRC_ALPHA_UP_04 +787 0x7FB0 //TX_TDDRC_ALPHA_DWN_01 +788 0x7FB0 //TX_TDDRC_ALPHA_DWN_02 +789 0x7FB0 //TX_TDDRC_ALPHA_DWN_03 +790 0x7FB0 //TX_TDDRC_ALPHA_DWN_04 +791 0x65AD //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0002 //TX_DEADMIC_SILENCE_TH +817 0x0147 //TX_MIC_DEGRADE_TH +818 0x0078 //TX_DEADMIC_CNT +819 0x0078 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x0000 //TX_KS_NOISEPASTE_FACTOR +824 0x0000 //TX_KS_CONFIG +825 0x0000 //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x0000 //TX_FFP_FP_K_METAL +834 0x0000 //TX_A_POST_FLT_FP +835 0x0000 //TX_RTO_OUTBEAM_TH +836 0x0000 //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0000 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0000 //TX_FFP_RESRV_2 +849 0x0000 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0002 //TX_FILTINDX +854 0x0000 //TX_TDDRC_THRD_0 +855 0x0000 //TX_TDDRC_THRD_1 +856 0x0E80 //TX_TDDRC_THRD_2 +857 0x3800 //TX_TDDRC_THRD_3 +858 0x2A00 //TX_TDDRC_SLANT_0 +859 0x6E00 //TX_TDDRC_SLANT_1 +860 0x3000 //TX_TDDRC_ALPHA_UP_00 +861 0x7FB0 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x0000 //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0000 //TX_TDDRC_SMT_W +866 0x0100 //TX_TDDRC_DRC_GAIN +867 0x0000 //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x1EB8 //TX_TFMASKLTH +870 0x170A //TX_TFMASKLTHL +871 0x7FFF //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0x0CCD //TX_TFMASKTH_BLESSCUT +876 0x4000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x0000 //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x0000 //TX_FASTNS_OUTIN_TH +884 0x0000 //TX_FASTNS_TFMASK_TH +885 0x0000 //TX_FASTNS_TFMASKBIN_TH1 +886 0x0000 //TX_FASTNS_TFMASKBIN_TH2 +887 0x0000 //TX_FASTNS_TFMASKBIN_TH3 +888 0x00C8 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x051F //TX_POSTSSA_MIN_G_VR_MASK +891 0x4000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x2339 //TX_SENDFUNC_REG_MICMUTE +898 0x0021 //TX_SENDFUNC_REG_MICMUTE1 +899 0x02BC //TX_MICMUTE_RATIO_THR +900 0x0140 //TX_MICMUTE_AMP_THR +901 0x0004 //TX_MICMUTE_HPF_IND +902 0x00C0 //TX_MICMUTE_LOG_EYR_TH +903 0x0008 //TX_MICMUTE_CVG_TIME +904 0x0008 //TX_MICMUTE_RELEASE_TIME +905 0x01FE //TX_MIC_VOLUME_MIC0MUTE +906 0x0020 //TX_MICMUTE_EPD_OFFSET_0 +907 0x001E //TX_MICMUTE_FRQ_AEC_L +908 0x7999 //TX_MICMUTE_EAD_THR +909 0x7FFF //TX_MICMUTE_LAMBDA_CB_NLE +910 0x7FFF //TX_MICMUTE_LAMBDA_RE_EST +911 0x4000 //TX_DTD_THR1_MICMUTE_0 +912 0x7000 //TX_DTD_THR1_MICMUTE_1 +913 0x7FFF //TX_DTD_THR1_MICMUTE_2 +914 0x7FFF //TX_DTD_THR1_MICMUTE_3 +915 0x6CCC //TX_DTD_THR2_MICMUTE_0 +916 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x1000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x4000 //TX_MICMUTE_C_POST_FLT +922 0x03E8 //TX_MICMUTE_DT_CUT_K +923 0x0001 //TX_MICMUTE_DT_CUT_THR +924 0x03E8 //TX_MICMUTE_DT_CUT_K2 +925 0x0001 //TX_MICMUTE_DT_CUT_THR2 +926 0x0064 //TX_MICMUTE_DT2_HOLD_N +927 0x1000 //TX_MICMUTE_RATIODTH_THCUT +928 0x1000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x7FFF //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0400 //TX_MICMUTE_C_POST_FLT_MASK +931 0x7999 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0258 //TX_MICMUTE_DT_CUT_K1 +933 0x0800 //TX_MICMUTE_N2_SN_EST +934 0xFC00 //TX_MICMUTE_THR_SN_EST_0 +935 0x001C //TX_MICMUTE_MIN_G_CTRL_0 +936 0x6000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x7000 //TX_MICMUTE_B_POST_FILT_0 +938 0x2710 //TX_MIC1RUB_AMP_THR +939 0x0010 //TX_MIC1MUTE_RATIO_THR +940 0x0450 //TX_MIC1MUTE_AMP_THR +941 0x0008 //TX_MIC1MUTE_CVG_TIME +942 0x0008 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x243C //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0000 //RX_SAMPLINGFREQ_SIG +3 0x0000 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +10 0x0403 //RX_PGA +11 0x7646 //RX_A_HP +12 0x4000 //RX_B_PE +13 0x7800 //RX_THR_PITCH_DET_0 +14 0x7000 //RX_THR_PITCH_DET_1 +15 0x6000 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0400 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x0010 //RX_NS_LVL_CTRL +23 0xF800 //RX_THR_SN_EST +24 0x7E00 //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x4000 //RX_TDDRC_ALPHA_DWN_2 +29 0x4000 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x4000 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0014 //RX_FDEQ_SUBNUM +39 0x8080 //RX_FDEQ_GAIN_0 +40 0x8054 //RX_FDEQ_GAIN_1 +41 0x5050 //RX_FDEQ_GAIN_2 +42 0x5058 //RX_FDEQ_GAIN_3 +43 0x5C70 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x484C //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x485A //RX_FDEQ_GAIN_8 +48 0x5A58 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0604 //RX_FDEQ_BIN_4 +68 0x0406 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x0060 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x0600 //RX_FDDRC_THRD_2_0 +95 0x0600 //RX_FDDRC_THRD_2_1 +96 0x0600 //RX_FDDRC_THRD_2_2 +97 0x0600 //RX_FDDRC_THRD_2_3 +98 0x0800 //RX_FDDRC_THRD_3_0 +99 0x0800 //RX_FDDRC_THRD_3_1 +100 0x0800 //RX_FDDRC_THRD_3_2 +101 0x0800 //RX_FDDRC_THRD_3_3 +102 0x0000 //RX_FDDRC_SLANT_0_0 +103 0x0000 //RX_FDDRC_SLANT_0_1 +104 0x0000 //RX_FDDRC_SLANT_0_2 +105 0x0000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0005 //RX_FILTINDX +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0780 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x1194 //RX_TPKA_FP +127 0x0400 //RX_MIN_G_FP +128 0x0800 //RX_MAX_G_FP +129 0x0015 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x4000 //RX_TDDRC_ALPHA_DWN_2 +29 0x4000 //RX_TDDRC_ALPHA_DWN_3 +32 0x4000 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0780 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x8080 //RX_FDEQ_GAIN_0 +40 0x8050 //RX_FDEQ_GAIN_1 +41 0x4840 //RX_FDEQ_GAIN_2 +42 0x4040 //RX_FDEQ_GAIN_3 +43 0x4C68 //RX_FDEQ_GAIN_4 +44 0x403C //RX_FDEQ_GAIN_5 +45 0x3C38 //RX_FDEQ_GAIN_6 +46 0x3430 //RX_FDEQ_GAIN_7 +47 0x303C //RX_FDEQ_GAIN_8 +48 0x4C50 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0703 //RX_FDEQ_BIN_4 +68 0x0406 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x0060 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x0600 //RX_FDDRC_THRD_2_0 +95 0x0600 //RX_FDDRC_THRD_2_1 +96 0x0600 //RX_FDDRC_THRD_2_2 +97 0x0600 //RX_FDDRC_THRD_2_3 +98 0x0800 //RX_FDDRC_THRD_3_0 +99 0x0800 //RX_FDDRC_THRD_3_1 +100 0x0800 //RX_FDDRC_THRD_3_2 +101 0x0800 //RX_FDDRC_THRD_3_3 +102 0x0000 //RX_FDDRC_SLANT_0_0 +103 0x0000 //RX_FDDRC_SLANT_0_1 +104 0x0000 //RX_FDDRC_SLANT_0_2 +105 0x0000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0012 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x4000 //RX_TDDRC_ALPHA_DWN_2 +29 0x4000 //RX_TDDRC_ALPHA_DWN_3 +32 0x4000 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0780 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x8080 //RX_FDEQ_GAIN_0 +40 0x8050 //RX_FDEQ_GAIN_1 +41 0x4840 //RX_FDEQ_GAIN_2 +42 0x4040 //RX_FDEQ_GAIN_3 +43 0x4C68 //RX_FDEQ_GAIN_4 +44 0x403C //RX_FDEQ_GAIN_5 +45 0x3C38 //RX_FDEQ_GAIN_6 +46 0x3430 //RX_FDEQ_GAIN_7 +47 0x303C //RX_FDEQ_GAIN_8 +48 0x4C50 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0703 //RX_FDEQ_BIN_4 +68 0x0406 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x0060 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x0600 //RX_FDDRC_THRD_2_0 +95 0x0600 //RX_FDDRC_THRD_2_1 +96 0x0600 //RX_FDDRC_THRD_2_2 +97 0x0600 //RX_FDDRC_THRD_2_3 +98 0x0800 //RX_FDDRC_THRD_3_0 +99 0x0800 //RX_FDDRC_THRD_3_1 +100 0x0800 //RX_FDDRC_THRD_3_2 +101 0x0800 //RX_FDDRC_THRD_3_3 +102 0x0000 //RX_FDDRC_SLANT_0_0 +103 0x0000 //RX_FDDRC_SLANT_0_1 +104 0x0000 //RX_FDDRC_SLANT_0_2 +105 0x0000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x001B //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x4000 //RX_TDDRC_ALPHA_DWN_2 +29 0x4000 //RX_TDDRC_ALPHA_DWN_3 +32 0x4000 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0780 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x8080 //RX_FDEQ_GAIN_0 +40 0x8050 //RX_FDEQ_GAIN_1 +41 0x4840 //RX_FDEQ_GAIN_2 +42 0x4040 //RX_FDEQ_GAIN_3 +43 0x4C68 //RX_FDEQ_GAIN_4 +44 0x403C //RX_FDEQ_GAIN_5 +45 0x3C38 //RX_FDEQ_GAIN_6 +46 0x3430 //RX_FDEQ_GAIN_7 +47 0x303C //RX_FDEQ_GAIN_8 +48 0x4C50 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0703 //RX_FDEQ_BIN_4 +68 0x0406 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x0060 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x0600 //RX_FDDRC_THRD_2_0 +95 0x0600 //RX_FDDRC_THRD_2_1 +96 0x0600 //RX_FDDRC_THRD_2_2 +97 0x0600 //RX_FDDRC_THRD_2_3 +98 0x0800 //RX_FDDRC_THRD_3_0 +99 0x0800 //RX_FDDRC_THRD_3_1 +100 0x0800 //RX_FDDRC_THRD_3_2 +101 0x0800 //RX_FDDRC_THRD_3_3 +102 0x0000 //RX_FDDRC_SLANT_0_0 +103 0x0000 //RX_FDDRC_SLANT_0_1 +104 0x0000 //RX_FDDRC_SLANT_0_2 +105 0x0000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0026 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x4000 //RX_TDDRC_ALPHA_DWN_2 +29 0x4000 //RX_TDDRC_ALPHA_DWN_3 +32 0x4000 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0780 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x8080 //RX_FDEQ_GAIN_0 +40 0x8050 //RX_FDEQ_GAIN_1 +41 0x4840 //RX_FDEQ_GAIN_2 +42 0x4040 //RX_FDEQ_GAIN_3 +43 0x4C68 //RX_FDEQ_GAIN_4 +44 0x403C //RX_FDEQ_GAIN_5 +45 0x3C38 //RX_FDEQ_GAIN_6 +46 0x3430 //RX_FDEQ_GAIN_7 +47 0x303C //RX_FDEQ_GAIN_8 +48 0x4C50 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0703 //RX_FDEQ_BIN_4 +68 0x0406 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x0060 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x0600 //RX_FDDRC_THRD_2_0 +95 0x0600 //RX_FDDRC_THRD_2_1 +96 0x0600 //RX_FDDRC_THRD_2_2 +97 0x0600 //RX_FDDRC_THRD_2_3 +98 0x0800 //RX_FDDRC_THRD_3_0 +99 0x0800 //RX_FDDRC_THRD_3_1 +100 0x0800 //RX_FDDRC_THRD_3_2 +101 0x0800 //RX_FDDRC_THRD_3_3 +102 0x0000 //RX_FDDRC_SLANT_0_0 +103 0x0000 //RX_FDDRC_SLANT_0_1 +104 0x0000 //RX_FDDRC_SLANT_0_2 +105 0x0000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0037 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x4000 //RX_TDDRC_ALPHA_DWN_2 +29 0x4000 //RX_TDDRC_ALPHA_DWN_3 +32 0x4000 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0D56 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x8080 //RX_FDEQ_GAIN_0 +40 0x8050 //RX_FDEQ_GAIN_1 +41 0x4840 //RX_FDEQ_GAIN_2 +42 0x4040 //RX_FDEQ_GAIN_3 +43 0x4470 //RX_FDEQ_GAIN_4 +44 0x383C //RX_FDEQ_GAIN_5 +45 0x3C3C //RX_FDEQ_GAIN_6 +46 0x3434 //RX_FDEQ_GAIN_7 +47 0x344C //RX_FDEQ_GAIN_8 +48 0x585C //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0703 //RX_FDEQ_BIN_4 +68 0x0406 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x0060 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x0600 //RX_FDDRC_THRD_2_0 +95 0x0600 //RX_FDDRC_THRD_2_1 +96 0x0600 //RX_FDDRC_THRD_2_2 +97 0x0600 //RX_FDDRC_THRD_2_3 +98 0x0800 //RX_FDDRC_THRD_3_0 +99 0x0800 //RX_FDDRC_THRD_3_1 +100 0x0800 //RX_FDDRC_THRD_3_2 +101 0x0800 //RX_FDDRC_THRD_3_3 +102 0x0000 //RX_FDDRC_SLANT_0_0 +103 0x0000 //RX_FDDRC_SLANT_0_1 +104 0x0000 //RX_FDDRC_SLANT_0_2 +105 0x0000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x002C //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x4000 //RX_TDDRC_ALPHA_DWN_2 +29 0x4000 //RX_TDDRC_ALPHA_DWN_3 +32 0x4000 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0D56 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x8080 //RX_FDEQ_GAIN_0 +40 0x8050 //RX_FDEQ_GAIN_1 +41 0x4840 //RX_FDEQ_GAIN_2 +42 0x4040 //RX_FDEQ_GAIN_3 +43 0x4470 //RX_FDEQ_GAIN_4 +44 0x383C //RX_FDEQ_GAIN_5 +45 0x3C3C //RX_FDEQ_GAIN_6 +46 0x3434 //RX_FDEQ_GAIN_7 +47 0x344C //RX_FDEQ_GAIN_8 +48 0x585C //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0703 //RX_FDEQ_BIN_4 +68 0x0406 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x0060 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x0600 //RX_FDDRC_THRD_2_0 +95 0x0600 //RX_FDDRC_THRD_2_1 +96 0x0600 //RX_FDDRC_THRD_2_2 +97 0x0600 //RX_FDDRC_THRD_2_3 +98 0x0800 //RX_FDDRC_THRD_3_0 +99 0x0800 //RX_FDDRC_THRD_3_1 +100 0x0800 //RX_FDDRC_THRD_3_2 +101 0x0800 //RX_FDDRC_THRD_3_3 +102 0x0000 //RX_FDDRC_SLANT_0_0 +103 0x0000 //RX_FDDRC_SLANT_0_1 +104 0x0000 //RX_FDDRC_SLANT_0_2 +105 0x0000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0051 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x1000 //RX_TDDRC_ALPHA_UP_1 +7 0x1000 //RX_TDDRC_ALPHA_UP_2 +8 0x1000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x4000 //RX_TDDRC_ALPHA_DWN_2 +29 0x4000 //RX_TDDRC_ALPHA_DWN_3 +32 0x4000 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x1000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0D56 //RX_TDDRC_DRC_GAIN +38 0x0014 //RX_FDEQ_SUBNUM +39 0x8080 //RX_FDEQ_GAIN_0 +40 0x8050 //RX_FDEQ_GAIN_1 +41 0x4840 //RX_FDEQ_GAIN_2 +42 0x4040 //RX_FDEQ_GAIN_3 +43 0x4470 //RX_FDEQ_GAIN_4 +44 0x383C //RX_FDEQ_GAIN_5 +45 0x3C3C //RX_FDEQ_GAIN_6 +46 0x3434 //RX_FDEQ_GAIN_7 +47 0x344C //RX_FDEQ_GAIN_8 +48 0x585C //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0703 //RX_FDEQ_BIN_4 +68 0x0406 //RX_FDEQ_BIN_5 +69 0x0708 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D08 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x0060 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x0600 //RX_FDDRC_THRD_2_0 +95 0x0600 //RX_FDDRC_THRD_2_1 +96 0x0600 //RX_FDDRC_THRD_2_2 +97 0x0600 //RX_FDDRC_THRD_2_3 +98 0x0800 //RX_FDDRC_THRD_3_0 +99 0x0800 //RX_FDDRC_THRD_3_1 +100 0x0800 //RX_FDDRC_THRD_3_2 +101 0x0800 //RX_FDDRC_THRD_3_3 +102 0x0000 //RX_FDDRC_SLANT_0_0 +103 0x0000 //RX_FDDRC_SLANT_0_1 +104 0x0000 //RX_FDDRC_SLANT_0_2 +105 0x0000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x243C //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0000 //RX_SAMPLINGFREQ_SIG +160 0x0000 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +167 0x0403 //RX_PGA +168 0x7646 //RX_A_HP +169 0x4000 //RX_B_PE +170 0x7800 //RX_THR_PITCH_DET_0 +171 0x7000 //RX_THR_PITCH_DET_1 +172 0x6000 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0400 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x0010 //RX_NS_LVL_CTRL +180 0xF800 //RX_THR_SN_EST +181 0x7E00 //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x4000 //RX_TDDRC_ALPHA_DWN_2 +186 0x4000 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x4000 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0014 //RX_FDEQ_SUBNUM +196 0x8080 //RX_FDEQ_GAIN_0 +197 0x8054 //RX_FDEQ_GAIN_1 +198 0x5050 //RX_FDEQ_GAIN_2 +199 0x5058 //RX_FDEQ_GAIN_3 +200 0x5C70 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x484C //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x485A //RX_FDEQ_GAIN_8 +205 0x5A58 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0604 //RX_FDEQ_BIN_4 +225 0x0406 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x0060 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x0600 //RX_FDDRC_THRD_2_0 +252 0x0600 //RX_FDDRC_THRD_2_1 +253 0x0600 //RX_FDDRC_THRD_2_2 +254 0x0600 //RX_FDDRC_THRD_2_3 +255 0x0800 //RX_FDDRC_THRD_3_0 +256 0x0800 //RX_FDDRC_THRD_3_1 +257 0x0800 //RX_FDDRC_THRD_3_2 +258 0x0800 //RX_FDDRC_THRD_3_3 +259 0x0000 //RX_FDDRC_SLANT_0_0 +260 0x0000 //RX_FDDRC_SLANT_0_1 +261 0x0000 //RX_FDDRC_SLANT_0_2 +262 0x0000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0005 //RX_FILTINDX +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0780 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x1194 //RX_TPKA_FP +284 0x0400 //RX_MIN_G_FP +285 0x0800 //RX_MAX_G_FP +286 0x0015 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x4000 //RX_TDDRC_ALPHA_DWN_2 +186 0x4000 //RX_TDDRC_ALPHA_DWN_3 +189 0x4000 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0780 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x8080 //RX_FDEQ_GAIN_0 +197 0x8050 //RX_FDEQ_GAIN_1 +198 0x4840 //RX_FDEQ_GAIN_2 +199 0x4040 //RX_FDEQ_GAIN_3 +200 0x4C68 //RX_FDEQ_GAIN_4 +201 0x403C //RX_FDEQ_GAIN_5 +202 0x3C38 //RX_FDEQ_GAIN_6 +203 0x3430 //RX_FDEQ_GAIN_7 +204 0x303C //RX_FDEQ_GAIN_8 +205 0x4C50 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0703 //RX_FDEQ_BIN_4 +225 0x0406 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x0060 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x0600 //RX_FDDRC_THRD_2_0 +252 0x0600 //RX_FDDRC_THRD_2_1 +253 0x0600 //RX_FDDRC_THRD_2_2 +254 0x0600 //RX_FDDRC_THRD_2_3 +255 0x0800 //RX_FDDRC_THRD_3_0 +256 0x0800 //RX_FDDRC_THRD_3_1 +257 0x0800 //RX_FDDRC_THRD_3_2 +258 0x0800 //RX_FDDRC_THRD_3_3 +259 0x0000 //RX_FDDRC_SLANT_0_0 +260 0x0000 //RX_FDDRC_SLANT_0_1 +261 0x0000 //RX_FDDRC_SLANT_0_2 +262 0x0000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0012 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x4000 //RX_TDDRC_ALPHA_DWN_2 +186 0x4000 //RX_TDDRC_ALPHA_DWN_3 +189 0x4000 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0780 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x8080 //RX_FDEQ_GAIN_0 +197 0x8050 //RX_FDEQ_GAIN_1 +198 0x4840 //RX_FDEQ_GAIN_2 +199 0x4040 //RX_FDEQ_GAIN_3 +200 0x4C68 //RX_FDEQ_GAIN_4 +201 0x403C //RX_FDEQ_GAIN_5 +202 0x3C38 //RX_FDEQ_GAIN_6 +203 0x3430 //RX_FDEQ_GAIN_7 +204 0x303C //RX_FDEQ_GAIN_8 +205 0x4C50 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0703 //RX_FDEQ_BIN_4 +225 0x0406 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x0060 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x0600 //RX_FDDRC_THRD_2_0 +252 0x0600 //RX_FDDRC_THRD_2_1 +253 0x0600 //RX_FDDRC_THRD_2_2 +254 0x0600 //RX_FDDRC_THRD_2_3 +255 0x0800 //RX_FDDRC_THRD_3_0 +256 0x0800 //RX_FDDRC_THRD_3_1 +257 0x0800 //RX_FDDRC_THRD_3_2 +258 0x0800 //RX_FDDRC_THRD_3_3 +259 0x0000 //RX_FDDRC_SLANT_0_0 +260 0x0000 //RX_FDDRC_SLANT_0_1 +261 0x0000 //RX_FDDRC_SLANT_0_2 +262 0x0000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x001B //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x4000 //RX_TDDRC_ALPHA_DWN_2 +186 0x4000 //RX_TDDRC_ALPHA_DWN_3 +189 0x4000 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0780 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x8080 //RX_FDEQ_GAIN_0 +197 0x8050 //RX_FDEQ_GAIN_1 +198 0x4840 //RX_FDEQ_GAIN_2 +199 0x4040 //RX_FDEQ_GAIN_3 +200 0x4C68 //RX_FDEQ_GAIN_4 +201 0x403C //RX_FDEQ_GAIN_5 +202 0x3C38 //RX_FDEQ_GAIN_6 +203 0x3430 //RX_FDEQ_GAIN_7 +204 0x303C //RX_FDEQ_GAIN_8 +205 0x4C50 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0703 //RX_FDEQ_BIN_4 +225 0x0406 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x0060 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x0600 //RX_FDDRC_THRD_2_0 +252 0x0600 //RX_FDDRC_THRD_2_1 +253 0x0600 //RX_FDDRC_THRD_2_2 +254 0x0600 //RX_FDDRC_THRD_2_3 +255 0x0800 //RX_FDDRC_THRD_3_0 +256 0x0800 //RX_FDDRC_THRD_3_1 +257 0x0800 //RX_FDDRC_THRD_3_2 +258 0x0800 //RX_FDDRC_THRD_3_3 +259 0x0000 //RX_FDDRC_SLANT_0_0 +260 0x0000 //RX_FDDRC_SLANT_0_1 +261 0x0000 //RX_FDDRC_SLANT_0_2 +262 0x0000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0026 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x4000 //RX_TDDRC_ALPHA_DWN_2 +186 0x4000 //RX_TDDRC_ALPHA_DWN_3 +189 0x4000 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0780 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x8080 //RX_FDEQ_GAIN_0 +197 0x8050 //RX_FDEQ_GAIN_1 +198 0x4840 //RX_FDEQ_GAIN_2 +199 0x4040 //RX_FDEQ_GAIN_3 +200 0x4C68 //RX_FDEQ_GAIN_4 +201 0x403C //RX_FDEQ_GAIN_5 +202 0x3C38 //RX_FDEQ_GAIN_6 +203 0x3430 //RX_FDEQ_GAIN_7 +204 0x303C //RX_FDEQ_GAIN_8 +205 0x4C50 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0703 //RX_FDEQ_BIN_4 +225 0x0406 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x0060 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x0600 //RX_FDDRC_THRD_2_0 +252 0x0600 //RX_FDDRC_THRD_2_1 +253 0x0600 //RX_FDDRC_THRD_2_2 +254 0x0600 //RX_FDDRC_THRD_2_3 +255 0x0800 //RX_FDDRC_THRD_3_0 +256 0x0800 //RX_FDDRC_THRD_3_1 +257 0x0800 //RX_FDDRC_THRD_3_2 +258 0x0800 //RX_FDDRC_THRD_3_3 +259 0x0000 //RX_FDDRC_SLANT_0_0 +260 0x0000 //RX_FDDRC_SLANT_0_1 +261 0x0000 //RX_FDDRC_SLANT_0_2 +262 0x0000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0037 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x4000 //RX_TDDRC_ALPHA_DWN_2 +186 0x4000 //RX_TDDRC_ALPHA_DWN_3 +189 0x4000 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0D56 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x8080 //RX_FDEQ_GAIN_0 +197 0x8050 //RX_FDEQ_GAIN_1 +198 0x4840 //RX_FDEQ_GAIN_2 +199 0x4040 //RX_FDEQ_GAIN_3 +200 0x4470 //RX_FDEQ_GAIN_4 +201 0x383C //RX_FDEQ_GAIN_5 +202 0x3C3C //RX_FDEQ_GAIN_6 +203 0x3434 //RX_FDEQ_GAIN_7 +204 0x344C //RX_FDEQ_GAIN_8 +205 0x585C //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0703 //RX_FDEQ_BIN_4 +225 0x0406 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x0060 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x0600 //RX_FDDRC_THRD_2_0 +252 0x0600 //RX_FDDRC_THRD_2_1 +253 0x0600 //RX_FDDRC_THRD_2_2 +254 0x0600 //RX_FDDRC_THRD_2_3 +255 0x0800 //RX_FDDRC_THRD_3_0 +256 0x0800 //RX_FDDRC_THRD_3_1 +257 0x0800 //RX_FDDRC_THRD_3_2 +258 0x0800 //RX_FDDRC_THRD_3_3 +259 0x0000 //RX_FDDRC_SLANT_0_0 +260 0x0000 //RX_FDDRC_SLANT_0_1 +261 0x0000 //RX_FDDRC_SLANT_0_2 +262 0x0000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x002C //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x4000 //RX_TDDRC_ALPHA_DWN_2 +186 0x4000 //RX_TDDRC_ALPHA_DWN_3 +189 0x4000 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0D56 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x8080 //RX_FDEQ_GAIN_0 +197 0x8050 //RX_FDEQ_GAIN_1 +198 0x4840 //RX_FDEQ_GAIN_2 +199 0x4040 //RX_FDEQ_GAIN_3 +200 0x4470 //RX_FDEQ_GAIN_4 +201 0x383C //RX_FDEQ_GAIN_5 +202 0x3C3C //RX_FDEQ_GAIN_6 +203 0x3434 //RX_FDEQ_GAIN_7 +204 0x344C //RX_FDEQ_GAIN_8 +205 0x585C //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0703 //RX_FDEQ_BIN_4 +225 0x0406 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x0060 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x0600 //RX_FDDRC_THRD_2_0 +252 0x0600 //RX_FDDRC_THRD_2_1 +253 0x0600 //RX_FDDRC_THRD_2_2 +254 0x0600 //RX_FDDRC_THRD_2_3 +255 0x0800 //RX_FDDRC_THRD_3_0 +256 0x0800 //RX_FDDRC_THRD_3_1 +257 0x0800 //RX_FDDRC_THRD_3_2 +258 0x0800 //RX_FDDRC_THRD_3_3 +259 0x0000 //RX_FDDRC_SLANT_0_0 +260 0x0000 //RX_FDDRC_SLANT_0_1 +261 0x0000 //RX_FDDRC_SLANT_0_2 +262 0x0000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0051 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x1000 //RX_TDDRC_ALPHA_UP_1 +164 0x1000 //RX_TDDRC_ALPHA_UP_2 +165 0x1000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x4000 //RX_TDDRC_ALPHA_DWN_2 +186 0x4000 //RX_TDDRC_ALPHA_DWN_3 +189 0x4000 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x1000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0D56 //RX_TDDRC_DRC_GAIN +195 0x0014 //RX_FDEQ_SUBNUM +196 0x8080 //RX_FDEQ_GAIN_0 +197 0x8050 //RX_FDEQ_GAIN_1 +198 0x4840 //RX_FDEQ_GAIN_2 +199 0x4040 //RX_FDEQ_GAIN_3 +200 0x4470 //RX_FDEQ_GAIN_4 +201 0x383C //RX_FDEQ_GAIN_5 +202 0x3C3C //RX_FDEQ_GAIN_6 +203 0x3434 //RX_FDEQ_GAIN_7 +204 0x344C //RX_FDEQ_GAIN_8 +205 0x585C //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0703 //RX_FDEQ_BIN_4 +225 0x0406 //RX_FDEQ_BIN_5 +226 0x0708 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D08 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x0060 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x0600 //RX_FDDRC_THRD_2_0 +252 0x0600 //RX_FDDRC_THRD_2_1 +253 0x0600 //RX_FDDRC_THRD_2_2 +254 0x0600 //RX_FDDRC_THRD_2_3 +255 0x0800 //RX_FDDRC_THRD_3_0 +256 0x0800 //RX_FDDRC_THRD_3_1 +257 0x0800 //RX_FDDRC_THRD_3_2 +258 0x0800 //RX_FDDRC_THRD_3_3 +259 0x0000 //RX_FDDRC_SLANT_0_0 +260 0x0000 //RX_FDDRC_SLANT_0_1 +261 0x0000 //RX_FDDRC_SLANT_0_2 +262 0x0000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME HEADSET-TTY_HCO-VOICE_GENERIC-WB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0001 //TX_OPERATION_MODE_0 +1 0x0000 //TX_OPERATION_MODE_1 +2 0x0000 //TX_PATCH_REG +3 0x0200 //TX_SENDFUNC_MODE_0 +4 0x0000 //TX_SENDFUNC_MODE_1 +5 0x0001 //TX_NUM_MIC +6 0x0000 //TX_SAMPLINGFREQ_SIG +7 0x0000 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x0078 //TX_DIST2REF1 +22 0x0000 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0302 //TX_PGA_0 +28 0x0800 //TX_PGA_1 +29 0x0800 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0000 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0000 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0000 //TX_MICS_OF_PAIR0 +38 0x0000 //TX_MICS_OF_PAIR1 +39 0x0000 //TX_MICS_OF_PAIR2 +40 0x0000 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0001 //TX_MIC_DATA_SRC1 +43 0x0002 //TX_MIC_DATA_SRC2 +44 0x0003 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x0000 //TX_HD_BIN_MASK +53 0x0000 //TX_HD_SUBAND_MASK +54 0x0000 //TX_HD_FRAME_AVG_MASK +55 0x0000 //TX_HD_MIN_FRQ +56 0x0000 //TX_HD_ALPHA_PSD +57 0x0000 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0x0000 //TX_T_PSDVAT +63 0x0000 //TX_CNT +64 0x0000 //TX_ANTI_HOWL_GAIN +65 0x0000 //TX_MICFORBFMARK_0 +66 0x0000 //TX_MICFORBFMARK_1 +67 0x0000 //TX_MICFORBFMARK_2 +68 0x0000 //TX_MICFORBFMARK_3 +69 0x0000 //TX_MICFORBFMARK_4 +70 0x0000 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x0000 //TX_DIST2REF_11 +73 0x0000 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0800 //TX_MIC_REFBLK_VOLUME +108 0x0800 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x0000 //TX_ADCS_GAIN +112 0x0000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x7FFF //TX_BLMIC_BLKFACTOR +116 0x7FFF //TX_BRMIC_BLKFACTOR +117 0x000A //TX_MICBLK_START_BIN +118 0x0041 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0015 //TX_FENE_HOLD +123 0x0000 //TX_FE_ENER_TH_MTS +124 0x0000 //TX_FE_ENER_TH_EXP +125 0x0000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x0000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0020 //TX_MIC_BLOCK_N +128 0x7652 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x7800 //TX_THR_PITCH_DET_0 +131 0x7000 //TX_THR_PITCH_DET_1 +132 0x6000 //TX_THR_PITCH_DET_2 +133 0x0000 //TX_PITCH_BFR_LEN +134 0x0000 //TX_SBD_PITCH_DET +135 0x0000 //TX_TD_AEC_L +136 0x0000 //TX_MU0_UNP_TD_AEC +137 0x0000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x0028 //TX_TAIL_LENGTH +147 0x2000 //TX_AEC_REF_GAIN_0 +148 0x2000 //TX_AEC_REF_GAIN_1 +149 0x2000 //TX_AEC_REF_GAIN_2 +150 0x4000 //TX_EAD_THR +151 0x0200 //TX_THR_RE_EST +152 0x0100 //TX_MIN_EQ_RE_EST_0 +153 0x0100 //TX_MIN_EQ_RE_EST_1 +154 0x0100 //TX_MIN_EQ_RE_EST_2 +155 0x0100 //TX_MIN_EQ_RE_EST_3 +156 0x0100 //TX_MIN_EQ_RE_EST_4 +157 0x0100 //TX_MIN_EQ_RE_EST_5 +158 0x0100 //TX_MIN_EQ_RE_EST_6 +159 0x0100 //TX_MIN_EQ_RE_EST_7 +160 0x0100 //TX_MIN_EQ_RE_EST_8 +161 0x0100 //TX_MIN_EQ_RE_EST_9 +162 0x0100 //TX_MIN_EQ_RE_EST_10 +163 0x0100 //TX_MIN_EQ_RE_EST_11 +164 0x0100 //TX_MIN_EQ_RE_EST_12 +165 0x4000 //TX_LAMBDA_RE_EST +166 0x0000 //TX_LAMBDA_CB_NLE +167 0x0000 //TX_C_POST_FLT +168 0x4000 //TX_GAIN_NP +169 0x0008 //TX_SE_HOLD_N +170 0x0050 //TX_DT_HOLD_N +171 0x03E8 //TX_DT2_HOLD_N +172 0x0000 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x0000 //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0000 //TX_FRQ_LIN_LEN +184 0x0000 //TX_FRQ_AEC_LEN_RHO +185 0x0000 //TX_MU0_UNP_FRQ_AEC +186 0x0000 //TX_MU0_PTD_FRQ_AEC +187 0x0000 //TX_MINENOISETH +188 0x0000 //TX_MU0_RE_EST +189 0x0000 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x0000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x7333 //TX_DTD_THR1_0 +198 0x7333 //TX_DTD_THR1_1 +199 0x7333 //TX_DTD_THR1_2 +200 0x7333 //TX_DTD_THR1_3 +201 0x7333 //TX_DTD_THR1_4 +202 0x7333 //TX_DTD_THR1_5 +203 0x7333 //TX_DTD_THR1_6 +204 0x0CCD //TX_DTD_THR2_0 +205 0x0CCD //TX_DTD_THR2_1 +206 0x0CCD //TX_DTD_THR2_2 +207 0x0CCD //TX_DTD_THR2_3 +208 0x0CCD //TX_DTD_THR2_4 +209 0x0CCD //TX_DTD_THR2_5 +210 0x0CCD //TX_DTD_THR2_6 +211 0x7FFF //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x0400 //TX_DT_CUT_K +214 0x0000 //TX_DT_CUT_THR +215 0x0000 //TX_COMFORT_G +216 0x0000 //TX_POWER_YOUT_TH +217 0x0000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x0400 //TX_ADPT_STRICT_L +222 0x0200 //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x0800 //TX_B_POST_FILT_ECHO_L +229 0x0800 //TX_B_POST_FILT_ECHO_H +230 0x0000 //TX_MIN_G_CTRL_ECHO +231 0x7FFF //TX_B_LESSCUT_RTO_ECHO +232 0x0000 //TX_EPD_OFFSET_00 +233 0x0000 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x0000 //TX_MIN_EQ_RE_EST_13 +237 0x0000 //TX_DTD_THR1_7 +238 0x0000 //TX_DTD_THR2_7 +239 0x0000 //TX_DT_RESRV_7 +240 0x0000 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xFA00 //TX_THR_SN_EST_0 +243 0xF400 //TX_THR_SN_EST_1 +244 0xF800 //TX_THR_SN_EST_2 +245 0xF600 //TX_THR_SN_EST_3 +246 0xF800 //TX_THR_SN_EST_4 +247 0xF800 //TX_THR_SN_EST_5 +248 0xF800 //TX_THR_SN_EST_6 +249 0xF800 //TX_THR_SN_EST_7 +250 0x0100 //TX_DELTA_THR_SN_EST_0 +251 0x0100 //TX_DELTA_THR_SN_EST_1 +252 0x0100 //TX_DELTA_THR_SN_EST_2 +253 0x0200 //TX_DELTA_THR_SN_EST_3 +254 0x0200 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0000 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x4000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x4000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0A00 //TX_N_SN_EST +267 0x0000 //TX_INBEAM_T +268 0x0000 //TX_INBEAMHOLDT +269 0x1FFF //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x1000 //TX_NE_RTO_TH_L +274 0x1000 //TX_MAINREFRTOH_TH_H +275 0x1000 //TX_MAINREFRTOH_TH_L +276 0x2000 //TX_MAINREFRTO_TH_H +277 0x1400 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x0000 //TX_B_POST_FLT_0 +280 0x0000 //TX_B_POST_FLT_1 +281 0x001A //TX_NS_LVL_CTRL_0 +282 0x0014 //TX_NS_LVL_CTRL_1 +283 0x0014 //TX_NS_LVL_CTRL_2 +284 0x000C //TX_NS_LVL_CTRL_3 +285 0x000C //TX_NS_LVL_CTRL_4 +286 0x000C //TX_NS_LVL_CTRL_5 +287 0x001A //TX_NS_LVL_CTRL_6 +288 0x000C //TX_NS_LVL_CTRL_7 +289 0x000E //TX_MIN_GAIN_S_0 +290 0x0014 //TX_MIN_GAIN_S_1 +291 0x0014 //TX_MIN_GAIN_S_2 +292 0x0014 //TX_MIN_GAIN_S_3 +293 0x0014 //TX_MIN_GAIN_S_4 +294 0x0014 //TX_MIN_GAIN_S_5 +295 0x0014 //TX_MIN_GAIN_S_6 +296 0x0014 //TX_MIN_GAIN_S_7 +297 0x0000 //TX_NMOS_SUP +298 0x0064 //TX_NS_MAX_PRI_SNR_TH +299 0x7FFF //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x7FFF //TX_SNRI_SUP_1 +302 0x7FFF //TX_SNRI_SUP_2 +303 0x4000 //TX_SNRI_SUP_3 +304 0x4000 //TX_SNRI_SUP_4 +305 0x4000 //TX_SNRI_SUP_5 +306 0x7FFF //TX_SNRI_SUP_6 +307 0x4000 //TX_SNRI_SUP_7 +308 0x1200 //TX_THR_LFNS +309 0x0147 //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x7FFF //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x7FFF //TX_A_POST_FILT_1 +314 0x4000 //TX_A_POST_FILT_S_0 +315 0x1000 //TX_A_POST_FILT_S_1 +316 0x1000 //TX_A_POST_FILT_S_2 +317 0x6666 //TX_A_POST_FILT_S_3 +318 0x6666 //TX_A_POST_FILT_S_4 +319 0x6666 //TX_A_POST_FILT_S_5 +320 0x199A //TX_A_POST_FILT_S_6 +321 0x6666 //TX_A_POST_FILT_S_7 +322 0x2000 //TX_B_POST_FILT_0 +323 0x2000 //TX_B_POST_FILT_1 +324 0x2000 //TX_B_POST_FILT_2 +325 0x2000 //TX_B_POST_FILT_3 +326 0x2000 //TX_B_POST_FILT_4 +327 0x2000 //TX_B_POST_FILT_5 +328 0x2000 //TX_B_POST_FILT_6 +329 0x2000 //TX_B_POST_FILT_7 +330 0x7FFF //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x7FFF //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7E00 //TX_LAMBDA_PFILT +339 0x7E00 //TX_LAMBDA_PFILT_S_0 +340 0x7E00 //TX_LAMBDA_PFILT_S_1 +341 0x7E00 //TX_LAMBDA_PFILT_S_2 +342 0x7E00 //TX_LAMBDA_PFILT_S_3 +343 0x7E00 //TX_LAMBDA_PFILT_S_4 +344 0x7E00 //TX_LAMBDA_PFILT_S_5 +345 0x7E00 //TX_LAMBDA_PFILT_S_6 +346 0x7E00 //TX_LAMBDA_PFILT_S_7 +347 0x0010 //TX_K_PEPPER +348 0x0400 //TX_A_PEPPER +349 0x0000 //TX_K_PEPPER_HF +350 0x0000 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x4000 //TX_HMNC_BST_THR +353 0x0000 //TX_DT_BINVAD_TH_0 +354 0x0000 //TX_DT_BINVAD_TH_1 +355 0x0000 //TX_DT_BINVAD_TH_2 +356 0x0000 //TX_DT_BINVAD_TH_3 +357 0x0000 //TX_DT_BINVAD_ENDF +358 0x0000 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0001 //TX_BF_SGRAD_FLG +362 0x0000 //TX_BF_DVG_TH +363 0x0000 //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x05A0 //TX_NDETCT +367 0x0102 //TX_NOISE_TH_0 +368 0x1388 //TX_NOISE_TH_0_2 +369 0x3A98 //TX_NOISE_TH_0_3 +370 0x0C80 //TX_NOISE_TH_1 +371 0x0032 //TX_NOISE_TH_2 +372 0x3D54 //TX_NOISE_TH_3 +373 0x012C //TX_NOISE_TH_4 +374 0x07D0 //TX_NOISE_TH_5 +375 0x6590 //TX_NOISE_TH_5_2 +376 0x7FFF //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x00C8 //TX_NOISE_TH_6 +379 0x00F8 //TX_MINENOISE_TH +380 0xD508 //TX_MORENS_TFMASK_TH +381 0x0001 //TX_DRC_QUIET_FLOOR +382 0x3A98 //TX_RATIODTL_CUT_TH +383 0x0DAC //TX_DT_CUT_K1 +384 0x6400 //TX_OUT_ENER_S_TH_CLEAN +385 0x6400 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x6400 //TX_OUT_ENER_S_TH_NOISY +387 0x6400 //TX_OUT_ENER_TH_NOISE +388 0x7D00 //TX_OUT_ENER_TH_SPEECH +389 0x0000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x7FFF //TX_POST_MASK_SUP_HSNE +392 0x1388 //TX_TAIL_DET_TH +393 0x4000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0080 //TX_SUPHIGH_TH +396 0x0000 //TX_MASK_G_R +397 0x0000 //TX_EXTRA_NS_L +398 0x1800 //TX_C_POST_FLT_MASK +399 0x7FFF //TX_A_POST_FLT_WNS +400 0x0000 //TX_MIN_G_LOW300HZ +401 0x0010 //TX_MAXLEVEL_CNG +402 0x0000 //TX_STN_NOISE_TH +403 0x0000 //TX_POST_MASK_SUP +404 0x0000 //TX_POST_MASK_ADJUST +405 0x0014 //TX_NS_ENOISE_MIC0_TH +406 0x00DC //TX_MINENOISE_MIC0_TH +407 0x0226 //TX_MINENOISE_MIC0_S_TH +408 0x2879 //TX_MIN_G_CTRL_SSNS +409 0x0400 //TX_METAL_RTO_THR +410 0x0080 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x2000 //TX_RHO_UPB +415 0x0020 //TX_N_HOLD_HS +416 0x0009 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0000 //TX_EXTRA_GAIN_MICBLOCK +419 0x0333 //TX_THR_STD_NSR +420 0x0219 //TX_THR_STD_PLH +421 0x09C4 //TX_N_HOLD_STD +422 0x0166 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0800 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x0000 //TX_SB_RTO_MEAN_TH_RUB +428 0x2000 //TX_WTA_EN_RTO_TH +429 0x1400 //TX_TOP_ENER_TH_F +430 0x0064 //TX_DESIRED_TALK_HOLDT +431 0x1000 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0000 //TX_HS_VAD_BIN +435 0x0000 //TX_THR_VAD_HS +436 0x0000 //TX_MEAN_RTO_MIN_TH2 +437 0x0000 //TX_SILENCE_T +438 0x4000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x099A //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x001E //TX_DOA_VAD_THR_1 +445 0x001E //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x00B4 //TX_SRC_DOA_RNG_HIGH_0B +453 0x005A //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x00B4 //TX_SRC_DOA_RNG_HIGH_0C +456 0x005A //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x00B4 //TX_SRC_DOA_RNG_HIGH_0D +459 0x005A //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0172 //TX_BF_HOLDOFF_T +473 0x8000 //TX_DOA_COST_FACTOR +474 0x0D9A //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x071C //TX_DOA_TRACK_HT +477 0x0280 //TX_N1_HOLD_HF +478 0x0140 //TX_N2_HOLD_HF +479 0x2AAB //TX_BF_RESET_THR_HF +480 0x4000 //TX_DOA_SMOOTH +481 0x0000 //TX_MU_BF +482 0x0200 //TX_BF_MU_LF_B2 +483 0x0000 //TX_BF_FC_END_BIN_B2 +484 0x0000 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0000 //TX_N_DOA_SEED +488 0x0000 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x0000 //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x0000 //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x0000 //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x0168 //TX_NOR_OFF_THR +498 0x0CCD //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0004 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0230 //TX_NOR_OFF_TH1 +503 0xD333 //TX_WIDE_MASK_TH +504 0x4650 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x6000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x000A //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x6666 //TX_MICTOBFGAIN0 +513 0x0014 //TX_FASTMUE_TH +514 0xC000 //TX_DEREVERB_LF_MU +515 0xC000 //TX_DEREVERB_HF_MU +516 0xCCCC //TX_DEREVERB_DELAY +517 0xD999 //TX_DEREVERB_COEF_LEN +518 0x1F40 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x7000 //TX_GSC_RTOH_TH +523 0x0064 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x0000 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0028 //TX_SNR_THR +531 0x03E8 //TX_ENGY_THR +532 0x0000 //TX_CORR_HIGH_TH +533 0x0000 //TX_ENGY_THR_2 +534 0x0000 //TX_MEAN_RTO_THR +535 0x0000 //TX_WNS_ENOISE_MIC0_TH +536 0x0000 //TX_RATIOMICL_TH +537 0x0000 //TX_CALIG_HS +538 0x000A //TX_LVL_CTRL +539 0x0000 //TX_WIND_SUPRTO +540 0x0000 //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x0000 //TX_RATIOMICH_TH +543 0x0000 //TX_WIND_INBEAM_L_TH +544 0x0000 //TX_WIND_INBEAM_H_TH +545 0x0000 //TX_WNS_RESRV_0 +546 0x0000 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0000 //TX_BF_LESSCUT_BBIN +554 0x0000 //TX_BF_LESSCUT_EBIN +555 0x0000 //TX_POSTBFB0 +556 0x0000 //TX_POSTBFB +557 0x0000 //TX_POSTBFE +558 0x0000 //TX_SPEECH_SNR_TH +559 0x0000 //TX_PB_MAX_PRI_SNR_TH +560 0x0000 //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0020 //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4848 //TX_FDEQ_GAIN_5 +573 0x4848 //TX_FDEQ_GAIN_6 +574 0x4848 //TX_FDEQ_GAIN_7 +575 0x4848 //TX_FDEQ_GAIN_8 +576 0x4848 //TX_FDEQ_GAIN_9 +577 0x4848 //TX_FDEQ_GAIN_10 +578 0x4848 //TX_FDEQ_GAIN_11 +579 0x4848 //TX_FDEQ_GAIN_12 +580 0x4848 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0000 //TX_FDEQ_BIN_0 +592 0x0000 //TX_FDEQ_BIN_1 +593 0x0000 //TX_FDEQ_BIN_2 +594 0x0000 //TX_FDEQ_BIN_3 +595 0x0000 //TX_FDEQ_BIN_4 +596 0x0000 //TX_FDEQ_BIN_5 +597 0x0000 //TX_FDEQ_BIN_6 +598 0x0000 //TX_FDEQ_BIN_7 +599 0x0000 //TX_FDEQ_BIN_8 +600 0x0000 //TX_FDEQ_BIN_9 +601 0x0000 //TX_FDEQ_BIN_10 +602 0x0000 //TX_FDEQ_BIN_11 +603 0x0000 //TX_FDEQ_BIN_12 +604 0x0000 //TX_FDEQ_BIN_13 +605 0x0000 //TX_FDEQ_BIN_14 +606 0x0000 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4848 //TX_PREEQ_GAIN_MIC0_8 +626 0x4848 //TX_PREEQ_GAIN_MIC0_9 +627 0x4848 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0000 //TX_PREEQ_BIN_MIC0_0 +642 0x0000 //TX_PREEQ_BIN_MIC0_1 +643 0x0000 //TX_PREEQ_BIN_MIC0_2 +644 0x0000 //TX_PREEQ_BIN_MIC0_3 +645 0x0000 //TX_PREEQ_BIN_MIC0_4 +646 0x0000 //TX_PREEQ_BIN_MIC0_5 +647 0x0000 //TX_PREEQ_BIN_MIC0_6 +648 0x0000 //TX_PREEQ_BIN_MIC0_7 +649 0x0000 //TX_PREEQ_BIN_MIC0_8 +650 0x0000 //TX_PREEQ_BIN_MIC0_9 +651 0x0000 //TX_PREEQ_BIN_MIC0_10 +652 0x0000 //TX_PREEQ_BIN_MIC0_11 +653 0x0000 //TX_PREEQ_BIN_MIC0_12 +654 0x0000 //TX_PREEQ_BIN_MIC0_13 +655 0x0000 //TX_PREEQ_BIN_MIC0_14 +656 0x0000 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0000 //TX_PREEQ_BIN_MIC1_0 +691 0x0000 //TX_PREEQ_BIN_MIC1_1 +692 0x0000 //TX_PREEQ_BIN_MIC1_2 +693 0x0000 //TX_PREEQ_BIN_MIC1_3 +694 0x0000 //TX_PREEQ_BIN_MIC1_4 +695 0x0000 //TX_PREEQ_BIN_MIC1_5 +696 0x0000 //TX_PREEQ_BIN_MIC1_6 +697 0x0000 //TX_PREEQ_BIN_MIC1_7 +698 0x0000 //TX_PREEQ_BIN_MIC1_8 +699 0x0000 //TX_PREEQ_BIN_MIC1_9 +700 0x0000 //TX_PREEQ_BIN_MIC1_10 +701 0x0000 //TX_PREEQ_BIN_MIC1_11 +702 0x0000 //TX_PREEQ_BIN_MIC1_12 +703 0x0000 //TX_PREEQ_BIN_MIC1_13 +704 0x0000 //TX_PREEQ_BIN_MIC1_14 +705 0x0000 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0000 //TX_PREEQ_BIN_MIC2_0 +740 0x0000 //TX_PREEQ_BIN_MIC2_1 +741 0x0000 //TX_PREEQ_BIN_MIC2_2 +742 0x0000 //TX_PREEQ_BIN_MIC2_3 +743 0x0000 //TX_PREEQ_BIN_MIC2_4 +744 0x0000 //TX_PREEQ_BIN_MIC2_5 +745 0x0000 //TX_PREEQ_BIN_MIC2_6 +746 0x0000 //TX_PREEQ_BIN_MIC2_7 +747 0x0000 //TX_PREEQ_BIN_MIC2_8 +748 0x0000 //TX_PREEQ_BIN_MIC2_9 +749 0x0000 //TX_PREEQ_BIN_MIC2_10 +750 0x0000 //TX_PREEQ_BIN_MIC2_11 +751 0x0000 //TX_PREEQ_BIN_MIC2_12 +752 0x0000 //TX_PREEQ_BIN_MIC2_13 +753 0x0000 //TX_PREEQ_BIN_MIC2_14 +754 0x0000 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x2000 //TX_NND_WEIGHT +765 0x0064 //TX_MIC_CALIBRATION_0 +766 0x006A //TX_MIC_CALIBRATION_1 +767 0x006A //TX_MIC_CALIBRATION_2 +768 0x006B //TX_MIC_CALIBRATION_3 +769 0x0048 //TX_MIC_PWR_BIAS_0 +770 0x003C //TX_MIC_PWR_BIAS_1 +771 0x003C //TX_MIC_PWR_BIAS_2 +772 0x003C //TX_MIC_PWR_BIAS_3 +773 0x0000 //TX_GAIN_LIMIT_0 +774 0x0009 //TX_GAIN_LIMIT_1 +775 0x000C //TX_GAIN_LIMIT_2 +776 0x000F //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F3D //TX_BVE_NOVAD0_ALPHAUP +783 0x3000 //TX_TDDRC_ALPHA_UP_01 +784 0x3000 //TX_TDDRC_ALPHA_UP_02 +785 0x3000 //TX_TDDRC_ALPHA_UP_03 +786 0x3000 //TX_TDDRC_ALPHA_UP_04 +787 0x7FB0 //TX_TDDRC_ALPHA_DWN_01 +788 0x7FB0 //TX_TDDRC_ALPHA_DWN_02 +789 0x7FB0 //TX_TDDRC_ALPHA_DWN_03 +790 0x7FB0 //TX_TDDRC_ALPHA_DWN_04 +791 0x65AD //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0002 //TX_DEADMIC_SILENCE_TH +817 0x0147 //TX_MIC_DEGRADE_TH +818 0x0078 //TX_DEADMIC_CNT +819 0x0078 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x0000 //TX_KS_NOISEPASTE_FACTOR +824 0x0000 //TX_KS_CONFIG +825 0x0000 //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x0000 //TX_FFP_FP_K_METAL +834 0x0000 //TX_A_POST_FLT_FP +835 0x0000 //TX_RTO_OUTBEAM_TH +836 0x0000 //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0000 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0000 //TX_FFP_RESRV_2 +849 0x0000 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0002 //TX_FILTINDX +854 0x0000 //TX_TDDRC_THRD_0 +855 0x0000 //TX_TDDRC_THRD_1 +856 0x0E80 //TX_TDDRC_THRD_2 +857 0x3800 //TX_TDDRC_THRD_3 +858 0x2A00 //TX_TDDRC_SLANT_0 +859 0x6E00 //TX_TDDRC_SLANT_1 +860 0x3000 //TX_TDDRC_ALPHA_UP_00 +861 0x7FB0 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x0000 //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0000 //TX_TDDRC_SMT_W +866 0x0100 //TX_TDDRC_DRC_GAIN +867 0x0000 //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x1EB8 //TX_TFMASKLTH +870 0x170A //TX_TFMASKLTHL +871 0x7FFF //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0x0CCD //TX_TFMASKTH_BLESSCUT +876 0x4000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x0000 //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x0000 //TX_FASTNS_OUTIN_TH +884 0x0000 //TX_FASTNS_TFMASK_TH +885 0x0000 //TX_FASTNS_TFMASKBIN_TH1 +886 0x0000 //TX_FASTNS_TFMASKBIN_TH2 +887 0x0000 //TX_FASTNS_TFMASKBIN_TH3 +888 0x00C8 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x051F //TX_POSTSSA_MIN_G_VR_MASK +891 0x4000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x2339 //TX_SENDFUNC_REG_MICMUTE +898 0x0021 //TX_SENDFUNC_REG_MICMUTE1 +899 0x02BC //TX_MICMUTE_RATIO_THR +900 0x0140 //TX_MICMUTE_AMP_THR +901 0x0004 //TX_MICMUTE_HPF_IND +902 0x00C0 //TX_MICMUTE_LOG_EYR_TH +903 0x0008 //TX_MICMUTE_CVG_TIME +904 0x0008 //TX_MICMUTE_RELEASE_TIME +905 0x01FE //TX_MIC_VOLUME_MIC0MUTE +906 0x0020 //TX_MICMUTE_EPD_OFFSET_0 +907 0x001E //TX_MICMUTE_FRQ_AEC_L +908 0x7999 //TX_MICMUTE_EAD_THR +909 0x7FFF //TX_MICMUTE_LAMBDA_CB_NLE +910 0x7FFF //TX_MICMUTE_LAMBDA_RE_EST +911 0x4000 //TX_DTD_THR1_MICMUTE_0 +912 0x7000 //TX_DTD_THR1_MICMUTE_1 +913 0x7FFF //TX_DTD_THR1_MICMUTE_2 +914 0x7FFF //TX_DTD_THR1_MICMUTE_3 +915 0x6CCC //TX_DTD_THR2_MICMUTE_0 +916 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x1000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x4000 //TX_MICMUTE_C_POST_FLT +922 0x03E8 //TX_MICMUTE_DT_CUT_K +923 0x0001 //TX_MICMUTE_DT_CUT_THR +924 0x03E8 //TX_MICMUTE_DT_CUT_K2 +925 0x0001 //TX_MICMUTE_DT_CUT_THR2 +926 0x0064 //TX_MICMUTE_DT2_HOLD_N +927 0x1000 //TX_MICMUTE_RATIODTH_THCUT +928 0x1000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x7FFF //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0400 //TX_MICMUTE_C_POST_FLT_MASK +931 0x7999 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0258 //TX_MICMUTE_DT_CUT_K1 +933 0x0800 //TX_MICMUTE_N2_SN_EST +934 0xFC00 //TX_MICMUTE_THR_SN_EST_0 +935 0x001C //TX_MICMUTE_MIN_G_CTRL_0 +936 0x6000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x7000 //TX_MICMUTE_B_POST_FILT_0 +938 0x2710 //TX_MIC1RUB_AMP_THR +939 0x0010 //TX_MIC1MUTE_RATIO_THR +940 0x0450 //TX_MIC1MUTE_AMP_THR +941 0x0008 //TX_MIC1MUTE_CVG_TIME +942 0x0008 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x243C //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0001 //RX_SAMPLINGFREQ_SIG +3 0x0001 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x6000 //RX_TDDRC_ALPHA_UP_1 +7 0x6000 //RX_TDDRC_ALPHA_UP_2 +8 0x6000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +10 0x0403 //RX_PGA +11 0x7B02 //RX_A_HP +12 0x4000 //RX_B_PE +13 0x7800 //RX_THR_PITCH_DET_0 +14 0x7000 //RX_THR_PITCH_DET_1 +15 0x6000 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0400 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x0010 //RX_NS_LVL_CTRL +23 0xF800 //RX_THR_SN_EST +24 0x7E00 //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x001C //RX_FDEQ_SUBNUM +39 0x6868 //RX_FDEQ_GAIN_0 +40 0x6864 //RX_FDEQ_GAIN_1 +41 0x7070 //RX_FDEQ_GAIN_2 +42 0x6058 //RX_FDEQ_GAIN_3 +43 0x5C5C //RX_FDEQ_GAIN_4 +44 0x8854 //RX_FDEQ_GAIN_5 +45 0x5448 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4860 //RX_FDEQ_GAIN_8 +48 0x6068 //RX_FDEQ_GAIN_9 +49 0x7070 //RX_FDEQ_GAIN_10 +50 0x8070 //RX_FDEQ_GAIN_11 +51 0x6060 //RX_FDEQ_GAIN_12 +52 0x7070 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0404 //RX_FDEQ_BIN_4 +68 0x0204 //RX_FDEQ_BIN_5 +69 0x0A0A //RX_FDEQ_BIN_6 +70 0x0A0A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +92 0x0120 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0002 //RX_FILTINDX +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1C00 //RX_TDDRC_THRD_2 +115 0x1C00 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x6000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0715 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x157C //RX_TPKA_FP +127 0x0400 //RX_MIN_G_FP +128 0x0800 //RX_MAX_G_FP +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x6000 //RX_TDDRC_ALPHA_UP_1 +7 0x6000 //RX_TDDRC_ALPHA_UP_2 +8 0x6000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x4000 //RX_TDDRC_ALPHA_DWN_2 +29 0x4000 //RX_TDDRC_ALPHA_DWN_3 +32 0x4000 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x6000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0780 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x5C5C //RX_FDEQ_GAIN_0 +40 0x5448 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4840 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x6048 //RX_FDEQ_GAIN_5 +45 0x4C40 //RX_FDEQ_GAIN_6 +46 0x4038 //RX_FDEQ_GAIN_7 +47 0x3C48 //RX_FDEQ_GAIN_8 +48 0x545C //RX_FDEQ_GAIN_9 +49 0x6864 //RX_FDEQ_GAIN_10 +50 0x7058 //RX_FDEQ_GAIN_11 +51 0x443C //RX_FDEQ_GAIN_12 +52 0x3838 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0404 //RX_FDEQ_BIN_4 +68 0x0204 //RX_FDEQ_BIN_5 +69 0x0A0A //RX_FDEQ_BIN_6 +70 0x0A0A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +92 0x0120 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0011 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x6000 //RX_TDDRC_ALPHA_UP_1 +7 0x6000 //RX_TDDRC_ALPHA_UP_2 +8 0x6000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x4000 //RX_TDDRC_ALPHA_DWN_2 +29 0x4000 //RX_TDDRC_ALPHA_DWN_3 +32 0x4000 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x6000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0780 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x5C5C //RX_FDEQ_GAIN_0 +40 0x5448 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4840 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x6048 //RX_FDEQ_GAIN_5 +45 0x4C40 //RX_FDEQ_GAIN_6 +46 0x4038 //RX_FDEQ_GAIN_7 +47 0x3C48 //RX_FDEQ_GAIN_8 +48 0x545C //RX_FDEQ_GAIN_9 +49 0x6864 //RX_FDEQ_GAIN_10 +50 0x7058 //RX_FDEQ_GAIN_11 +51 0x443C //RX_FDEQ_GAIN_12 +52 0x3838 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0404 //RX_FDEQ_BIN_4 +68 0x0204 //RX_FDEQ_BIN_5 +69 0x0A0A //RX_FDEQ_BIN_6 +70 0x0A0A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +92 0x0120 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0019 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x6000 //RX_TDDRC_ALPHA_UP_1 +7 0x6000 //RX_TDDRC_ALPHA_UP_2 +8 0x6000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x4000 //RX_TDDRC_ALPHA_DWN_2 +29 0x4000 //RX_TDDRC_ALPHA_DWN_3 +32 0x4000 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x6000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0780 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x5C5C //RX_FDEQ_GAIN_0 +40 0x5448 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4840 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x6048 //RX_FDEQ_GAIN_5 +45 0x4C40 //RX_FDEQ_GAIN_6 +46 0x4038 //RX_FDEQ_GAIN_7 +47 0x3C48 //RX_FDEQ_GAIN_8 +48 0x545C //RX_FDEQ_GAIN_9 +49 0x6864 //RX_FDEQ_GAIN_10 +50 0x7058 //RX_FDEQ_GAIN_11 +51 0x443C //RX_FDEQ_GAIN_12 +52 0x3838 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0404 //RX_FDEQ_BIN_4 +68 0x0204 //RX_FDEQ_BIN_5 +69 0x0A0A //RX_FDEQ_BIN_6 +70 0x0A0A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +92 0x0120 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0024 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x6000 //RX_TDDRC_ALPHA_UP_1 +7 0x6000 //RX_TDDRC_ALPHA_UP_2 +8 0x6000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x4000 //RX_TDDRC_ALPHA_DWN_2 +29 0x4000 //RX_TDDRC_ALPHA_DWN_3 +32 0x4000 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x6000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0780 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x5C5C //RX_FDEQ_GAIN_0 +40 0x5448 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4840 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x6048 //RX_FDEQ_GAIN_5 +45 0x4C40 //RX_FDEQ_GAIN_6 +46 0x4038 //RX_FDEQ_GAIN_7 +47 0x3C48 //RX_FDEQ_GAIN_8 +48 0x545C //RX_FDEQ_GAIN_9 +49 0x6864 //RX_FDEQ_GAIN_10 +50 0x7058 //RX_FDEQ_GAIN_11 +51 0x443C //RX_FDEQ_GAIN_12 +52 0x3838 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0404 //RX_FDEQ_BIN_4 +68 0x0204 //RX_FDEQ_BIN_5 +69 0x0A0A //RX_FDEQ_BIN_6 +70 0x0A0A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +92 0x0120 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0034 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x6000 //RX_TDDRC_ALPHA_UP_1 +7 0x6000 //RX_TDDRC_ALPHA_UP_2 +8 0x6000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x4000 //RX_TDDRC_ALPHA_DWN_2 +29 0x4000 //RX_TDDRC_ALPHA_DWN_3 +32 0x4000 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x6000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0B39 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x6868 //RX_FDEQ_GAIN_0 +40 0x685C //RX_FDEQ_GAIN_1 +41 0x6868 //RX_FDEQ_GAIN_2 +42 0x544C //RX_FDEQ_GAIN_3 +43 0x4C54 //RX_FDEQ_GAIN_4 +44 0x704C //RX_FDEQ_GAIN_5 +45 0x4C40 //RX_FDEQ_GAIN_6 +46 0x4040 //RX_FDEQ_GAIN_7 +47 0x445C //RX_FDEQ_GAIN_8 +48 0x6068 //RX_FDEQ_GAIN_9 +49 0x7070 //RX_FDEQ_GAIN_10 +50 0x7C74 //RX_FDEQ_GAIN_11 +51 0x6060 //RX_FDEQ_GAIN_12 +52 0x6C6C //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0404 //RX_FDEQ_BIN_4 +68 0x0204 //RX_FDEQ_BIN_5 +69 0x0A0A //RX_FDEQ_BIN_6 +70 0x0A0A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +92 0x0120 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0038 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x6000 //RX_TDDRC_ALPHA_UP_1 +7 0x6000 //RX_TDDRC_ALPHA_UP_2 +8 0x6000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x4000 //RX_TDDRC_ALPHA_DWN_2 +29 0x4000 //RX_TDDRC_ALPHA_DWN_3 +32 0x4000 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x6000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0B39 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x6868 //RX_FDEQ_GAIN_0 +40 0x685C //RX_FDEQ_GAIN_1 +41 0x6868 //RX_FDEQ_GAIN_2 +42 0x544C //RX_FDEQ_GAIN_3 +43 0x4C54 //RX_FDEQ_GAIN_4 +44 0x704C //RX_FDEQ_GAIN_5 +45 0x4C40 //RX_FDEQ_GAIN_6 +46 0x4040 //RX_FDEQ_GAIN_7 +47 0x445C //RX_FDEQ_GAIN_8 +48 0x6068 //RX_FDEQ_GAIN_9 +49 0x7070 //RX_FDEQ_GAIN_10 +50 0x7C74 //RX_FDEQ_GAIN_11 +51 0x6060 //RX_FDEQ_GAIN_12 +52 0x6C6C //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0404 //RX_FDEQ_BIN_4 +68 0x0204 //RX_FDEQ_BIN_5 +69 0x0A0A //RX_FDEQ_BIN_6 +70 0x0A0A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +92 0x0120 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0060 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x6000 //RX_TDDRC_ALPHA_UP_1 +7 0x6000 //RX_TDDRC_ALPHA_UP_2 +8 0x6000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x4000 //RX_TDDRC_ALPHA_DWN_2 +29 0x4000 //RX_TDDRC_ALPHA_DWN_3 +32 0x4000 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x6000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0B39 //RX_TDDRC_DRC_GAIN +38 0x001C //RX_FDEQ_SUBNUM +39 0x6868 //RX_FDEQ_GAIN_0 +40 0x685C //RX_FDEQ_GAIN_1 +41 0x6868 //RX_FDEQ_GAIN_2 +42 0x544C //RX_FDEQ_GAIN_3 +43 0x4C54 //RX_FDEQ_GAIN_4 +44 0x704C //RX_FDEQ_GAIN_5 +45 0x4C40 //RX_FDEQ_GAIN_6 +46 0x4040 //RX_FDEQ_GAIN_7 +47 0x445C //RX_FDEQ_GAIN_8 +48 0x6068 //RX_FDEQ_GAIN_9 +49 0x7070 //RX_FDEQ_GAIN_10 +50 0x7C74 //RX_FDEQ_GAIN_11 +51 0x6060 //RX_FDEQ_GAIN_12 +52 0x6C6C //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0404 //RX_FDEQ_BIN_4 +68 0x0204 //RX_FDEQ_BIN_5 +69 0x0A0A //RX_FDEQ_BIN_6 +70 0x0A0A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x0E0F //RX_FDEQ_BIN_10 +74 0x0F10 //RX_FDEQ_BIN_11 +75 0x1011 //RX_FDEQ_BIN_12 +76 0x1104 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +92 0x0120 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x243C //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0001 //RX_SAMPLINGFREQ_SIG +160 0x0001 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x6000 //RX_TDDRC_ALPHA_UP_1 +164 0x6000 //RX_TDDRC_ALPHA_UP_2 +165 0x6000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +167 0x0403 //RX_PGA +168 0x7B02 //RX_A_HP +169 0x4000 //RX_B_PE +170 0x7800 //RX_THR_PITCH_DET_0 +171 0x7000 //RX_THR_PITCH_DET_1 +172 0x6000 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0400 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x0010 //RX_NS_LVL_CTRL +180 0xF800 //RX_THR_SN_EST +181 0x7E00 //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x001C //RX_FDEQ_SUBNUM +196 0x6868 //RX_FDEQ_GAIN_0 +197 0x6864 //RX_FDEQ_GAIN_1 +198 0x7070 //RX_FDEQ_GAIN_2 +199 0x6058 //RX_FDEQ_GAIN_3 +200 0x5C5C //RX_FDEQ_GAIN_4 +201 0x8854 //RX_FDEQ_GAIN_5 +202 0x5448 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4860 //RX_FDEQ_GAIN_8 +205 0x6068 //RX_FDEQ_GAIN_9 +206 0x7070 //RX_FDEQ_GAIN_10 +207 0x8070 //RX_FDEQ_GAIN_11 +208 0x6060 //RX_FDEQ_GAIN_12 +209 0x7070 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0404 //RX_FDEQ_BIN_4 +225 0x0204 //RX_FDEQ_BIN_5 +226 0x0A0A //RX_FDEQ_BIN_6 +227 0x0A0A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +249 0x0120 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0002 //RX_FILTINDX +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1C00 //RX_TDDRC_THRD_2 +272 0x1C00 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x6000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0715 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x157C //RX_TPKA_FP +284 0x0400 //RX_MIN_G_FP +285 0x0800 //RX_MAX_G_FP +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x6000 //RX_TDDRC_ALPHA_UP_1 +164 0x6000 //RX_TDDRC_ALPHA_UP_2 +165 0x6000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x4000 //RX_TDDRC_ALPHA_DWN_2 +186 0x4000 //RX_TDDRC_ALPHA_DWN_3 +189 0x4000 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x6000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0780 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x5C5C //RX_FDEQ_GAIN_0 +197 0x5448 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4840 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x6048 //RX_FDEQ_GAIN_5 +202 0x4C40 //RX_FDEQ_GAIN_6 +203 0x4038 //RX_FDEQ_GAIN_7 +204 0x3C48 //RX_FDEQ_GAIN_8 +205 0x545C //RX_FDEQ_GAIN_9 +206 0x6864 //RX_FDEQ_GAIN_10 +207 0x7058 //RX_FDEQ_GAIN_11 +208 0x443C //RX_FDEQ_GAIN_12 +209 0x3838 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0404 //RX_FDEQ_BIN_4 +225 0x0204 //RX_FDEQ_BIN_5 +226 0x0A0A //RX_FDEQ_BIN_6 +227 0x0A0A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +249 0x0120 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0011 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x6000 //RX_TDDRC_ALPHA_UP_1 +164 0x6000 //RX_TDDRC_ALPHA_UP_2 +165 0x6000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x4000 //RX_TDDRC_ALPHA_DWN_2 +186 0x4000 //RX_TDDRC_ALPHA_DWN_3 +189 0x4000 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x6000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0780 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x5C5C //RX_FDEQ_GAIN_0 +197 0x5448 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4840 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x6048 //RX_FDEQ_GAIN_5 +202 0x4C40 //RX_FDEQ_GAIN_6 +203 0x4038 //RX_FDEQ_GAIN_7 +204 0x3C48 //RX_FDEQ_GAIN_8 +205 0x545C //RX_FDEQ_GAIN_9 +206 0x6864 //RX_FDEQ_GAIN_10 +207 0x7058 //RX_FDEQ_GAIN_11 +208 0x443C //RX_FDEQ_GAIN_12 +209 0x3838 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0404 //RX_FDEQ_BIN_4 +225 0x0204 //RX_FDEQ_BIN_5 +226 0x0A0A //RX_FDEQ_BIN_6 +227 0x0A0A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +249 0x0120 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0019 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x6000 //RX_TDDRC_ALPHA_UP_1 +164 0x6000 //RX_TDDRC_ALPHA_UP_2 +165 0x6000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x4000 //RX_TDDRC_ALPHA_DWN_2 +186 0x4000 //RX_TDDRC_ALPHA_DWN_3 +189 0x4000 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x6000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0780 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x5C5C //RX_FDEQ_GAIN_0 +197 0x5448 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4840 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x6048 //RX_FDEQ_GAIN_5 +202 0x4C40 //RX_FDEQ_GAIN_6 +203 0x4038 //RX_FDEQ_GAIN_7 +204 0x3C48 //RX_FDEQ_GAIN_8 +205 0x545C //RX_FDEQ_GAIN_9 +206 0x6864 //RX_FDEQ_GAIN_10 +207 0x7058 //RX_FDEQ_GAIN_11 +208 0x443C //RX_FDEQ_GAIN_12 +209 0x3838 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0404 //RX_FDEQ_BIN_4 +225 0x0204 //RX_FDEQ_BIN_5 +226 0x0A0A //RX_FDEQ_BIN_6 +227 0x0A0A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +249 0x0120 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0024 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x6000 //RX_TDDRC_ALPHA_UP_1 +164 0x6000 //RX_TDDRC_ALPHA_UP_2 +165 0x6000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x4000 //RX_TDDRC_ALPHA_DWN_2 +186 0x4000 //RX_TDDRC_ALPHA_DWN_3 +189 0x4000 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x6000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0780 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x5C5C //RX_FDEQ_GAIN_0 +197 0x5448 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4840 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x6048 //RX_FDEQ_GAIN_5 +202 0x4C40 //RX_FDEQ_GAIN_6 +203 0x4038 //RX_FDEQ_GAIN_7 +204 0x3C48 //RX_FDEQ_GAIN_8 +205 0x545C //RX_FDEQ_GAIN_9 +206 0x6864 //RX_FDEQ_GAIN_10 +207 0x7058 //RX_FDEQ_GAIN_11 +208 0x443C //RX_FDEQ_GAIN_12 +209 0x3838 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0404 //RX_FDEQ_BIN_4 +225 0x0204 //RX_FDEQ_BIN_5 +226 0x0A0A //RX_FDEQ_BIN_6 +227 0x0A0A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +249 0x0120 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0034 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x6000 //RX_TDDRC_ALPHA_UP_1 +164 0x6000 //RX_TDDRC_ALPHA_UP_2 +165 0x6000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x4000 //RX_TDDRC_ALPHA_DWN_2 +186 0x4000 //RX_TDDRC_ALPHA_DWN_3 +189 0x4000 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x6000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0B39 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x6868 //RX_FDEQ_GAIN_0 +197 0x685C //RX_FDEQ_GAIN_1 +198 0x6868 //RX_FDEQ_GAIN_2 +199 0x544C //RX_FDEQ_GAIN_3 +200 0x4C54 //RX_FDEQ_GAIN_4 +201 0x704C //RX_FDEQ_GAIN_5 +202 0x4C40 //RX_FDEQ_GAIN_6 +203 0x4040 //RX_FDEQ_GAIN_7 +204 0x445C //RX_FDEQ_GAIN_8 +205 0x6068 //RX_FDEQ_GAIN_9 +206 0x7070 //RX_FDEQ_GAIN_10 +207 0x7C74 //RX_FDEQ_GAIN_11 +208 0x6060 //RX_FDEQ_GAIN_12 +209 0x6C6C //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0404 //RX_FDEQ_BIN_4 +225 0x0204 //RX_FDEQ_BIN_5 +226 0x0A0A //RX_FDEQ_BIN_6 +227 0x0A0A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +249 0x0120 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0038 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x6000 //RX_TDDRC_ALPHA_UP_1 +164 0x6000 //RX_TDDRC_ALPHA_UP_2 +165 0x6000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x4000 //RX_TDDRC_ALPHA_DWN_2 +186 0x4000 //RX_TDDRC_ALPHA_DWN_3 +189 0x4000 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x6000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0B39 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x6868 //RX_FDEQ_GAIN_0 +197 0x685C //RX_FDEQ_GAIN_1 +198 0x6868 //RX_FDEQ_GAIN_2 +199 0x544C //RX_FDEQ_GAIN_3 +200 0x4C54 //RX_FDEQ_GAIN_4 +201 0x704C //RX_FDEQ_GAIN_5 +202 0x4C40 //RX_FDEQ_GAIN_6 +203 0x4040 //RX_FDEQ_GAIN_7 +204 0x445C //RX_FDEQ_GAIN_8 +205 0x6068 //RX_FDEQ_GAIN_9 +206 0x7070 //RX_FDEQ_GAIN_10 +207 0x7C74 //RX_FDEQ_GAIN_11 +208 0x6060 //RX_FDEQ_GAIN_12 +209 0x6C6C //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0404 //RX_FDEQ_BIN_4 +225 0x0204 //RX_FDEQ_BIN_5 +226 0x0A0A //RX_FDEQ_BIN_6 +227 0x0A0A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +249 0x0120 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0060 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x6000 //RX_TDDRC_ALPHA_UP_1 +164 0x6000 //RX_TDDRC_ALPHA_UP_2 +165 0x6000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x4000 //RX_TDDRC_ALPHA_DWN_2 +186 0x4000 //RX_TDDRC_ALPHA_DWN_3 +189 0x4000 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x6000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0B39 //RX_TDDRC_DRC_GAIN +195 0x001C //RX_FDEQ_SUBNUM +196 0x6868 //RX_FDEQ_GAIN_0 +197 0x685C //RX_FDEQ_GAIN_1 +198 0x6868 //RX_FDEQ_GAIN_2 +199 0x544C //RX_FDEQ_GAIN_3 +200 0x4C54 //RX_FDEQ_GAIN_4 +201 0x704C //RX_FDEQ_GAIN_5 +202 0x4C40 //RX_FDEQ_GAIN_6 +203 0x4040 //RX_FDEQ_GAIN_7 +204 0x445C //RX_FDEQ_GAIN_8 +205 0x6068 //RX_FDEQ_GAIN_9 +206 0x7070 //RX_FDEQ_GAIN_10 +207 0x7C74 //RX_FDEQ_GAIN_11 +208 0x6060 //RX_FDEQ_GAIN_12 +209 0x6C6C //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0404 //RX_FDEQ_BIN_4 +225 0x0204 //RX_FDEQ_BIN_5 +226 0x0A0A //RX_FDEQ_BIN_6 +227 0x0A0A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x0E0F //RX_FDEQ_BIN_10 +231 0x0F10 //RX_FDEQ_BIN_11 +232 0x1011 //RX_FDEQ_BIN_12 +233 0x1104 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +249 0x0120 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME HEADSET-TTY_HCO-VOICE_GENERIC-SWB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0001 //TX_OPERATION_MODE_0 +1 0x0000 //TX_OPERATION_MODE_1 +2 0x0000 //TX_PATCH_REG +3 0x0200 //TX_SENDFUNC_MODE_0 +4 0x0000 //TX_SENDFUNC_MODE_1 +5 0x0001 //TX_NUM_MIC +6 0x0000 //TX_SAMPLINGFREQ_SIG +7 0x0000 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x0078 //TX_DIST2REF1 +22 0x0000 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0302 //TX_PGA_0 +28 0x0800 //TX_PGA_1 +29 0x0800 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0000 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0000 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0000 //TX_MICS_OF_PAIR0 +38 0x0000 //TX_MICS_OF_PAIR1 +39 0x0000 //TX_MICS_OF_PAIR2 +40 0x0000 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0001 //TX_MIC_DATA_SRC1 +43 0x0002 //TX_MIC_DATA_SRC2 +44 0x0003 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x0000 //TX_HD_BIN_MASK +53 0x0000 //TX_HD_SUBAND_MASK +54 0x0000 //TX_HD_FRAME_AVG_MASK +55 0x0000 //TX_HD_MIN_FRQ +56 0x0000 //TX_HD_ALPHA_PSD +57 0x0000 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0x0000 //TX_T_PSDVAT +63 0x0000 //TX_CNT +64 0x0000 //TX_ANTI_HOWL_GAIN +65 0x0000 //TX_MICFORBFMARK_0 +66 0x0000 //TX_MICFORBFMARK_1 +67 0x0000 //TX_MICFORBFMARK_2 +68 0x0000 //TX_MICFORBFMARK_3 +69 0x0000 //TX_MICFORBFMARK_4 +70 0x0000 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x0000 //TX_DIST2REF_11 +73 0x0000 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0800 //TX_MIC_REFBLK_VOLUME +108 0x0800 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x0000 //TX_ADCS_GAIN +112 0x0000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x7FFF //TX_BLMIC_BLKFACTOR +116 0x7FFF //TX_BRMIC_BLKFACTOR +117 0x000A //TX_MICBLK_START_BIN +118 0x0041 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0015 //TX_FENE_HOLD +123 0x0000 //TX_FE_ENER_TH_MTS +124 0x0000 //TX_FE_ENER_TH_EXP +125 0x0000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x0000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0020 //TX_MIC_BLOCK_N +128 0x7652 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x7800 //TX_THR_PITCH_DET_0 +131 0x7000 //TX_THR_PITCH_DET_1 +132 0x6000 //TX_THR_PITCH_DET_2 +133 0x0000 //TX_PITCH_BFR_LEN +134 0x0000 //TX_SBD_PITCH_DET +135 0x0000 //TX_TD_AEC_L +136 0x0000 //TX_MU0_UNP_TD_AEC +137 0x0000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x0028 //TX_TAIL_LENGTH +147 0x2000 //TX_AEC_REF_GAIN_0 +148 0x2000 //TX_AEC_REF_GAIN_1 +149 0x2000 //TX_AEC_REF_GAIN_2 +150 0x4000 //TX_EAD_THR +151 0x0200 //TX_THR_RE_EST +152 0x0100 //TX_MIN_EQ_RE_EST_0 +153 0x0100 //TX_MIN_EQ_RE_EST_1 +154 0x0100 //TX_MIN_EQ_RE_EST_2 +155 0x0100 //TX_MIN_EQ_RE_EST_3 +156 0x0100 //TX_MIN_EQ_RE_EST_4 +157 0x0100 //TX_MIN_EQ_RE_EST_5 +158 0x0100 //TX_MIN_EQ_RE_EST_6 +159 0x0100 //TX_MIN_EQ_RE_EST_7 +160 0x0100 //TX_MIN_EQ_RE_EST_8 +161 0x0100 //TX_MIN_EQ_RE_EST_9 +162 0x0100 //TX_MIN_EQ_RE_EST_10 +163 0x0100 //TX_MIN_EQ_RE_EST_11 +164 0x0100 //TX_MIN_EQ_RE_EST_12 +165 0x4000 //TX_LAMBDA_RE_EST +166 0x0000 //TX_LAMBDA_CB_NLE +167 0x0000 //TX_C_POST_FLT +168 0x4000 //TX_GAIN_NP +169 0x0008 //TX_SE_HOLD_N +170 0x0050 //TX_DT_HOLD_N +171 0x03E8 //TX_DT2_HOLD_N +172 0x0000 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x0000 //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0000 //TX_FRQ_LIN_LEN +184 0x0000 //TX_FRQ_AEC_LEN_RHO +185 0x0000 //TX_MU0_UNP_FRQ_AEC +186 0x0000 //TX_MU0_PTD_FRQ_AEC +187 0x0000 //TX_MINENOISETH +188 0x0000 //TX_MU0_RE_EST +189 0x0000 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x0000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x7333 //TX_DTD_THR1_0 +198 0x7333 //TX_DTD_THR1_1 +199 0x7333 //TX_DTD_THR1_2 +200 0x7333 //TX_DTD_THR1_3 +201 0x7333 //TX_DTD_THR1_4 +202 0x7333 //TX_DTD_THR1_5 +203 0x7333 //TX_DTD_THR1_6 +204 0x0CCD //TX_DTD_THR2_0 +205 0x0CCD //TX_DTD_THR2_1 +206 0x0CCD //TX_DTD_THR2_2 +207 0x0CCD //TX_DTD_THR2_3 +208 0x0CCD //TX_DTD_THR2_4 +209 0x0CCD //TX_DTD_THR2_5 +210 0x0CCD //TX_DTD_THR2_6 +211 0x7FFF //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x0400 //TX_DT_CUT_K +214 0x0000 //TX_DT_CUT_THR +215 0x0000 //TX_COMFORT_G +216 0x0000 //TX_POWER_YOUT_TH +217 0x0000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x0400 //TX_ADPT_STRICT_L +222 0x0200 //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x0800 //TX_B_POST_FILT_ECHO_L +229 0x0800 //TX_B_POST_FILT_ECHO_H +230 0x0000 //TX_MIN_G_CTRL_ECHO +231 0x7FFF //TX_B_LESSCUT_RTO_ECHO +232 0x0000 //TX_EPD_OFFSET_00 +233 0x0000 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x0000 //TX_MIN_EQ_RE_EST_13 +237 0x0000 //TX_DTD_THR1_7 +238 0x0000 //TX_DTD_THR2_7 +239 0x0000 //TX_DT_RESRV_7 +240 0x0000 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xFA00 //TX_THR_SN_EST_0 +243 0xF400 //TX_THR_SN_EST_1 +244 0xF800 //TX_THR_SN_EST_2 +245 0xF600 //TX_THR_SN_EST_3 +246 0xF800 //TX_THR_SN_EST_4 +247 0xF800 //TX_THR_SN_EST_5 +248 0xF800 //TX_THR_SN_EST_6 +249 0xF800 //TX_THR_SN_EST_7 +250 0x0100 //TX_DELTA_THR_SN_EST_0 +251 0x0100 //TX_DELTA_THR_SN_EST_1 +252 0x0100 //TX_DELTA_THR_SN_EST_2 +253 0x0200 //TX_DELTA_THR_SN_EST_3 +254 0x0200 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0000 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x4000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x4000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0A00 //TX_N_SN_EST +267 0x0000 //TX_INBEAM_T +268 0x0000 //TX_INBEAMHOLDT +269 0x1FFF //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x1000 //TX_NE_RTO_TH_L +274 0x1000 //TX_MAINREFRTOH_TH_H +275 0x1000 //TX_MAINREFRTOH_TH_L +276 0x2000 //TX_MAINREFRTO_TH_H +277 0x1400 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x0000 //TX_B_POST_FLT_0 +280 0x0000 //TX_B_POST_FLT_1 +281 0x001A //TX_NS_LVL_CTRL_0 +282 0x0014 //TX_NS_LVL_CTRL_1 +283 0x0014 //TX_NS_LVL_CTRL_2 +284 0x000C //TX_NS_LVL_CTRL_3 +285 0x000C //TX_NS_LVL_CTRL_4 +286 0x000C //TX_NS_LVL_CTRL_5 +287 0x001A //TX_NS_LVL_CTRL_6 +288 0x000C //TX_NS_LVL_CTRL_7 +289 0x000E //TX_MIN_GAIN_S_0 +290 0x0014 //TX_MIN_GAIN_S_1 +291 0x0014 //TX_MIN_GAIN_S_2 +292 0x0014 //TX_MIN_GAIN_S_3 +293 0x0014 //TX_MIN_GAIN_S_4 +294 0x0014 //TX_MIN_GAIN_S_5 +295 0x0014 //TX_MIN_GAIN_S_6 +296 0x0014 //TX_MIN_GAIN_S_7 +297 0x0000 //TX_NMOS_SUP +298 0x0064 //TX_NS_MAX_PRI_SNR_TH +299 0x7FFF //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x7FFF //TX_SNRI_SUP_1 +302 0x7FFF //TX_SNRI_SUP_2 +303 0x4000 //TX_SNRI_SUP_3 +304 0x4000 //TX_SNRI_SUP_4 +305 0x4000 //TX_SNRI_SUP_5 +306 0x7FFF //TX_SNRI_SUP_6 +307 0x4000 //TX_SNRI_SUP_7 +308 0x1200 //TX_THR_LFNS +309 0x0147 //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x7FFF //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x7FFF //TX_A_POST_FILT_1 +314 0x4000 //TX_A_POST_FILT_S_0 +315 0x1000 //TX_A_POST_FILT_S_1 +316 0x1000 //TX_A_POST_FILT_S_2 +317 0x6666 //TX_A_POST_FILT_S_3 +318 0x6666 //TX_A_POST_FILT_S_4 +319 0x6666 //TX_A_POST_FILT_S_5 +320 0x199A //TX_A_POST_FILT_S_6 +321 0x6666 //TX_A_POST_FILT_S_7 +322 0x2000 //TX_B_POST_FILT_0 +323 0x2000 //TX_B_POST_FILT_1 +324 0x2000 //TX_B_POST_FILT_2 +325 0x2000 //TX_B_POST_FILT_3 +326 0x2000 //TX_B_POST_FILT_4 +327 0x2000 //TX_B_POST_FILT_5 +328 0x2000 //TX_B_POST_FILT_6 +329 0x2000 //TX_B_POST_FILT_7 +330 0x7FFF //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x7FFF //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7E00 //TX_LAMBDA_PFILT +339 0x7E00 //TX_LAMBDA_PFILT_S_0 +340 0x7E00 //TX_LAMBDA_PFILT_S_1 +341 0x7E00 //TX_LAMBDA_PFILT_S_2 +342 0x7E00 //TX_LAMBDA_PFILT_S_3 +343 0x7E00 //TX_LAMBDA_PFILT_S_4 +344 0x7E00 //TX_LAMBDA_PFILT_S_5 +345 0x7E00 //TX_LAMBDA_PFILT_S_6 +346 0x7E00 //TX_LAMBDA_PFILT_S_7 +347 0x0010 //TX_K_PEPPER +348 0x0400 //TX_A_PEPPER +349 0x0000 //TX_K_PEPPER_HF +350 0x0000 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x4000 //TX_HMNC_BST_THR +353 0x0000 //TX_DT_BINVAD_TH_0 +354 0x0000 //TX_DT_BINVAD_TH_1 +355 0x0000 //TX_DT_BINVAD_TH_2 +356 0x0000 //TX_DT_BINVAD_TH_3 +357 0x0000 //TX_DT_BINVAD_ENDF +358 0x0000 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0001 //TX_BF_SGRAD_FLG +362 0x0000 //TX_BF_DVG_TH +363 0x0000 //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x05A0 //TX_NDETCT +367 0x0383 //TX_NOISE_TH_0 +368 0x1388 //TX_NOISE_TH_0_2 +369 0x3A98 //TX_NOISE_TH_0_3 +370 0x0C80 //TX_NOISE_TH_1 +371 0x0032 //TX_NOISE_TH_2 +372 0x3D54 //TX_NOISE_TH_3 +373 0x012C //TX_NOISE_TH_4 +374 0x07D0 //TX_NOISE_TH_5 +375 0x6590 //TX_NOISE_TH_5_2 +376 0x7FFF //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x00C8 //TX_NOISE_TH_6 +379 0x044C //TX_MINENOISE_TH +380 0xD508 //TX_MORENS_TFMASK_TH +381 0x0001 //TX_DRC_QUIET_FLOOR +382 0x3A98 //TX_RATIODTL_CUT_TH +383 0x0DAC //TX_DT_CUT_K1 +384 0x6400 //TX_OUT_ENER_S_TH_CLEAN +385 0x6400 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x6400 //TX_OUT_ENER_S_TH_NOISY +387 0x6400 //TX_OUT_ENER_TH_NOISE +388 0x7D00 //TX_OUT_ENER_TH_SPEECH +389 0x0000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x7FFF //TX_POST_MASK_SUP_HSNE +392 0x1388 //TX_TAIL_DET_TH +393 0x4000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0080 //TX_SUPHIGH_TH +396 0x0000 //TX_MASK_G_R +397 0x0000 //TX_EXTRA_NS_L +398 0x1800 //TX_C_POST_FLT_MASK +399 0x7FFF //TX_A_POST_FLT_WNS +400 0x0000 //TX_MIN_G_LOW300HZ +401 0x0010 //TX_MAXLEVEL_CNG +402 0x0000 //TX_STN_NOISE_TH +403 0x0000 //TX_POST_MASK_SUP +404 0x0000 //TX_POST_MASK_ADJUST +405 0x0014 //TX_NS_ENOISE_MIC0_TH +406 0x02F3 //TX_MINENOISE_MIC0_TH +407 0x0226 //TX_MINENOISE_MIC0_S_TH +408 0x2879 //TX_MIN_G_CTRL_SSNS +409 0x0400 //TX_METAL_RTO_THR +410 0x0080 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x2000 //TX_RHO_UPB +415 0x0020 //TX_N_HOLD_HS +416 0x0009 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0000 //TX_EXTRA_GAIN_MICBLOCK +419 0x0333 //TX_THR_STD_NSR +420 0x0219 //TX_THR_STD_PLH +421 0x09C4 //TX_N_HOLD_STD +422 0x0166 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0800 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x0000 //TX_SB_RTO_MEAN_TH_RUB +428 0x2000 //TX_WTA_EN_RTO_TH +429 0x1400 //TX_TOP_ENER_TH_F +430 0x0064 //TX_DESIRED_TALK_HOLDT +431 0x1000 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0000 //TX_HS_VAD_BIN +435 0x0000 //TX_THR_VAD_HS +436 0x0000 //TX_MEAN_RTO_MIN_TH2 +437 0x0000 //TX_SILENCE_T +438 0x4000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x099A //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x001E //TX_DOA_VAD_THR_1 +445 0x001E //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x00B4 //TX_SRC_DOA_RNG_HIGH_0B +453 0x005A //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x00B4 //TX_SRC_DOA_RNG_HIGH_0C +456 0x005A //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x00B4 //TX_SRC_DOA_RNG_HIGH_0D +459 0x005A //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0172 //TX_BF_HOLDOFF_T +473 0x8000 //TX_DOA_COST_FACTOR +474 0x0D9A //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x071C //TX_DOA_TRACK_HT +477 0x0280 //TX_N1_HOLD_HF +478 0x0140 //TX_N2_HOLD_HF +479 0x2AAB //TX_BF_RESET_THR_HF +480 0x4000 //TX_DOA_SMOOTH +481 0x0000 //TX_MU_BF +482 0x0200 //TX_BF_MU_LF_B2 +483 0x0000 //TX_BF_FC_END_BIN_B2 +484 0x0000 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0000 //TX_N_DOA_SEED +488 0x0000 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x0000 //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x0000 //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x0000 //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x0168 //TX_NOR_OFF_THR +498 0x0CCD //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0004 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0230 //TX_NOR_OFF_TH1 +503 0xD333 //TX_WIDE_MASK_TH +504 0x4650 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x6000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x000A //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x6666 //TX_MICTOBFGAIN0 +513 0x0014 //TX_FASTMUE_TH +514 0xC000 //TX_DEREVERB_LF_MU +515 0xC000 //TX_DEREVERB_HF_MU +516 0xCCCC //TX_DEREVERB_DELAY +517 0xD999 //TX_DEREVERB_COEF_LEN +518 0x1F40 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x7000 //TX_GSC_RTOH_TH +523 0x0064 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x0000 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0028 //TX_SNR_THR +531 0x03E8 //TX_ENGY_THR +532 0x0000 //TX_CORR_HIGH_TH +533 0x0000 //TX_ENGY_THR_2 +534 0x0000 //TX_MEAN_RTO_THR +535 0x0000 //TX_WNS_ENOISE_MIC0_TH +536 0x0000 //TX_RATIOMICL_TH +537 0x0000 //TX_CALIG_HS +538 0x000A //TX_LVL_CTRL +539 0x0000 //TX_WIND_SUPRTO +540 0x0000 //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x0000 //TX_RATIOMICH_TH +543 0x0000 //TX_WIND_INBEAM_L_TH +544 0x0000 //TX_WIND_INBEAM_H_TH +545 0x0000 //TX_WNS_RESRV_0 +546 0x0000 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0000 //TX_BF_LESSCUT_BBIN +554 0x0000 //TX_BF_LESSCUT_EBIN +555 0x0000 //TX_POSTBFB0 +556 0x0000 //TX_POSTBFB +557 0x0000 //TX_POSTBFE +558 0x0000 //TX_SPEECH_SNR_TH +559 0x0000 //TX_PB_MAX_PRI_SNR_TH +560 0x0000 //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0020 //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4848 //TX_FDEQ_GAIN_5 +573 0x4848 //TX_FDEQ_GAIN_6 +574 0x4848 //TX_FDEQ_GAIN_7 +575 0x4848 //TX_FDEQ_GAIN_8 +576 0x4848 //TX_FDEQ_GAIN_9 +577 0x4848 //TX_FDEQ_GAIN_10 +578 0x4848 //TX_FDEQ_GAIN_11 +579 0x4848 //TX_FDEQ_GAIN_12 +580 0x4848 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0000 //TX_FDEQ_BIN_0 +592 0x0000 //TX_FDEQ_BIN_1 +593 0x0000 //TX_FDEQ_BIN_2 +594 0x0000 //TX_FDEQ_BIN_3 +595 0x0000 //TX_FDEQ_BIN_4 +596 0x0000 //TX_FDEQ_BIN_5 +597 0x0000 //TX_FDEQ_BIN_6 +598 0x0000 //TX_FDEQ_BIN_7 +599 0x0000 //TX_FDEQ_BIN_8 +600 0x0000 //TX_FDEQ_BIN_9 +601 0x0000 //TX_FDEQ_BIN_10 +602 0x0000 //TX_FDEQ_BIN_11 +603 0x0000 //TX_FDEQ_BIN_12 +604 0x0000 //TX_FDEQ_BIN_13 +605 0x0000 //TX_FDEQ_BIN_14 +606 0x0000 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4848 //TX_PREEQ_GAIN_MIC0_8 +626 0x4848 //TX_PREEQ_GAIN_MIC0_9 +627 0x4848 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0000 //TX_PREEQ_BIN_MIC0_0 +642 0x0000 //TX_PREEQ_BIN_MIC0_1 +643 0x0000 //TX_PREEQ_BIN_MIC0_2 +644 0x0000 //TX_PREEQ_BIN_MIC0_3 +645 0x0000 //TX_PREEQ_BIN_MIC0_4 +646 0x0000 //TX_PREEQ_BIN_MIC0_5 +647 0x0000 //TX_PREEQ_BIN_MIC0_6 +648 0x0000 //TX_PREEQ_BIN_MIC0_7 +649 0x0000 //TX_PREEQ_BIN_MIC0_8 +650 0x0000 //TX_PREEQ_BIN_MIC0_9 +651 0x0000 //TX_PREEQ_BIN_MIC0_10 +652 0x0000 //TX_PREEQ_BIN_MIC0_11 +653 0x0000 //TX_PREEQ_BIN_MIC0_12 +654 0x0000 //TX_PREEQ_BIN_MIC0_13 +655 0x0000 //TX_PREEQ_BIN_MIC0_14 +656 0x0000 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0000 //TX_PREEQ_BIN_MIC1_0 +691 0x0000 //TX_PREEQ_BIN_MIC1_1 +692 0x0000 //TX_PREEQ_BIN_MIC1_2 +693 0x0000 //TX_PREEQ_BIN_MIC1_3 +694 0x0000 //TX_PREEQ_BIN_MIC1_4 +695 0x0000 //TX_PREEQ_BIN_MIC1_5 +696 0x0000 //TX_PREEQ_BIN_MIC1_6 +697 0x0000 //TX_PREEQ_BIN_MIC1_7 +698 0x0000 //TX_PREEQ_BIN_MIC1_8 +699 0x0000 //TX_PREEQ_BIN_MIC1_9 +700 0x0000 //TX_PREEQ_BIN_MIC1_10 +701 0x0000 //TX_PREEQ_BIN_MIC1_11 +702 0x0000 //TX_PREEQ_BIN_MIC1_12 +703 0x0000 //TX_PREEQ_BIN_MIC1_13 +704 0x0000 //TX_PREEQ_BIN_MIC1_14 +705 0x0000 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0000 //TX_PREEQ_BIN_MIC2_0 +740 0x0000 //TX_PREEQ_BIN_MIC2_1 +741 0x0000 //TX_PREEQ_BIN_MIC2_2 +742 0x0000 //TX_PREEQ_BIN_MIC2_3 +743 0x0000 //TX_PREEQ_BIN_MIC2_4 +744 0x0000 //TX_PREEQ_BIN_MIC2_5 +745 0x0000 //TX_PREEQ_BIN_MIC2_6 +746 0x0000 //TX_PREEQ_BIN_MIC2_7 +747 0x0000 //TX_PREEQ_BIN_MIC2_8 +748 0x0000 //TX_PREEQ_BIN_MIC2_9 +749 0x0000 //TX_PREEQ_BIN_MIC2_10 +750 0x0000 //TX_PREEQ_BIN_MIC2_11 +751 0x0000 //TX_PREEQ_BIN_MIC2_12 +752 0x0000 //TX_PREEQ_BIN_MIC2_13 +753 0x0000 //TX_PREEQ_BIN_MIC2_14 +754 0x0000 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x2000 //TX_NND_WEIGHT +765 0x0064 //TX_MIC_CALIBRATION_0 +766 0x006A //TX_MIC_CALIBRATION_1 +767 0x006A //TX_MIC_CALIBRATION_2 +768 0x006B //TX_MIC_CALIBRATION_3 +769 0x0048 //TX_MIC_PWR_BIAS_0 +770 0x003C //TX_MIC_PWR_BIAS_1 +771 0x003C //TX_MIC_PWR_BIAS_2 +772 0x003C //TX_MIC_PWR_BIAS_3 +773 0x0000 //TX_GAIN_LIMIT_0 +774 0x0009 //TX_GAIN_LIMIT_1 +775 0x000C //TX_GAIN_LIMIT_2 +776 0x000F //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F3D //TX_BVE_NOVAD0_ALPHAUP +783 0x3000 //TX_TDDRC_ALPHA_UP_01 +784 0x3000 //TX_TDDRC_ALPHA_UP_02 +785 0x3000 //TX_TDDRC_ALPHA_UP_03 +786 0x3000 //TX_TDDRC_ALPHA_UP_04 +787 0x7FB0 //TX_TDDRC_ALPHA_DWN_01 +788 0x7FB0 //TX_TDDRC_ALPHA_DWN_02 +789 0x7FB0 //TX_TDDRC_ALPHA_DWN_03 +790 0x7FB0 //TX_TDDRC_ALPHA_DWN_04 +791 0x65AD //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0002 //TX_DEADMIC_SILENCE_TH +817 0x0147 //TX_MIC_DEGRADE_TH +818 0x0078 //TX_DEADMIC_CNT +819 0x0078 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x0000 //TX_KS_NOISEPASTE_FACTOR +824 0x0000 //TX_KS_CONFIG +825 0x0000 //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x0000 //TX_FFP_FP_K_METAL +834 0x0000 //TX_A_POST_FLT_FP +835 0x0000 //TX_RTO_OUTBEAM_TH +836 0x0000 //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0000 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0000 //TX_FFP_RESRV_2 +849 0x0000 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0002 //TX_FILTINDX +854 0x0000 //TX_TDDRC_THRD_0 +855 0x0000 //TX_TDDRC_THRD_1 +856 0x0E80 //TX_TDDRC_THRD_2 +857 0x3800 //TX_TDDRC_THRD_3 +858 0x2A00 //TX_TDDRC_SLANT_0 +859 0x6E00 //TX_TDDRC_SLANT_1 +860 0x3000 //TX_TDDRC_ALPHA_UP_00 +861 0x7FB0 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x0000 //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0000 //TX_TDDRC_SMT_W +866 0x0100 //TX_TDDRC_DRC_GAIN +867 0x0000 //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x1EB8 //TX_TFMASKLTH +870 0x170A //TX_TFMASKLTHL +871 0x7FFF //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0x0CCD //TX_TFMASKTH_BLESSCUT +876 0x4000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x0000 //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x0000 //TX_FASTNS_OUTIN_TH +884 0x0000 //TX_FASTNS_TFMASK_TH +885 0x0000 //TX_FASTNS_TFMASKBIN_TH1 +886 0x0000 //TX_FASTNS_TFMASKBIN_TH2 +887 0x0000 //TX_FASTNS_TFMASKBIN_TH3 +888 0x00C8 //TX_FASTNS_ARSPC_TH +889 0x8000 //TX_FASTNS_MASK5_TH +890 0x051F //TX_POSTSSA_MIN_G_VR_MASK +891 0x4000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x2339 //TX_SENDFUNC_REG_MICMUTE +898 0x0021 //TX_SENDFUNC_REG_MICMUTE1 +899 0x02BC //TX_MICMUTE_RATIO_THR +900 0x0140 //TX_MICMUTE_AMP_THR +901 0x0004 //TX_MICMUTE_HPF_IND +902 0x00C0 //TX_MICMUTE_LOG_EYR_TH +903 0x0008 //TX_MICMUTE_CVG_TIME +904 0x0008 //TX_MICMUTE_RELEASE_TIME +905 0x01FE //TX_MIC_VOLUME_MIC0MUTE +906 0x0020 //TX_MICMUTE_EPD_OFFSET_0 +907 0x001E //TX_MICMUTE_FRQ_AEC_L +908 0x7999 //TX_MICMUTE_EAD_THR +909 0x7FFF //TX_MICMUTE_LAMBDA_CB_NLE +910 0x7FFF //TX_MICMUTE_LAMBDA_RE_EST +911 0x4000 //TX_DTD_THR1_MICMUTE_0 +912 0x7000 //TX_DTD_THR1_MICMUTE_1 +913 0x7FFF //TX_DTD_THR1_MICMUTE_2 +914 0x7FFF //TX_DTD_THR1_MICMUTE_3 +915 0x6CCC //TX_DTD_THR2_MICMUTE_0 +916 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x1000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x4000 //TX_MICMUTE_C_POST_FLT +922 0x03E8 //TX_MICMUTE_DT_CUT_K +923 0x0001 //TX_MICMUTE_DT_CUT_THR +924 0x03E8 //TX_MICMUTE_DT_CUT_K2 +925 0x0001 //TX_MICMUTE_DT_CUT_THR2 +926 0x0064 //TX_MICMUTE_DT2_HOLD_N +927 0x1000 //TX_MICMUTE_RATIODTH_THCUT +928 0x1000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x7FFF //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0400 //TX_MICMUTE_C_POST_FLT_MASK +931 0x7999 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0258 //TX_MICMUTE_DT_CUT_K1 +933 0x0800 //TX_MICMUTE_N2_SN_EST +934 0xFC00 //TX_MICMUTE_THR_SN_EST_0 +935 0x001C //TX_MICMUTE_MIN_G_CTRL_0 +936 0x6000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x7000 //TX_MICMUTE_B_POST_FILT_0 +938 0x2710 //TX_MIC1RUB_AMP_THR +939 0x0010 //TX_MIC1MUTE_RATIO_THR +940 0x0450 //TX_MIC1MUTE_AMP_THR +941 0x0008 //TX_MIC1MUTE_CVG_TIME +942 0x0008 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x243C //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0003 //RX_SAMPLINGFREQ_SIG +3 0x0003 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x6000 //RX_TDDRC_ALPHA_UP_1 +7 0x6000 //RX_TDDRC_ALPHA_UP_2 +8 0x6000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +10 0x0403 //RX_PGA +11 0x7D83 //RX_A_HP +12 0x4000 //RX_B_PE +13 0x7800 //RX_THR_PITCH_DET_0 +14 0x7000 //RX_THR_PITCH_DET_1 +15 0x6000 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0400 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x0010 //RX_NS_LVL_CTRL +23 0xF800 //RX_THR_SN_EST +24 0x7E00 //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +29 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x7C48 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4860 //RX_FDEQ_GAIN_8 +48 0x7468 //RX_FDEQ_GAIN_9 +49 0x5858 //RX_FDEQ_GAIN_10 +50 0x5858 //RX_FDEQ_GAIN_11 +51 0x5C54 //RX_FDEQ_GAIN_12 +52 0x5448 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x5858 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0404 //RX_FDEQ_BIN_4 +68 0x0308 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +92 0x0120 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0002 //RX_FILTINDX +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1A00 //RX_TDDRC_THRD_2 +115 0x1A00 //RX_TDDRC_THRD_3 +116 0x7EB8 //RX_TDDRC_SLANT_0 +117 0x2500 //RX_TDDRC_SLANT_1 +118 0x6000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0550 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x0FA0 //RX_TPKA_FP +127 0x0400 //RX_MIN_G_FP +128 0x0800 //RX_MAX_G_FP +129 0x0014 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x6000 //RX_TDDRC_ALPHA_UP_1 +7 0x6000 //RX_TDDRC_ALPHA_UP_2 +8 0x6000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x4000 //RX_TDDRC_ALPHA_DWN_2 +29 0x4000 //RX_TDDRC_ALPHA_DWN_3 +32 0x4000 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x6000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0780 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x6868 //RX_FDEQ_GAIN_0 +40 0x6848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x3434 //RX_FDEQ_GAIN_3 +43 0x3840 //RX_FDEQ_GAIN_4 +44 0x4838 //RX_FDEQ_GAIN_5 +45 0x5444 //RX_FDEQ_GAIN_6 +46 0x443C //RX_FDEQ_GAIN_7 +47 0x3C60 //RX_FDEQ_GAIN_8 +48 0x6460 //RX_FDEQ_GAIN_9 +49 0x6064 //RX_FDEQ_GAIN_10 +50 0x5C5C //RX_FDEQ_GAIN_11 +51 0x5440 //RX_FDEQ_GAIN_12 +52 0x4040 //RX_FDEQ_GAIN_13 +53 0x4040 //RX_FDEQ_GAIN_14 +54 0x5858 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0404 //RX_FDEQ_BIN_4 +68 0x0308 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +92 0x0120 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0011 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x6000 //RX_TDDRC_ALPHA_UP_1 +7 0x6000 //RX_TDDRC_ALPHA_UP_2 +8 0x6000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x4000 //RX_TDDRC_ALPHA_DWN_2 +29 0x4000 //RX_TDDRC_ALPHA_DWN_3 +32 0x4000 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x6000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0780 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x6868 //RX_FDEQ_GAIN_0 +40 0x6848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x3434 //RX_FDEQ_GAIN_3 +43 0x3840 //RX_FDEQ_GAIN_4 +44 0x4838 //RX_FDEQ_GAIN_5 +45 0x5444 //RX_FDEQ_GAIN_6 +46 0x443C //RX_FDEQ_GAIN_7 +47 0x3C60 //RX_FDEQ_GAIN_8 +48 0x6460 //RX_FDEQ_GAIN_9 +49 0x6064 //RX_FDEQ_GAIN_10 +50 0x5C5C //RX_FDEQ_GAIN_11 +51 0x5440 //RX_FDEQ_GAIN_12 +52 0x4040 //RX_FDEQ_GAIN_13 +53 0x4040 //RX_FDEQ_GAIN_14 +54 0x5858 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0404 //RX_FDEQ_BIN_4 +68 0x0308 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +92 0x0120 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0019 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x6000 //RX_TDDRC_ALPHA_UP_1 +7 0x6000 //RX_TDDRC_ALPHA_UP_2 +8 0x6000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x4000 //RX_TDDRC_ALPHA_DWN_2 +29 0x4000 //RX_TDDRC_ALPHA_DWN_3 +32 0x4000 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x6000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0780 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x6868 //RX_FDEQ_GAIN_0 +40 0x6848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x3434 //RX_FDEQ_GAIN_3 +43 0x3840 //RX_FDEQ_GAIN_4 +44 0x4838 //RX_FDEQ_GAIN_5 +45 0x5444 //RX_FDEQ_GAIN_6 +46 0x443C //RX_FDEQ_GAIN_7 +47 0x3C60 //RX_FDEQ_GAIN_8 +48 0x6460 //RX_FDEQ_GAIN_9 +49 0x6064 //RX_FDEQ_GAIN_10 +50 0x5C5C //RX_FDEQ_GAIN_11 +51 0x5440 //RX_FDEQ_GAIN_12 +52 0x4040 //RX_FDEQ_GAIN_13 +53 0x4040 //RX_FDEQ_GAIN_14 +54 0x5858 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0404 //RX_FDEQ_BIN_4 +68 0x0308 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +92 0x0120 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0025 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x6000 //RX_TDDRC_ALPHA_UP_1 +7 0x6000 //RX_TDDRC_ALPHA_UP_2 +8 0x6000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x4000 //RX_TDDRC_ALPHA_DWN_2 +29 0x4000 //RX_TDDRC_ALPHA_DWN_3 +32 0x4000 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x6000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0780 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x6868 //RX_FDEQ_GAIN_0 +40 0x6848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x3434 //RX_FDEQ_GAIN_3 +43 0x3840 //RX_FDEQ_GAIN_4 +44 0x4838 //RX_FDEQ_GAIN_5 +45 0x5444 //RX_FDEQ_GAIN_6 +46 0x443C //RX_FDEQ_GAIN_7 +47 0x3C60 //RX_FDEQ_GAIN_8 +48 0x6460 //RX_FDEQ_GAIN_9 +49 0x6064 //RX_FDEQ_GAIN_10 +50 0x5C5C //RX_FDEQ_GAIN_11 +51 0x5440 //RX_FDEQ_GAIN_12 +52 0x4040 //RX_FDEQ_GAIN_13 +53 0x4040 //RX_FDEQ_GAIN_14 +54 0x5858 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0404 //RX_FDEQ_BIN_4 +68 0x0308 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +92 0x0120 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0036 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x6000 //RX_TDDRC_ALPHA_UP_1 +7 0x6000 //RX_TDDRC_ALPHA_UP_2 +8 0x6000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x4000 //RX_TDDRC_ALPHA_DWN_2 +29 0x4000 //RX_TDDRC_ALPHA_DWN_3 +32 0x4000 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x6000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0D56 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x6868 //RX_FDEQ_GAIN_0 +40 0x6850 //RX_FDEQ_GAIN_1 +41 0x5048 //RX_FDEQ_GAIN_2 +42 0x383C //RX_FDEQ_GAIN_3 +43 0x4048 //RX_FDEQ_GAIN_4 +44 0x7040 //RX_FDEQ_GAIN_5 +45 0x4C44 //RX_FDEQ_GAIN_6 +46 0x4448 //RX_FDEQ_GAIN_7 +47 0x4868 //RX_FDEQ_GAIN_8 +48 0x7C70 //RX_FDEQ_GAIN_9 +49 0x707C //RX_FDEQ_GAIN_10 +50 0x786C //RX_FDEQ_GAIN_11 +51 0x6454 //RX_FDEQ_GAIN_12 +52 0x604C //RX_FDEQ_GAIN_13 +53 0x585C //RX_FDEQ_GAIN_14 +54 0x7480 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0404 //RX_FDEQ_BIN_4 +68 0x0308 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +92 0x0120 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0034 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x6000 //RX_TDDRC_ALPHA_UP_1 +7 0x6000 //RX_TDDRC_ALPHA_UP_2 +8 0x6000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x4000 //RX_TDDRC_ALPHA_DWN_2 +29 0x4000 //RX_TDDRC_ALPHA_DWN_3 +32 0x4000 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x6000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0D56 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x6868 //RX_FDEQ_GAIN_0 +40 0x6850 //RX_FDEQ_GAIN_1 +41 0x5048 //RX_FDEQ_GAIN_2 +42 0x383C //RX_FDEQ_GAIN_3 +43 0x4048 //RX_FDEQ_GAIN_4 +44 0x7040 //RX_FDEQ_GAIN_5 +45 0x4C44 //RX_FDEQ_GAIN_6 +46 0x4448 //RX_FDEQ_GAIN_7 +47 0x4868 //RX_FDEQ_GAIN_8 +48 0x7C70 //RX_FDEQ_GAIN_9 +49 0x707C //RX_FDEQ_GAIN_10 +50 0x786C //RX_FDEQ_GAIN_11 +51 0x6454 //RX_FDEQ_GAIN_12 +52 0x604C //RX_FDEQ_GAIN_13 +53 0x585C //RX_FDEQ_GAIN_14 +54 0x7480 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0404 //RX_FDEQ_BIN_4 +68 0x0308 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +92 0x0120 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0059 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x6000 //RX_TDDRC_ALPHA_UP_1 +7 0x6000 //RX_TDDRC_ALPHA_UP_2 +8 0x6000 //RX_TDDRC_ALPHA_UP_3 +9 0x1000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x4000 //RX_TDDRC_ALPHA_DWN_2 +29 0x4000 //RX_TDDRC_ALPHA_DWN_3 +32 0x4000 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0002 //RX_TDDRC_THRD_0 +113 0x0004 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x6000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0D56 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x6868 //RX_FDEQ_GAIN_0 +40 0x6850 //RX_FDEQ_GAIN_1 +41 0x5048 //RX_FDEQ_GAIN_2 +42 0x383C //RX_FDEQ_GAIN_3 +43 0x4048 //RX_FDEQ_GAIN_4 +44 0x7040 //RX_FDEQ_GAIN_5 +45 0x4C44 //RX_FDEQ_GAIN_6 +46 0x4448 //RX_FDEQ_GAIN_7 +47 0x4868 //RX_FDEQ_GAIN_8 +48 0x7C70 //RX_FDEQ_GAIN_9 +49 0x707C //RX_FDEQ_GAIN_10 +50 0x786C //RX_FDEQ_GAIN_11 +51 0x6454 //RX_FDEQ_GAIN_12 +52 0x604C //RX_FDEQ_GAIN_13 +53 0x585C //RX_FDEQ_GAIN_14 +54 0x7480 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0304 //RX_FDEQ_BIN_3 +67 0x0404 //RX_FDEQ_BIN_4 +68 0x0308 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0035 //RX_FDDRC_BAND_MARGIN_1 +91 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +92 0x0120 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x243C //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0003 //RX_SAMPLINGFREQ_SIG +160 0x0003 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x6000 //RX_TDDRC_ALPHA_UP_1 +164 0x6000 //RX_TDDRC_ALPHA_UP_2 +165 0x6000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +167 0x0403 //RX_PGA +168 0x7D83 //RX_A_HP +169 0x4000 //RX_B_PE +170 0x7800 //RX_THR_PITCH_DET_0 +171 0x7000 //RX_THR_PITCH_DET_1 +172 0x6000 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0400 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x0010 //RX_NS_LVL_CTRL +180 0xF800 //RX_THR_SN_EST +181 0x7E00 //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x7EB8 //RX_TDDRC_ALPHA_DWN_2 +186 0x7EB8 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x7EB8 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x7C48 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4860 //RX_FDEQ_GAIN_8 +205 0x7468 //RX_FDEQ_GAIN_9 +206 0x5858 //RX_FDEQ_GAIN_10 +207 0x5858 //RX_FDEQ_GAIN_11 +208 0x5C54 //RX_FDEQ_GAIN_12 +209 0x5448 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x5858 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0404 //RX_FDEQ_BIN_4 +225 0x0308 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +249 0x0120 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0002 //RX_FILTINDX +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1A00 //RX_TDDRC_THRD_2 +272 0x1A00 //RX_TDDRC_THRD_3 +273 0x7EB8 //RX_TDDRC_SLANT_0 +274 0x2500 //RX_TDDRC_SLANT_1 +275 0x6000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0550 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x0FA0 //RX_TPKA_FP +284 0x0400 //RX_MIN_G_FP +285 0x0800 //RX_MAX_G_FP +286 0x0014 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x6000 //RX_TDDRC_ALPHA_UP_1 +164 0x6000 //RX_TDDRC_ALPHA_UP_2 +165 0x6000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x4000 //RX_TDDRC_ALPHA_DWN_2 +186 0x4000 //RX_TDDRC_ALPHA_DWN_3 +189 0x4000 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x6000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0780 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x6868 //RX_FDEQ_GAIN_0 +197 0x6848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x3434 //RX_FDEQ_GAIN_3 +200 0x3840 //RX_FDEQ_GAIN_4 +201 0x4838 //RX_FDEQ_GAIN_5 +202 0x5444 //RX_FDEQ_GAIN_6 +203 0x443C //RX_FDEQ_GAIN_7 +204 0x3C60 //RX_FDEQ_GAIN_8 +205 0x6460 //RX_FDEQ_GAIN_9 +206 0x6064 //RX_FDEQ_GAIN_10 +207 0x5C5C //RX_FDEQ_GAIN_11 +208 0x5440 //RX_FDEQ_GAIN_12 +209 0x4040 //RX_FDEQ_GAIN_13 +210 0x4040 //RX_FDEQ_GAIN_14 +211 0x5858 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0404 //RX_FDEQ_BIN_4 +225 0x0308 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +249 0x0120 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0011 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x6000 //RX_TDDRC_ALPHA_UP_1 +164 0x6000 //RX_TDDRC_ALPHA_UP_2 +165 0x6000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x4000 //RX_TDDRC_ALPHA_DWN_2 +186 0x4000 //RX_TDDRC_ALPHA_DWN_3 +189 0x4000 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x6000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0780 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x6868 //RX_FDEQ_GAIN_0 +197 0x6848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x3434 //RX_FDEQ_GAIN_3 +200 0x3840 //RX_FDEQ_GAIN_4 +201 0x4838 //RX_FDEQ_GAIN_5 +202 0x5444 //RX_FDEQ_GAIN_6 +203 0x443C //RX_FDEQ_GAIN_7 +204 0x3C60 //RX_FDEQ_GAIN_8 +205 0x6460 //RX_FDEQ_GAIN_9 +206 0x6064 //RX_FDEQ_GAIN_10 +207 0x5C5C //RX_FDEQ_GAIN_11 +208 0x5440 //RX_FDEQ_GAIN_12 +209 0x4040 //RX_FDEQ_GAIN_13 +210 0x4040 //RX_FDEQ_GAIN_14 +211 0x5858 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0404 //RX_FDEQ_BIN_4 +225 0x0308 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +249 0x0120 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0019 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x6000 //RX_TDDRC_ALPHA_UP_1 +164 0x6000 //RX_TDDRC_ALPHA_UP_2 +165 0x6000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x4000 //RX_TDDRC_ALPHA_DWN_2 +186 0x4000 //RX_TDDRC_ALPHA_DWN_3 +189 0x4000 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x6000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0780 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x6868 //RX_FDEQ_GAIN_0 +197 0x6848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x3434 //RX_FDEQ_GAIN_3 +200 0x3840 //RX_FDEQ_GAIN_4 +201 0x4838 //RX_FDEQ_GAIN_5 +202 0x5444 //RX_FDEQ_GAIN_6 +203 0x443C //RX_FDEQ_GAIN_7 +204 0x3C60 //RX_FDEQ_GAIN_8 +205 0x6460 //RX_FDEQ_GAIN_9 +206 0x6064 //RX_FDEQ_GAIN_10 +207 0x5C5C //RX_FDEQ_GAIN_11 +208 0x5440 //RX_FDEQ_GAIN_12 +209 0x4040 //RX_FDEQ_GAIN_13 +210 0x4040 //RX_FDEQ_GAIN_14 +211 0x5858 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0404 //RX_FDEQ_BIN_4 +225 0x0308 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +249 0x0120 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0025 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x6000 //RX_TDDRC_ALPHA_UP_1 +164 0x6000 //RX_TDDRC_ALPHA_UP_2 +165 0x6000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x4000 //RX_TDDRC_ALPHA_DWN_2 +186 0x4000 //RX_TDDRC_ALPHA_DWN_3 +189 0x4000 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x6000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0780 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x6868 //RX_FDEQ_GAIN_0 +197 0x6848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x3434 //RX_FDEQ_GAIN_3 +200 0x3840 //RX_FDEQ_GAIN_4 +201 0x4838 //RX_FDEQ_GAIN_5 +202 0x5444 //RX_FDEQ_GAIN_6 +203 0x443C //RX_FDEQ_GAIN_7 +204 0x3C60 //RX_FDEQ_GAIN_8 +205 0x6460 //RX_FDEQ_GAIN_9 +206 0x6064 //RX_FDEQ_GAIN_10 +207 0x5C5C //RX_FDEQ_GAIN_11 +208 0x5440 //RX_FDEQ_GAIN_12 +209 0x4040 //RX_FDEQ_GAIN_13 +210 0x4040 //RX_FDEQ_GAIN_14 +211 0x5858 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0404 //RX_FDEQ_BIN_4 +225 0x0308 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +249 0x0120 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0036 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x6000 //RX_TDDRC_ALPHA_UP_1 +164 0x6000 //RX_TDDRC_ALPHA_UP_2 +165 0x6000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x4000 //RX_TDDRC_ALPHA_DWN_2 +186 0x4000 //RX_TDDRC_ALPHA_DWN_3 +189 0x4000 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x6000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0D56 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x6868 //RX_FDEQ_GAIN_0 +197 0x6850 //RX_FDEQ_GAIN_1 +198 0x5048 //RX_FDEQ_GAIN_2 +199 0x383C //RX_FDEQ_GAIN_3 +200 0x4048 //RX_FDEQ_GAIN_4 +201 0x7040 //RX_FDEQ_GAIN_5 +202 0x4C44 //RX_FDEQ_GAIN_6 +203 0x4448 //RX_FDEQ_GAIN_7 +204 0x4868 //RX_FDEQ_GAIN_8 +205 0x7C70 //RX_FDEQ_GAIN_9 +206 0x707C //RX_FDEQ_GAIN_10 +207 0x786C //RX_FDEQ_GAIN_11 +208 0x6454 //RX_FDEQ_GAIN_12 +209 0x604C //RX_FDEQ_GAIN_13 +210 0x585C //RX_FDEQ_GAIN_14 +211 0x7480 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0404 //RX_FDEQ_BIN_4 +225 0x0308 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +249 0x0120 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0034 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x6000 //RX_TDDRC_ALPHA_UP_1 +164 0x6000 //RX_TDDRC_ALPHA_UP_2 +165 0x6000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x4000 //RX_TDDRC_ALPHA_DWN_2 +186 0x4000 //RX_TDDRC_ALPHA_DWN_3 +189 0x4000 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x6000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0D56 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x6868 //RX_FDEQ_GAIN_0 +197 0x6850 //RX_FDEQ_GAIN_1 +198 0x5048 //RX_FDEQ_GAIN_2 +199 0x383C //RX_FDEQ_GAIN_3 +200 0x4048 //RX_FDEQ_GAIN_4 +201 0x7040 //RX_FDEQ_GAIN_5 +202 0x4C44 //RX_FDEQ_GAIN_6 +203 0x4448 //RX_FDEQ_GAIN_7 +204 0x4868 //RX_FDEQ_GAIN_8 +205 0x7C70 //RX_FDEQ_GAIN_9 +206 0x707C //RX_FDEQ_GAIN_10 +207 0x786C //RX_FDEQ_GAIN_11 +208 0x6454 //RX_FDEQ_GAIN_12 +209 0x604C //RX_FDEQ_GAIN_13 +210 0x585C //RX_FDEQ_GAIN_14 +211 0x7480 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0404 //RX_FDEQ_BIN_4 +225 0x0308 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +249 0x0120 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0059 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x6000 //RX_TDDRC_ALPHA_UP_1 +164 0x6000 //RX_TDDRC_ALPHA_UP_2 +165 0x6000 //RX_TDDRC_ALPHA_UP_3 +166 0x1000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x4000 //RX_TDDRC_ALPHA_DWN_2 +186 0x4000 //RX_TDDRC_ALPHA_DWN_3 +189 0x4000 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0002 //RX_TDDRC_THRD_0 +270 0x0004 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x6000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0D56 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x6868 //RX_FDEQ_GAIN_0 +197 0x6850 //RX_FDEQ_GAIN_1 +198 0x5048 //RX_FDEQ_GAIN_2 +199 0x383C //RX_FDEQ_GAIN_3 +200 0x4048 //RX_FDEQ_GAIN_4 +201 0x7040 //RX_FDEQ_GAIN_5 +202 0x4C44 //RX_FDEQ_GAIN_6 +203 0x4448 //RX_FDEQ_GAIN_7 +204 0x4868 //RX_FDEQ_GAIN_8 +205 0x7C70 //RX_FDEQ_GAIN_9 +206 0x707C //RX_FDEQ_GAIN_10 +207 0x786C //RX_FDEQ_GAIN_11 +208 0x6454 //RX_FDEQ_GAIN_12 +209 0x604C //RX_FDEQ_GAIN_13 +210 0x585C //RX_FDEQ_GAIN_14 +211 0x7480 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0304 //RX_FDEQ_BIN_3 +224 0x0404 //RX_FDEQ_BIN_4 +225 0x0308 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0035 //RX_FDDRC_BAND_MARGIN_1 +248 0x00D5 //RX_FDDRC_BAND_MARGIN_2 +249 0x0120 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME HEADSET-TTY_HCO-VOICE_GENERIC-FB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0001 //TX_OPERATION_MODE_0 +1 0x0000 //TX_OPERATION_MODE_1 +2 0x0000 //TX_PATCH_REG +3 0x0200 //TX_SENDFUNC_MODE_0 +4 0x0000 //TX_SENDFUNC_MODE_1 +5 0x0001 //TX_NUM_MIC +6 0x0000 //TX_SAMPLINGFREQ_SIG +7 0x0000 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x0078 //TX_DIST2REF1 +22 0x0000 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0302 //TX_PGA_0 +28 0x0800 //TX_PGA_1 +29 0x0800 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0000 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0000 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0000 //TX_MICS_OF_PAIR0 +38 0x0000 //TX_MICS_OF_PAIR1 +39 0x0000 //TX_MICS_OF_PAIR2 +40 0x0000 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0001 //TX_MIC_DATA_SRC1 +43 0x0002 //TX_MIC_DATA_SRC2 +44 0x0003 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x0000 //TX_HD_BIN_MASK +53 0x0000 //TX_HD_SUBAND_MASK +54 0x0000 //TX_HD_FRAME_AVG_MASK +55 0x0000 //TX_HD_MIN_FRQ +56 0x0000 //TX_HD_ALPHA_PSD +57 0x0000 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0x0000 //TX_T_PSDVAT +63 0x0000 //TX_CNT +64 0x0000 //TX_ANTI_HOWL_GAIN +65 0x0000 //TX_MICFORBFMARK_0 +66 0x0000 //TX_MICFORBFMARK_1 +67 0x0000 //TX_MICFORBFMARK_2 +68 0x0000 //TX_MICFORBFMARK_3 +69 0x0000 //TX_MICFORBFMARK_4 +70 0x0000 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x0000 //TX_DIST2REF_11 +73 0x0000 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0800 //TX_MIC_REFBLK_VOLUME +108 0x0800 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x0000 //TX_ADCS_GAIN +112 0x0000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x7FFF //TX_BLMIC_BLKFACTOR +116 0x7FFF //TX_BRMIC_BLKFACTOR +117 0x000A //TX_MICBLK_START_BIN +118 0x0041 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0015 //TX_FENE_HOLD +123 0x0000 //TX_FE_ENER_TH_MTS +124 0x0000 //TX_FE_ENER_TH_EXP +125 0x0000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x0000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0020 //TX_MIC_BLOCK_N +128 0x7652 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x7800 //TX_THR_PITCH_DET_0 +131 0x7000 //TX_THR_PITCH_DET_1 +132 0x6000 //TX_THR_PITCH_DET_2 +133 0x0000 //TX_PITCH_BFR_LEN +134 0x0000 //TX_SBD_PITCH_DET +135 0x0000 //TX_TD_AEC_L +136 0x0000 //TX_MU0_UNP_TD_AEC +137 0x0000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x0028 //TX_TAIL_LENGTH +147 0x2000 //TX_AEC_REF_GAIN_0 +148 0x2000 //TX_AEC_REF_GAIN_1 +149 0x2000 //TX_AEC_REF_GAIN_2 +150 0x4000 //TX_EAD_THR +151 0x0200 //TX_THR_RE_EST +152 0x0100 //TX_MIN_EQ_RE_EST_0 +153 0x0100 //TX_MIN_EQ_RE_EST_1 +154 0x0100 //TX_MIN_EQ_RE_EST_2 +155 0x0100 //TX_MIN_EQ_RE_EST_3 +156 0x0100 //TX_MIN_EQ_RE_EST_4 +157 0x0100 //TX_MIN_EQ_RE_EST_5 +158 0x0100 //TX_MIN_EQ_RE_EST_6 +159 0x0100 //TX_MIN_EQ_RE_EST_7 +160 0x0100 //TX_MIN_EQ_RE_EST_8 +161 0x0100 //TX_MIN_EQ_RE_EST_9 +162 0x0100 //TX_MIN_EQ_RE_EST_10 +163 0x0100 //TX_MIN_EQ_RE_EST_11 +164 0x0100 //TX_MIN_EQ_RE_EST_12 +165 0x4000 //TX_LAMBDA_RE_EST +166 0x0000 //TX_LAMBDA_CB_NLE +167 0x0000 //TX_C_POST_FLT +168 0x4000 //TX_GAIN_NP +169 0x0008 //TX_SE_HOLD_N +170 0x0050 //TX_DT_HOLD_N +171 0x03E8 //TX_DT2_HOLD_N +172 0x0000 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x0000 //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0000 //TX_FRQ_LIN_LEN +184 0x0000 //TX_FRQ_AEC_LEN_RHO +185 0x0000 //TX_MU0_UNP_FRQ_AEC +186 0x0000 //TX_MU0_PTD_FRQ_AEC +187 0x0000 //TX_MINENOISETH +188 0x0000 //TX_MU0_RE_EST +189 0x0000 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x0000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x7333 //TX_DTD_THR1_0 +198 0x7333 //TX_DTD_THR1_1 +199 0x7333 //TX_DTD_THR1_2 +200 0x7333 //TX_DTD_THR1_3 +201 0x7333 //TX_DTD_THR1_4 +202 0x7333 //TX_DTD_THR1_5 +203 0x7333 //TX_DTD_THR1_6 +204 0x0CCD //TX_DTD_THR2_0 +205 0x0CCD //TX_DTD_THR2_1 +206 0x0CCD //TX_DTD_THR2_2 +207 0x0CCD //TX_DTD_THR2_3 +208 0x0CCD //TX_DTD_THR2_4 +209 0x0CCD //TX_DTD_THR2_5 +210 0x0CCD //TX_DTD_THR2_6 +211 0x7FFF //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x0400 //TX_DT_CUT_K +214 0x0000 //TX_DT_CUT_THR +215 0x0000 //TX_COMFORT_G +216 0x0000 //TX_POWER_YOUT_TH +217 0x0000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x0400 //TX_ADPT_STRICT_L +222 0x0200 //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x0800 //TX_B_POST_FILT_ECHO_L +229 0x0800 //TX_B_POST_FILT_ECHO_H +230 0x0000 //TX_MIN_G_CTRL_ECHO +231 0x7FFF //TX_B_LESSCUT_RTO_ECHO +232 0x0000 //TX_EPD_OFFSET_00 +233 0x0000 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x0000 //TX_MIN_EQ_RE_EST_13 +237 0x0000 //TX_DTD_THR1_7 +238 0x0000 //TX_DTD_THR2_7 +239 0x0000 //TX_DT_RESRV_7 +240 0x0000 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xF700 //TX_THR_SN_EST_0 +243 0xF400 //TX_THR_SN_EST_1 +244 0xF800 //TX_THR_SN_EST_2 +245 0xF600 //TX_THR_SN_EST_3 +246 0xF800 //TX_THR_SN_EST_4 +247 0xF800 //TX_THR_SN_EST_5 +248 0xF800 //TX_THR_SN_EST_6 +249 0xF800 //TX_THR_SN_EST_7 +250 0x0100 //TX_DELTA_THR_SN_EST_0 +251 0x0100 //TX_DELTA_THR_SN_EST_1 +252 0x0100 //TX_DELTA_THR_SN_EST_2 +253 0x0200 //TX_DELTA_THR_SN_EST_3 +254 0x0200 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0000 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x4000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x4000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0A00 //TX_N_SN_EST +267 0x0000 //TX_INBEAM_T +268 0x0000 //TX_INBEAMHOLDT +269 0x1FFF //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x1000 //TX_NE_RTO_TH_L +274 0x1000 //TX_MAINREFRTOH_TH_H +275 0x1000 //TX_MAINREFRTOH_TH_L +276 0x2000 //TX_MAINREFRTO_TH_H +277 0x1400 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x0000 //TX_B_POST_FLT_0 +280 0x0000 //TX_B_POST_FLT_1 +281 0x001A //TX_NS_LVL_CTRL_0 +282 0x0014 //TX_NS_LVL_CTRL_1 +283 0x0014 //TX_NS_LVL_CTRL_2 +284 0x000C //TX_NS_LVL_CTRL_3 +285 0x000C //TX_NS_LVL_CTRL_4 +286 0x000C //TX_NS_LVL_CTRL_5 +287 0x001A //TX_NS_LVL_CTRL_6 +288 0x000C //TX_NS_LVL_CTRL_7 +289 0x000E //TX_MIN_GAIN_S_0 +290 0x0014 //TX_MIN_GAIN_S_1 +291 0x0014 //TX_MIN_GAIN_S_2 +292 0x0014 //TX_MIN_GAIN_S_3 +293 0x0014 //TX_MIN_GAIN_S_4 +294 0x0014 //TX_MIN_GAIN_S_5 +295 0x0014 //TX_MIN_GAIN_S_6 +296 0x0014 //TX_MIN_GAIN_S_7 +297 0x0000 //TX_NMOS_SUP +298 0x0064 //TX_NS_MAX_PRI_SNR_TH +299 0x7FFF //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x7FFF //TX_SNRI_SUP_1 +302 0x7FFF //TX_SNRI_SUP_2 +303 0x4000 //TX_SNRI_SUP_3 +304 0x4000 //TX_SNRI_SUP_4 +305 0x4000 //TX_SNRI_SUP_5 +306 0x7FFF //TX_SNRI_SUP_6 +307 0x4000 //TX_SNRI_SUP_7 +308 0x1200 //TX_THR_LFNS +309 0x0147 //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x7FFF //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x7FFF //TX_A_POST_FILT_1 +314 0x4000 //TX_A_POST_FILT_S_0 +315 0x1000 //TX_A_POST_FILT_S_1 +316 0x1000 //TX_A_POST_FILT_S_2 +317 0x6666 //TX_A_POST_FILT_S_3 +318 0x6666 //TX_A_POST_FILT_S_4 +319 0x6666 //TX_A_POST_FILT_S_5 +320 0x199A //TX_A_POST_FILT_S_6 +321 0x6666 //TX_A_POST_FILT_S_7 +322 0x2000 //TX_B_POST_FILT_0 +323 0x2000 //TX_B_POST_FILT_1 +324 0x2000 //TX_B_POST_FILT_2 +325 0x2000 //TX_B_POST_FILT_3 +326 0x2000 //TX_B_POST_FILT_4 +327 0x2000 //TX_B_POST_FILT_5 +328 0x2000 //TX_B_POST_FILT_6 +329 0x2000 //TX_B_POST_FILT_7 +330 0x7FFF //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x7FFF //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7E00 //TX_LAMBDA_PFILT +339 0x7E00 //TX_LAMBDA_PFILT_S_0 +340 0x7E00 //TX_LAMBDA_PFILT_S_1 +341 0x7E00 //TX_LAMBDA_PFILT_S_2 +342 0x7E00 //TX_LAMBDA_PFILT_S_3 +343 0x7E00 //TX_LAMBDA_PFILT_S_4 +344 0x7E00 //TX_LAMBDA_PFILT_S_5 +345 0x7E00 //TX_LAMBDA_PFILT_S_6 +346 0x7E00 //TX_LAMBDA_PFILT_S_7 +347 0x0010 //TX_K_PEPPER +348 0x0400 //TX_A_PEPPER +349 0x0000 //TX_K_PEPPER_HF +350 0x0000 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x4000 //TX_HMNC_BST_THR +353 0x0000 //TX_DT_BINVAD_TH_0 +354 0x0000 //TX_DT_BINVAD_TH_1 +355 0x0000 //TX_DT_BINVAD_TH_2 +356 0x0000 //TX_DT_BINVAD_TH_3 +357 0x0000 //TX_DT_BINVAD_ENDF +358 0x0000 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0001 //TX_BF_SGRAD_FLG +362 0x0000 //TX_BF_DVG_TH +363 0x0000 //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x05A0 //TX_NDETCT +367 0x04E8 //TX_NOISE_TH_0 +368 0x1388 //TX_NOISE_TH_0_2 +369 0x3A98 //TX_NOISE_TH_0_3 +370 0x0C80 //TX_NOISE_TH_1 +371 0x0032 //TX_NOISE_TH_2 +372 0x3D54 //TX_NOISE_TH_3 +373 0x012C //TX_NOISE_TH_4 +374 0x07D0 //TX_NOISE_TH_5 +375 0x6590 //TX_NOISE_TH_5_2 +376 0x7FFF //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x00C8 //TX_NOISE_TH_6 +379 0x02BC //TX_MINENOISE_TH +380 0xD508 //TX_MORENS_TFMASK_TH +381 0x0001 //TX_DRC_QUIET_FLOOR +382 0x3A98 //TX_RATIODTL_CUT_TH +383 0x1482 //TX_DT_CUT_K1 +384 0x6400 //TX_OUT_ENER_S_TH_CLEAN +385 0x6400 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x6400 //TX_OUT_ENER_S_TH_NOISY +387 0x6400 //TX_OUT_ENER_TH_NOISE +388 0x7D00 //TX_OUT_ENER_TH_SPEECH +389 0x0000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x7FFF //TX_POST_MASK_SUP_HSNE +392 0x1388 //TX_TAIL_DET_TH +393 0x4000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0080 //TX_SUPHIGH_TH +396 0x0000 //TX_MASK_G_R +397 0x0000 //TX_EXTRA_NS_L +398 0x1800 //TX_C_POST_FLT_MASK +399 0x7FFF //TX_A_POST_FLT_WNS +400 0x0000 //TX_MIN_G_LOW300HZ +401 0x0010 //TX_MAXLEVEL_CNG +402 0x0000 //TX_STN_NOISE_TH +403 0x0000 //TX_POST_MASK_SUP +404 0x0000 //TX_POST_MASK_ADJUST +405 0x0014 //TX_NS_ENOISE_MIC0_TH +406 0x04E7 //TX_MINENOISE_MIC0_TH +407 0x0226 //TX_MINENOISE_MIC0_S_TH +408 0x2879 //TX_MIN_G_CTRL_SSNS +409 0x0400 //TX_METAL_RTO_THR +410 0x0080 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x2000 //TX_RHO_UPB +415 0x0020 //TX_N_HOLD_HS +416 0x0009 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0000 //TX_EXTRA_GAIN_MICBLOCK +419 0x0333 //TX_THR_STD_NSR +420 0x0219 //TX_THR_STD_PLH +421 0x09C4 //TX_N_HOLD_STD +422 0x0166 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0800 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x0000 //TX_SB_RTO_MEAN_TH_RUB +428 0x2000 //TX_WTA_EN_RTO_TH +429 0x1400 //TX_TOP_ENER_TH_F +430 0x0064 //TX_DESIRED_TALK_HOLDT +431 0x1000 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0000 //TX_HS_VAD_BIN +435 0x0000 //TX_THR_VAD_HS +436 0x0000 //TX_MEAN_RTO_MIN_TH2 +437 0x0000 //TX_SILENCE_T +438 0x4000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x099A //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x001E //TX_DOA_VAD_THR_1 +445 0x001E //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x00B4 //TX_SRC_DOA_RNG_HIGH_0B +453 0x005A //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x00B4 //TX_SRC_DOA_RNG_HIGH_0C +456 0x005A //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x00B4 //TX_SRC_DOA_RNG_HIGH_0D +459 0x005A //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0172 //TX_BF_HOLDOFF_T +473 0x8000 //TX_DOA_COST_FACTOR +474 0x0D9A //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x071C //TX_DOA_TRACK_HT +477 0x0280 //TX_N1_HOLD_HF +478 0x0140 //TX_N2_HOLD_HF +479 0x2AAB //TX_BF_RESET_THR_HF +480 0x4000 //TX_DOA_SMOOTH +481 0x0000 //TX_MU_BF +482 0x0200 //TX_BF_MU_LF_B2 +483 0x0000 //TX_BF_FC_END_BIN_B2 +484 0x0000 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0000 //TX_N_DOA_SEED +488 0x0000 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x0000 //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x0000 //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x0000 //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x0168 //TX_NOR_OFF_THR +498 0x0CCD //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0004 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0230 //TX_NOR_OFF_TH1 +503 0xD333 //TX_WIDE_MASK_TH +504 0x4650 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x6000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x000A //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x6666 //TX_MICTOBFGAIN0 +513 0x0014 //TX_FASTMUE_TH +514 0xC000 //TX_DEREVERB_LF_MU +515 0xC000 //TX_DEREVERB_HF_MU +516 0xCCCC //TX_DEREVERB_DELAY +517 0xD999 //TX_DEREVERB_COEF_LEN +518 0x1F40 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x7000 //TX_GSC_RTOH_TH +523 0x0064 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x0000 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0028 //TX_SNR_THR +531 0x03E8 //TX_ENGY_THR +532 0x0000 //TX_CORR_HIGH_TH +533 0x0000 //TX_ENGY_THR_2 +534 0x0000 //TX_MEAN_RTO_THR +535 0x0000 //TX_WNS_ENOISE_MIC0_TH +536 0x0000 //TX_RATIOMICL_TH +537 0x0000 //TX_CALIG_HS +538 0x000A //TX_LVL_CTRL +539 0x0000 //TX_WIND_SUPRTO +540 0x0000 //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x0000 //TX_RATIOMICH_TH +543 0x0000 //TX_WIND_INBEAM_L_TH +544 0x0000 //TX_WIND_INBEAM_H_TH +545 0x0000 //TX_WNS_RESRV_0 +546 0x0000 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0000 //TX_BF_LESSCUT_BBIN +554 0x0000 //TX_BF_LESSCUT_EBIN +555 0x0000 //TX_POSTBFB0 +556 0x0000 //TX_POSTBFB +557 0x0000 //TX_POSTBFE +558 0x0000 //TX_SPEECH_SNR_TH +559 0x0000 //TX_PB_MAX_PRI_SNR_TH +560 0x0000 //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0020 //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4848 //TX_FDEQ_GAIN_5 +573 0x4848 //TX_FDEQ_GAIN_6 +574 0x4848 //TX_FDEQ_GAIN_7 +575 0x4848 //TX_FDEQ_GAIN_8 +576 0x4848 //TX_FDEQ_GAIN_9 +577 0x4848 //TX_FDEQ_GAIN_10 +578 0x4848 //TX_FDEQ_GAIN_11 +579 0x4848 //TX_FDEQ_GAIN_12 +580 0x4848 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0000 //TX_FDEQ_BIN_0 +592 0x0000 //TX_FDEQ_BIN_1 +593 0x0000 //TX_FDEQ_BIN_2 +594 0x0000 //TX_FDEQ_BIN_3 +595 0x0000 //TX_FDEQ_BIN_4 +596 0x0000 //TX_FDEQ_BIN_5 +597 0x0000 //TX_FDEQ_BIN_6 +598 0x0000 //TX_FDEQ_BIN_7 +599 0x0000 //TX_FDEQ_BIN_8 +600 0x0000 //TX_FDEQ_BIN_9 +601 0x0000 //TX_FDEQ_BIN_10 +602 0x0000 //TX_FDEQ_BIN_11 +603 0x0000 //TX_FDEQ_BIN_12 +604 0x0000 //TX_FDEQ_BIN_13 +605 0x0000 //TX_FDEQ_BIN_14 +606 0x0000 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4848 //TX_PREEQ_GAIN_MIC0_8 +626 0x4848 //TX_PREEQ_GAIN_MIC0_9 +627 0x4848 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0000 //TX_PREEQ_BIN_MIC0_0 +642 0x0000 //TX_PREEQ_BIN_MIC0_1 +643 0x0000 //TX_PREEQ_BIN_MIC0_2 +644 0x0000 //TX_PREEQ_BIN_MIC0_3 +645 0x0000 //TX_PREEQ_BIN_MIC0_4 +646 0x0000 //TX_PREEQ_BIN_MIC0_5 +647 0x0000 //TX_PREEQ_BIN_MIC0_6 +648 0x0000 //TX_PREEQ_BIN_MIC0_7 +649 0x0000 //TX_PREEQ_BIN_MIC0_8 +650 0x0000 //TX_PREEQ_BIN_MIC0_9 +651 0x0000 //TX_PREEQ_BIN_MIC0_10 +652 0x0000 //TX_PREEQ_BIN_MIC0_11 +653 0x0000 //TX_PREEQ_BIN_MIC0_12 +654 0x0000 //TX_PREEQ_BIN_MIC0_13 +655 0x0000 //TX_PREEQ_BIN_MIC0_14 +656 0x0000 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0000 //TX_PREEQ_BIN_MIC1_0 +691 0x0000 //TX_PREEQ_BIN_MIC1_1 +692 0x0000 //TX_PREEQ_BIN_MIC1_2 +693 0x0000 //TX_PREEQ_BIN_MIC1_3 +694 0x0000 //TX_PREEQ_BIN_MIC1_4 +695 0x0000 //TX_PREEQ_BIN_MIC1_5 +696 0x0000 //TX_PREEQ_BIN_MIC1_6 +697 0x0000 //TX_PREEQ_BIN_MIC1_7 +698 0x0000 //TX_PREEQ_BIN_MIC1_8 +699 0x0000 //TX_PREEQ_BIN_MIC1_9 +700 0x0000 //TX_PREEQ_BIN_MIC1_10 +701 0x0000 //TX_PREEQ_BIN_MIC1_11 +702 0x0000 //TX_PREEQ_BIN_MIC1_12 +703 0x0000 //TX_PREEQ_BIN_MIC1_13 +704 0x0000 //TX_PREEQ_BIN_MIC1_14 +705 0x0000 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0000 //TX_PREEQ_BIN_MIC2_0 +740 0x0000 //TX_PREEQ_BIN_MIC2_1 +741 0x0000 //TX_PREEQ_BIN_MIC2_2 +742 0x0000 //TX_PREEQ_BIN_MIC2_3 +743 0x0000 //TX_PREEQ_BIN_MIC2_4 +744 0x0000 //TX_PREEQ_BIN_MIC2_5 +745 0x0000 //TX_PREEQ_BIN_MIC2_6 +746 0x0000 //TX_PREEQ_BIN_MIC2_7 +747 0x0000 //TX_PREEQ_BIN_MIC2_8 +748 0x0000 //TX_PREEQ_BIN_MIC2_9 +749 0x0000 //TX_PREEQ_BIN_MIC2_10 +750 0x0000 //TX_PREEQ_BIN_MIC2_11 +751 0x0000 //TX_PREEQ_BIN_MIC2_12 +752 0x0000 //TX_PREEQ_BIN_MIC2_13 +753 0x0000 //TX_PREEQ_BIN_MIC2_14 +754 0x0000 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x2000 //TX_NND_WEIGHT +765 0x0064 //TX_MIC_CALIBRATION_0 +766 0x006A //TX_MIC_CALIBRATION_1 +767 0x006A //TX_MIC_CALIBRATION_2 +768 0x006B //TX_MIC_CALIBRATION_3 +769 0x0048 //TX_MIC_PWR_BIAS_0 +770 0x003C //TX_MIC_PWR_BIAS_1 +771 0x003C //TX_MIC_PWR_BIAS_2 +772 0x003C //TX_MIC_PWR_BIAS_3 +773 0x0000 //TX_GAIN_LIMIT_0 +774 0x0009 //TX_GAIN_LIMIT_1 +775 0x000C //TX_GAIN_LIMIT_2 +776 0x000F //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F3D //TX_BVE_NOVAD0_ALPHAUP +783 0x3000 //TX_TDDRC_ALPHA_UP_01 +784 0x3000 //TX_TDDRC_ALPHA_UP_02 +785 0x3000 //TX_TDDRC_ALPHA_UP_03 +786 0x3000 //TX_TDDRC_ALPHA_UP_04 +787 0x7FB0 //TX_TDDRC_ALPHA_DWN_01 +788 0x7FB0 //TX_TDDRC_ALPHA_DWN_02 +789 0x7FB0 //TX_TDDRC_ALPHA_DWN_03 +790 0x7FB0 //TX_TDDRC_ALPHA_DWN_04 +791 0x65AD //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0002 //TX_DEADMIC_SILENCE_TH +817 0x0147 //TX_MIC_DEGRADE_TH +818 0x0078 //TX_DEADMIC_CNT +819 0x0078 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x0000 //TX_KS_NOISEPASTE_FACTOR +824 0x0000 //TX_KS_CONFIG +825 0x0000 //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x0000 //TX_FFP_FP_K_METAL +834 0x0000 //TX_A_POST_FLT_FP +835 0x0000 //TX_RTO_OUTBEAM_TH +836 0x0000 //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0000 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0000 //TX_FFP_RESRV_2 +849 0x0000 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0002 //TX_FILTINDX +854 0x0000 //TX_TDDRC_THRD_0 +855 0x0000 //TX_TDDRC_THRD_1 +856 0x0E80 //TX_TDDRC_THRD_2 +857 0x3800 //TX_TDDRC_THRD_3 +858 0x2A00 //TX_TDDRC_SLANT_0 +859 0x6E00 //TX_TDDRC_SLANT_1 +860 0x3000 //TX_TDDRC_ALPHA_UP_00 +861 0x7FB0 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x0000 //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0000 //TX_TDDRC_SMT_W +866 0x0100 //TX_TDDRC_DRC_GAIN +867 0x0000 //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x1EB8 //TX_TFMASKLTH +870 0x170A //TX_TFMASKLTHL +871 0x7FFF //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0x0CCD //TX_TFMASKTH_BLESSCUT +876 0x4000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x0000 //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x0000 //TX_FASTNS_OUTIN_TH +884 0x0000 //TX_FASTNS_TFMASK_TH +885 0x0000 //TX_FASTNS_TFMASKBIN_TH1 +886 0x0000 //TX_FASTNS_TFMASKBIN_TH2 +887 0x0000 //TX_FASTNS_TFMASKBIN_TH3 +888 0x00C8 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x051F //TX_POSTSSA_MIN_G_VR_MASK +891 0x7000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x2339 //TX_SENDFUNC_REG_MICMUTE +898 0x0021 //TX_SENDFUNC_REG_MICMUTE1 +899 0x02BC //TX_MICMUTE_RATIO_THR +900 0x0140 //TX_MICMUTE_AMP_THR +901 0x0004 //TX_MICMUTE_HPF_IND +902 0x00C0 //TX_MICMUTE_LOG_EYR_TH +903 0x0008 //TX_MICMUTE_CVG_TIME +904 0x0008 //TX_MICMUTE_RELEASE_TIME +905 0x01FE //TX_MIC_VOLUME_MIC0MUTE +906 0x0020 //TX_MICMUTE_EPD_OFFSET_0 +907 0x001E //TX_MICMUTE_FRQ_AEC_L +908 0x7999 //TX_MICMUTE_EAD_THR +909 0x7FFF //TX_MICMUTE_LAMBDA_CB_NLE +910 0x7FFF //TX_MICMUTE_LAMBDA_RE_EST +911 0x4000 //TX_DTD_THR1_MICMUTE_0 +912 0x7000 //TX_DTD_THR1_MICMUTE_1 +913 0x7FFF //TX_DTD_THR1_MICMUTE_2 +914 0x7FFF //TX_DTD_THR1_MICMUTE_3 +915 0x6CCC //TX_DTD_THR2_MICMUTE_0 +916 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x1000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x4000 //TX_MICMUTE_C_POST_FLT +922 0x03E8 //TX_MICMUTE_DT_CUT_K +923 0x0001 //TX_MICMUTE_DT_CUT_THR +924 0x03E8 //TX_MICMUTE_DT_CUT_K2 +925 0x0001 //TX_MICMUTE_DT_CUT_THR2 +926 0x0064 //TX_MICMUTE_DT2_HOLD_N +927 0x1000 //TX_MICMUTE_RATIODTH_THCUT +928 0x1000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x7FFF //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0400 //TX_MICMUTE_C_POST_FLT_MASK +931 0x7999 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0258 //TX_MICMUTE_DT_CUT_K1 +933 0x0800 //TX_MICMUTE_N2_SN_EST +934 0xFC00 //TX_MICMUTE_THR_SN_EST_0 +935 0x001C //TX_MICMUTE_MIN_G_CTRL_0 +936 0x6000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x7000 //TX_MICMUTE_B_POST_FILT_0 +938 0x2710 //TX_MIC1RUB_AMP_THR +939 0x0010 //TX_MIC1MUTE_RATIO_THR +940 0x0450 //TX_MIC1MUTE_AMP_THR +941 0x0008 //TX_MIC1MUTE_CVG_TIME +942 0x0008 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x242C //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0004 //RX_SAMPLINGFREQ_SIG +3 0x0004 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x4000 //RX_TDDRC_ALPHA_UP_1 +7 0x4000 //RX_TDDRC_ALPHA_UP_2 +8 0x4000 //RX_TDDRC_ALPHA_UP_3 +9 0x4000 //RX_TDDRC_ALPHA_UP_4 +10 0x0403 //RX_PGA +11 0x7E56 //RX_A_HP +12 0x4000 //RX_B_PE +13 0x7800 //RX_THR_PITCH_DET_0 +14 0x7000 //RX_THR_PITCH_DET_1 +15 0x6000 //RX_THR_PITCH_DET_2 +16 0x0008 //RX_PITCH_BFR_LEN +17 0x0003 //RX_SBD_PITCH_DET +18 0x0100 //RX_PP_RESRV_0 +19 0x0020 //RX_PP_RESRV_1 +20 0x0400 //RX_N_SN_EST +21 0x000C //RX_N2_SN_EST +22 0x0014 //RX_NS_LVL_CTRL +23 0xF400 //RX_THR_SN_EST +24 0x7E00 //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0190 //RX_FENS_RESRV_1 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x4000 //RX_TDDRC_ALPHA_DWN_2 +29 0x4000 //RX_TDDRC_ALPHA_DWN_3 +30 0x0002 //RX_EXTRA_NS_L +31 0x0800 //RX_EXTRA_NS_A +32 0x4000 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x199A //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4040 //RX_FDEQ_GAIN_1 +41 0x3838 //RX_FDEQ_GAIN_2 +42 0x3448 //RX_FDEQ_GAIN_3 +43 0x343C //RX_FDEQ_GAIN_4 +44 0x4040 //RX_FDEQ_GAIN_5 +45 0x4048 //RX_FDEQ_GAIN_6 +46 0x384C //RX_FDEQ_GAIN_7 +47 0x4C54 //RX_FDEQ_GAIN_8 +48 0x5C54 //RX_FDEQ_GAIN_9 +49 0x4E38 //RX_FDEQ_GAIN_10 +50 0x303C //RX_FDEQ_GAIN_11 +51 0x5450 //RX_FDEQ_GAIN_12 +52 0x4860 //RX_FDEQ_GAIN_13 +53 0x6060 //RX_FDEQ_GAIN_14 +54 0x6060 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0402 //RX_FDEQ_BIN_3 +67 0x0504 //RX_FDEQ_BIN_4 +68 0x0209 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0002 //RX_FILTINDX +112 0x0001 //RX_TDDRC_THRD_0 +113 0x0002 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x4000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0439 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x1B58 //RX_TPKA_FP +127 0x0400 //RX_MIN_G_FP +128 0x0800 //RX_MAX_G_FP +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0000 //RX_MAXLEVEL_CNG +132 0x3000 //RX_BWE_UV_TH +133 0x3000 //RX_BWE_UV_TH2 +134 0x1800 //RX_BWE_UV_TH3 +135 0x1000 //RX_BWE_V_TH +136 0x04CD //RX_BWE_GAIN1_V_TH1 +137 0x0F33 //RX_BWE_GAIN1_V_TH2 +138 0x7333 //RX_BWE_UV_EQ +139 0x199A //RX_BWE_V_EQ +140 0x7333 //RX_BWE_TONE_TH +141 0x0004 //RX_BWE_UV_HOLD_T +142 0x6CCD //RX_BWE_GAIN2_ALPHA +143 0x799A //RX_BWE_GAIN3_ALPHA +144 0x001E //RX_BWE_CUTOFF +145 0x3000 //RX_BWE_GAINFILL +146 0x3200 //RX_BWE_MAXTH_TONE +147 0x2000 //RX_BWE_EQ_0 +148 0x2000 //RX_BWE_EQ_1 +149 0x2000 //RX_BWE_EQ_2 +150 0x2000 //RX_BWE_EQ_3 +151 0x2000 //RX_BWE_EQ_4 +152 0x2000 //RX_BWE_EQ_5 +153 0x2000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x4000 //RX_TDDRC_ALPHA_UP_1 +7 0x4000 //RX_TDDRC_ALPHA_UP_2 +8 0x4000 //RX_TDDRC_ALPHA_UP_3 +9 0x4000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x4000 //RX_TDDRC_ALPHA_DWN_2 +29 0x4000 //RX_TDDRC_ALPHA_DWN_3 +32 0x4000 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0001 //RX_TDDRC_THRD_0 +113 0x0002 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x4000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0439 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4040 //RX_FDEQ_GAIN_1 +41 0x3838 //RX_FDEQ_GAIN_2 +42 0x3448 //RX_FDEQ_GAIN_3 +43 0x343C //RX_FDEQ_GAIN_4 +44 0x4040 //RX_FDEQ_GAIN_5 +45 0x4048 //RX_FDEQ_GAIN_6 +46 0x384C //RX_FDEQ_GAIN_7 +47 0x4C54 //RX_FDEQ_GAIN_8 +48 0x5C54 //RX_FDEQ_GAIN_9 +49 0x4E38 //RX_FDEQ_GAIN_10 +50 0x303C //RX_FDEQ_GAIN_11 +51 0x5450 //RX_FDEQ_GAIN_12 +52 0x4860 //RX_FDEQ_GAIN_13 +53 0x6060 //RX_FDEQ_GAIN_14 +54 0x6060 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0402 //RX_FDEQ_BIN_3 +67 0x0504 //RX_FDEQ_BIN_4 +68 0x0209 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0012 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x4000 //RX_TDDRC_ALPHA_UP_1 +7 0x4000 //RX_TDDRC_ALPHA_UP_2 +8 0x4000 //RX_TDDRC_ALPHA_UP_3 +9 0x4000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x4000 //RX_TDDRC_ALPHA_DWN_2 +29 0x4000 //RX_TDDRC_ALPHA_DWN_3 +32 0x4000 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0001 //RX_TDDRC_THRD_0 +113 0x0002 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x4000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0439 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4040 //RX_FDEQ_GAIN_1 +41 0x3838 //RX_FDEQ_GAIN_2 +42 0x3448 //RX_FDEQ_GAIN_3 +43 0x343C //RX_FDEQ_GAIN_4 +44 0x4040 //RX_FDEQ_GAIN_5 +45 0x4048 //RX_FDEQ_GAIN_6 +46 0x384C //RX_FDEQ_GAIN_7 +47 0x4C54 //RX_FDEQ_GAIN_8 +48 0x5C54 //RX_FDEQ_GAIN_9 +49 0x4E38 //RX_FDEQ_GAIN_10 +50 0x303C //RX_FDEQ_GAIN_11 +51 0x5450 //RX_FDEQ_GAIN_12 +52 0x4860 //RX_FDEQ_GAIN_13 +53 0x6060 //RX_FDEQ_GAIN_14 +54 0x6060 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0402 //RX_FDEQ_BIN_3 +67 0x0504 //RX_FDEQ_BIN_4 +68 0x0209 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x001A //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x4000 //RX_TDDRC_ALPHA_UP_1 +7 0x4000 //RX_TDDRC_ALPHA_UP_2 +8 0x4000 //RX_TDDRC_ALPHA_UP_3 +9 0x4000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x4000 //RX_TDDRC_ALPHA_DWN_2 +29 0x4000 //RX_TDDRC_ALPHA_DWN_3 +32 0x4000 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0001 //RX_TDDRC_THRD_0 +113 0x0002 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x4000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0439 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4040 //RX_FDEQ_GAIN_1 +41 0x3838 //RX_FDEQ_GAIN_2 +42 0x3448 //RX_FDEQ_GAIN_3 +43 0x343C //RX_FDEQ_GAIN_4 +44 0x4040 //RX_FDEQ_GAIN_5 +45 0x4048 //RX_FDEQ_GAIN_6 +46 0x384C //RX_FDEQ_GAIN_7 +47 0x4C54 //RX_FDEQ_GAIN_8 +48 0x5C54 //RX_FDEQ_GAIN_9 +49 0x4E38 //RX_FDEQ_GAIN_10 +50 0x303C //RX_FDEQ_GAIN_11 +51 0x5450 //RX_FDEQ_GAIN_12 +52 0x4860 //RX_FDEQ_GAIN_13 +53 0x6060 //RX_FDEQ_GAIN_14 +54 0x6060 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0402 //RX_FDEQ_BIN_3 +67 0x0504 //RX_FDEQ_BIN_4 +68 0x0209 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0025 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x4000 //RX_TDDRC_ALPHA_UP_1 +7 0x4000 //RX_TDDRC_ALPHA_UP_2 +8 0x4000 //RX_TDDRC_ALPHA_UP_3 +9 0x4000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x4000 //RX_TDDRC_ALPHA_DWN_2 +29 0x4000 //RX_TDDRC_ALPHA_DWN_3 +32 0x4000 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0001 //RX_TDDRC_THRD_0 +113 0x0002 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x4000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0439 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4040 //RX_FDEQ_GAIN_1 +41 0x3838 //RX_FDEQ_GAIN_2 +42 0x3448 //RX_FDEQ_GAIN_3 +43 0x343C //RX_FDEQ_GAIN_4 +44 0x4040 //RX_FDEQ_GAIN_5 +45 0x4048 //RX_FDEQ_GAIN_6 +46 0x384C //RX_FDEQ_GAIN_7 +47 0x4C54 //RX_FDEQ_GAIN_8 +48 0x5C54 //RX_FDEQ_GAIN_9 +49 0x4E38 //RX_FDEQ_GAIN_10 +50 0x303C //RX_FDEQ_GAIN_11 +51 0x5450 //RX_FDEQ_GAIN_12 +52 0x4860 //RX_FDEQ_GAIN_13 +53 0x6060 //RX_FDEQ_GAIN_14 +54 0x6060 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0402 //RX_FDEQ_BIN_3 +67 0x0504 //RX_FDEQ_BIN_4 +68 0x0209 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0035 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x4000 //RX_TDDRC_ALPHA_UP_1 +7 0x4000 //RX_TDDRC_ALPHA_UP_2 +8 0x4000 //RX_TDDRC_ALPHA_UP_3 +9 0x4000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x4000 //RX_TDDRC_ALPHA_DWN_2 +29 0x4000 //RX_TDDRC_ALPHA_DWN_3 +32 0x4000 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0001 //RX_TDDRC_THRD_0 +113 0x0002 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x4000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0439 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4040 //RX_FDEQ_GAIN_1 +41 0x3838 //RX_FDEQ_GAIN_2 +42 0x3448 //RX_FDEQ_GAIN_3 +43 0x343C //RX_FDEQ_GAIN_4 +44 0x4040 //RX_FDEQ_GAIN_5 +45 0x4048 //RX_FDEQ_GAIN_6 +46 0x384C //RX_FDEQ_GAIN_7 +47 0x4C54 //RX_FDEQ_GAIN_8 +48 0x5C54 //RX_FDEQ_GAIN_9 +49 0x4E38 //RX_FDEQ_GAIN_10 +50 0x303C //RX_FDEQ_GAIN_11 +51 0x5450 //RX_FDEQ_GAIN_12 +52 0x4860 //RX_FDEQ_GAIN_13 +53 0x6060 //RX_FDEQ_GAIN_14 +54 0x6060 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0402 //RX_FDEQ_BIN_3 +67 0x0504 //RX_FDEQ_BIN_4 +68 0x0209 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x004D //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x4000 //RX_TDDRC_ALPHA_UP_1 +7 0x4000 //RX_TDDRC_ALPHA_UP_2 +8 0x4000 //RX_TDDRC_ALPHA_UP_3 +9 0x4000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x4000 //RX_TDDRC_ALPHA_DWN_2 +29 0x4000 //RX_TDDRC_ALPHA_DWN_3 +32 0x4000 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0001 //RX_TDDRC_THRD_0 +113 0x0002 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x4000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0439 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4040 //RX_FDEQ_GAIN_1 +41 0x3838 //RX_FDEQ_GAIN_2 +42 0x3448 //RX_FDEQ_GAIN_3 +43 0x343C //RX_FDEQ_GAIN_4 +44 0x4040 //RX_FDEQ_GAIN_5 +45 0x4048 //RX_FDEQ_GAIN_6 +46 0x384C //RX_FDEQ_GAIN_7 +47 0x4C54 //RX_FDEQ_GAIN_8 +48 0x5C54 //RX_FDEQ_GAIN_9 +49 0x4E38 //RX_FDEQ_GAIN_10 +50 0x303C //RX_FDEQ_GAIN_11 +51 0x5450 //RX_FDEQ_GAIN_12 +52 0x4860 //RX_FDEQ_GAIN_13 +53 0x6060 //RX_FDEQ_GAIN_14 +54 0x6060 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0402 //RX_FDEQ_BIN_3 +67 0x0504 //RX_FDEQ_BIN_4 +68 0x0209 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0074 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x4000 //RX_TDDRC_ALPHA_UP_1 +7 0x4000 //RX_TDDRC_ALPHA_UP_2 +8 0x4000 //RX_TDDRC_ALPHA_UP_3 +9 0x4000 //RX_TDDRC_ALPHA_UP_4 +27 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +28 0x4000 //RX_TDDRC_ALPHA_DWN_2 +29 0x4000 //RX_TDDRC_ALPHA_DWN_3 +32 0x4000 //RX_TDDRC_ALPHA_DWN_4 +33 0x7214 //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0001 //RX_TDDRC_THRD_0 +113 0x0002 //RX_TDDRC_THRD_1 +114 0x1800 //RX_TDDRC_THRD_2 +115 0x1800 //RX_TDDRC_THRD_3 +116 0x7FFF //RX_TDDRC_SLANT_0 +117 0x7FFF //RX_TDDRC_SLANT_1 +118 0x4000 //RX_TDDRC_ALPHA_UP_0 +119 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x199A //RX_TDDRC_HMNC_GAIN +122 0x0001 //RX_TDDRC_SMT_FLAG +123 0x0CCD //RX_TDDRC_SMT_W +124 0x0439 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4040 //RX_FDEQ_GAIN_1 +41 0x3838 //RX_FDEQ_GAIN_2 +42 0x3448 //RX_FDEQ_GAIN_3 +43 0x343C //RX_FDEQ_GAIN_4 +44 0x4040 //RX_FDEQ_GAIN_5 +45 0x4048 //RX_FDEQ_GAIN_6 +46 0x384C //RX_FDEQ_GAIN_7 +47 0x4C54 //RX_FDEQ_GAIN_8 +48 0x5C54 //RX_FDEQ_GAIN_9 +49 0x4E38 //RX_FDEQ_GAIN_10 +50 0x303C //RX_FDEQ_GAIN_11 +51 0x5450 //RX_FDEQ_GAIN_12 +52 0x4860 //RX_FDEQ_GAIN_13 +53 0x6060 //RX_FDEQ_GAIN_14 +54 0x6060 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0202 //RX_FDEQ_BIN_0 +64 0x0203 //RX_FDEQ_BIN_1 +65 0x0303 //RX_FDEQ_BIN_2 +66 0x0402 //RX_FDEQ_BIN_3 +67 0x0504 //RX_FDEQ_BIN_4 +68 0x0209 //RX_FDEQ_BIN_5 +69 0x0808 //RX_FDEQ_BIN_6 +70 0x090A //RX_FDEQ_BIN_7 +71 0x0B0C //RX_FDEQ_BIN_8 +72 0x0D0E //RX_FDEQ_BIN_9 +73 0x1013 //RX_FDEQ_BIN_10 +74 0x1719 //RX_FDEQ_BIN_11 +75 0x1B1E //RX_FDEQ_BIN_12 +76 0x1E1E //RX_FDEQ_BIN_13 +77 0x1E28 //RX_FDEQ_BIN_14 +78 0x282C //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x4000 //RX_FDEQ_RESRV_0 +88 0x0320 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x2000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x2000 //RX_FDDRC_THRD_3_2 +101 0x5000 //RX_FDDRC_THRD_3_3 +102 0x4000 //RX_FDDRC_SLANT_0_0 +103 0x4000 //RX_FDDRC_SLANT_0_1 +104 0x4000 //RX_FDDRC_SLANT_0_2 +105 0x4000 //RX_FDDRC_SLANT_0_3 +106 0x7FFF //RX_FDDRC_SLANT_1_0 +107 0x7FFF //RX_FDDRC_SLANT_1_1 +108 0x7FFF //RX_FDDRC_SLANT_1_2 +109 0x7FFF //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x242C //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0004 //RX_SAMPLINGFREQ_SIG +160 0x0004 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x4000 //RX_TDDRC_ALPHA_UP_1 +164 0x4000 //RX_TDDRC_ALPHA_UP_2 +165 0x4000 //RX_TDDRC_ALPHA_UP_3 +166 0x4000 //RX_TDDRC_ALPHA_UP_4 +167 0x0403 //RX_PGA +168 0x7E56 //RX_A_HP +169 0x4000 //RX_B_PE +170 0x7800 //RX_THR_PITCH_DET_0 +171 0x7000 //RX_THR_PITCH_DET_1 +172 0x6000 //RX_THR_PITCH_DET_2 +173 0x0008 //RX_PITCH_BFR_LEN +174 0x0003 //RX_SBD_PITCH_DET +175 0x0100 //RX_PP_RESRV_0 +176 0x0020 //RX_PP_RESRV_1 +177 0x0400 //RX_N_SN_EST +178 0x000C //RX_N2_SN_EST +179 0x0014 //RX_NS_LVL_CTRL +180 0xF400 //RX_THR_SN_EST +181 0x7E00 //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0190 //RX_FENS_RESRV_1 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x4000 //RX_TDDRC_ALPHA_DWN_2 +186 0x4000 //RX_TDDRC_ALPHA_DWN_3 +187 0x0002 //RX_EXTRA_NS_L +188 0x0800 //RX_EXTRA_NS_A +189 0x4000 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x199A //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4040 //RX_FDEQ_GAIN_1 +198 0x3838 //RX_FDEQ_GAIN_2 +199 0x3448 //RX_FDEQ_GAIN_3 +200 0x343C //RX_FDEQ_GAIN_4 +201 0x4040 //RX_FDEQ_GAIN_5 +202 0x4048 //RX_FDEQ_GAIN_6 +203 0x384C //RX_FDEQ_GAIN_7 +204 0x4C54 //RX_FDEQ_GAIN_8 +205 0x5C54 //RX_FDEQ_GAIN_9 +206 0x4E38 //RX_FDEQ_GAIN_10 +207 0x303C //RX_FDEQ_GAIN_11 +208 0x5450 //RX_FDEQ_GAIN_12 +209 0x4860 //RX_FDEQ_GAIN_13 +210 0x6060 //RX_FDEQ_GAIN_14 +211 0x6060 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0402 //RX_FDEQ_BIN_3 +224 0x0504 //RX_FDEQ_BIN_4 +225 0x0209 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0002 //RX_FILTINDX +269 0x0001 //RX_TDDRC_THRD_0 +270 0x0002 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x4000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0439 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x1B58 //RX_TPKA_FP +284 0x0400 //RX_MIN_G_FP +285 0x0800 //RX_MAX_G_FP +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0000 //RX_MAXLEVEL_CNG +289 0x3000 //RX_BWE_UV_TH +290 0x3000 //RX_BWE_UV_TH2 +291 0x1800 //RX_BWE_UV_TH3 +292 0x1000 //RX_BWE_V_TH +293 0x04CD //RX_BWE_GAIN1_V_TH1 +294 0x0F33 //RX_BWE_GAIN1_V_TH2 +295 0x7333 //RX_BWE_UV_EQ +296 0x199A //RX_BWE_V_EQ +297 0x7333 //RX_BWE_TONE_TH +298 0x0004 //RX_BWE_UV_HOLD_T +299 0x6CCD //RX_BWE_GAIN2_ALPHA +300 0x799A //RX_BWE_GAIN3_ALPHA +301 0x001E //RX_BWE_CUTOFF +302 0x3000 //RX_BWE_GAINFILL +303 0x3200 //RX_BWE_MAXTH_TONE +304 0x2000 //RX_BWE_EQ_0 +305 0x2000 //RX_BWE_EQ_1 +306 0x2000 //RX_BWE_EQ_2 +307 0x2000 //RX_BWE_EQ_3 +308 0x2000 //RX_BWE_EQ_4 +309 0x2000 //RX_BWE_EQ_5 +310 0x2000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x4000 //RX_TDDRC_ALPHA_UP_1 +164 0x4000 //RX_TDDRC_ALPHA_UP_2 +165 0x4000 //RX_TDDRC_ALPHA_UP_3 +166 0x4000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x4000 //RX_TDDRC_ALPHA_DWN_2 +186 0x4000 //RX_TDDRC_ALPHA_DWN_3 +189 0x4000 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0001 //RX_TDDRC_THRD_0 +270 0x0002 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x4000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0439 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4040 //RX_FDEQ_GAIN_1 +198 0x3838 //RX_FDEQ_GAIN_2 +199 0x3448 //RX_FDEQ_GAIN_3 +200 0x343C //RX_FDEQ_GAIN_4 +201 0x4040 //RX_FDEQ_GAIN_5 +202 0x4048 //RX_FDEQ_GAIN_6 +203 0x384C //RX_FDEQ_GAIN_7 +204 0x4C54 //RX_FDEQ_GAIN_8 +205 0x5C54 //RX_FDEQ_GAIN_9 +206 0x4E38 //RX_FDEQ_GAIN_10 +207 0x303C //RX_FDEQ_GAIN_11 +208 0x5450 //RX_FDEQ_GAIN_12 +209 0x4860 //RX_FDEQ_GAIN_13 +210 0x6060 //RX_FDEQ_GAIN_14 +211 0x6060 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0402 //RX_FDEQ_BIN_3 +224 0x0504 //RX_FDEQ_BIN_4 +225 0x0209 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0012 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x4000 //RX_TDDRC_ALPHA_UP_1 +164 0x4000 //RX_TDDRC_ALPHA_UP_2 +165 0x4000 //RX_TDDRC_ALPHA_UP_3 +166 0x4000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x4000 //RX_TDDRC_ALPHA_DWN_2 +186 0x4000 //RX_TDDRC_ALPHA_DWN_3 +189 0x4000 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0001 //RX_TDDRC_THRD_0 +270 0x0002 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x4000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0439 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4040 //RX_FDEQ_GAIN_1 +198 0x3838 //RX_FDEQ_GAIN_2 +199 0x3448 //RX_FDEQ_GAIN_3 +200 0x343C //RX_FDEQ_GAIN_4 +201 0x4040 //RX_FDEQ_GAIN_5 +202 0x4048 //RX_FDEQ_GAIN_6 +203 0x384C //RX_FDEQ_GAIN_7 +204 0x4C54 //RX_FDEQ_GAIN_8 +205 0x5C54 //RX_FDEQ_GAIN_9 +206 0x4E38 //RX_FDEQ_GAIN_10 +207 0x303C //RX_FDEQ_GAIN_11 +208 0x5450 //RX_FDEQ_GAIN_12 +209 0x4860 //RX_FDEQ_GAIN_13 +210 0x6060 //RX_FDEQ_GAIN_14 +211 0x6060 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0402 //RX_FDEQ_BIN_3 +224 0x0504 //RX_FDEQ_BIN_4 +225 0x0209 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x001A //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x4000 //RX_TDDRC_ALPHA_UP_1 +164 0x4000 //RX_TDDRC_ALPHA_UP_2 +165 0x4000 //RX_TDDRC_ALPHA_UP_3 +166 0x4000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x4000 //RX_TDDRC_ALPHA_DWN_2 +186 0x4000 //RX_TDDRC_ALPHA_DWN_3 +189 0x4000 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0001 //RX_TDDRC_THRD_0 +270 0x0002 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x4000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0439 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4040 //RX_FDEQ_GAIN_1 +198 0x3838 //RX_FDEQ_GAIN_2 +199 0x3448 //RX_FDEQ_GAIN_3 +200 0x343C //RX_FDEQ_GAIN_4 +201 0x4040 //RX_FDEQ_GAIN_5 +202 0x4048 //RX_FDEQ_GAIN_6 +203 0x384C //RX_FDEQ_GAIN_7 +204 0x4C54 //RX_FDEQ_GAIN_8 +205 0x5C54 //RX_FDEQ_GAIN_9 +206 0x4E38 //RX_FDEQ_GAIN_10 +207 0x303C //RX_FDEQ_GAIN_11 +208 0x5450 //RX_FDEQ_GAIN_12 +209 0x4860 //RX_FDEQ_GAIN_13 +210 0x6060 //RX_FDEQ_GAIN_14 +211 0x6060 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0402 //RX_FDEQ_BIN_3 +224 0x0504 //RX_FDEQ_BIN_4 +225 0x0209 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0025 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x4000 //RX_TDDRC_ALPHA_UP_1 +164 0x4000 //RX_TDDRC_ALPHA_UP_2 +165 0x4000 //RX_TDDRC_ALPHA_UP_3 +166 0x4000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x4000 //RX_TDDRC_ALPHA_DWN_2 +186 0x4000 //RX_TDDRC_ALPHA_DWN_3 +189 0x4000 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0001 //RX_TDDRC_THRD_0 +270 0x0002 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x4000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0439 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4040 //RX_FDEQ_GAIN_1 +198 0x3838 //RX_FDEQ_GAIN_2 +199 0x3448 //RX_FDEQ_GAIN_3 +200 0x343C //RX_FDEQ_GAIN_4 +201 0x4040 //RX_FDEQ_GAIN_5 +202 0x4048 //RX_FDEQ_GAIN_6 +203 0x384C //RX_FDEQ_GAIN_7 +204 0x4C54 //RX_FDEQ_GAIN_8 +205 0x5C54 //RX_FDEQ_GAIN_9 +206 0x4E38 //RX_FDEQ_GAIN_10 +207 0x303C //RX_FDEQ_GAIN_11 +208 0x5450 //RX_FDEQ_GAIN_12 +209 0x4860 //RX_FDEQ_GAIN_13 +210 0x6060 //RX_FDEQ_GAIN_14 +211 0x6060 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0402 //RX_FDEQ_BIN_3 +224 0x0504 //RX_FDEQ_BIN_4 +225 0x0209 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0035 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x4000 //RX_TDDRC_ALPHA_UP_1 +164 0x4000 //RX_TDDRC_ALPHA_UP_2 +165 0x4000 //RX_TDDRC_ALPHA_UP_3 +166 0x4000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x4000 //RX_TDDRC_ALPHA_DWN_2 +186 0x4000 //RX_TDDRC_ALPHA_DWN_3 +189 0x4000 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0001 //RX_TDDRC_THRD_0 +270 0x0002 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x4000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0439 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4040 //RX_FDEQ_GAIN_1 +198 0x3838 //RX_FDEQ_GAIN_2 +199 0x3448 //RX_FDEQ_GAIN_3 +200 0x343C //RX_FDEQ_GAIN_4 +201 0x4040 //RX_FDEQ_GAIN_5 +202 0x4048 //RX_FDEQ_GAIN_6 +203 0x384C //RX_FDEQ_GAIN_7 +204 0x4C54 //RX_FDEQ_GAIN_8 +205 0x5C54 //RX_FDEQ_GAIN_9 +206 0x4E38 //RX_FDEQ_GAIN_10 +207 0x303C //RX_FDEQ_GAIN_11 +208 0x5450 //RX_FDEQ_GAIN_12 +209 0x4860 //RX_FDEQ_GAIN_13 +210 0x6060 //RX_FDEQ_GAIN_14 +211 0x6060 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0402 //RX_FDEQ_BIN_3 +224 0x0504 //RX_FDEQ_BIN_4 +225 0x0209 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x004D //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x4000 //RX_TDDRC_ALPHA_UP_1 +164 0x4000 //RX_TDDRC_ALPHA_UP_2 +165 0x4000 //RX_TDDRC_ALPHA_UP_3 +166 0x4000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x4000 //RX_TDDRC_ALPHA_DWN_2 +186 0x4000 //RX_TDDRC_ALPHA_DWN_3 +189 0x4000 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0001 //RX_TDDRC_THRD_0 +270 0x0002 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x4000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0439 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4040 //RX_FDEQ_GAIN_1 +198 0x3838 //RX_FDEQ_GAIN_2 +199 0x3448 //RX_FDEQ_GAIN_3 +200 0x343C //RX_FDEQ_GAIN_4 +201 0x4040 //RX_FDEQ_GAIN_5 +202 0x4048 //RX_FDEQ_GAIN_6 +203 0x384C //RX_FDEQ_GAIN_7 +204 0x4C54 //RX_FDEQ_GAIN_8 +205 0x5C54 //RX_FDEQ_GAIN_9 +206 0x4E38 //RX_FDEQ_GAIN_10 +207 0x303C //RX_FDEQ_GAIN_11 +208 0x5450 //RX_FDEQ_GAIN_12 +209 0x4860 //RX_FDEQ_GAIN_13 +210 0x6060 //RX_FDEQ_GAIN_14 +211 0x6060 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0402 //RX_FDEQ_BIN_3 +224 0x0504 //RX_FDEQ_BIN_4 +225 0x0209 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0074 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x4000 //RX_TDDRC_ALPHA_UP_1 +164 0x4000 //RX_TDDRC_ALPHA_UP_2 +165 0x4000 //RX_TDDRC_ALPHA_UP_3 +166 0x4000 //RX_TDDRC_ALPHA_UP_4 +184 0x7EB8 //RX_TDDRC_ALPHA_DWN_1 +185 0x4000 //RX_TDDRC_ALPHA_DWN_2 +186 0x4000 //RX_TDDRC_ALPHA_DWN_3 +189 0x4000 //RX_TDDRC_ALPHA_DWN_4 +190 0x7214 //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0001 //RX_TDDRC_THRD_0 +270 0x0002 //RX_TDDRC_THRD_1 +271 0x1800 //RX_TDDRC_THRD_2 +272 0x1800 //RX_TDDRC_THRD_3 +273 0x7FFF //RX_TDDRC_SLANT_0 +274 0x7FFF //RX_TDDRC_SLANT_1 +275 0x4000 //RX_TDDRC_ALPHA_UP_0 +276 0x7EB8 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x199A //RX_TDDRC_HMNC_GAIN +279 0x0001 //RX_TDDRC_SMT_FLAG +280 0x0CCD //RX_TDDRC_SMT_W +281 0x0439 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4040 //RX_FDEQ_GAIN_1 +198 0x3838 //RX_FDEQ_GAIN_2 +199 0x3448 //RX_FDEQ_GAIN_3 +200 0x343C //RX_FDEQ_GAIN_4 +201 0x4040 //RX_FDEQ_GAIN_5 +202 0x4048 //RX_FDEQ_GAIN_6 +203 0x384C //RX_FDEQ_GAIN_7 +204 0x4C54 //RX_FDEQ_GAIN_8 +205 0x5C54 //RX_FDEQ_GAIN_9 +206 0x4E38 //RX_FDEQ_GAIN_10 +207 0x303C //RX_FDEQ_GAIN_11 +208 0x5450 //RX_FDEQ_GAIN_12 +209 0x4860 //RX_FDEQ_GAIN_13 +210 0x6060 //RX_FDEQ_GAIN_14 +211 0x6060 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0202 //RX_FDEQ_BIN_0 +221 0x0203 //RX_FDEQ_BIN_1 +222 0x0303 //RX_FDEQ_BIN_2 +223 0x0402 //RX_FDEQ_BIN_3 +224 0x0504 //RX_FDEQ_BIN_4 +225 0x0209 //RX_FDEQ_BIN_5 +226 0x0808 //RX_FDEQ_BIN_6 +227 0x090A //RX_FDEQ_BIN_7 +228 0x0B0C //RX_FDEQ_BIN_8 +229 0x0D0E //RX_FDEQ_BIN_9 +230 0x1013 //RX_FDEQ_BIN_10 +231 0x1719 //RX_FDEQ_BIN_11 +232 0x1B1E //RX_FDEQ_BIN_12 +233 0x1E1E //RX_FDEQ_BIN_13 +234 0x1E28 //RX_FDEQ_BIN_14 +235 0x282C //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x4000 //RX_FDEQ_RESRV_0 +245 0x0320 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x2000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x2000 //RX_FDDRC_THRD_3_2 +258 0x5000 //RX_FDDRC_THRD_3_3 +259 0x4000 //RX_FDDRC_SLANT_0_0 +260 0x4000 //RX_FDDRC_SLANT_0_1 +261 0x4000 //RX_FDDRC_SLANT_0_2 +262 0x4000 //RX_FDDRC_SLANT_0_3 +263 0x7FFF //RX_FDDRC_SLANT_1_0 +264 0x7FFF //RX_FDDRC_SLANT_1_1 +265 0x7FFF //RX_FDDRC_SLANT_1_2 +266 0x7FFF //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME HEADSET-TTY_VCO-VOICE_GENERIC-NB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0001 //TX_OPERATION_MODE_0 +1 0x0001 //TX_OPERATION_MODE_1 +2 0x0033 //TX_PATCH_REG +3 0x6F7C //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0002 //TX_NUM_MIC +6 0x0000 //TX_SAMPLINGFREQ_SIG +7 0x0000 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009D //TX_DIST2REF1 +22 0x0010 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x1000 //TX_PGA_0 +28 0x1000 //TX_PGA_1 +29 0x1000 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0001 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0002 //TX_MIC_DATA_SRC0 +42 0x0000 //TX_MIC_DATA_SRC1 +43 0x0001 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3A66 //TX_DIST2REF_11 +73 0x053D //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0200 //TX_MIC_REFBLK_VOLUME +108 0x0CAE //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0000 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7646 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x5000 //TX_THR_PITCH_DET_0 +131 0x4800 //TX_THR_PITCH_DET_1 +132 0x4000 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x0028 //TX_TAIL_LENGTH +147 0x0100 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x7500 //TX_EAD_THR +151 0x1000 //TX_THR_RE_EST +152 0x0200 //TX_MIN_EQ_RE_EST_0 +153 0x0200 //TX_MIN_EQ_RE_EST_1 +154 0x0200 //TX_MIN_EQ_RE_EST_2 +155 0x0200 //TX_MIN_EQ_RE_EST_3 +156 0x0200 //TX_MIN_EQ_RE_EST_4 +157 0x0200 //TX_MIN_EQ_RE_EST_5 +158 0x0200 //TX_MIN_EQ_RE_EST_6 +159 0x1800 //TX_MIN_EQ_RE_EST_7 +160 0x1800 //TX_MIN_EQ_RE_EST_8 +161 0x3000 //TX_MIN_EQ_RE_EST_9 +162 0x4000 //TX_MIN_EQ_RE_EST_10 +163 0x6000 //TX_MIN_EQ_RE_EST_11 +164 0x7FFF //TX_MIN_EQ_RE_EST_12 +165 0x2000 //TX_LAMBDA_RE_EST +166 0x0000 //TX_LAMBDA_CB_NLE +167 0x4000 //TX_C_POST_FLT +168 0x2000 //TX_GAIN_NP +169 0x0180 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x05DC //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x7FF0 //TX_DTD_THR1_0 +198 0x7FF0 //TX_DTD_THR1_1 +199 0x7FF0 //TX_DTD_THR1_2 +200 0x7FF0 //TX_DTD_THR1_3 +201 0x7FF0 //TX_DTD_THR1_4 +202 0x7FF0 //TX_DTD_THR1_5 +203 0x7FF0 //TX_DTD_THR1_6 +204 0x7E00 //TX_DTD_THR2_0 +205 0x0CCD //TX_DTD_THR2_1 +206 0x0CCD //TX_DTD_THR2_2 +207 0x0CCD //TX_DTD_THR2_3 +208 0x0CCD //TX_DTD_THR2_4 +209 0x0CCD //TX_DTD_THR2_5 +210 0x0CCD //TX_DTD_THR2_6 +211 0x7FFF //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x1F40 //TX_DT_CUT_K +214 0x0100 //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x1000 //TX_ADPT_STRICT_L +222 0x1000 //TX_ADPT_STRICT_H +223 0x0001 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x0640 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x0001 //TX_RATIO_DT_L0_TH +228 0x7FFF //TX_B_POST_FILT_ECHO_L +229 0x2000 //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x1000 //TX_B_LESSCUT_RTO_ECHO +232 0x0000 //TX_EPD_OFFSET_00 +233 0x0000 //TX_EPD_OFFST_01 +234 0x05DC //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x0000 //TX_DTD_THR1_7 +238 0x0000 //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xFA00 //TX_THR_SN_EST_0 +243 0xFA00 //TX_THR_SN_EST_1 +244 0xFA00 //TX_THR_SN_EST_2 +245 0xF900 //TX_THR_SN_EST_3 +246 0xFA00 //TX_THR_SN_EST_4 +247 0xFA00 //TX_THR_SN_EST_5 +248 0xF800 //TX_THR_SN_EST_6 +249 0xF800 //TX_THR_SN_EST_7 +250 0x0050 //TX_DELTA_THR_SN_EST_0 +251 0x0200 //TX_DELTA_THR_SN_EST_1 +252 0x0200 //TX_DELTA_THR_SN_EST_2 +253 0x0100 //TX_DELTA_THR_SN_EST_3 +254 0x0200 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x01A0 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x4000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x4000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x7F00 //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0800 //TX_MAINREFRTO_TH_EQ +279 0x1000 //TX_B_POST_FLT_0 +280 0x1000 //TX_B_POST_FLT_1 +281 0x0010 //TX_NS_LVL_CTRL_0 +282 0x0012 //TX_NS_LVL_CTRL_1 +283 0x0015 //TX_NS_LVL_CTRL_2 +284 0x0012 //TX_NS_LVL_CTRL_3 +285 0x0012 //TX_NS_LVL_CTRL_4 +286 0x0011 //TX_NS_LVL_CTRL_5 +287 0x0012 //TX_NS_LVL_CTRL_6 +288 0x0011 //TX_NS_LVL_CTRL_7 +289 0x000F //TX_MIN_GAIN_S_0 +290 0x000D //TX_MIN_GAIN_S_1 +291 0x000F //TX_MIN_GAIN_S_2 +292 0x000F //TX_MIN_GAIN_S_3 +293 0x000F //TX_MIN_GAIN_S_4 +294 0x0010 //TX_MIN_GAIN_S_5 +295 0x000F //TX_MIN_GAIN_S_6 +296 0x000F //TX_MIN_GAIN_S_7 +297 0x4000 //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x3000 //TX_SNRI_SUP_1 +302 0x4000 //TX_SNRI_SUP_2 +303 0x2400 //TX_SNRI_SUP_3 +304 0x4000 //TX_SNRI_SUP_4 +305 0x4000 //TX_SNRI_SUP_5 +306 0x4000 //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x0018 //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x4000 //TX_A_POST_FILT_S_0 +315 0x2000 //TX_A_POST_FILT_S_1 +316 0x4000 //TX_A_POST_FILT_S_2 +317 0x1000 //TX_A_POST_FILT_S_3 +318 0x3000 //TX_A_POST_FILT_S_4 +319 0x5000 //TX_A_POST_FILT_S_5 +320 0x5000 //TX_A_POST_FILT_S_6 +321 0x7000 //TX_A_POST_FILT_S_7 +322 0x1000 //TX_B_POST_FILT_0 +323 0x1000 //TX_B_POST_FILT_1 +324 0x1000 //TX_B_POST_FILT_2 +325 0x5000 //TX_B_POST_FILT_3 +326 0x3000 //TX_B_POST_FILT_4 +327 0x1000 //TX_B_POST_FILT_5 +328 0x1000 //TX_B_POST_FILT_6 +329 0x2000 //TX_B_POST_FILT_7 +330 0x4000 //TX_B_LESSCUT_RTO_S_0 +331 0x6000 //TX_B_LESSCUT_RTO_S_1 +332 0x6000 //TX_B_LESSCUT_RTO_S_2 +333 0x6000 //TX_B_LESSCUT_RTO_S_3 +334 0x6000 //TX_B_LESSCUT_RTO_S_4 +335 0x6000 //TX_B_LESSCUT_RTO_S_5 +336 0x6000 //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7E00 //TX_LAMBDA_PFILT +339 0x7D00 //TX_LAMBDA_PFILT_S_0 +340 0x7C00 //TX_LAMBDA_PFILT_S_1 +341 0x7900 //TX_LAMBDA_PFILT_S_2 +342 0x7000 //TX_LAMBDA_PFILT_S_3 +343 0x7D00 //TX_LAMBDA_PFILT_S_4 +344 0x7D00 //TX_LAMBDA_PFILT_S_5 +345 0x7900 //TX_LAMBDA_PFILT_S_6 +346 0x7D00 //TX_LAMBDA_PFILT_S_7 +347 0x0200 //TX_K_PEPPER +348 0x0800 //TX_A_PEPPER +349 0x1EAA //TX_K_PEPPER_HF +350 0x0600 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0800 //TX_DT_BINVAD_TH_0 +354 0x0100 //TX_DT_BINVAD_TH_1 +355 0x0100 //TX_DT_BINVAD_TH_2 +356 0x0800 //TX_DT_BINVAD_TH_3 +357 0x0FA0 //TX_DT_BINVAD_ENDF +358 0x7000 //TX_C_POST_FLT_DT +359 0x4000 //TX_NS_B_POST_FLT_LESSCUT +360 0x01B0 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0064 //TX_NDETCT +367 0x003B //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x07D0 //TX_NOISE_TH_1 +371 0x03ED //TX_NOISE_TH_2 +372 0x2EE0 //TX_NOISE_TH_3 +373 0x5528 //TX_NOISE_TH_4 +374 0x7FFF //TX_NOISE_TH_5 +375 0x7FFF //TX_NOISE_TH_5_2 +376 0x0000 //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x0FA0 //TX_NOISE_TH_6 +379 0x00C8 //TX_MINENOISE_TH +380 0xD508 //TX_MORENS_TFMASK_TH +381 0x0001 //TX_DRC_QUIET_FLOOR +382 0x3A98 //TX_RATIODTL_CUT_TH +383 0x0DAC //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x1000 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x7FFF //TX_POST_MASK_SUP_HSNE +392 0x1388 //TX_TAIL_DET_TH +393 0x4000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0080 //TX_SUPHIGH_TH +396 0x0000 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x1800 //TX_C_POST_FLT_MASK +399 0x7FFF //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0004 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x0032 //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x7FFF //TX_MIN_G_CTRL_SSNS +409 0x0000 //TX_METAL_RTO_THR +410 0x4848 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x007A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x5000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x01E0 //TX_NOR_OFF_THR +498 0x7C00 //TX_MORE_ON_700HZ_THR +499 0x0000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0xD333 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x7FFF //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0xC000 //TX_DEREVERB_LF_MU +515 0xC000 //TX_DEREVERB_HF_MU +516 0xCCCC //TX_DEREVERB_DELAY +517 0xD999 //TX_DEREVERB_COEF_LEN +518 0x1F40 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x7000 //TX_GSC_RTOH_TH +523 0x0064 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0014 //TX_FDEQ_SUBNUM +567 0x5050 //TX_FDEQ_GAIN_0 +568 0x5048 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x483C //TX_FDEQ_GAIN_3 +571 0x3034 //TX_FDEQ_GAIN_4 +572 0x3048 //TX_FDEQ_GAIN_5 +573 0x4840 //TX_FDEQ_GAIN_6 +574 0x403C //TX_FDEQ_GAIN_7 +575 0x262C //TX_FDEQ_GAIN_8 +576 0x3A3C //TX_FDEQ_GAIN_9 +577 0x4848 //TX_FDEQ_GAIN_10 +578 0x4848 //TX_FDEQ_GAIN_11 +579 0x4848 //TX_FDEQ_GAIN_12 +580 0x4848 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0303 //TX_FDEQ_BIN_2 +594 0x0304 //TX_FDEQ_BIN_3 +595 0x0405 //TX_FDEQ_BIN_4 +596 0x0506 //TX_FDEQ_BIN_5 +597 0x0708 //TX_FDEQ_BIN_6 +598 0x090A //TX_FDEQ_BIN_7 +599 0x0B0C //TX_FDEQ_BIN_8 +600 0x0D0E //TX_FDEQ_BIN_9 +601 0x0000 //TX_FDEQ_BIN_10 +602 0x0000 //TX_FDEQ_BIN_11 +603 0x0000 //TX_FDEQ_BIN_12 +604 0x0000 //TX_FDEQ_BIN_13 +605 0x0000 //TX_FDEQ_BIN_14 +606 0x0000 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0014 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4A4C //TX_PREEQ_GAIN_MIC0_8 +626 0x4E50 //TX_PREEQ_GAIN_MIC0_9 +627 0x4848 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0202 //TX_PREEQ_BIN_MIC0_0 +642 0x0203 //TX_PREEQ_BIN_MIC0_1 +643 0x0303 //TX_PREEQ_BIN_MIC0_2 +644 0x0304 //TX_PREEQ_BIN_MIC0_3 +645 0x0405 //TX_PREEQ_BIN_MIC0_4 +646 0x0506 //TX_PREEQ_BIN_MIC0_5 +647 0x0708 //TX_PREEQ_BIN_MIC0_6 +648 0x090A //TX_PREEQ_BIN_MIC0_7 +649 0x0B0C //TX_PREEQ_BIN_MIC0_8 +650 0x0D0E //TX_PREEQ_BIN_MIC0_9 +651 0x0000 //TX_PREEQ_BIN_MIC0_10 +652 0x0000 //TX_PREEQ_BIN_MIC0_11 +653 0x0000 //TX_PREEQ_BIN_MIC0_12 +654 0x0000 //TX_PREEQ_BIN_MIC0_13 +655 0x0000 //TX_PREEQ_BIN_MIC0_14 +656 0x0000 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4846 //TX_PREEQ_GAIN_MIC1_7 +674 0x4544 //TX_PREEQ_GAIN_MIC1_8 +675 0x4241 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0202 //TX_PREEQ_BIN_MIC1_0 +691 0x0203 //TX_PREEQ_BIN_MIC1_1 +692 0x0303 //TX_PREEQ_BIN_MIC1_2 +693 0x0304 //TX_PREEQ_BIN_MIC1_3 +694 0x0405 //TX_PREEQ_BIN_MIC1_4 +695 0x0506 //TX_PREEQ_BIN_MIC1_5 +696 0x0708 //TX_PREEQ_BIN_MIC1_6 +697 0x090A //TX_PREEQ_BIN_MIC1_7 +698 0x0B0C //TX_PREEQ_BIN_MIC1_8 +699 0x0D0E //TX_PREEQ_BIN_MIC1_9 +700 0x0000 //TX_PREEQ_BIN_MIC1_10 +701 0x0000 //TX_PREEQ_BIN_MIC1_11 +702 0x0000 //TX_PREEQ_BIN_MIC1_12 +703 0x0000 //TX_PREEQ_BIN_MIC1_13 +704 0x0000 //TX_PREEQ_BIN_MIC1_14 +705 0x0000 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0000 //TX_PREEQ_BIN_MIC2_0 +740 0x0000 //TX_PREEQ_BIN_MIC2_1 +741 0x0000 //TX_PREEQ_BIN_MIC2_2 +742 0x0000 //TX_PREEQ_BIN_MIC2_3 +743 0x0000 //TX_PREEQ_BIN_MIC2_4 +744 0x0000 //TX_PREEQ_BIN_MIC2_5 +745 0x0000 //TX_PREEQ_BIN_MIC2_6 +746 0x0000 //TX_PREEQ_BIN_MIC2_7 +747 0x0000 //TX_PREEQ_BIN_MIC2_8 +748 0x0000 //TX_PREEQ_BIN_MIC2_9 +749 0x0000 //TX_PREEQ_BIN_MIC2_10 +750 0x0000 //TX_PREEQ_BIN_MIC2_11 +751 0x0000 //TX_PREEQ_BIN_MIC2_12 +752 0x0000 //TX_PREEQ_BIN_MIC2_13 +753 0x0000 //TX_PREEQ_BIN_MIC2_14 +754 0x0000 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x0800 //TX_NND_WEIGHT +765 0x0065 //TX_MIC_CALIBRATION_0 +766 0x0065 //TX_MIC_CALIBRATION_1 +767 0x0065 //TX_MIC_CALIBRATION_2 +768 0x0065 //TX_MIC_CALIBRATION_3 +769 0x0044 //TX_MIC_PWR_BIAS_0 +770 0x0044 //TX_MIC_PWR_BIAS_1 +771 0x0044 //TX_MIC_PWR_BIAS_2 +772 0x0044 //TX_MIC_PWR_BIAS_3 +773 0x0009 //TX_GAIN_LIMIT_0 +774 0x000F //TX_GAIN_LIMIT_1 +775 0x000F //TX_GAIN_LIMIT_2 +776 0x000F //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x4000 //TX_TDDRC_ALPHA_UP_01 +784 0x4000 //TX_TDDRC_ALPHA_UP_02 +785 0x4000 //TX_TDDRC_ALPHA_UP_03 +786 0x4000 //TX_TDDRC_ALPHA_UP_04 +787 0x6000 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x7214 //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0010 //TX_DEADMIC_SILENCE_TH +817 0x0600 //TX_MIC_DEGRADE_TH +818 0x0078 //TX_DEADMIC_CNT +819 0x0078 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x4848 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0096 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0002 //TX_FILTINDX +854 0x0004 //TX_TDDRC_THRD_0 +855 0x0010 //TX_TDDRC_THRD_1 +856 0x1800 //TX_TDDRC_THRD_2 +857 0x1800 //TX_TDDRC_THRD_3 +858 0x7FFF //TX_TDDRC_SLANT_0 +859 0x7FFF //TX_TDDRC_SLANT_1 +860 0x4000 //TX_TDDRC_ALPHA_UP_00 +861 0x6000 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x0A00 //TX_TDDRC_DRC_GAIN +867 0x7FFF //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x0028 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x4000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x2339 //TX_SENDFUNC_REG_MICMUTE +898 0x0021 //TX_SENDFUNC_REG_MICMUTE1 +899 0x02BC //TX_MICMUTE_RATIO_THR +900 0x0140 //TX_MICMUTE_AMP_THR +901 0x0004 //TX_MICMUTE_HPF_IND +902 0x00C0 //TX_MICMUTE_LOG_EYR_TH +903 0x0008 //TX_MICMUTE_CVG_TIME +904 0x0008 //TX_MICMUTE_RELEASE_TIME +905 0x01FE //TX_MIC_VOLUME_MIC0MUTE +906 0x0020 //TX_MICMUTE_EPD_OFFSET_0 +907 0x001E //TX_MICMUTE_FRQ_AEC_L +908 0x7999 //TX_MICMUTE_EAD_THR +909 0x7FFF //TX_MICMUTE_LAMBDA_CB_NLE +910 0x7FFF //TX_MICMUTE_LAMBDA_RE_EST +911 0x4000 //TX_DTD_THR1_MICMUTE_0 +912 0x7000 //TX_DTD_THR1_MICMUTE_1 +913 0x7FFF //TX_DTD_THR1_MICMUTE_2 +914 0x7FFF //TX_DTD_THR1_MICMUTE_3 +915 0x6CCC //TX_DTD_THR2_MICMUTE_0 +916 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x1000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x4000 //TX_MICMUTE_C_POST_FLT +922 0x03E8 //TX_MICMUTE_DT_CUT_K +923 0x0001 //TX_MICMUTE_DT_CUT_THR +924 0x03E8 //TX_MICMUTE_DT_CUT_K2 +925 0x0001 //TX_MICMUTE_DT_CUT_THR2 +926 0x0064 //TX_MICMUTE_DT2_HOLD_N +927 0x1000 //TX_MICMUTE_RATIODTH_THCUT +928 0x1000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x7FFF //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0400 //TX_MICMUTE_C_POST_FLT_MASK +931 0x7999 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0258 //TX_MICMUTE_DT_CUT_K1 +933 0x0800 //TX_MICMUTE_N2_SN_EST +934 0xFC00 //TX_MICMUTE_THR_SN_EST_0 +935 0x001C //TX_MICMUTE_MIN_G_CTRL_0 +936 0x6000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x7000 //TX_MICMUTE_B_POST_FILT_0 +938 0x2710 //TX_MIC1RUB_AMP_THR +939 0x0010 //TX_MIC1MUTE_RATIO_THR +940 0x0450 //TX_MIC1MUTE_AMP_THR +941 0x0008 //TX_MIC1MUTE_CVG_TIME +942 0x0008 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x2040 //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0000 //RX_SAMPLINGFREQ_SIG +3 0x0000 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +10 0x050D //RX_PGA +11 0x7652 //RX_A_HP +12 0x4000 //RX_B_PE +13 0x7800 //RX_THR_PITCH_DET_0 +14 0x7000 //RX_THR_PITCH_DET_1 +15 0x6000 //RX_THR_PITCH_DET_2 +16 0x0000 //RX_PITCH_BFR_LEN +17 0x0000 //RX_SBD_PITCH_DET +18 0x0000 //RX_PP_RESRV_0 +19 0x0000 //RX_PP_RESRV_1 +20 0xF800 //RX_N_SN_EST +21 0x0000 //RX_N2_SN_EST +22 0x000F //RX_NS_LVL_CTRL +23 0xF800 //RX_THR_SN_EST +24 0x7E00 //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0000 //RX_FENS_RESRV_1 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +30 0x0000 //RX_EXTRA_NS_L +31 0x0000 //RX_EXTRA_NS_A +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x0000 //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0003 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x0080 //RX_MIN_G_FP +128 0x2000 //RX_MAX_G_FP +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0010 //RX_MAXLEVEL_CNG +132 0x0000 //RX_BWE_UV_TH +133 0x0000 //RX_BWE_UV_TH2 +134 0x0000 //RX_BWE_UV_TH3 +135 0x0000 //RX_BWE_V_TH +136 0x0000 //RX_BWE_GAIN1_V_TH1 +137 0x0000 //RX_BWE_GAIN1_V_TH2 +138 0x0000 //RX_BWE_UV_EQ +139 0x0000 //RX_BWE_V_EQ +140 0x0000 //RX_BWE_TONE_TH +141 0x0000 //RX_BWE_UV_HOLD_T +142 0x0000 //RX_BWE_GAIN2_ALPHA +143 0x0000 //RX_BWE_GAIN3_ALPHA +144 0x0000 //RX_BWE_CUTOFF +145 0x0000 //RX_BWE_GAINFILL +146 0x0000 //RX_BWE_MAXTH_TONE +147 0x0000 //RX_BWE_EQ_0 +148 0x0000 //RX_BWE_EQ_1 +149 0x0000 //RX_BWE_EQ_2 +150 0x0000 //RX_BWE_EQ_3 +151 0x0000 //RX_BWE_EQ_4 +152 0x0000 //RX_BWE_EQ_5 +153 0x0000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x2040 //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0000 //RX_SAMPLINGFREQ_SIG +160 0x0000 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +167 0x050D //RX_PGA +168 0x7652 //RX_A_HP +169 0x4000 //RX_B_PE +170 0x7800 //RX_THR_PITCH_DET_0 +171 0x7000 //RX_THR_PITCH_DET_1 +172 0x6000 //RX_THR_PITCH_DET_2 +173 0x0000 //RX_PITCH_BFR_LEN +174 0x0000 //RX_SBD_PITCH_DET +175 0x0000 //RX_PP_RESRV_0 +176 0x0000 //RX_PP_RESRV_1 +177 0xF800 //RX_N_SN_EST +178 0x0000 //RX_N2_SN_EST +179 0x000F //RX_NS_LVL_CTRL +180 0xF800 //RX_THR_SN_EST +181 0x7E00 //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0000 //RX_FENS_RESRV_1 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +187 0x0000 //RX_EXTRA_NS_L +188 0x0000 //RX_EXTRA_NS_A +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x0000 //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0003 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x0080 //RX_MIN_G_FP +285 0x2000 //RX_MAX_G_FP +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0010 //RX_MAXLEVEL_CNG +289 0x0000 //RX_BWE_UV_TH +290 0x0000 //RX_BWE_UV_TH2 +291 0x0000 //RX_BWE_UV_TH3 +292 0x0000 //RX_BWE_V_TH +293 0x0000 //RX_BWE_GAIN1_V_TH1 +294 0x0000 //RX_BWE_GAIN1_V_TH2 +295 0x0000 //RX_BWE_UV_EQ +296 0x0000 //RX_BWE_V_EQ +297 0x0000 //RX_BWE_TONE_TH +298 0x0000 //RX_BWE_UV_HOLD_T +299 0x0000 //RX_BWE_GAIN2_ALPHA +300 0x0000 //RX_BWE_GAIN3_ALPHA +301 0x0000 //RX_BWE_CUTOFF +302 0x0000 //RX_BWE_GAINFILL +303 0x0000 //RX_BWE_MAXTH_TONE +304 0x0000 //RX_BWE_EQ_0 +305 0x0000 //RX_BWE_EQ_1 +306 0x0000 //RX_BWE_EQ_2 +307 0x0000 //RX_BWE_EQ_3 +308 0x0000 //RX_BWE_EQ_4 +309 0x0000 //RX_BWE_EQ_5 +310 0x0000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME HEADSET-TTY_VCO-VOICE_GENERIC-WB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0001 //TX_OPERATION_MODE_0 +1 0x0001 //TX_OPERATION_MODE_1 +2 0x0033 //TX_PATCH_REG +3 0x6F7C //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0002 //TX_NUM_MIC +6 0x0001 //TX_SAMPLINGFREQ_SIG +7 0x0001 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009D //TX_DIST2REF1 +22 0x0010 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x1000 //TX_PGA_0 +28 0x1000 //TX_PGA_1 +29 0x1000 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0001 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0002 //TX_MIC_DATA_SRC0 +42 0x0000 //TX_MIC_DATA_SRC1 +43 0x0001 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3A66 //TX_DIST2REF_11 +73 0x053D //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0800 //TX_MIC_REFBLK_VOLUME +108 0x0C00 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0004 //TX_MAINMIC_BLKFACTOR +114 0x0004 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0000 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7B02 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x5000 //TX_THR_PITCH_DET_0 +131 0x4800 //TX_THR_PITCH_DET_1 +132 0x4000 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x0028 //TX_TAIL_LENGTH +147 0x0300 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x6800 //TX_EAD_THR +151 0x1000 //TX_THR_RE_EST +152 0x3000 //TX_MIN_EQ_RE_EST_0 +153 0x0100 //TX_MIN_EQ_RE_EST_1 +154 0x0200 //TX_MIN_EQ_RE_EST_2 +155 0x0200 //TX_MIN_EQ_RE_EST_3 +156 0x0200 //TX_MIN_EQ_RE_EST_4 +157 0x0200 //TX_MIN_EQ_RE_EST_5 +158 0x0200 //TX_MIN_EQ_RE_EST_6 +159 0x1000 //TX_MIN_EQ_RE_EST_7 +160 0x1000 //TX_MIN_EQ_RE_EST_8 +161 0x1000 //TX_MIN_EQ_RE_EST_9 +162 0x1000 //TX_MIN_EQ_RE_EST_10 +163 0x1000 //TX_MIN_EQ_RE_EST_11 +164 0x1000 //TX_MIN_EQ_RE_EST_12 +165 0x1B00 //TX_LAMBDA_RE_EST +166 0x4000 //TX_LAMBDA_CB_NLE +167 0x7FFF //TX_C_POST_FLT +168 0x5000 //TX_GAIN_NP +169 0x0180 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x0020 //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x76D0 //TX_DTD_THR1_0 +198 0x76D0 //TX_DTD_THR1_1 +199 0x76D0 //TX_DTD_THR1_2 +200 0x7FF0 //TX_DTD_THR1_3 +201 0x7FF0 //TX_DTD_THR1_4 +202 0x7FF0 //TX_DTD_THR1_5 +203 0x7FF0 //TX_DTD_THR1_6 +204 0x7E00 //TX_DTD_THR2_0 +205 0x7E00 //TX_DTD_THR2_1 +206 0x5000 //TX_DTD_THR2_2 +207 0x5000 //TX_DTD_THR2_3 +208 0x5000 //TX_DTD_THR2_4 +209 0x5000 //TX_DTD_THR2_5 +210 0x5000 //TX_DTD_THR2_6 +211 0x7FFF //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x03E8 //TX_DT_CUT_K +214 0x0010 //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x023E //TX_ADPT_STRICT_L +222 0x023E //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x044C //TX_RATIO_DT_L_TH_HIGH +226 0x7800 //TX_RATIO_DT_H_TH_HIGH +227 0x0001 //TX_RATIO_DT_L0_TH +228 0x7FFF //TX_B_POST_FILT_ECHO_L +229 0x7FFF //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x1000 //TX_B_LESSCUT_RTO_ECHO +232 0x0000 //TX_EPD_OFFSET_00 +233 0x0000 //TX_EPD_OFFST_01 +234 0x03E8 //TX_RATIO_DT_L0_TH_HIGH +235 0x7FFF //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x0000 //TX_DTD_THR1_7 +238 0x0000 //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xFA00 //TX_THR_SN_EST_0 +243 0xFA00 //TX_THR_SN_EST_1 +244 0xFA00 //TX_THR_SN_EST_2 +245 0xFB00 //TX_THR_SN_EST_3 +246 0xFA00 //TX_THR_SN_EST_4 +247 0xFA00 //TX_THR_SN_EST_5 +248 0xF800 //TX_THR_SN_EST_6 +249 0xF800 //TX_THR_SN_EST_7 +250 0x0100 //TX_DELTA_THR_SN_EST_0 +251 0x0100 //TX_DELTA_THR_SN_EST_1 +252 0x0200 //TX_DELTA_THR_SN_EST_2 +253 0x0100 //TX_DELTA_THR_SN_EST_3 +254 0x0100 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0200 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x4000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x4000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x2000 //TX_B_POST_FLT_0 +280 0x1000 //TX_B_POST_FLT_1 +281 0x0010 //TX_NS_LVL_CTRL_0 +282 0x0014 //TX_NS_LVL_CTRL_1 +283 0x0018 //TX_NS_LVL_CTRL_2 +284 0x0016 //TX_NS_LVL_CTRL_3 +285 0x0014 //TX_NS_LVL_CTRL_4 +286 0x0011 //TX_NS_LVL_CTRL_5 +287 0x0014 //TX_NS_LVL_CTRL_6 +288 0x0011 //TX_NS_LVL_CTRL_7 +289 0x000F //TX_MIN_GAIN_S_0 +290 0x0010 //TX_MIN_GAIN_S_1 +291 0x0010 //TX_MIN_GAIN_S_2 +292 0x0010 //TX_MIN_GAIN_S_3 +293 0x0010 //TX_MIN_GAIN_S_4 +294 0x0010 //TX_MIN_GAIN_S_5 +295 0x0010 //TX_MIN_GAIN_S_6 +296 0x000F //TX_MIN_GAIN_S_7 +297 0x6000 //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x4000 //TX_SNRI_SUP_1 +302 0x4000 //TX_SNRI_SUP_2 +303 0x4000 //TX_SNRI_SUP_3 +304 0x4000 //TX_SNRI_SUP_4 +305 0x50C0 //TX_SNRI_SUP_5 +306 0x4000 //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x0018 //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x5000 //TX_A_POST_FILT_S_0 +315 0x4C00 //TX_A_POST_FILT_S_1 +316 0x4000 //TX_A_POST_FILT_S_2 +317 0x6000 //TX_A_POST_FILT_S_3 +318 0x4000 //TX_A_POST_FILT_S_4 +319 0x5000 //TX_A_POST_FILT_S_5 +320 0x6000 //TX_A_POST_FILT_S_6 +321 0x7000 //TX_A_POST_FILT_S_7 +322 0x2000 //TX_B_POST_FILT_0 +323 0x2000 //TX_B_POST_FILT_1 +324 0x2000 //TX_B_POST_FILT_2 +325 0x4000 //TX_B_POST_FILT_3 +326 0x4000 //TX_B_POST_FILT_4 +327 0x1000 //TX_B_POST_FILT_5 +328 0x1000 //TX_B_POST_FILT_6 +329 0x2000 //TX_B_POST_FILT_7 +330 0x4000 //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x6000 //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7C00 //TX_LAMBDA_PFILT +339 0x7C00 //TX_LAMBDA_PFILT_S_0 +340 0x7C00 //TX_LAMBDA_PFILT_S_1 +341 0x7A00 //TX_LAMBDA_PFILT_S_2 +342 0x7C00 //TX_LAMBDA_PFILT_S_3 +343 0x7C00 //TX_LAMBDA_PFILT_S_4 +344 0x7C00 //TX_LAMBDA_PFILT_S_5 +345 0x7C00 //TX_LAMBDA_PFILT_S_6 +346 0x7C00 //TX_LAMBDA_PFILT_S_7 +347 0x0200 //TX_K_PEPPER +348 0x0800 //TX_A_PEPPER +349 0x1EAA //TX_K_PEPPER_HF +350 0x0600 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0800 //TX_DT_BINVAD_TH_0 +354 0x0800 //TX_DT_BINVAD_TH_1 +355 0x0800 //TX_DT_BINVAD_TH_2 +356 0x0800 //TX_DT_BINVAD_TH_3 +357 0x1D4C //TX_DT_BINVAD_ENDF +358 0x0800 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0140 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0064 //TX_NDETCT +367 0x0102 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x017E //TX_NOISE_TH_1 +371 0x0230 //TX_NOISE_TH_2 +372 0x3492 //TX_NOISE_TH_3 +373 0x4E20 //TX_NOISE_TH_4 +374 0x55B8 //TX_NOISE_TH_5 +375 0x49E6 //TX_NOISE_TH_5_2 +376 0x0001 //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x0F0A //TX_NOISE_TH_6 +379 0x00F8 //TX_MINENOISE_TH +380 0xD508 //TX_MORENS_TFMASK_TH +381 0x0001 //TX_DRC_QUIET_FLOOR +382 0x3A98 //TX_RATIODTL_CUT_TH +383 0x0DAC //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x0333 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x7FFF //TX_POST_MASK_SUP_HSNE +392 0x1388 //TX_TAIL_DET_TH +393 0x4000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0080 //TX_SUPHIGH_TH +396 0x0000 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x1800 //TX_C_POST_FLT_MASK +399 0x7FFF //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0004 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x00DC //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x7FFF //TX_MIN_G_CTRL_SSNS +409 0x0000 //TX_METAL_RTO_THR +410 0x4848 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x4000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x01E0 //TX_NOR_OFF_THR +498 0x7C00 //TX_MORE_ON_700HZ_THR +499 0x0000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0xD333 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x4000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0xC000 //TX_DEREVERB_LF_MU +515 0xC000 //TX_DEREVERB_HF_MU +516 0xCCCC //TX_DEREVERB_DELAY +517 0xD999 //TX_DEREVERB_COEF_LEN +518 0x1F40 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x7000 //TX_GSC_RTOH_TH +523 0x0064 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0020 //TX_FDEQ_SUBNUM +567 0x5454 //TX_FDEQ_GAIN_0 +568 0x5448 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4850 //TX_FDEQ_GAIN_5 +573 0x5050 //TX_FDEQ_GAIN_6 +574 0x5448 //TX_FDEQ_GAIN_7 +575 0x464C //TX_FDEQ_GAIN_8 +576 0x5050 //TX_FDEQ_GAIN_9 +577 0x4848 //TX_FDEQ_GAIN_10 +578 0x4848 //TX_FDEQ_GAIN_11 +579 0x4848 //TX_FDEQ_GAIN_12 +580 0x4848 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0303 //TX_FDEQ_BIN_2 +594 0x0304 //TX_FDEQ_BIN_3 +595 0x0405 //TX_FDEQ_BIN_4 +596 0x0506 //TX_FDEQ_BIN_5 +597 0x0708 //TX_FDEQ_BIN_6 +598 0x090A //TX_FDEQ_BIN_7 +599 0x0B0C //TX_FDEQ_BIN_8 +600 0x0D0E //TX_FDEQ_BIN_9 +601 0x0F10 //TX_FDEQ_BIN_10 +602 0x1011 //TX_FDEQ_BIN_11 +603 0x1112 //TX_FDEQ_BIN_12 +604 0x120B //TX_FDEQ_BIN_13 +605 0x0000 //TX_FDEQ_BIN_14 +606 0x0000 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x484A //TX_PREEQ_GAIN_MIC0_8 +626 0x4B4C //TX_PREEQ_GAIN_MIC0_9 +627 0x4B4A //TX_PREEQ_GAIN_MIC0_10 +628 0x4A48 //TX_PREEQ_GAIN_MIC0_11 +629 0x4C4C //TX_PREEQ_GAIN_MIC0_12 +630 0x4C4C //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0202 //TX_PREEQ_BIN_MIC0_0 +642 0x0203 //TX_PREEQ_BIN_MIC0_1 +643 0x0303 //TX_PREEQ_BIN_MIC0_2 +644 0x0304 //TX_PREEQ_BIN_MIC0_3 +645 0x0405 //TX_PREEQ_BIN_MIC0_4 +646 0x0506 //TX_PREEQ_BIN_MIC0_5 +647 0x0708 //TX_PREEQ_BIN_MIC0_6 +648 0x090A //TX_PREEQ_BIN_MIC0_7 +649 0x0B0C //TX_PREEQ_BIN_MIC0_8 +650 0x0D0E //TX_PREEQ_BIN_MIC0_9 +651 0x0F10 //TX_PREEQ_BIN_MIC0_10 +652 0x1011 //TX_PREEQ_BIN_MIC0_11 +653 0x1112 //TX_PREEQ_BIN_MIC0_12 +654 0x120B //TX_PREEQ_BIN_MIC0_13 +655 0x0000 //TX_PREEQ_BIN_MIC0_14 +656 0x0000 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4846 //TX_PREEQ_GAIN_MIC1_7 +674 0x4544 //TX_PREEQ_GAIN_MIC1_8 +675 0x4241 //TX_PREEQ_GAIN_MIC1_9 +676 0x403E //TX_PREEQ_GAIN_MIC1_10 +677 0x3D3C //TX_PREEQ_GAIN_MIC1_11 +678 0x3C3C //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0202 //TX_PREEQ_BIN_MIC1_0 +691 0x0203 //TX_PREEQ_BIN_MIC1_1 +692 0x0303 //TX_PREEQ_BIN_MIC1_2 +693 0x0304 //TX_PREEQ_BIN_MIC1_3 +694 0x0405 //TX_PREEQ_BIN_MIC1_4 +695 0x0506 //TX_PREEQ_BIN_MIC1_5 +696 0x0708 //TX_PREEQ_BIN_MIC1_6 +697 0x090A //TX_PREEQ_BIN_MIC1_7 +698 0x0B0C //TX_PREEQ_BIN_MIC1_8 +699 0x0F10 //TX_PREEQ_BIN_MIC1_9 +700 0x1011 //TX_PREEQ_BIN_MIC1_10 +701 0x1112 //TX_PREEQ_BIN_MIC1_11 +702 0x1208 //TX_PREEQ_BIN_MIC1_12 +703 0x0000 //TX_PREEQ_BIN_MIC1_13 +704 0x0000 //TX_PREEQ_BIN_MIC1_14 +705 0x0000 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0608 //TX_PREEQ_BIN_MIC2_0 +740 0x0808 //TX_PREEQ_BIN_MIC2_1 +741 0x0808 //TX_PREEQ_BIN_MIC2_2 +742 0x0808 //TX_PREEQ_BIN_MIC2_3 +743 0x0808 //TX_PREEQ_BIN_MIC2_4 +744 0x0808 //TX_PREEQ_BIN_MIC2_5 +745 0x0808 //TX_PREEQ_BIN_MIC2_6 +746 0x0808 //TX_PREEQ_BIN_MIC2_7 +747 0x0808 //TX_PREEQ_BIN_MIC2_8 +748 0x0808 //TX_PREEQ_BIN_MIC2_9 +749 0x0808 //TX_PREEQ_BIN_MIC2_10 +750 0x0808 //TX_PREEQ_BIN_MIC2_11 +751 0x0808 //TX_PREEQ_BIN_MIC2_12 +752 0x0808 //TX_PREEQ_BIN_MIC2_13 +753 0x0808 //TX_PREEQ_BIN_MIC2_14 +754 0x0200 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x0800 //TX_NND_WEIGHT +765 0x0062 //TX_MIC_CALIBRATION_0 +766 0x0062 //TX_MIC_CALIBRATION_1 +767 0x0062 //TX_MIC_CALIBRATION_2 +768 0x0062 //TX_MIC_CALIBRATION_3 +769 0x0046 //TX_MIC_PWR_BIAS_0 +770 0x0046 //TX_MIC_PWR_BIAS_1 +771 0x0046 //TX_MIC_PWR_BIAS_2 +772 0x0046 //TX_MIC_PWR_BIAS_3 +773 0x0009 //TX_GAIN_LIMIT_0 +774 0x000F //TX_GAIN_LIMIT_1 +775 0x000F //TX_GAIN_LIMIT_2 +776 0x000F //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x0800 //TX_TDDRC_ALPHA_UP_01 +784 0x0800 //TX_TDDRC_ALPHA_UP_02 +785 0x0800 //TX_TDDRC_ALPHA_UP_03 +786 0x0800 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x7214 //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0010 //TX_DEADMIC_SILENCE_TH +817 0x0600 //TX_MIC_DEGRADE_TH +818 0x0078 //TX_DEADMIC_CNT +819 0x0078 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x4848 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0096 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0002 //TX_FILTINDX +854 0x0001 //TX_TDDRC_THRD_0 +855 0x0002 //TX_TDDRC_THRD_1 +856 0x1800 //TX_TDDRC_THRD_2 +857 0x1800 //TX_TDDRC_THRD_3 +858 0x7FFF //TX_TDDRC_SLANT_0 +859 0x7FFF //TX_TDDRC_SLANT_1 +860 0x0800 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x0C97 //TX_TDDRC_DRC_GAIN +867 0x7FFF //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x0028 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x4000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x2339 //TX_SENDFUNC_REG_MICMUTE +898 0x0021 //TX_SENDFUNC_REG_MICMUTE1 +899 0x02BC //TX_MICMUTE_RATIO_THR +900 0x0140 //TX_MICMUTE_AMP_THR +901 0x0004 //TX_MICMUTE_HPF_IND +902 0x00C0 //TX_MICMUTE_LOG_EYR_TH +903 0x0008 //TX_MICMUTE_CVG_TIME +904 0x0008 //TX_MICMUTE_RELEASE_TIME +905 0x01FE //TX_MIC_VOLUME_MIC0MUTE +906 0x0020 //TX_MICMUTE_EPD_OFFSET_0 +907 0x001E //TX_MICMUTE_FRQ_AEC_L +908 0x7999 //TX_MICMUTE_EAD_THR +909 0x7FFF //TX_MICMUTE_LAMBDA_CB_NLE +910 0x7FFF //TX_MICMUTE_LAMBDA_RE_EST +911 0x4000 //TX_DTD_THR1_MICMUTE_0 +912 0x7000 //TX_DTD_THR1_MICMUTE_1 +913 0x7FFF //TX_DTD_THR1_MICMUTE_2 +914 0x7FFF //TX_DTD_THR1_MICMUTE_3 +915 0x6CCC //TX_DTD_THR2_MICMUTE_0 +916 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x1000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x4000 //TX_MICMUTE_C_POST_FLT +922 0x03E8 //TX_MICMUTE_DT_CUT_K +923 0x0001 //TX_MICMUTE_DT_CUT_THR +924 0x03E8 //TX_MICMUTE_DT_CUT_K2 +925 0x0001 //TX_MICMUTE_DT_CUT_THR2 +926 0x0064 //TX_MICMUTE_DT2_HOLD_N +927 0x1000 //TX_MICMUTE_RATIODTH_THCUT +928 0x1000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x7FFF //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0400 //TX_MICMUTE_C_POST_FLT_MASK +931 0x7999 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0258 //TX_MICMUTE_DT_CUT_K1 +933 0x0800 //TX_MICMUTE_N2_SN_EST +934 0xFC00 //TX_MICMUTE_THR_SN_EST_0 +935 0x001C //TX_MICMUTE_MIN_G_CTRL_0 +936 0x6000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x7000 //TX_MICMUTE_B_POST_FILT_0 +938 0x2710 //TX_MIC1RUB_AMP_THR +939 0x0010 //TX_MIC1MUTE_RATIO_THR +940 0x0450 //TX_MIC1MUTE_AMP_THR +941 0x0008 //TX_MIC1MUTE_CVG_TIME +942 0x0008 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x2040 //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0000 //RX_SAMPLINGFREQ_SIG +3 0x0000 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +10 0x050D //RX_PGA +11 0x7652 //RX_A_HP +12 0x4000 //RX_B_PE +13 0x7800 //RX_THR_PITCH_DET_0 +14 0x7000 //RX_THR_PITCH_DET_1 +15 0x6000 //RX_THR_PITCH_DET_2 +16 0x0000 //RX_PITCH_BFR_LEN +17 0x0000 //RX_SBD_PITCH_DET +18 0x0000 //RX_PP_RESRV_0 +19 0x0000 //RX_PP_RESRV_1 +20 0xF800 //RX_N_SN_EST +21 0x0000 //RX_N2_SN_EST +22 0x000F //RX_NS_LVL_CTRL +23 0xF800 //RX_THR_SN_EST +24 0x7E00 //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0000 //RX_FENS_RESRV_1 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +30 0x0000 //RX_EXTRA_NS_L +31 0x0000 //RX_EXTRA_NS_A +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x0000 //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0003 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x0080 //RX_MIN_G_FP +128 0x2000 //RX_MAX_G_FP +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0010 //RX_MAXLEVEL_CNG +132 0x0000 //RX_BWE_UV_TH +133 0x0000 //RX_BWE_UV_TH2 +134 0x0000 //RX_BWE_UV_TH3 +135 0x0000 //RX_BWE_V_TH +136 0x0000 //RX_BWE_GAIN1_V_TH1 +137 0x0000 //RX_BWE_GAIN1_V_TH2 +138 0x0000 //RX_BWE_UV_EQ +139 0x0000 //RX_BWE_V_EQ +140 0x0000 //RX_BWE_TONE_TH +141 0x0000 //RX_BWE_UV_HOLD_T +142 0x0000 //RX_BWE_GAIN2_ALPHA +143 0x0000 //RX_BWE_GAIN3_ALPHA +144 0x0000 //RX_BWE_CUTOFF +145 0x0000 //RX_BWE_GAINFILL +146 0x0000 //RX_BWE_MAXTH_TONE +147 0x0000 //RX_BWE_EQ_0 +148 0x0000 //RX_BWE_EQ_1 +149 0x0000 //RX_BWE_EQ_2 +150 0x0000 //RX_BWE_EQ_3 +151 0x0000 //RX_BWE_EQ_4 +152 0x0000 //RX_BWE_EQ_5 +153 0x0000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x2040 //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0000 //RX_SAMPLINGFREQ_SIG +160 0x0000 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +167 0x050D //RX_PGA +168 0x7652 //RX_A_HP +169 0x4000 //RX_B_PE +170 0x7800 //RX_THR_PITCH_DET_0 +171 0x7000 //RX_THR_PITCH_DET_1 +172 0x6000 //RX_THR_PITCH_DET_2 +173 0x0000 //RX_PITCH_BFR_LEN +174 0x0000 //RX_SBD_PITCH_DET +175 0x0000 //RX_PP_RESRV_0 +176 0x0000 //RX_PP_RESRV_1 +177 0xF800 //RX_N_SN_EST +178 0x0000 //RX_N2_SN_EST +179 0x000F //RX_NS_LVL_CTRL +180 0xF800 //RX_THR_SN_EST +181 0x7E00 //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0000 //RX_FENS_RESRV_1 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +187 0x0000 //RX_EXTRA_NS_L +188 0x0000 //RX_EXTRA_NS_A +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x0000 //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0003 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x0080 //RX_MIN_G_FP +285 0x2000 //RX_MAX_G_FP +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0010 //RX_MAXLEVEL_CNG +289 0x0000 //RX_BWE_UV_TH +290 0x0000 //RX_BWE_UV_TH2 +291 0x0000 //RX_BWE_UV_TH3 +292 0x0000 //RX_BWE_V_TH +293 0x0000 //RX_BWE_GAIN1_V_TH1 +294 0x0000 //RX_BWE_GAIN1_V_TH2 +295 0x0000 //RX_BWE_UV_EQ +296 0x0000 //RX_BWE_V_EQ +297 0x0000 //RX_BWE_TONE_TH +298 0x0000 //RX_BWE_UV_HOLD_T +299 0x0000 //RX_BWE_GAIN2_ALPHA +300 0x0000 //RX_BWE_GAIN3_ALPHA +301 0x0000 //RX_BWE_CUTOFF +302 0x0000 //RX_BWE_GAINFILL +303 0x0000 //RX_BWE_MAXTH_TONE +304 0x0000 //RX_BWE_EQ_0 +305 0x0000 //RX_BWE_EQ_1 +306 0x0000 //RX_BWE_EQ_2 +307 0x0000 //RX_BWE_EQ_3 +308 0x0000 //RX_BWE_EQ_4 +309 0x0000 //RX_BWE_EQ_5 +310 0x0000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME HEADSET-TTY_VCO-VOICE_GENERIC-SWB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0001 //TX_OPERATION_MODE_0 +1 0x0001 //TX_OPERATION_MODE_1 +2 0x0033 //TX_PATCH_REG +3 0x6F7C //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0002 //TX_NUM_MIC +6 0x0003 //TX_SAMPLINGFREQ_SIG +7 0x0003 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009D //TX_DIST2REF1 +22 0x0010 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x1000 //TX_PGA_0 +28 0x1000 //TX_PGA_1 +29 0x1000 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0001 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0002 //TX_MIC_DATA_SRC0 +42 0x0000 //TX_MIC_DATA_SRC1 +43 0x0001 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3B33 //TX_DIST2REF_11 +73 0x0A70 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0800 //TX_MIC_REFBLK_VOLUME +108 0x0CAE //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0015 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7D83 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x5000 //TX_THR_PITCH_DET_0 +131 0x4800 //TX_THR_PITCH_DET_1 +132 0x4000 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x0028 //TX_TAIL_LENGTH +147 0x0400 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x7600 //TX_EAD_THR +151 0x1000 //TX_THR_RE_EST +152 0x2000 //TX_MIN_EQ_RE_EST_0 +153 0x0600 //TX_MIN_EQ_RE_EST_1 +154 0x3000 //TX_MIN_EQ_RE_EST_2 +155 0x3000 //TX_MIN_EQ_RE_EST_3 +156 0x3000 //TX_MIN_EQ_RE_EST_4 +157 0x3000 //TX_MIN_EQ_RE_EST_5 +158 0x3000 //TX_MIN_EQ_RE_EST_6 +159 0x1000 //TX_MIN_EQ_RE_EST_7 +160 0x7800 //TX_MIN_EQ_RE_EST_8 +161 0x7800 //TX_MIN_EQ_RE_EST_9 +162 0x7800 //TX_MIN_EQ_RE_EST_10 +163 0x7800 //TX_MIN_EQ_RE_EST_11 +164 0x7800 //TX_MIN_EQ_RE_EST_12 +165 0x0880 //TX_LAMBDA_RE_EST +166 0x7FFF //TX_LAMBDA_CB_NLE +167 0x7FFF //TX_C_POST_FLT +168 0x4000 //TX_GAIN_NP +169 0x0180 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x05DC //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x7FF0 //TX_DTD_THR1_0 +198 0x7FF0 //TX_DTD_THR1_1 +199 0x7FF0 //TX_DTD_THR1_2 +200 0x7FF0 //TX_DTD_THR1_3 +201 0x7FF0 //TX_DTD_THR1_4 +202 0x7FF0 //TX_DTD_THR1_5 +203 0x7FF0 //TX_DTD_THR1_6 +204 0x7E00 //TX_DTD_THR2_0 +205 0x7E00 //TX_DTD_THR2_1 +206 0x5000 //TX_DTD_THR2_2 +207 0x5000 //TX_DTD_THR2_3 +208 0x5000 //TX_DTD_THR2_4 +209 0x5000 //TX_DTD_THR2_5 +210 0x5000 //TX_DTD_THR2_6 +211 0x7FFF //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x36B0 //TX_DT_CUT_K +214 0x0100 //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x7FFF //TX_DTD_MIC_BLK +221 0x023E //TX_ADPT_STRICT_L +222 0x023E //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x733C //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x7FFF //TX_B_POST_FILT_ECHO_L +229 0x7FFF //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x1000 //TX_B_LESSCUT_RTO_ECHO +232 0x0000 //TX_EPD_OFFSET_00 +233 0x0000 //TX_EPD_OFFST_01 +234 0x3A98 //TX_RATIO_DT_L0_TH_HIGH +235 0x7FFF //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x0000 //TX_DTD_THR1_7 +238 0x0000 //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xFA00 //TX_THR_SN_EST_0 +243 0xFA00 //TX_THR_SN_EST_1 +244 0xFA00 //TX_THR_SN_EST_2 +245 0xFA00 //TX_THR_SN_EST_3 +246 0xF800 //TX_THR_SN_EST_4 +247 0xFA00 //TX_THR_SN_EST_5 +248 0xF800 //TX_THR_SN_EST_6 +249 0xF800 //TX_THR_SN_EST_7 +250 0x0100 //TX_DELTA_THR_SN_EST_0 +251 0x0100 //TX_DELTA_THR_SN_EST_1 +252 0x0100 //TX_DELTA_THR_SN_EST_2 +253 0x0000 //TX_DELTA_THR_SN_EST_3 +254 0x0100 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0100 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x4000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x4000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x2000 //TX_B_POST_FLT_0 +280 0x1000 //TX_B_POST_FLT_1 +281 0x0010 //TX_NS_LVL_CTRL_0 +282 0x003C //TX_NS_LVL_CTRL_1 +283 0x0024 //TX_NS_LVL_CTRL_2 +284 0x003C //TX_NS_LVL_CTRL_3 +285 0x0014 //TX_NS_LVL_CTRL_4 +286 0x0011 //TX_NS_LVL_CTRL_5 +287 0x003C //TX_NS_LVL_CTRL_6 +288 0x0011 //TX_NS_LVL_CTRL_7 +289 0x000F //TX_MIN_GAIN_S_0 +290 0x0010 //TX_MIN_GAIN_S_1 +291 0x0010 //TX_MIN_GAIN_S_2 +292 0x0010 //TX_MIN_GAIN_S_3 +293 0x0010 //TX_MIN_GAIN_S_4 +294 0x0010 //TX_MIN_GAIN_S_5 +295 0x0010 //TX_MIN_GAIN_S_6 +296 0x000F //TX_MIN_GAIN_S_7 +297 0x6000 //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x1400 //TX_SNRI_SUP_1 +302 0x1400 //TX_SNRI_SUP_2 +303 0x4000 //TX_SNRI_SUP_3 +304 0x4000 //TX_SNRI_SUP_4 +305 0x50C0 //TX_SNRI_SUP_5 +306 0x1400 //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x0018 //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x5000 //TX_A_POST_FILT_S_0 +315 0x4C00 //TX_A_POST_FILT_S_1 +316 0x4000 //TX_A_POST_FILT_S_2 +317 0x6000 //TX_A_POST_FILT_S_3 +318 0x4000 //TX_A_POST_FILT_S_4 +319 0x5000 //TX_A_POST_FILT_S_5 +320 0x7C00 //TX_A_POST_FILT_S_6 +321 0x7000 //TX_A_POST_FILT_S_7 +322 0x2000 //TX_B_POST_FILT_0 +323 0x6000 //TX_B_POST_FILT_1 +324 0x6000 //TX_B_POST_FILT_2 +325 0x6000 //TX_B_POST_FILT_3 +326 0x4000 //TX_B_POST_FILT_4 +327 0x1000 //TX_B_POST_FILT_5 +328 0x1000 //TX_B_POST_FILT_6 +329 0x2000 //TX_B_POST_FILT_7 +330 0x4000 //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x6000 //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7C00 //TX_LAMBDA_PFILT +339 0x7D00 //TX_LAMBDA_PFILT_S_0 +340 0x7D00 //TX_LAMBDA_PFILT_S_1 +341 0x7D00 //TX_LAMBDA_PFILT_S_2 +342 0x7D00 //TX_LAMBDA_PFILT_S_3 +343 0x7D00 //TX_LAMBDA_PFILT_S_4 +344 0x7D00 //TX_LAMBDA_PFILT_S_5 +345 0x7D00 //TX_LAMBDA_PFILT_S_6 +346 0x7D00 //TX_LAMBDA_PFILT_S_7 +347 0x0200 //TX_K_PEPPER +348 0x0400 //TX_A_PEPPER +349 0x1EAA //TX_K_PEPPER_HF +350 0x0600 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x0040 //TX_DT_BINVAD_TH_0 +354 0x0040 //TX_DT_BINVAD_TH_1 +355 0x0100 //TX_DT_BINVAD_TH_2 +356 0x0100 //TX_DT_BINVAD_TH_3 +357 0x36B0 //TX_DT_BINVAD_ENDF +358 0x0200 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0140 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0064 //TX_NDETCT +367 0x0383 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x07D0 //TX_NOISE_TH_1 +371 0x01F4 //TX_NOISE_TH_2 +372 0x36B0 //TX_NOISE_TH_3 +373 0x2710 //TX_NOISE_TH_4 +374 0x2CEC //TX_NOISE_TH_5 +375 0x7FFF //TX_NOISE_TH_5_2 +376 0x0000 //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x0DAC //TX_NOISE_TH_6 +379 0x044C //TX_MINENOISE_TH +380 0xD508 //TX_MORENS_TFMASK_TH +381 0x0001 //TX_DRC_QUIET_FLOOR +382 0x3A98 //TX_RATIODTL_CUT_TH +383 0x0DAC //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x0333 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x7FFF //TX_POST_MASK_SUP_HSNE +392 0x1388 //TX_TAIL_DET_TH +393 0x4000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0080 //TX_SUPHIGH_TH +396 0x0000 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x1800 //TX_C_POST_FLT_MASK +399 0x7FFF //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0004 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x02F3 //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x4000 //TX_MIN_G_CTRL_SSNS +409 0x0000 //TX_METAL_RTO_THR +410 0x4848 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x4000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x0230 //TX_NOR_OFF_THR +498 0x0CCD //TX_MORE_ON_700HZ_THR +499 0x0000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x2000 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0x4650 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x4000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0xC000 //TX_DEREVERB_LF_MU +515 0xC000 //TX_DEREVERB_HF_MU +516 0xCCCC //TX_DEREVERB_DELAY +517 0xD999 //TX_DEREVERB_COEF_LEN +518 0x1F40 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x7000 //TX_GSC_RTOH_TH +523 0x0064 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0020 //TX_FDEQ_SUBNUM +567 0x5450 //TX_FDEQ_GAIN_0 +568 0x4C48 //TX_FDEQ_GAIN_1 +569 0x4850 //TX_FDEQ_GAIN_2 +570 0x5050 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x484E //TX_FDEQ_GAIN_5 +573 0x4E5E //TX_FDEQ_GAIN_6 +574 0x584E //TX_FDEQ_GAIN_7 +575 0x4C4E //TX_FDEQ_GAIN_8 +576 0x564E //TX_FDEQ_GAIN_9 +577 0x5058 //TX_FDEQ_GAIN_10 +578 0x625C //TX_FDEQ_GAIN_11 +579 0x6C6C //TX_FDEQ_GAIN_12 +580 0x7086 //TX_FDEQ_GAIN_13 +581 0x869C //TX_FDEQ_GAIN_14 +582 0xB0B0 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0303 //TX_FDEQ_BIN_2 +594 0x0304 //TX_FDEQ_BIN_3 +595 0x0405 //TX_FDEQ_BIN_4 +596 0x0506 //TX_FDEQ_BIN_5 +597 0x0708 //TX_FDEQ_BIN_6 +598 0x090A //TX_FDEQ_BIN_7 +599 0x0B0C //TX_FDEQ_BIN_8 +600 0x0D0E //TX_FDEQ_BIN_9 +601 0x1013 //TX_FDEQ_BIN_10 +602 0x1719 //TX_FDEQ_BIN_11 +603 0x1B1E //TX_FDEQ_BIN_12 +604 0x1E1E //TX_FDEQ_BIN_13 +605 0x1E28 //TX_FDEQ_BIN_14 +606 0x284A //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x494A //TX_PREEQ_GAIN_MIC0_8 +626 0x4B4C //TX_PREEQ_GAIN_MIC0_9 +627 0x4B4A //TX_PREEQ_GAIN_MIC0_10 +628 0x484B //TX_PREEQ_GAIN_MIC0_11 +629 0x4C4C //TX_PREEQ_GAIN_MIC0_12 +630 0x4B48 //TX_PREEQ_GAIN_MIC0_13 +631 0x3838 //TX_PREEQ_GAIN_MIC0_14 +632 0x3835 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0202 //TX_PREEQ_BIN_MIC0_0 +642 0x0203 //TX_PREEQ_BIN_MIC0_1 +643 0x0303 //TX_PREEQ_BIN_MIC0_2 +644 0x0304 //TX_PREEQ_BIN_MIC0_3 +645 0x0405 //TX_PREEQ_BIN_MIC0_4 +646 0x0506 //TX_PREEQ_BIN_MIC0_5 +647 0x0708 //TX_PREEQ_BIN_MIC0_6 +648 0x090A //TX_PREEQ_BIN_MIC0_7 +649 0x0B0C //TX_PREEQ_BIN_MIC0_8 +650 0x0D0E //TX_PREEQ_BIN_MIC0_9 +651 0x1013 //TX_PREEQ_BIN_MIC0_10 +652 0x1719 //TX_PREEQ_BIN_MIC0_11 +653 0x1B1E //TX_PREEQ_BIN_MIC0_12 +654 0x1E1E //TX_PREEQ_BIN_MIC0_13 +655 0x1E28 //TX_PREEQ_BIN_MIC0_14 +656 0x282C //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4846 //TX_PREEQ_GAIN_MIC1_7 +674 0x4544 //TX_PREEQ_GAIN_MIC1_8 +675 0x4241 //TX_PREEQ_GAIN_MIC1_9 +676 0x403E //TX_PREEQ_GAIN_MIC1_10 +677 0x3D3C //TX_PREEQ_GAIN_MIC1_11 +678 0x3C3C //TX_PREEQ_GAIN_MIC1_12 +679 0x3C39 //TX_PREEQ_GAIN_MIC1_13 +680 0x3838 //TX_PREEQ_GAIN_MIC1_14 +681 0x3A3C //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0202 //TX_PREEQ_BIN_MIC1_0 +691 0x0203 //TX_PREEQ_BIN_MIC1_1 +692 0x0303 //TX_PREEQ_BIN_MIC1_2 +693 0x0304 //TX_PREEQ_BIN_MIC1_3 +694 0x0405 //TX_PREEQ_BIN_MIC1_4 +695 0x0506 //TX_PREEQ_BIN_MIC1_5 +696 0x0708 //TX_PREEQ_BIN_MIC1_6 +697 0x090A //TX_PREEQ_BIN_MIC1_7 +698 0x0B0C //TX_PREEQ_BIN_MIC1_8 +699 0x0D0E //TX_PREEQ_BIN_MIC1_9 +700 0x1013 //TX_PREEQ_BIN_MIC1_10 +701 0x1719 //TX_PREEQ_BIN_MIC1_11 +702 0x1B1E //TX_PREEQ_BIN_MIC1_12 +703 0x1E1E //TX_PREEQ_BIN_MIC1_13 +704 0x1E28 //TX_PREEQ_BIN_MIC1_14 +705 0x282C //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0608 //TX_PREEQ_BIN_MIC2_0 +740 0x0808 //TX_PREEQ_BIN_MIC2_1 +741 0x0808 //TX_PREEQ_BIN_MIC2_2 +742 0x0808 //TX_PREEQ_BIN_MIC2_3 +743 0x0808 //TX_PREEQ_BIN_MIC2_4 +744 0x0808 //TX_PREEQ_BIN_MIC2_5 +745 0x0808 //TX_PREEQ_BIN_MIC2_6 +746 0x0808 //TX_PREEQ_BIN_MIC2_7 +747 0x0808 //TX_PREEQ_BIN_MIC2_8 +748 0x0808 //TX_PREEQ_BIN_MIC2_9 +749 0x0808 //TX_PREEQ_BIN_MIC2_10 +750 0x0808 //TX_PREEQ_BIN_MIC2_11 +751 0x0808 //TX_PREEQ_BIN_MIC2_12 +752 0x0808 //TX_PREEQ_BIN_MIC2_13 +753 0x0808 //TX_PREEQ_BIN_MIC2_14 +754 0xF200 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x0800 //TX_NND_WEIGHT +765 0x0050 //TX_MIC_CALIBRATION_0 +766 0x0065 //TX_MIC_CALIBRATION_1 +767 0x0050 //TX_MIC_CALIBRATION_2 +768 0x0050 //TX_MIC_CALIBRATION_3 +769 0x0046 //TX_MIC_PWR_BIAS_0 +770 0x0040 //TX_MIC_PWR_BIAS_1 +771 0x0046 //TX_MIC_PWR_BIAS_2 +772 0x0046 //TX_MIC_PWR_BIAS_3 +773 0x0000 //TX_GAIN_LIMIT_0 +774 0x000F //TX_GAIN_LIMIT_1 +775 0x0000 //TX_GAIN_LIMIT_2 +776 0x0000 //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x0800 //TX_TDDRC_ALPHA_UP_01 +784 0x0800 //TX_TDDRC_ALPHA_UP_02 +785 0x0800 //TX_TDDRC_ALPHA_UP_03 +786 0x0800 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x7214 //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0010 //TX_DEADMIC_SILENCE_TH +817 0x0600 //TX_MIC_DEGRADE_TH +818 0x0078 //TX_DEADMIC_CNT +819 0x0078 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x4848 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0096 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0002 //TX_FILTINDX +854 0x0003 //TX_TDDRC_THRD_0 +855 0x0004 //TX_TDDRC_THRD_1 +856 0x1800 //TX_TDDRC_THRD_2 +857 0x1800 //TX_TDDRC_THRD_3 +858 0x7FFF //TX_TDDRC_SLANT_0 +859 0x7FFF //TX_TDDRC_SLANT_1 +860 0x0800 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x0E21 //TX_TDDRC_DRC_GAIN +867 0x7FFF //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x00C8 //TX_FASTNS_ARSPC_TH +889 0x8000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x4000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x2339 //TX_SENDFUNC_REG_MICMUTE +898 0x0021 //TX_SENDFUNC_REG_MICMUTE1 +899 0x02BC //TX_MICMUTE_RATIO_THR +900 0x0140 //TX_MICMUTE_AMP_THR +901 0x0004 //TX_MICMUTE_HPF_IND +902 0x00C0 //TX_MICMUTE_LOG_EYR_TH +903 0x0008 //TX_MICMUTE_CVG_TIME +904 0x0008 //TX_MICMUTE_RELEASE_TIME +905 0x01FE //TX_MIC_VOLUME_MIC0MUTE +906 0x0020 //TX_MICMUTE_EPD_OFFSET_0 +907 0x001E //TX_MICMUTE_FRQ_AEC_L +908 0x7999 //TX_MICMUTE_EAD_THR +909 0x7FFF //TX_MICMUTE_LAMBDA_CB_NLE +910 0x7FFF //TX_MICMUTE_LAMBDA_RE_EST +911 0x4000 //TX_DTD_THR1_MICMUTE_0 +912 0x7000 //TX_DTD_THR1_MICMUTE_1 +913 0x7FFF //TX_DTD_THR1_MICMUTE_2 +914 0x7FFF //TX_DTD_THR1_MICMUTE_3 +915 0x6CCC //TX_DTD_THR2_MICMUTE_0 +916 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x1000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x4000 //TX_MICMUTE_C_POST_FLT +922 0x03E8 //TX_MICMUTE_DT_CUT_K +923 0x0001 //TX_MICMUTE_DT_CUT_THR +924 0x03E8 //TX_MICMUTE_DT_CUT_K2 +925 0x0001 //TX_MICMUTE_DT_CUT_THR2 +926 0x0064 //TX_MICMUTE_DT2_HOLD_N +927 0x1000 //TX_MICMUTE_RATIODTH_THCUT +928 0x1000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x7FFF //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0400 //TX_MICMUTE_C_POST_FLT_MASK +931 0x7999 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0258 //TX_MICMUTE_DT_CUT_K1 +933 0x0800 //TX_MICMUTE_N2_SN_EST +934 0xFC00 //TX_MICMUTE_THR_SN_EST_0 +935 0x001C //TX_MICMUTE_MIN_G_CTRL_0 +936 0x6000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x7000 //TX_MICMUTE_B_POST_FILT_0 +938 0x2710 //TX_MIC1RUB_AMP_THR +939 0x0010 //TX_MIC1MUTE_RATIO_THR +940 0x0450 //TX_MIC1MUTE_AMP_THR +941 0x0008 //TX_MIC1MUTE_CVG_TIME +942 0x0008 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x2040 //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0000 //RX_SAMPLINGFREQ_SIG +3 0x0000 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +10 0x050D //RX_PGA +11 0x7652 //RX_A_HP +12 0x4000 //RX_B_PE +13 0x7800 //RX_THR_PITCH_DET_0 +14 0x7000 //RX_THR_PITCH_DET_1 +15 0x6000 //RX_THR_PITCH_DET_2 +16 0x0000 //RX_PITCH_BFR_LEN +17 0x0000 //RX_SBD_PITCH_DET +18 0x0000 //RX_PP_RESRV_0 +19 0x0000 //RX_PP_RESRV_1 +20 0xF800 //RX_N_SN_EST +21 0x0000 //RX_N2_SN_EST +22 0x000F //RX_NS_LVL_CTRL +23 0xF800 //RX_THR_SN_EST +24 0x7E00 //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0000 //RX_FENS_RESRV_1 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +30 0x0000 //RX_EXTRA_NS_L +31 0x0000 //RX_EXTRA_NS_A +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x0000 //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0003 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x0080 //RX_MIN_G_FP +128 0x2000 //RX_MAX_G_FP +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0010 //RX_MAXLEVEL_CNG +132 0x0000 //RX_BWE_UV_TH +133 0x0000 //RX_BWE_UV_TH2 +134 0x0000 //RX_BWE_UV_TH3 +135 0x0000 //RX_BWE_V_TH +136 0x0000 //RX_BWE_GAIN1_V_TH1 +137 0x0000 //RX_BWE_GAIN1_V_TH2 +138 0x0000 //RX_BWE_UV_EQ +139 0x0000 //RX_BWE_V_EQ +140 0x0000 //RX_BWE_TONE_TH +141 0x0000 //RX_BWE_UV_HOLD_T +142 0x0000 //RX_BWE_GAIN2_ALPHA +143 0x0000 //RX_BWE_GAIN3_ALPHA +144 0x0000 //RX_BWE_CUTOFF +145 0x0000 //RX_BWE_GAINFILL +146 0x0000 //RX_BWE_MAXTH_TONE +147 0x0000 //RX_BWE_EQ_0 +148 0x0000 //RX_BWE_EQ_1 +149 0x0000 //RX_BWE_EQ_2 +150 0x0000 //RX_BWE_EQ_3 +151 0x0000 //RX_BWE_EQ_4 +152 0x0000 //RX_BWE_EQ_5 +153 0x0000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x2040 //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0000 //RX_SAMPLINGFREQ_SIG +160 0x0000 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +167 0x050D //RX_PGA +168 0x7652 //RX_A_HP +169 0x4000 //RX_B_PE +170 0x7800 //RX_THR_PITCH_DET_0 +171 0x7000 //RX_THR_PITCH_DET_1 +172 0x6000 //RX_THR_PITCH_DET_2 +173 0x0000 //RX_PITCH_BFR_LEN +174 0x0000 //RX_SBD_PITCH_DET +175 0x0000 //RX_PP_RESRV_0 +176 0x0000 //RX_PP_RESRV_1 +177 0xF800 //RX_N_SN_EST +178 0x0000 //RX_N2_SN_EST +179 0x000F //RX_NS_LVL_CTRL +180 0xF800 //RX_THR_SN_EST +181 0x7E00 //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0000 //RX_FENS_RESRV_1 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +187 0x0000 //RX_EXTRA_NS_L +188 0x0000 //RX_EXTRA_NS_A +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x0000 //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0003 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x0080 //RX_MIN_G_FP +285 0x2000 //RX_MAX_G_FP +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0010 //RX_MAXLEVEL_CNG +289 0x0000 //RX_BWE_UV_TH +290 0x0000 //RX_BWE_UV_TH2 +291 0x0000 //RX_BWE_UV_TH3 +292 0x0000 //RX_BWE_V_TH +293 0x0000 //RX_BWE_GAIN1_V_TH1 +294 0x0000 //RX_BWE_GAIN1_V_TH2 +295 0x0000 //RX_BWE_UV_EQ +296 0x0000 //RX_BWE_V_EQ +297 0x0000 //RX_BWE_TONE_TH +298 0x0000 //RX_BWE_UV_HOLD_T +299 0x0000 //RX_BWE_GAIN2_ALPHA +300 0x0000 //RX_BWE_GAIN3_ALPHA +301 0x0000 //RX_BWE_CUTOFF +302 0x0000 //RX_BWE_GAINFILL +303 0x0000 //RX_BWE_MAXTH_TONE +304 0x0000 //RX_BWE_EQ_0 +305 0x0000 //RX_BWE_EQ_1 +306 0x0000 //RX_BWE_EQ_2 +307 0x0000 //RX_BWE_EQ_3 +308 0x0000 //RX_BWE_EQ_4 +309 0x0000 //RX_BWE_EQ_5 +310 0x0000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME HEADSET-TTY_VCO-VOICE_GENERIC-FB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0001 //TX_OPERATION_MODE_0 +1 0x0001 //TX_OPERATION_MODE_1 +2 0x0033 //TX_PATCH_REG +3 0x6B7C //TX_SENDFUNC_MODE_0 +4 0x0001 //TX_SENDFUNC_MODE_1 +5 0x0002 //TX_NUM_MIC +6 0x0004 //TX_SAMPLINGFREQ_SIG +7 0x0004 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x009D //TX_DIST2REF1 +22 0x0010 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x1000 //TX_PGA_0 +28 0x1000 //TX_PGA_1 +29 0x1000 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0001 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0002 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0002 //TX_MICS_OF_PAIR0 +38 0x0002 //TX_MICS_OF_PAIR1 +39 0x0002 //TX_MICS_OF_PAIR2 +40 0x0002 //TX_MICS_OF_PAIR3 +41 0x0002 //TX_MIC_DATA_SRC0 +42 0x0000 //TX_MIC_DATA_SRC1 +43 0x0001 //TX_MIC_DATA_SRC2 +44 0x0000 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x05DC //TX_HD_BIN_MASK +53 0x0010 //TX_HD_SUBAND_MASK +54 0x19A1 //TX_HD_FRAME_AVG_MASK +55 0x0320 //TX_HD_MIN_FRQ +56 0x1000 //TX_HD_ALPHA_PSD +57 0x1100 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0xEE6C //TX_T_PSDVAT +63 0x0800 //TX_CNT +64 0x4000 //TX_ANTI_HOWL_GAIN +65 0x0001 //TX_MICFORBFMARK_0 +66 0x0001 //TX_MICFORBFMARK_1 +67 0x0001 //TX_MICFORBFMARK_2 +68 0x0001 //TX_MICFORBFMARK_3 +69 0x0001 //TX_MICFORBFMARK_4 +70 0x0001 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x3B33 //TX_DIST2REF_11 +73 0x0A70 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0800 //TX_MIC_REFBLK_VOLUME +108 0x0CAE //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x04D0 //TX_ADCS_GAIN +112 0x4000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x0000 //TX_BLMIC_BLKFACTOR +116 0x0000 //TX_BRMIC_BLKFACTOR +117 0x0031 //TX_MICBLK_START_BIN +118 0x0060 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0015 //TX_FENE_HOLD +123 0x4000 //TX_FE_ENER_TH_MTS +124 0x0004 //TX_FE_ENER_TH_EXP +125 0x6000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x6000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0010 //TX_MIC_BLOCK_N +128 0x7E56 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x1800 //TX_THR_PITCH_DET_0 +131 0x1000 //TX_THR_PITCH_DET_1 +132 0x0800 //TX_THR_PITCH_DET_2 +133 0x0008 //TX_PITCH_BFR_LEN +134 0x0003 //TX_SBD_PITCH_DET +135 0x0050 //TX_TD_AEC_L +136 0x4000 //TX_MU0_UNP_TD_AEC +137 0x1000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x0028 //TX_TAIL_LENGTH +147 0x0300 //TX_AEC_REF_GAIN_0 +148 0x0800 //TX_AEC_REF_GAIN_1 +149 0x0800 //TX_AEC_REF_GAIN_2 +150 0x7A00 //TX_EAD_THR +151 0x1000 //TX_THR_RE_EST +152 0x0800 //TX_MIN_EQ_RE_EST_0 +153 0x2000 //TX_MIN_EQ_RE_EST_1 +154 0x2000 //TX_MIN_EQ_RE_EST_2 +155 0x4000 //TX_MIN_EQ_RE_EST_3 +156 0x4000 //TX_MIN_EQ_RE_EST_4 +157 0x7FFF //TX_MIN_EQ_RE_EST_5 +158 0x7FFF //TX_MIN_EQ_RE_EST_6 +159 0x7FFF //TX_MIN_EQ_RE_EST_7 +160 0x7FFF //TX_MIN_EQ_RE_EST_8 +161 0x7FFF //TX_MIN_EQ_RE_EST_9 +162 0x7FFF //TX_MIN_EQ_RE_EST_10 +163 0x7FFF //TX_MIN_EQ_RE_EST_11 +164 0x7FFF //TX_MIN_EQ_RE_EST_12 +165 0x0700 //TX_LAMBDA_RE_EST +166 0x0CCD //TX_LAMBDA_CB_NLE +167 0x2000 //TX_C_POST_FLT +168 0x7FFF //TX_GAIN_NP +169 0x0180 //TX_SE_HOLD_N +170 0x00C8 //TX_DT_HOLD_N +171 0x09C4 //TX_DT2_HOLD_N +172 0x6666 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x7FFF //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0008 //TX_FRQ_LIN_LEN +184 0x7FFF //TX_FRQ_AEC_LEN_RHO +185 0x6000 //TX_MU0_UNP_FRQ_AEC +186 0x4000 //TX_MU0_PTD_FRQ_AEC +187 0x000A //TX_MINENOISETH +188 0x0800 //TX_MU0_RE_EST +189 0x0001 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x2000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x7D00 //TX_DTD_THR1_0 +198 0x7FF0 //TX_DTD_THR1_1 +199 0x7FF0 //TX_DTD_THR1_2 +200 0x7FF0 //TX_DTD_THR1_3 +201 0x7FF0 //TX_DTD_THR1_4 +202 0x7FF0 //TX_DTD_THR1_5 +203 0x7FF0 //TX_DTD_THR1_6 +204 0x0CCD //TX_DTD_THR2_0 +205 0x0CCD //TX_DTD_THR2_1 +206 0x0CCD //TX_DTD_THR2_2 +207 0x0CCD //TX_DTD_THR2_3 +208 0x0CCD //TX_DTD_THR2_4 +209 0x0CCD //TX_DTD_THR2_5 +210 0x0CCD //TX_DTD_THR2_6 +211 0x7FFF //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x0DAC //TX_DT_CUT_K +214 0x0020 //TX_DT_CUT_THR +215 0x04EB //TX_COMFORT_G +216 0x01F4 //TX_POWER_YOUT_TH +217 0x4000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x7FFF //TX_DTD_MIC_BLK +221 0x023E //TX_ADPT_STRICT_L +222 0x023E //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1194 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x7FFF //TX_B_POST_FILT_ECHO_L +229 0x2000 //TX_B_POST_FILT_ECHO_H +230 0x0200 //TX_MIN_G_CTRL_ECHO +231 0x1000 //TX_B_LESSCUT_RTO_ECHO +232 0x0063 //TX_EPD_OFFSET_00 +233 0x0000 //TX_EPD_OFFST_01 +234 0x0A28 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x7FFF //TX_MIN_EQ_RE_EST_13 +237 0x0000 //TX_DTD_THR1_7 +238 0x0000 //TX_DTD_THR2_7 +239 0x0800 //TX_DT_RESRV_7 +240 0x0800 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xF700 //TX_THR_SN_EST_0 +243 0xFA00 //TX_THR_SN_EST_1 +244 0xFA00 //TX_THR_SN_EST_2 +245 0xFB00 //TX_THR_SN_EST_3 +246 0xFA00 //TX_THR_SN_EST_4 +247 0xFA00 //TX_THR_SN_EST_5 +248 0xF800 //TX_THR_SN_EST_6 +249 0xF800 //TX_THR_SN_EST_7 +250 0x0100 //TX_DELTA_THR_SN_EST_0 +251 0x0100 //TX_DELTA_THR_SN_EST_1 +252 0x0200 //TX_DELTA_THR_SN_EST_2 +253 0x0100 //TX_DELTA_THR_SN_EST_3 +254 0x0100 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0200 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x4000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x4000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0400 //TX_N_SN_EST +267 0x001E //TX_INBEAM_T +268 0x0041 //TX_INBEAMHOLDT +269 0x2000 //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x0400 //TX_NE_RTO_TH_L +274 0x0800 //TX_MAINREFRTOH_TH_H +275 0x0800 //TX_MAINREFRTOH_TH_L +276 0x0800 //TX_MAINREFRTO_TH_H +277 0x0800 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x2000 //TX_B_POST_FLT_0 +280 0x1000 //TX_B_POST_FLT_1 +281 0x0010 //TX_NS_LVL_CTRL_0 +282 0x0014 //TX_NS_LVL_CTRL_1 +283 0x0018 //TX_NS_LVL_CTRL_2 +284 0x0016 //TX_NS_LVL_CTRL_3 +285 0x0014 //TX_NS_LVL_CTRL_4 +286 0x0011 //TX_NS_LVL_CTRL_5 +287 0x0014 //TX_NS_LVL_CTRL_6 +288 0x0011 //TX_NS_LVL_CTRL_7 +289 0x000F //TX_MIN_GAIN_S_0 +290 0x0010 //TX_MIN_GAIN_S_1 +291 0x0010 //TX_MIN_GAIN_S_2 +292 0x0010 //TX_MIN_GAIN_S_3 +293 0x0010 //TX_MIN_GAIN_S_4 +294 0x0010 //TX_MIN_GAIN_S_5 +295 0x0010 //TX_MIN_GAIN_S_6 +296 0x000F //TX_MIN_GAIN_S_7 +297 0x6000 //TX_NMOS_SUP +298 0x0000 //TX_NS_MAX_PRI_SNR_TH +299 0x0000 //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x4000 //TX_SNRI_SUP_1 +302 0x4000 //TX_SNRI_SUP_2 +303 0x4000 //TX_SNRI_SUP_3 +304 0x4000 //TX_SNRI_SUP_4 +305 0x50C0 //TX_SNRI_SUP_5 +306 0x4000 //TX_SNRI_SUP_6 +307 0x7FFF //TX_SNRI_SUP_7 +308 0x7FFF //TX_THR_LFNS +309 0x0018 //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x000A //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x2000 //TX_A_POST_FILT_1 +314 0x5000 //TX_A_POST_FILT_S_0 +315 0x4C00 //TX_A_POST_FILT_S_1 +316 0x4000 //TX_A_POST_FILT_S_2 +317 0x6000 //TX_A_POST_FILT_S_3 +318 0x4000 //TX_A_POST_FILT_S_4 +319 0x5000 //TX_A_POST_FILT_S_5 +320 0x6000 //TX_A_POST_FILT_S_6 +321 0x7000 //TX_A_POST_FILT_S_7 +322 0x2000 //TX_B_POST_FILT_0 +323 0x2000 //TX_B_POST_FILT_1 +324 0x2000 //TX_B_POST_FILT_2 +325 0x4000 //TX_B_POST_FILT_3 +326 0x4000 //TX_B_POST_FILT_4 +327 0x1000 //TX_B_POST_FILT_5 +328 0x1000 //TX_B_POST_FILT_6 +329 0x2000 //TX_B_POST_FILT_7 +330 0x4000 //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x6000 //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7C00 //TX_LAMBDA_PFILT +339 0x7C00 //TX_LAMBDA_PFILT_S_0 +340 0x7C00 //TX_LAMBDA_PFILT_S_1 +341 0x7A00 //TX_LAMBDA_PFILT_S_2 +342 0x7C00 //TX_LAMBDA_PFILT_S_3 +343 0x7C00 //TX_LAMBDA_PFILT_S_4 +344 0x7C00 //TX_LAMBDA_PFILT_S_5 +345 0x7C00 //TX_LAMBDA_PFILT_S_6 +346 0x7C00 //TX_LAMBDA_PFILT_S_7 +347 0x0180 //TX_K_PEPPER +348 0x0800 //TX_A_PEPPER +349 0x1EAA //TX_K_PEPPER_HF +350 0x0600 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x0200 //TX_HMNC_BST_THR +353 0x2000 //TX_DT_BINVAD_TH_0 +354 0x0800 //TX_DT_BINVAD_TH_1 +355 0x0200 //TX_DT_BINVAD_TH_2 +356 0x0200 //TX_DT_BINVAD_TH_3 +357 0x1F40 //TX_DT_BINVAD_ENDF +358 0x0100 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0000 //TX_BF_SGRAD_FLG +362 0x0005 //TX_BF_DVG_TH +363 0x001E //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x0064 //TX_NDETCT +367 0x04E8 //TX_NOISE_TH_0 +368 0x7FFF //TX_NOISE_TH_0_2 +369 0x7FFF //TX_NOISE_TH_0_3 +370 0x07D0 //TX_NOISE_TH_1 +371 0x0DAC //TX_NOISE_TH_2 +372 0x4E20 //TX_NOISE_TH_3 +373 0x4E20 //TX_NOISE_TH_4 +374 0x59D8 //TX_NOISE_TH_5 +375 0x7FFF //TX_NOISE_TH_5_2 +376 0x0000 //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x2710 //TX_NOISE_TH_6 +379 0x02BC //TX_MINENOISE_TH +380 0xD508 //TX_MORENS_TFMASK_TH +381 0x0001 //TX_DRC_QUIET_FLOOR +382 0x3A98 //TX_RATIODTL_CUT_TH +383 0x1482 //TX_DT_CUT_K1 +384 0x0666 //TX_OUT_ENER_S_TH_CLEAN +385 0x0666 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x0333 //TX_OUT_ENER_S_TH_NOISY +387 0x019A //TX_OUT_ENER_TH_NOISE +388 0x0333 //TX_OUT_ENER_TH_SPEECH +389 0x2000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x7FFF //TX_POST_MASK_SUP_HSNE +392 0x1388 //TX_TAIL_DET_TH +393 0x4000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0080 //TX_SUPHIGH_TH +396 0x0000 //TX_MASK_G_R +397 0x0002 //TX_EXTRA_NS_L +398 0x1800 //TX_C_POST_FLT_MASK +399 0x7FFF //TX_A_POST_FLT_WNS +400 0x0148 //TX_MIN_G_LOW300HZ +401 0x0004 //TX_MAXLEVEL_CNG +402 0x00B4 //TX_STN_NOISE_TH +403 0x4000 //TX_POST_MASK_SUP +404 0x7FFF //TX_POST_MASK_ADJUST +405 0x00C8 //TX_NS_ENOISE_MIC0_TH +406 0x04E7 //TX_MINENOISE_MIC0_TH +407 0x012C //TX_MINENOISE_MIC0_S_TH +408 0x7FFF //TX_MIN_G_CTRL_SSNS +409 0x0000 //TX_METAL_RTO_THR +410 0x4848 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x1800 //TX_RHO_UPB +415 0x0BB8 //TX_N_HOLD_HS +416 0x0050 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0100 //TX_EXTRA_GAIN_MICBLOCK +419 0x0CCD //TX_THR_STD_NSR +420 0x019A //TX_THR_STD_PLH +421 0x2AF8 //TX_N_HOLD_STD +422 0x0066 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0000 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x2EE0 //TX_SB_RTO_MEAN_TH_RUB +428 0x0000 //TX_WTA_EN_RTO_TH +429 0x0000 //TX_TOP_ENER_TH_F +430 0x0000 //TX_DESIRED_TALK_HOLDT +431 0x0800 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0010 //TX_HS_VAD_BIN +435 0x2666 //TX_THR_VAD_HS +436 0x2CCD //TX_MEAN_RTO_MIN_TH2 +437 0x0032 //TX_SILENCE_T +438 0x0000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x0000 //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x003C //TX_DOA_VAD_THR_1 +445 0x0000 //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x0000 //TX_SRC_DOA_RNG_HIGH_0B +453 0x0000 //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x0000 //TX_SRC_DOA_RNG_HIGH_0C +456 0x0000 //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x0000 //TX_SRC_DOA_RNG_HIGH_0D +459 0x0000 //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0100 //TX_BF_HOLDOFF_T +473 0x7FFF //TX_DOA_COST_FACTOR +474 0x4000 //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x012C //TX_DOA_TRACK_HT +477 0x0200 //TX_N1_HOLD_HF +478 0x0100 //TX_N2_HOLD_HF +479 0x3000 //TX_BF_RESET_THR_HF +480 0x7333 //TX_DOA_SMOOTH +481 0x0800 //TX_MU_BF +482 0x0800 //TX_BF_MU_LF_B2 +483 0x0040 //TX_BF_FC_END_BIN_B2 +484 0x0020 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0007 //TX_N_DOA_SEED +488 0x0001 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x038E //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x7FFF //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x038E //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x0230 //TX_NOR_OFF_THR +498 0x0CCD //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0000 //TX_ADAPT_LEN +501 0x2000 //TX_MORE_SNS +502 0x0000 //TX_NOR_OFF_TH1 +503 0x0000 //TX_WIDE_MASK_TH +504 0x4650 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x7FFF //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x0000 //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x0000 //TX_MICTOBFGAIN0 +513 0x0000 //TX_FASTMUE_TH +514 0xC000 //TX_DEREVERB_LF_MU +515 0xC000 //TX_DEREVERB_HF_MU +516 0xCCCC //TX_DEREVERB_DELAY +517 0xD999 //TX_DEREVERB_COEF_LEN +518 0x1F40 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x7000 //TX_GSC_RTOH_TH +523 0x0064 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x1333 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0004 //TX_SNR_THR +531 0x0010 //TX_ENGY_THR +532 0x1770 //TX_CORR_HIGH_TH +533 0x6000 //TX_ENGY_THR_2 +534 0x3400 //TX_MEAN_RTO_THR +535 0x0028 //TX_WNS_ENOISE_MIC0_TH +536 0x3000 //TX_RATIOMICL_TH +537 0x64CD //TX_CALIG_HS +538 0x0000 //TX_LVL_CTRL +539 0x0014 //TX_WIND_SUPRTO +540 0x000A //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x2800 //TX_RATIOMICH_TH +543 0xD120 //TX_WIND_INBEAM_L_TH +544 0x0FA0 //TX_WIND_INBEAM_H_TH +545 0x2000 //TX_WNS_RESRV_0 +546 0x59D8 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0070 //TX_BF_LESSCUT_BBIN +554 0x0070 //TX_BF_LESSCUT_EBIN +555 0x0010 //TX_POSTBFB0 +556 0x0070 //TX_POSTBFB +557 0x00B0 //TX_POSTBFE +558 0x0E66 //TX_SPEECH_SNR_TH +559 0x0050 //TX_PB_MAX_PRI_SNR_TH +560 0x770A //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0020 //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x484C //TX_FDEQ_GAIN_3 +571 0x4C4C //TX_FDEQ_GAIN_4 +572 0x544C //TX_FDEQ_GAIN_5 +573 0x5454 //TX_FDEQ_GAIN_6 +574 0x5454 //TX_FDEQ_GAIN_7 +575 0x585A //TX_FDEQ_GAIN_8 +576 0x5C5C //TX_FDEQ_GAIN_9 +577 0x6068 //TX_FDEQ_GAIN_10 +578 0x8894 //TX_FDEQ_GAIN_11 +579 0x94B4 //TX_FDEQ_GAIN_12 +580 0xB4C7 //TX_FDEQ_GAIN_13 +581 0xC7C6 //TX_FDEQ_GAIN_14 +582 0xC6C6 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0202 //TX_FDEQ_BIN_0 +592 0x0203 //TX_FDEQ_BIN_1 +593 0x0304 //TX_FDEQ_BIN_2 +594 0x0405 //TX_FDEQ_BIN_3 +595 0x0607 //TX_FDEQ_BIN_4 +596 0x0809 //TX_FDEQ_BIN_5 +597 0x0A0B //TX_FDEQ_BIN_6 +598 0x0C0D //TX_FDEQ_BIN_7 +599 0x0E0F //TX_FDEQ_BIN_8 +600 0x1011 //TX_FDEQ_BIN_9 +601 0x1214 //TX_FDEQ_BIN_10 +602 0x1618 //TX_FDEQ_BIN_11 +603 0x1C1C //TX_FDEQ_BIN_12 +604 0x2020 //TX_FDEQ_BIN_13 +605 0x2020 //TX_FDEQ_BIN_14 +606 0x2011 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0030 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4849 //TX_PREEQ_GAIN_MIC0_6 +624 0x4A4B //TX_PREEQ_GAIN_MIC0_7 +625 0x4C4B //TX_PREEQ_GAIN_MIC0_8 +626 0x4A48 //TX_PREEQ_GAIN_MIC0_9 +627 0x4B4C //TX_PREEQ_GAIN_MIC0_10 +628 0x4C4B //TX_PREEQ_GAIN_MIC0_11 +629 0x4838 //TX_PREEQ_GAIN_MIC0_12 +630 0x3858 //TX_PREEQ_GAIN_MIC0_13 +631 0x7060 //TX_PREEQ_GAIN_MIC0_14 +632 0x9870 //TX_PREEQ_GAIN_MIC0_15 +633 0x5848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0202 //TX_PREEQ_BIN_MIC0_0 +642 0x0203 //TX_PREEQ_BIN_MIC0_1 +643 0x0303 //TX_PREEQ_BIN_MIC0_2 +644 0x0304 //TX_PREEQ_BIN_MIC0_3 +645 0x0405 //TX_PREEQ_BIN_MIC0_4 +646 0x0506 //TX_PREEQ_BIN_MIC0_5 +647 0x0808 //TX_PREEQ_BIN_MIC0_6 +648 0x0809 //TX_PREEQ_BIN_MIC0_7 +649 0x0A0A //TX_PREEQ_BIN_MIC0_8 +650 0x0C10 //TX_PREEQ_BIN_MIC0_9 +651 0x1013 //TX_PREEQ_BIN_MIC0_10 +652 0x1414 //TX_PREEQ_BIN_MIC0_11 +653 0x261E //TX_PREEQ_BIN_MIC0_12 +654 0x1E14 //TX_PREEQ_BIN_MIC0_13 +655 0x1414 //TX_PREEQ_BIN_MIC0_14 +656 0x2814 //TX_PREEQ_BIN_MIC0_15 +657 0x4000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0030 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4645 //TX_PREEQ_GAIN_MIC1_6 +673 0x4442 //TX_PREEQ_GAIN_MIC1_7 +674 0x4140 //TX_PREEQ_GAIN_MIC1_8 +675 0x3E3D //TX_PREEQ_GAIN_MIC1_9 +676 0x3C3C //TX_PREEQ_GAIN_MIC1_10 +677 0x3C3C //TX_PREEQ_GAIN_MIC1_11 +678 0x3938 //TX_PREEQ_GAIN_MIC1_12 +679 0x3A3C //TX_PREEQ_GAIN_MIC1_13 +680 0x3C3E //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0202 //TX_PREEQ_BIN_MIC1_0 +691 0x0203 //TX_PREEQ_BIN_MIC1_1 +692 0x0303 //TX_PREEQ_BIN_MIC1_2 +693 0x0304 //TX_PREEQ_BIN_MIC1_3 +694 0x0405 //TX_PREEQ_BIN_MIC1_4 +695 0x0506 //TX_PREEQ_BIN_MIC1_5 +696 0x0808 //TX_PREEQ_BIN_MIC1_6 +697 0x0809 //TX_PREEQ_BIN_MIC1_7 +698 0x0A0A //TX_PREEQ_BIN_MIC1_8 +699 0x0C10 //TX_PREEQ_BIN_MIC1_9 +700 0x1013 //TX_PREEQ_BIN_MIC1_10 +701 0x1414 //TX_PREEQ_BIN_MIC1_11 +702 0x261E //TX_PREEQ_BIN_MIC1_12 +703 0x1E14 //TX_PREEQ_BIN_MIC1_13 +704 0x1414 //TX_PREEQ_BIN_MIC1_14 +705 0x2814 //TX_PREEQ_BIN_MIC1_15 +706 0x4000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0E10 //TX_PREEQ_BIN_MIC2_0 +740 0x1010 //TX_PREEQ_BIN_MIC2_1 +741 0x1010 //TX_PREEQ_BIN_MIC2_2 +742 0x1010 //TX_PREEQ_BIN_MIC2_3 +743 0x1010 //TX_PREEQ_BIN_MIC2_4 +744 0x1010 //TX_PREEQ_BIN_MIC2_5 +745 0x1010 //TX_PREEQ_BIN_MIC2_6 +746 0x1010 //TX_PREEQ_BIN_MIC2_7 +747 0x1010 //TX_PREEQ_BIN_MIC2_8 +748 0x1010 //TX_PREEQ_BIN_MIC2_9 +749 0x1010 //TX_PREEQ_BIN_MIC2_10 +750 0x1010 //TX_PREEQ_BIN_MIC2_11 +751 0x1010 //TX_PREEQ_BIN_MIC2_12 +752 0x1010 //TX_PREEQ_BIN_MIC2_13 +753 0x1010 //TX_PREEQ_BIN_MIC2_14 +754 0x0200 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x2000 //TX_NND_WEIGHT +765 0x0060 //TX_MIC_CALIBRATION_0 +766 0x0060 //TX_MIC_CALIBRATION_1 +767 0x0070 //TX_MIC_CALIBRATION_2 +768 0x0070 //TX_MIC_CALIBRATION_3 +769 0x0050 //TX_MIC_PWR_BIAS_0 +770 0x0040 //TX_MIC_PWR_BIAS_1 +771 0x0040 //TX_MIC_PWR_BIAS_2 +772 0x0040 //TX_MIC_PWR_BIAS_3 +773 0x0009 //TX_GAIN_LIMIT_0 +774 0x000F //TX_GAIN_LIMIT_1 +775 0x000F //TX_GAIN_LIMIT_2 +776 0x000F //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F19 //TX_BVE_NOVAD0_ALPHAUP +783 0x0C00 //TX_TDDRC_ALPHA_UP_01 +784 0x0C00 //TX_TDDRC_ALPHA_UP_02 +785 0x0C00 //TX_TDDRC_ALPHA_UP_03 +786 0x0C00 //TX_TDDRC_ALPHA_UP_04 +787 0x7EB8 //TX_TDDRC_ALPHA_DWN_01 +788 0x7EB8 //TX_TDDRC_ALPHA_DWN_02 +789 0x7EB8 //TX_TDDRC_ALPHA_DWN_03 +790 0x7EB8 //TX_TDDRC_ALPHA_DWN_04 +791 0x7214 //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0010 //TX_DEADMIC_SILENCE_TH +817 0x0600 //TX_MIC_DEGRADE_TH +818 0x0078 //TX_DEADMIC_CNT +819 0x0078 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x7FFF //TX_KS_NOISEPASTE_FACTOR +824 0x0001 //TX_KS_CONFIG +825 0x7FFF //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x4848 //TX_FFP_FP_K_METAL +834 0x4000 //TX_A_POST_FLT_FP +835 0x0F5C //TX_RTO_OUTBEAM_TH +836 0x4CCD //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0096 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0100 //TX_FFP_RESRV_2 +849 0x0020 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0002 //TX_FILTINDX +854 0x0004 //TX_TDDRC_THRD_0 +855 0x0016 //TX_TDDRC_THRD_1 +856 0x1800 //TX_TDDRC_THRD_2 +857 0x1800 //TX_TDDRC_THRD_3 +858 0x7FFF //TX_TDDRC_SLANT_0 +859 0x7FFF //TX_TDDRC_SLANT_1 +860 0x0C00 //TX_TDDRC_ALPHA_UP_00 +861 0x7EB8 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x199A //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0CCD //TX_TDDRC_SMT_W +866 0x0B39 //TX_TDDRC_DRC_GAIN +867 0x7FFF //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x0000 //TX_TFMASKLTH +870 0x0000 //TX_TFMASKLTHL +871 0x0CCD //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0xECCD //TX_TFMASKTH_BLESSCUT +876 0x1000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x7FFF //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x7333 //TX_FASTNS_OUTIN_TH +884 0x0CCD //TX_FASTNS_TFMASK_TH +885 0x0CCD //TX_FASTNS_TFMASKBIN_TH1 +886 0x0CCD //TX_FASTNS_TFMASKBIN_TH2 +887 0x0CCD //TX_FASTNS_TFMASKBIN_TH3 +888 0x0028 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x4848 //TX_POSTSSA_MIN_G_VR_MASK +891 0x7000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x2339 //TX_SENDFUNC_REG_MICMUTE +898 0x0021 //TX_SENDFUNC_REG_MICMUTE1 +899 0x02BC //TX_MICMUTE_RATIO_THR +900 0x0140 //TX_MICMUTE_AMP_THR +901 0x0004 //TX_MICMUTE_HPF_IND +902 0x00C0 //TX_MICMUTE_LOG_EYR_TH +903 0x0008 //TX_MICMUTE_CVG_TIME +904 0x0008 //TX_MICMUTE_RELEASE_TIME +905 0x01FE //TX_MIC_VOLUME_MIC0MUTE +906 0x0020 //TX_MICMUTE_EPD_OFFSET_0 +907 0x001E //TX_MICMUTE_FRQ_AEC_L +908 0x7999 //TX_MICMUTE_EAD_THR +909 0x7FFF //TX_MICMUTE_LAMBDA_CB_NLE +910 0x7FFF //TX_MICMUTE_LAMBDA_RE_EST +911 0x4000 //TX_DTD_THR1_MICMUTE_0 +912 0x7000 //TX_DTD_THR1_MICMUTE_1 +913 0x7FFF //TX_DTD_THR1_MICMUTE_2 +914 0x7FFF //TX_DTD_THR1_MICMUTE_3 +915 0x6CCC //TX_DTD_THR2_MICMUTE_0 +916 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x1000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x4000 //TX_MICMUTE_C_POST_FLT +922 0x03E8 //TX_MICMUTE_DT_CUT_K +923 0x0001 //TX_MICMUTE_DT_CUT_THR +924 0x03E8 //TX_MICMUTE_DT_CUT_K2 +925 0x0001 //TX_MICMUTE_DT_CUT_THR2 +926 0x0064 //TX_MICMUTE_DT2_HOLD_N +927 0x1000 //TX_MICMUTE_RATIODTH_THCUT +928 0x1000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x7FFF //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0400 //TX_MICMUTE_C_POST_FLT_MASK +931 0x7999 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0258 //TX_MICMUTE_DT_CUT_K1 +933 0x0800 //TX_MICMUTE_N2_SN_EST +934 0xFC00 //TX_MICMUTE_THR_SN_EST_0 +935 0x001C //TX_MICMUTE_MIN_G_CTRL_0 +936 0x6000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x7000 //TX_MICMUTE_B_POST_FILT_0 +938 0x2710 //TX_MIC1RUB_AMP_THR +939 0x0010 //TX_MIC1MUTE_RATIO_THR +940 0x0450 //TX_MIC1MUTE_AMP_THR +941 0x0008 //TX_MIC1MUTE_CVG_TIME +942 0x0008 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x2040 //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0000 //RX_SAMPLINGFREQ_SIG +3 0x0000 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +10 0x050D //RX_PGA +11 0x7652 //RX_A_HP +12 0x4000 //RX_B_PE +13 0x7800 //RX_THR_PITCH_DET_0 +14 0x7000 //RX_THR_PITCH_DET_1 +15 0x6000 //RX_THR_PITCH_DET_2 +16 0x0000 //RX_PITCH_BFR_LEN +17 0x0000 //RX_SBD_PITCH_DET +18 0x0000 //RX_PP_RESRV_0 +19 0x0000 //RX_PP_RESRV_1 +20 0xF800 //RX_N_SN_EST +21 0x0000 //RX_N2_SN_EST +22 0x000F //RX_NS_LVL_CTRL +23 0xF800 //RX_THR_SN_EST +24 0x7E00 //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0000 //RX_FENS_RESRV_1 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +30 0x0000 //RX_EXTRA_NS_L +31 0x0000 //RX_EXTRA_NS_A +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x0000 //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0003 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x0080 //RX_MIN_G_FP +128 0x2000 //RX_MAX_G_FP +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0010 //RX_MAXLEVEL_CNG +132 0x0000 //RX_BWE_UV_TH +133 0x0000 //RX_BWE_UV_TH2 +134 0x0000 //RX_BWE_UV_TH3 +135 0x0000 //RX_BWE_V_TH +136 0x0000 //RX_BWE_GAIN1_V_TH1 +137 0x0000 //RX_BWE_GAIN1_V_TH2 +138 0x0000 //RX_BWE_UV_EQ +139 0x0000 //RX_BWE_V_EQ +140 0x0000 //RX_BWE_TONE_TH +141 0x0000 //RX_BWE_UV_HOLD_T +142 0x0000 //RX_BWE_GAIN2_ALPHA +143 0x0000 //RX_BWE_GAIN3_ALPHA +144 0x0000 //RX_BWE_CUTOFF +145 0x0000 //RX_BWE_GAINFILL +146 0x0000 //RX_BWE_MAXTH_TONE +147 0x0000 //RX_BWE_EQ_0 +148 0x0000 //RX_BWE_EQ_1 +149 0x0000 //RX_BWE_EQ_2 +150 0x0000 //RX_BWE_EQ_3 +151 0x0000 //RX_BWE_EQ_4 +152 0x0000 //RX_BWE_EQ_5 +153 0x0000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x2040 //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0000 //RX_SAMPLINGFREQ_SIG +160 0x0000 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +167 0x050D //RX_PGA +168 0x7652 //RX_A_HP +169 0x4000 //RX_B_PE +170 0x7800 //RX_THR_PITCH_DET_0 +171 0x7000 //RX_THR_PITCH_DET_1 +172 0x6000 //RX_THR_PITCH_DET_2 +173 0x0000 //RX_PITCH_BFR_LEN +174 0x0000 //RX_SBD_PITCH_DET +175 0x0000 //RX_PP_RESRV_0 +176 0x0000 //RX_PP_RESRV_1 +177 0xF800 //RX_N_SN_EST +178 0x0000 //RX_N2_SN_EST +179 0x000F //RX_NS_LVL_CTRL +180 0xF800 //RX_THR_SN_EST +181 0x7E00 //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0000 //RX_FENS_RESRV_1 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +187 0x0000 //RX_EXTRA_NS_L +188 0x0000 //RX_EXTRA_NS_A +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x0000 //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0003 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x0080 //RX_MIN_G_FP +285 0x2000 //RX_MAX_G_FP +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0010 //RX_MAXLEVEL_CNG +289 0x0000 //RX_BWE_UV_TH +290 0x0000 //RX_BWE_UV_TH2 +291 0x0000 //RX_BWE_UV_TH3 +292 0x0000 //RX_BWE_V_TH +293 0x0000 //RX_BWE_GAIN1_V_TH1 +294 0x0000 //RX_BWE_GAIN1_V_TH2 +295 0x0000 //RX_BWE_UV_EQ +296 0x0000 //RX_BWE_V_EQ +297 0x0000 //RX_BWE_TONE_TH +298 0x0000 //RX_BWE_UV_HOLD_T +299 0x0000 //RX_BWE_GAIN2_ALPHA +300 0x0000 //RX_BWE_GAIN3_ALPHA +301 0x0000 //RX_BWE_CUTOFF +302 0x0000 //RX_BWE_GAINFILL +303 0x0000 //RX_BWE_MAXTH_TONE +304 0x0000 //RX_BWE_EQ_0 +305 0x0000 //RX_BWE_EQ_1 +306 0x0000 //RX_BWE_EQ_2 +307 0x0000 //RX_BWE_EQ_3 +308 0x0000 //RX_BWE_EQ_4 +309 0x0000 //RX_BWE_EQ_5 +310 0x0000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME HEADSET-TTY_FULL-VOICE_GENERIC-NB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0001 //TX_OPERATION_MODE_0 +1 0x0000 //TX_OPERATION_MODE_1 +2 0x0000 //TX_PATCH_REG +3 0x0200 //TX_SENDFUNC_MODE_0 +4 0x0000 //TX_SENDFUNC_MODE_1 +5 0x0001 //TX_NUM_MIC +6 0x0000 //TX_SAMPLINGFREQ_SIG +7 0x0000 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x0078 //TX_DIST2REF1 +22 0x0000 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0302 //TX_PGA_0 +28 0x0800 //TX_PGA_1 +29 0x0800 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0000 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0000 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0000 //TX_MICS_OF_PAIR0 +38 0x0000 //TX_MICS_OF_PAIR1 +39 0x0000 //TX_MICS_OF_PAIR2 +40 0x0000 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0001 //TX_MIC_DATA_SRC1 +43 0x0002 //TX_MIC_DATA_SRC2 +44 0x0003 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x0000 //TX_HD_BIN_MASK +53 0x0000 //TX_HD_SUBAND_MASK +54 0x0000 //TX_HD_FRAME_AVG_MASK +55 0x0000 //TX_HD_MIN_FRQ +56 0x0000 //TX_HD_ALPHA_PSD +57 0x0000 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0x0000 //TX_T_PSDVAT +63 0x0000 //TX_CNT +64 0x0000 //TX_ANTI_HOWL_GAIN +65 0x0000 //TX_MICFORBFMARK_0 +66 0x0000 //TX_MICFORBFMARK_1 +67 0x0000 //TX_MICFORBFMARK_2 +68 0x0000 //TX_MICFORBFMARK_3 +69 0x0000 //TX_MICFORBFMARK_4 +70 0x0000 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x0000 //TX_DIST2REF_11 +73 0x0000 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0800 //TX_MIC_REFBLK_VOLUME +108 0x0800 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x0000 //TX_ADCS_GAIN +112 0x0000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x7FFF //TX_BLMIC_BLKFACTOR +116 0x7FFF //TX_BRMIC_BLKFACTOR +117 0x000A //TX_MICBLK_START_BIN +118 0x0041 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0015 //TX_FENE_HOLD +123 0x0000 //TX_FE_ENER_TH_MTS +124 0x0000 //TX_FE_ENER_TH_EXP +125 0x0000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x0000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0020 //TX_MIC_BLOCK_N +128 0x7652 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x7800 //TX_THR_PITCH_DET_0 +131 0x7000 //TX_THR_PITCH_DET_1 +132 0x6000 //TX_THR_PITCH_DET_2 +133 0x0000 //TX_PITCH_BFR_LEN +134 0x0000 //TX_SBD_PITCH_DET +135 0x0000 //TX_TD_AEC_L +136 0x0000 //TX_MU0_UNP_TD_AEC +137 0x0000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x0028 //TX_TAIL_LENGTH +147 0x2000 //TX_AEC_REF_GAIN_0 +148 0x2000 //TX_AEC_REF_GAIN_1 +149 0x2000 //TX_AEC_REF_GAIN_2 +150 0x4000 //TX_EAD_THR +151 0x0200 //TX_THR_RE_EST +152 0x0100 //TX_MIN_EQ_RE_EST_0 +153 0x0100 //TX_MIN_EQ_RE_EST_1 +154 0x0100 //TX_MIN_EQ_RE_EST_2 +155 0x0100 //TX_MIN_EQ_RE_EST_3 +156 0x0100 //TX_MIN_EQ_RE_EST_4 +157 0x0100 //TX_MIN_EQ_RE_EST_5 +158 0x0100 //TX_MIN_EQ_RE_EST_6 +159 0x0100 //TX_MIN_EQ_RE_EST_7 +160 0x0100 //TX_MIN_EQ_RE_EST_8 +161 0x0100 //TX_MIN_EQ_RE_EST_9 +162 0x0100 //TX_MIN_EQ_RE_EST_10 +163 0x0100 //TX_MIN_EQ_RE_EST_11 +164 0x0100 //TX_MIN_EQ_RE_EST_12 +165 0x4000 //TX_LAMBDA_RE_EST +166 0x0000 //TX_LAMBDA_CB_NLE +167 0x0000 //TX_C_POST_FLT +168 0x4000 //TX_GAIN_NP +169 0x0008 //TX_SE_HOLD_N +170 0x0050 //TX_DT_HOLD_N +171 0x03E8 //TX_DT2_HOLD_N +172 0x0000 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x0000 //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0000 //TX_FRQ_LIN_LEN +184 0x0000 //TX_FRQ_AEC_LEN_RHO +185 0x0000 //TX_MU0_UNP_FRQ_AEC +186 0x0000 //TX_MU0_PTD_FRQ_AEC +187 0x0000 //TX_MINENOISETH +188 0x0000 //TX_MU0_RE_EST +189 0x0000 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x0000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x7333 //TX_DTD_THR1_0 +198 0x7333 //TX_DTD_THR1_1 +199 0x7333 //TX_DTD_THR1_2 +200 0x7333 //TX_DTD_THR1_3 +201 0x7333 //TX_DTD_THR1_4 +202 0x7333 //TX_DTD_THR1_5 +203 0x7333 //TX_DTD_THR1_6 +204 0x0CCD //TX_DTD_THR2_0 +205 0x0CCD //TX_DTD_THR2_1 +206 0x0CCD //TX_DTD_THR2_2 +207 0x0CCD //TX_DTD_THR2_3 +208 0x0CCD //TX_DTD_THR2_4 +209 0x0CCD //TX_DTD_THR2_5 +210 0x0CCD //TX_DTD_THR2_6 +211 0x7FFF //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x0400 //TX_DT_CUT_K +214 0x0000 //TX_DT_CUT_THR +215 0x0000 //TX_COMFORT_G +216 0x0000 //TX_POWER_YOUT_TH +217 0x0000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x0400 //TX_ADPT_STRICT_L +222 0x0200 //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x0800 //TX_B_POST_FILT_ECHO_L +229 0x0800 //TX_B_POST_FILT_ECHO_H +230 0x0000 //TX_MIN_G_CTRL_ECHO +231 0x7FFF //TX_B_LESSCUT_RTO_ECHO +232 0x0000 //TX_EPD_OFFSET_00 +233 0x0000 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x0000 //TX_MIN_EQ_RE_EST_13 +237 0x0000 //TX_DTD_THR1_7 +238 0x0000 //TX_DTD_THR2_7 +239 0x0000 //TX_DT_RESRV_7 +240 0x0000 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xFA00 //TX_THR_SN_EST_0 +243 0xF400 //TX_THR_SN_EST_1 +244 0xF800 //TX_THR_SN_EST_2 +245 0xF600 //TX_THR_SN_EST_3 +246 0xF800 //TX_THR_SN_EST_4 +247 0xF800 //TX_THR_SN_EST_5 +248 0xF800 //TX_THR_SN_EST_6 +249 0xF800 //TX_THR_SN_EST_7 +250 0x0100 //TX_DELTA_THR_SN_EST_0 +251 0x0100 //TX_DELTA_THR_SN_EST_1 +252 0x0100 //TX_DELTA_THR_SN_EST_2 +253 0x0200 //TX_DELTA_THR_SN_EST_3 +254 0x0200 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0000 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x4000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x4000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0A00 //TX_N_SN_EST +267 0x0000 //TX_INBEAM_T +268 0x0000 //TX_INBEAMHOLDT +269 0x1FFF //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x1000 //TX_NE_RTO_TH_L +274 0x1000 //TX_MAINREFRTOH_TH_H +275 0x1000 //TX_MAINREFRTOH_TH_L +276 0x2000 //TX_MAINREFRTO_TH_H +277 0x1400 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x0000 //TX_B_POST_FLT_0 +280 0x0000 //TX_B_POST_FLT_1 +281 0x001A //TX_NS_LVL_CTRL_0 +282 0x0014 //TX_NS_LVL_CTRL_1 +283 0x0014 //TX_NS_LVL_CTRL_2 +284 0x000C //TX_NS_LVL_CTRL_3 +285 0x000C //TX_NS_LVL_CTRL_4 +286 0x000C //TX_NS_LVL_CTRL_5 +287 0x001A //TX_NS_LVL_CTRL_6 +288 0x000C //TX_NS_LVL_CTRL_7 +289 0x000E //TX_MIN_GAIN_S_0 +290 0x0014 //TX_MIN_GAIN_S_1 +291 0x0014 //TX_MIN_GAIN_S_2 +292 0x0014 //TX_MIN_GAIN_S_3 +293 0x0014 //TX_MIN_GAIN_S_4 +294 0x0014 //TX_MIN_GAIN_S_5 +295 0x0014 //TX_MIN_GAIN_S_6 +296 0x0014 //TX_MIN_GAIN_S_7 +297 0x0000 //TX_NMOS_SUP +298 0x0064 //TX_NS_MAX_PRI_SNR_TH +299 0x7FFF //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x7FFF //TX_SNRI_SUP_1 +302 0x7FFF //TX_SNRI_SUP_2 +303 0x4000 //TX_SNRI_SUP_3 +304 0x4000 //TX_SNRI_SUP_4 +305 0x4000 //TX_SNRI_SUP_5 +306 0x7FFF //TX_SNRI_SUP_6 +307 0x4000 //TX_SNRI_SUP_7 +308 0x1200 //TX_THR_LFNS +309 0x0147 //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x7FFF //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x7FFF //TX_A_POST_FILT_1 +314 0x4000 //TX_A_POST_FILT_S_0 +315 0x1000 //TX_A_POST_FILT_S_1 +316 0x1000 //TX_A_POST_FILT_S_2 +317 0x6666 //TX_A_POST_FILT_S_3 +318 0x6666 //TX_A_POST_FILT_S_4 +319 0x6666 //TX_A_POST_FILT_S_5 +320 0x199A //TX_A_POST_FILT_S_6 +321 0x6666 //TX_A_POST_FILT_S_7 +322 0x2000 //TX_B_POST_FILT_0 +323 0x2000 //TX_B_POST_FILT_1 +324 0x2000 //TX_B_POST_FILT_2 +325 0x2000 //TX_B_POST_FILT_3 +326 0x2000 //TX_B_POST_FILT_4 +327 0x2000 //TX_B_POST_FILT_5 +328 0x2000 //TX_B_POST_FILT_6 +329 0x2000 //TX_B_POST_FILT_7 +330 0x7FFF //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x7FFF //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7E00 //TX_LAMBDA_PFILT +339 0x7E00 //TX_LAMBDA_PFILT_S_0 +340 0x7E00 //TX_LAMBDA_PFILT_S_1 +341 0x7E00 //TX_LAMBDA_PFILT_S_2 +342 0x7E00 //TX_LAMBDA_PFILT_S_3 +343 0x7E00 //TX_LAMBDA_PFILT_S_4 +344 0x7E00 //TX_LAMBDA_PFILT_S_5 +345 0x7E00 //TX_LAMBDA_PFILT_S_6 +346 0x7E00 //TX_LAMBDA_PFILT_S_7 +347 0x0010 //TX_K_PEPPER +348 0x0400 //TX_A_PEPPER +349 0x0000 //TX_K_PEPPER_HF +350 0x0000 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x4000 //TX_HMNC_BST_THR +353 0x0000 //TX_DT_BINVAD_TH_0 +354 0x0000 //TX_DT_BINVAD_TH_1 +355 0x0000 //TX_DT_BINVAD_TH_2 +356 0x0000 //TX_DT_BINVAD_TH_3 +357 0x0000 //TX_DT_BINVAD_ENDF +358 0x0000 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0001 //TX_BF_SGRAD_FLG +362 0x0000 //TX_BF_DVG_TH +363 0x0000 //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x05A0 //TX_NDETCT +367 0x003B //TX_NOISE_TH_0 +368 0x1388 //TX_NOISE_TH_0_2 +369 0x3A98 //TX_NOISE_TH_0_3 +370 0x0C80 //TX_NOISE_TH_1 +371 0x0032 //TX_NOISE_TH_2 +372 0x3D54 //TX_NOISE_TH_3 +373 0x012C //TX_NOISE_TH_4 +374 0x07D0 //TX_NOISE_TH_5 +375 0x6590 //TX_NOISE_TH_5_2 +376 0x7FFF //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x00C8 //TX_NOISE_TH_6 +379 0x00C8 //TX_MINENOISE_TH +380 0xD508 //TX_MORENS_TFMASK_TH +381 0x0001 //TX_DRC_QUIET_FLOOR +382 0x3A98 //TX_RATIODTL_CUT_TH +383 0x0DAC //TX_DT_CUT_K1 +384 0x6400 //TX_OUT_ENER_S_TH_CLEAN +385 0x6400 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x6400 //TX_OUT_ENER_S_TH_NOISY +387 0x6400 //TX_OUT_ENER_TH_NOISE +388 0x7D00 //TX_OUT_ENER_TH_SPEECH +389 0x0000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x7FFF //TX_POST_MASK_SUP_HSNE +392 0x1388 //TX_TAIL_DET_TH +393 0x4000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0080 //TX_SUPHIGH_TH +396 0x0000 //TX_MASK_G_R +397 0x0000 //TX_EXTRA_NS_L +398 0x1800 //TX_C_POST_FLT_MASK +399 0x7FFF //TX_A_POST_FLT_WNS +400 0x0000 //TX_MIN_G_LOW300HZ +401 0x0010 //TX_MAXLEVEL_CNG +402 0x0000 //TX_STN_NOISE_TH +403 0x0000 //TX_POST_MASK_SUP +404 0x0000 //TX_POST_MASK_ADJUST +405 0x0014 //TX_NS_ENOISE_MIC0_TH +406 0x0032 //TX_MINENOISE_MIC0_TH +407 0x0226 //TX_MINENOISE_MIC0_S_TH +408 0x2879 //TX_MIN_G_CTRL_SSNS +409 0x0400 //TX_METAL_RTO_THR +410 0x0080 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x2000 //TX_RHO_UPB +415 0x0020 //TX_N_HOLD_HS +416 0x0009 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0000 //TX_EXTRA_GAIN_MICBLOCK +419 0x0333 //TX_THR_STD_NSR +420 0x0219 //TX_THR_STD_PLH +421 0x09C4 //TX_N_HOLD_STD +422 0x0166 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0800 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x0000 //TX_SB_RTO_MEAN_TH_RUB +428 0x2000 //TX_WTA_EN_RTO_TH +429 0x1400 //TX_TOP_ENER_TH_F +430 0x0064 //TX_DESIRED_TALK_HOLDT +431 0x1000 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0000 //TX_HS_VAD_BIN +435 0x0000 //TX_THR_VAD_HS +436 0x0000 //TX_MEAN_RTO_MIN_TH2 +437 0x0000 //TX_SILENCE_T +438 0x4000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x099A //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x001E //TX_DOA_VAD_THR_1 +445 0x001E //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x00B4 //TX_SRC_DOA_RNG_HIGH_0B +453 0x005A //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x00B4 //TX_SRC_DOA_RNG_HIGH_0C +456 0x005A //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x00B4 //TX_SRC_DOA_RNG_HIGH_0D +459 0x005A //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0172 //TX_BF_HOLDOFF_T +473 0x8000 //TX_DOA_COST_FACTOR +474 0x0D9A //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x071C //TX_DOA_TRACK_HT +477 0x0280 //TX_N1_HOLD_HF +478 0x0140 //TX_N2_HOLD_HF +479 0x2AAB //TX_BF_RESET_THR_HF +480 0x4000 //TX_DOA_SMOOTH +481 0x0000 //TX_MU_BF +482 0x0200 //TX_BF_MU_LF_B2 +483 0x0000 //TX_BF_FC_END_BIN_B2 +484 0x0000 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0000 //TX_N_DOA_SEED +488 0x0000 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x0000 //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x0000 //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x0000 //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x0168 //TX_NOR_OFF_THR +498 0x0CCD //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0004 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0230 //TX_NOR_OFF_TH1 +503 0xD333 //TX_WIDE_MASK_TH +504 0x4650 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x6000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x000A //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x6666 //TX_MICTOBFGAIN0 +513 0x0014 //TX_FASTMUE_TH +514 0xC000 //TX_DEREVERB_LF_MU +515 0xC000 //TX_DEREVERB_HF_MU +516 0xCCCC //TX_DEREVERB_DELAY +517 0xD999 //TX_DEREVERB_COEF_LEN +518 0x1F40 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x7000 //TX_GSC_RTOH_TH +523 0x0064 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x0000 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0028 //TX_SNR_THR +531 0x03E8 //TX_ENGY_THR +532 0x0000 //TX_CORR_HIGH_TH +533 0x0000 //TX_ENGY_THR_2 +534 0x0000 //TX_MEAN_RTO_THR +535 0x0000 //TX_WNS_ENOISE_MIC0_TH +536 0x0000 //TX_RATIOMICL_TH +537 0x0000 //TX_CALIG_HS +538 0x000A //TX_LVL_CTRL +539 0x0000 //TX_WIND_SUPRTO +540 0x0000 //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x0000 //TX_RATIOMICH_TH +543 0x0000 //TX_WIND_INBEAM_L_TH +544 0x0000 //TX_WIND_INBEAM_H_TH +545 0x0000 //TX_WNS_RESRV_0 +546 0x0000 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0000 //TX_BF_LESSCUT_BBIN +554 0x0000 //TX_BF_LESSCUT_EBIN +555 0x0000 //TX_POSTBFB0 +556 0x0000 //TX_POSTBFB +557 0x0000 //TX_POSTBFE +558 0x0000 //TX_SPEECH_SNR_TH +559 0x0000 //TX_PB_MAX_PRI_SNR_TH +560 0x0000 //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0020 //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4848 //TX_FDEQ_GAIN_5 +573 0x4848 //TX_FDEQ_GAIN_6 +574 0x4848 //TX_FDEQ_GAIN_7 +575 0x4848 //TX_FDEQ_GAIN_8 +576 0x4848 //TX_FDEQ_GAIN_9 +577 0x4848 //TX_FDEQ_GAIN_10 +578 0x4848 //TX_FDEQ_GAIN_11 +579 0x4848 //TX_FDEQ_GAIN_12 +580 0x4848 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0000 //TX_FDEQ_BIN_0 +592 0x0000 //TX_FDEQ_BIN_1 +593 0x0000 //TX_FDEQ_BIN_2 +594 0x0000 //TX_FDEQ_BIN_3 +595 0x0000 //TX_FDEQ_BIN_4 +596 0x0000 //TX_FDEQ_BIN_5 +597 0x0000 //TX_FDEQ_BIN_6 +598 0x0000 //TX_FDEQ_BIN_7 +599 0x0000 //TX_FDEQ_BIN_8 +600 0x0000 //TX_FDEQ_BIN_9 +601 0x0000 //TX_FDEQ_BIN_10 +602 0x0000 //TX_FDEQ_BIN_11 +603 0x0000 //TX_FDEQ_BIN_12 +604 0x0000 //TX_FDEQ_BIN_13 +605 0x0000 //TX_FDEQ_BIN_14 +606 0x0000 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4848 //TX_PREEQ_GAIN_MIC0_8 +626 0x4848 //TX_PREEQ_GAIN_MIC0_9 +627 0x4848 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0000 //TX_PREEQ_BIN_MIC0_0 +642 0x0000 //TX_PREEQ_BIN_MIC0_1 +643 0x0000 //TX_PREEQ_BIN_MIC0_2 +644 0x0000 //TX_PREEQ_BIN_MIC0_3 +645 0x0000 //TX_PREEQ_BIN_MIC0_4 +646 0x0000 //TX_PREEQ_BIN_MIC0_5 +647 0x0000 //TX_PREEQ_BIN_MIC0_6 +648 0x0000 //TX_PREEQ_BIN_MIC0_7 +649 0x0000 //TX_PREEQ_BIN_MIC0_8 +650 0x0000 //TX_PREEQ_BIN_MIC0_9 +651 0x0000 //TX_PREEQ_BIN_MIC0_10 +652 0x0000 //TX_PREEQ_BIN_MIC0_11 +653 0x0000 //TX_PREEQ_BIN_MIC0_12 +654 0x0000 //TX_PREEQ_BIN_MIC0_13 +655 0x0000 //TX_PREEQ_BIN_MIC0_14 +656 0x0000 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0000 //TX_PREEQ_BIN_MIC1_0 +691 0x0000 //TX_PREEQ_BIN_MIC1_1 +692 0x0000 //TX_PREEQ_BIN_MIC1_2 +693 0x0000 //TX_PREEQ_BIN_MIC1_3 +694 0x0000 //TX_PREEQ_BIN_MIC1_4 +695 0x0000 //TX_PREEQ_BIN_MIC1_5 +696 0x0000 //TX_PREEQ_BIN_MIC1_6 +697 0x0000 //TX_PREEQ_BIN_MIC1_7 +698 0x0000 //TX_PREEQ_BIN_MIC1_8 +699 0x0000 //TX_PREEQ_BIN_MIC1_9 +700 0x0000 //TX_PREEQ_BIN_MIC1_10 +701 0x0000 //TX_PREEQ_BIN_MIC1_11 +702 0x0000 //TX_PREEQ_BIN_MIC1_12 +703 0x0000 //TX_PREEQ_BIN_MIC1_13 +704 0x0000 //TX_PREEQ_BIN_MIC1_14 +705 0x0000 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0000 //TX_PREEQ_BIN_MIC2_0 +740 0x0000 //TX_PREEQ_BIN_MIC2_1 +741 0x0000 //TX_PREEQ_BIN_MIC2_2 +742 0x0000 //TX_PREEQ_BIN_MIC2_3 +743 0x0000 //TX_PREEQ_BIN_MIC2_4 +744 0x0000 //TX_PREEQ_BIN_MIC2_5 +745 0x0000 //TX_PREEQ_BIN_MIC2_6 +746 0x0000 //TX_PREEQ_BIN_MIC2_7 +747 0x0000 //TX_PREEQ_BIN_MIC2_8 +748 0x0000 //TX_PREEQ_BIN_MIC2_9 +749 0x0000 //TX_PREEQ_BIN_MIC2_10 +750 0x0000 //TX_PREEQ_BIN_MIC2_11 +751 0x0000 //TX_PREEQ_BIN_MIC2_12 +752 0x0000 //TX_PREEQ_BIN_MIC2_13 +753 0x0000 //TX_PREEQ_BIN_MIC2_14 +754 0x0000 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x2000 //TX_NND_WEIGHT +765 0x0064 //TX_MIC_CALIBRATION_0 +766 0x006A //TX_MIC_CALIBRATION_1 +767 0x006A //TX_MIC_CALIBRATION_2 +768 0x006B //TX_MIC_CALIBRATION_3 +769 0x0048 //TX_MIC_PWR_BIAS_0 +770 0x003C //TX_MIC_PWR_BIAS_1 +771 0x003C //TX_MIC_PWR_BIAS_2 +772 0x003C //TX_MIC_PWR_BIAS_3 +773 0x0000 //TX_GAIN_LIMIT_0 +774 0x0009 //TX_GAIN_LIMIT_1 +775 0x000C //TX_GAIN_LIMIT_2 +776 0x000F //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F3D //TX_BVE_NOVAD0_ALPHAUP +783 0x3000 //TX_TDDRC_ALPHA_UP_01 +784 0x3000 //TX_TDDRC_ALPHA_UP_02 +785 0x3000 //TX_TDDRC_ALPHA_UP_03 +786 0x3000 //TX_TDDRC_ALPHA_UP_04 +787 0x7FB0 //TX_TDDRC_ALPHA_DWN_01 +788 0x7FB0 //TX_TDDRC_ALPHA_DWN_02 +789 0x7FB0 //TX_TDDRC_ALPHA_DWN_03 +790 0x7FB0 //TX_TDDRC_ALPHA_DWN_04 +791 0x65AD //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0002 //TX_DEADMIC_SILENCE_TH +817 0x0147 //TX_MIC_DEGRADE_TH +818 0x0078 //TX_DEADMIC_CNT +819 0x0078 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x0000 //TX_KS_NOISEPASTE_FACTOR +824 0x0000 //TX_KS_CONFIG +825 0x0000 //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x0000 //TX_FFP_FP_K_METAL +834 0x0000 //TX_A_POST_FLT_FP +835 0x0000 //TX_RTO_OUTBEAM_TH +836 0x0000 //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0000 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0000 //TX_FFP_RESRV_2 +849 0x0000 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0002 //TX_FILTINDX +854 0x0000 //TX_TDDRC_THRD_0 +855 0x0000 //TX_TDDRC_THRD_1 +856 0x0E80 //TX_TDDRC_THRD_2 +857 0x3800 //TX_TDDRC_THRD_3 +858 0x2A00 //TX_TDDRC_SLANT_0 +859 0x6E00 //TX_TDDRC_SLANT_1 +860 0x3000 //TX_TDDRC_ALPHA_UP_00 +861 0x7FB0 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x0000 //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0000 //TX_TDDRC_SMT_W +866 0x0100 //TX_TDDRC_DRC_GAIN +867 0x0000 //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x1EB8 //TX_TFMASKLTH +870 0x170A //TX_TFMASKLTHL +871 0x7FFF //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0x0CCD //TX_TFMASKTH_BLESSCUT +876 0x4000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x0000 //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x0000 //TX_FASTNS_OUTIN_TH +884 0x0000 //TX_FASTNS_TFMASK_TH +885 0x0000 //TX_FASTNS_TFMASKBIN_TH1 +886 0x0000 //TX_FASTNS_TFMASKBIN_TH2 +887 0x0000 //TX_FASTNS_TFMASKBIN_TH3 +888 0x00C8 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x051F //TX_POSTSSA_MIN_G_VR_MASK +891 0x4000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x2339 //TX_SENDFUNC_REG_MICMUTE +898 0x0021 //TX_SENDFUNC_REG_MICMUTE1 +899 0x02BC //TX_MICMUTE_RATIO_THR +900 0x0140 //TX_MICMUTE_AMP_THR +901 0x0004 //TX_MICMUTE_HPF_IND +902 0x00C0 //TX_MICMUTE_LOG_EYR_TH +903 0x0008 //TX_MICMUTE_CVG_TIME +904 0x0008 //TX_MICMUTE_RELEASE_TIME +905 0x01FE //TX_MIC_VOLUME_MIC0MUTE +906 0x0020 //TX_MICMUTE_EPD_OFFSET_0 +907 0x001E //TX_MICMUTE_FRQ_AEC_L +908 0x7999 //TX_MICMUTE_EAD_THR +909 0x7FFF //TX_MICMUTE_LAMBDA_CB_NLE +910 0x7FFF //TX_MICMUTE_LAMBDA_RE_EST +911 0x4000 //TX_DTD_THR1_MICMUTE_0 +912 0x7000 //TX_DTD_THR1_MICMUTE_1 +913 0x7FFF //TX_DTD_THR1_MICMUTE_2 +914 0x7FFF //TX_DTD_THR1_MICMUTE_3 +915 0x6CCC //TX_DTD_THR2_MICMUTE_0 +916 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x1000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x4000 //TX_MICMUTE_C_POST_FLT +922 0x03E8 //TX_MICMUTE_DT_CUT_K +923 0x0001 //TX_MICMUTE_DT_CUT_THR +924 0x03E8 //TX_MICMUTE_DT_CUT_K2 +925 0x0001 //TX_MICMUTE_DT_CUT_THR2 +926 0x0064 //TX_MICMUTE_DT2_HOLD_N +927 0x1000 //TX_MICMUTE_RATIODTH_THCUT +928 0x1000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x7FFF //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0400 //TX_MICMUTE_C_POST_FLT_MASK +931 0x7999 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0258 //TX_MICMUTE_DT_CUT_K1 +933 0x0800 //TX_MICMUTE_N2_SN_EST +934 0xFC00 //TX_MICMUTE_THR_SN_EST_0 +935 0x001C //TX_MICMUTE_MIN_G_CTRL_0 +936 0x6000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x7000 //TX_MICMUTE_B_POST_FILT_0 +938 0x2710 //TX_MIC1RUB_AMP_THR +939 0x0010 //TX_MIC1MUTE_RATIO_THR +940 0x0450 //TX_MIC1MUTE_AMP_THR +941 0x0008 //TX_MIC1MUTE_CVG_TIME +942 0x0008 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x2040 //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0000 //RX_SAMPLINGFREQ_SIG +3 0x0000 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +10 0x050D //RX_PGA +11 0x7652 //RX_A_HP +12 0x4000 //RX_B_PE +13 0x7800 //RX_THR_PITCH_DET_0 +14 0x7000 //RX_THR_PITCH_DET_1 +15 0x6000 //RX_THR_PITCH_DET_2 +16 0x0000 //RX_PITCH_BFR_LEN +17 0x0000 //RX_SBD_PITCH_DET +18 0x0000 //RX_PP_RESRV_0 +19 0x0000 //RX_PP_RESRV_1 +20 0xF800 //RX_N_SN_EST +21 0x0000 //RX_N2_SN_EST +22 0x000F //RX_NS_LVL_CTRL +23 0xF800 //RX_THR_SN_EST +24 0x7E00 //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0000 //RX_FENS_RESRV_1 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +30 0x0000 //RX_EXTRA_NS_L +31 0x0000 //RX_EXTRA_NS_A +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x0000 //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0003 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x0080 //RX_MIN_G_FP +128 0x2000 //RX_MAX_G_FP +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0010 //RX_MAXLEVEL_CNG +132 0x0000 //RX_BWE_UV_TH +133 0x0000 //RX_BWE_UV_TH2 +134 0x0000 //RX_BWE_UV_TH3 +135 0x0000 //RX_BWE_V_TH +136 0x0000 //RX_BWE_GAIN1_V_TH1 +137 0x0000 //RX_BWE_GAIN1_V_TH2 +138 0x0000 //RX_BWE_UV_EQ +139 0x0000 //RX_BWE_V_EQ +140 0x0000 //RX_BWE_TONE_TH +141 0x0000 //RX_BWE_UV_HOLD_T +142 0x0000 //RX_BWE_GAIN2_ALPHA +143 0x0000 //RX_BWE_GAIN3_ALPHA +144 0x0000 //RX_BWE_CUTOFF +145 0x0000 //RX_BWE_GAINFILL +146 0x0000 //RX_BWE_MAXTH_TONE +147 0x0000 //RX_BWE_EQ_0 +148 0x0000 //RX_BWE_EQ_1 +149 0x0000 //RX_BWE_EQ_2 +150 0x0000 //RX_BWE_EQ_3 +151 0x0000 //RX_BWE_EQ_4 +152 0x0000 //RX_BWE_EQ_5 +153 0x0000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x2040 //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0000 //RX_SAMPLINGFREQ_SIG +160 0x0000 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +167 0x050D //RX_PGA +168 0x7652 //RX_A_HP +169 0x4000 //RX_B_PE +170 0x7800 //RX_THR_PITCH_DET_0 +171 0x7000 //RX_THR_PITCH_DET_1 +172 0x6000 //RX_THR_PITCH_DET_2 +173 0x0000 //RX_PITCH_BFR_LEN +174 0x0000 //RX_SBD_PITCH_DET +175 0x0000 //RX_PP_RESRV_0 +176 0x0000 //RX_PP_RESRV_1 +177 0xF800 //RX_N_SN_EST +178 0x0000 //RX_N2_SN_EST +179 0x000F //RX_NS_LVL_CTRL +180 0xF800 //RX_THR_SN_EST +181 0x7E00 //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0000 //RX_FENS_RESRV_1 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +187 0x0000 //RX_EXTRA_NS_L +188 0x0000 //RX_EXTRA_NS_A +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x0000 //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0003 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x0080 //RX_MIN_G_FP +285 0x2000 //RX_MAX_G_FP +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0010 //RX_MAXLEVEL_CNG +289 0x0000 //RX_BWE_UV_TH +290 0x0000 //RX_BWE_UV_TH2 +291 0x0000 //RX_BWE_UV_TH3 +292 0x0000 //RX_BWE_V_TH +293 0x0000 //RX_BWE_GAIN1_V_TH1 +294 0x0000 //RX_BWE_GAIN1_V_TH2 +295 0x0000 //RX_BWE_UV_EQ +296 0x0000 //RX_BWE_V_EQ +297 0x0000 //RX_BWE_TONE_TH +298 0x0000 //RX_BWE_UV_HOLD_T +299 0x0000 //RX_BWE_GAIN2_ALPHA +300 0x0000 //RX_BWE_GAIN3_ALPHA +301 0x0000 //RX_BWE_CUTOFF +302 0x0000 //RX_BWE_GAINFILL +303 0x0000 //RX_BWE_MAXTH_TONE +304 0x0000 //RX_BWE_EQ_0 +305 0x0000 //RX_BWE_EQ_1 +306 0x0000 //RX_BWE_EQ_2 +307 0x0000 //RX_BWE_EQ_3 +308 0x0000 //RX_BWE_EQ_4 +309 0x0000 //RX_BWE_EQ_5 +310 0x0000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME HEADSET-TTY_FULL-VOICE_GENERIC-WB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0001 //TX_OPERATION_MODE_0 +1 0x0000 //TX_OPERATION_MODE_1 +2 0x0000 //TX_PATCH_REG +3 0x0200 //TX_SENDFUNC_MODE_0 +4 0x0000 //TX_SENDFUNC_MODE_1 +5 0x0001 //TX_NUM_MIC +6 0x0000 //TX_SAMPLINGFREQ_SIG +7 0x0000 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x0078 //TX_DIST2REF1 +22 0x0000 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0302 //TX_PGA_0 +28 0x0800 //TX_PGA_1 +29 0x0800 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0000 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0000 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0000 //TX_MICS_OF_PAIR0 +38 0x0000 //TX_MICS_OF_PAIR1 +39 0x0000 //TX_MICS_OF_PAIR2 +40 0x0000 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0001 //TX_MIC_DATA_SRC1 +43 0x0002 //TX_MIC_DATA_SRC2 +44 0x0003 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x0000 //TX_HD_BIN_MASK +53 0x0000 //TX_HD_SUBAND_MASK +54 0x0000 //TX_HD_FRAME_AVG_MASK +55 0x0000 //TX_HD_MIN_FRQ +56 0x0000 //TX_HD_ALPHA_PSD +57 0x0000 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0x0000 //TX_T_PSDVAT +63 0x0000 //TX_CNT +64 0x0000 //TX_ANTI_HOWL_GAIN +65 0x0000 //TX_MICFORBFMARK_0 +66 0x0000 //TX_MICFORBFMARK_1 +67 0x0000 //TX_MICFORBFMARK_2 +68 0x0000 //TX_MICFORBFMARK_3 +69 0x0000 //TX_MICFORBFMARK_4 +70 0x0000 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x0000 //TX_DIST2REF_11 +73 0x0000 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0800 //TX_MIC_REFBLK_VOLUME +108 0x0800 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x0000 //TX_ADCS_GAIN +112 0x0000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x7FFF //TX_BLMIC_BLKFACTOR +116 0x7FFF //TX_BRMIC_BLKFACTOR +117 0x000A //TX_MICBLK_START_BIN +118 0x0041 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0015 //TX_FENE_HOLD +123 0x0000 //TX_FE_ENER_TH_MTS +124 0x0000 //TX_FE_ENER_TH_EXP +125 0x0000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x0000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0020 //TX_MIC_BLOCK_N +128 0x7652 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x7800 //TX_THR_PITCH_DET_0 +131 0x7000 //TX_THR_PITCH_DET_1 +132 0x6000 //TX_THR_PITCH_DET_2 +133 0x0000 //TX_PITCH_BFR_LEN +134 0x0000 //TX_SBD_PITCH_DET +135 0x0000 //TX_TD_AEC_L +136 0x0000 //TX_MU0_UNP_TD_AEC +137 0x0000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x0028 //TX_TAIL_LENGTH +147 0x2000 //TX_AEC_REF_GAIN_0 +148 0x2000 //TX_AEC_REF_GAIN_1 +149 0x2000 //TX_AEC_REF_GAIN_2 +150 0x4000 //TX_EAD_THR +151 0x0200 //TX_THR_RE_EST +152 0x0100 //TX_MIN_EQ_RE_EST_0 +153 0x0100 //TX_MIN_EQ_RE_EST_1 +154 0x0100 //TX_MIN_EQ_RE_EST_2 +155 0x0100 //TX_MIN_EQ_RE_EST_3 +156 0x0100 //TX_MIN_EQ_RE_EST_4 +157 0x0100 //TX_MIN_EQ_RE_EST_5 +158 0x0100 //TX_MIN_EQ_RE_EST_6 +159 0x0100 //TX_MIN_EQ_RE_EST_7 +160 0x0100 //TX_MIN_EQ_RE_EST_8 +161 0x0100 //TX_MIN_EQ_RE_EST_9 +162 0x0100 //TX_MIN_EQ_RE_EST_10 +163 0x0100 //TX_MIN_EQ_RE_EST_11 +164 0x0100 //TX_MIN_EQ_RE_EST_12 +165 0x4000 //TX_LAMBDA_RE_EST +166 0x0000 //TX_LAMBDA_CB_NLE +167 0x0000 //TX_C_POST_FLT +168 0x4000 //TX_GAIN_NP +169 0x0008 //TX_SE_HOLD_N +170 0x0050 //TX_DT_HOLD_N +171 0x03E8 //TX_DT2_HOLD_N +172 0x0000 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x0000 //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0000 //TX_FRQ_LIN_LEN +184 0x0000 //TX_FRQ_AEC_LEN_RHO +185 0x0000 //TX_MU0_UNP_FRQ_AEC +186 0x0000 //TX_MU0_PTD_FRQ_AEC +187 0x0000 //TX_MINENOISETH +188 0x0000 //TX_MU0_RE_EST +189 0x0000 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x0000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x7333 //TX_DTD_THR1_0 +198 0x7333 //TX_DTD_THR1_1 +199 0x7333 //TX_DTD_THR1_2 +200 0x7333 //TX_DTD_THR1_3 +201 0x7333 //TX_DTD_THR1_4 +202 0x7333 //TX_DTD_THR1_5 +203 0x7333 //TX_DTD_THR1_6 +204 0x0CCD //TX_DTD_THR2_0 +205 0x0CCD //TX_DTD_THR2_1 +206 0x0CCD //TX_DTD_THR2_2 +207 0x0CCD //TX_DTD_THR2_3 +208 0x0CCD //TX_DTD_THR2_4 +209 0x0CCD //TX_DTD_THR2_5 +210 0x0CCD //TX_DTD_THR2_6 +211 0x7FFF //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x0400 //TX_DT_CUT_K +214 0x0000 //TX_DT_CUT_THR +215 0x0000 //TX_COMFORT_G +216 0x0000 //TX_POWER_YOUT_TH +217 0x0000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x0400 //TX_ADPT_STRICT_L +222 0x0200 //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x0800 //TX_B_POST_FILT_ECHO_L +229 0x0800 //TX_B_POST_FILT_ECHO_H +230 0x0000 //TX_MIN_G_CTRL_ECHO +231 0x7FFF //TX_B_LESSCUT_RTO_ECHO +232 0x0000 //TX_EPD_OFFSET_00 +233 0x0000 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x0000 //TX_MIN_EQ_RE_EST_13 +237 0x0000 //TX_DTD_THR1_7 +238 0x0000 //TX_DTD_THR2_7 +239 0x0000 //TX_DT_RESRV_7 +240 0x0000 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xFA00 //TX_THR_SN_EST_0 +243 0xF400 //TX_THR_SN_EST_1 +244 0xF800 //TX_THR_SN_EST_2 +245 0xF600 //TX_THR_SN_EST_3 +246 0xF800 //TX_THR_SN_EST_4 +247 0xF800 //TX_THR_SN_EST_5 +248 0xF800 //TX_THR_SN_EST_6 +249 0xF800 //TX_THR_SN_EST_7 +250 0x0100 //TX_DELTA_THR_SN_EST_0 +251 0x0100 //TX_DELTA_THR_SN_EST_1 +252 0x0100 //TX_DELTA_THR_SN_EST_2 +253 0x0200 //TX_DELTA_THR_SN_EST_3 +254 0x0200 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0000 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x4000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x4000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0A00 //TX_N_SN_EST +267 0x0000 //TX_INBEAM_T +268 0x0000 //TX_INBEAMHOLDT +269 0x1FFF //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x1000 //TX_NE_RTO_TH_L +274 0x1000 //TX_MAINREFRTOH_TH_H +275 0x1000 //TX_MAINREFRTOH_TH_L +276 0x2000 //TX_MAINREFRTO_TH_H +277 0x1400 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x0000 //TX_B_POST_FLT_0 +280 0x0000 //TX_B_POST_FLT_1 +281 0x001A //TX_NS_LVL_CTRL_0 +282 0x0014 //TX_NS_LVL_CTRL_1 +283 0x0014 //TX_NS_LVL_CTRL_2 +284 0x000C //TX_NS_LVL_CTRL_3 +285 0x000C //TX_NS_LVL_CTRL_4 +286 0x000C //TX_NS_LVL_CTRL_5 +287 0x001A //TX_NS_LVL_CTRL_6 +288 0x000C //TX_NS_LVL_CTRL_7 +289 0x000E //TX_MIN_GAIN_S_0 +290 0x0014 //TX_MIN_GAIN_S_1 +291 0x0014 //TX_MIN_GAIN_S_2 +292 0x0014 //TX_MIN_GAIN_S_3 +293 0x0014 //TX_MIN_GAIN_S_4 +294 0x0014 //TX_MIN_GAIN_S_5 +295 0x0014 //TX_MIN_GAIN_S_6 +296 0x0014 //TX_MIN_GAIN_S_7 +297 0x0000 //TX_NMOS_SUP +298 0x0064 //TX_NS_MAX_PRI_SNR_TH +299 0x7FFF //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x7FFF //TX_SNRI_SUP_1 +302 0x7FFF //TX_SNRI_SUP_2 +303 0x4000 //TX_SNRI_SUP_3 +304 0x4000 //TX_SNRI_SUP_4 +305 0x4000 //TX_SNRI_SUP_5 +306 0x7FFF //TX_SNRI_SUP_6 +307 0x4000 //TX_SNRI_SUP_7 +308 0x1200 //TX_THR_LFNS +309 0x0147 //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x7FFF //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x7FFF //TX_A_POST_FILT_1 +314 0x4000 //TX_A_POST_FILT_S_0 +315 0x1000 //TX_A_POST_FILT_S_1 +316 0x1000 //TX_A_POST_FILT_S_2 +317 0x6666 //TX_A_POST_FILT_S_3 +318 0x6666 //TX_A_POST_FILT_S_4 +319 0x6666 //TX_A_POST_FILT_S_5 +320 0x199A //TX_A_POST_FILT_S_6 +321 0x6666 //TX_A_POST_FILT_S_7 +322 0x2000 //TX_B_POST_FILT_0 +323 0x2000 //TX_B_POST_FILT_1 +324 0x2000 //TX_B_POST_FILT_2 +325 0x2000 //TX_B_POST_FILT_3 +326 0x2000 //TX_B_POST_FILT_4 +327 0x2000 //TX_B_POST_FILT_5 +328 0x2000 //TX_B_POST_FILT_6 +329 0x2000 //TX_B_POST_FILT_7 +330 0x7FFF //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x7FFF //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7E00 //TX_LAMBDA_PFILT +339 0x7E00 //TX_LAMBDA_PFILT_S_0 +340 0x7E00 //TX_LAMBDA_PFILT_S_1 +341 0x7E00 //TX_LAMBDA_PFILT_S_2 +342 0x7E00 //TX_LAMBDA_PFILT_S_3 +343 0x7E00 //TX_LAMBDA_PFILT_S_4 +344 0x7E00 //TX_LAMBDA_PFILT_S_5 +345 0x7E00 //TX_LAMBDA_PFILT_S_6 +346 0x7E00 //TX_LAMBDA_PFILT_S_7 +347 0x0010 //TX_K_PEPPER +348 0x0400 //TX_A_PEPPER +349 0x0000 //TX_K_PEPPER_HF +350 0x0000 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x4000 //TX_HMNC_BST_THR +353 0x0000 //TX_DT_BINVAD_TH_0 +354 0x0000 //TX_DT_BINVAD_TH_1 +355 0x0000 //TX_DT_BINVAD_TH_2 +356 0x0000 //TX_DT_BINVAD_TH_3 +357 0x0000 //TX_DT_BINVAD_ENDF +358 0x0000 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0001 //TX_BF_SGRAD_FLG +362 0x0000 //TX_BF_DVG_TH +363 0x0000 //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x05A0 //TX_NDETCT +367 0x0102 //TX_NOISE_TH_0 +368 0x1388 //TX_NOISE_TH_0_2 +369 0x3A98 //TX_NOISE_TH_0_3 +370 0x0C80 //TX_NOISE_TH_1 +371 0x0032 //TX_NOISE_TH_2 +372 0x3D54 //TX_NOISE_TH_3 +373 0x012C //TX_NOISE_TH_4 +374 0x07D0 //TX_NOISE_TH_5 +375 0x6590 //TX_NOISE_TH_5_2 +376 0x7FFF //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x00C8 //TX_NOISE_TH_6 +379 0x00F8 //TX_MINENOISE_TH +380 0xD508 //TX_MORENS_TFMASK_TH +381 0x0001 //TX_DRC_QUIET_FLOOR +382 0x3A98 //TX_RATIODTL_CUT_TH +383 0x0DAC //TX_DT_CUT_K1 +384 0x6400 //TX_OUT_ENER_S_TH_CLEAN +385 0x6400 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x6400 //TX_OUT_ENER_S_TH_NOISY +387 0x6400 //TX_OUT_ENER_TH_NOISE +388 0x7D00 //TX_OUT_ENER_TH_SPEECH +389 0x0000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x7FFF //TX_POST_MASK_SUP_HSNE +392 0x1388 //TX_TAIL_DET_TH +393 0x4000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0080 //TX_SUPHIGH_TH +396 0x0000 //TX_MASK_G_R +397 0x0000 //TX_EXTRA_NS_L +398 0x1800 //TX_C_POST_FLT_MASK +399 0x7FFF //TX_A_POST_FLT_WNS +400 0x0000 //TX_MIN_G_LOW300HZ +401 0x0010 //TX_MAXLEVEL_CNG +402 0x0000 //TX_STN_NOISE_TH +403 0x0000 //TX_POST_MASK_SUP +404 0x0000 //TX_POST_MASK_ADJUST +405 0x0014 //TX_NS_ENOISE_MIC0_TH +406 0x00DC //TX_MINENOISE_MIC0_TH +407 0x0226 //TX_MINENOISE_MIC0_S_TH +408 0x2879 //TX_MIN_G_CTRL_SSNS +409 0x0400 //TX_METAL_RTO_THR +410 0x0080 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x2000 //TX_RHO_UPB +415 0x0020 //TX_N_HOLD_HS +416 0x0009 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0000 //TX_EXTRA_GAIN_MICBLOCK +419 0x0333 //TX_THR_STD_NSR +420 0x0219 //TX_THR_STD_PLH +421 0x09C4 //TX_N_HOLD_STD +422 0x0166 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0800 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x0000 //TX_SB_RTO_MEAN_TH_RUB +428 0x2000 //TX_WTA_EN_RTO_TH +429 0x1400 //TX_TOP_ENER_TH_F +430 0x0064 //TX_DESIRED_TALK_HOLDT +431 0x1000 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0000 //TX_HS_VAD_BIN +435 0x0000 //TX_THR_VAD_HS +436 0x0000 //TX_MEAN_RTO_MIN_TH2 +437 0x0000 //TX_SILENCE_T +438 0x4000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x099A //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x001E //TX_DOA_VAD_THR_1 +445 0x001E //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x00B4 //TX_SRC_DOA_RNG_HIGH_0B +453 0x005A //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x00B4 //TX_SRC_DOA_RNG_HIGH_0C +456 0x005A //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x00B4 //TX_SRC_DOA_RNG_HIGH_0D +459 0x005A //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0172 //TX_BF_HOLDOFF_T +473 0x8000 //TX_DOA_COST_FACTOR +474 0x0D9A //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x071C //TX_DOA_TRACK_HT +477 0x0280 //TX_N1_HOLD_HF +478 0x0140 //TX_N2_HOLD_HF +479 0x2AAB //TX_BF_RESET_THR_HF +480 0x4000 //TX_DOA_SMOOTH +481 0x0000 //TX_MU_BF +482 0x0200 //TX_BF_MU_LF_B2 +483 0x0000 //TX_BF_FC_END_BIN_B2 +484 0x0000 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0000 //TX_N_DOA_SEED +488 0x0000 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x0000 //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x0000 //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x0000 //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x0168 //TX_NOR_OFF_THR +498 0x0CCD //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0004 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0230 //TX_NOR_OFF_TH1 +503 0xD333 //TX_WIDE_MASK_TH +504 0x4650 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x6000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x000A //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x6666 //TX_MICTOBFGAIN0 +513 0x0014 //TX_FASTMUE_TH +514 0xC000 //TX_DEREVERB_LF_MU +515 0xC000 //TX_DEREVERB_HF_MU +516 0xCCCC //TX_DEREVERB_DELAY +517 0xD999 //TX_DEREVERB_COEF_LEN +518 0x1F40 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x7000 //TX_GSC_RTOH_TH +523 0x0064 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x0000 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0028 //TX_SNR_THR +531 0x03E8 //TX_ENGY_THR +532 0x0000 //TX_CORR_HIGH_TH +533 0x0000 //TX_ENGY_THR_2 +534 0x0000 //TX_MEAN_RTO_THR +535 0x0000 //TX_WNS_ENOISE_MIC0_TH +536 0x0000 //TX_RATIOMICL_TH +537 0x0000 //TX_CALIG_HS +538 0x000A //TX_LVL_CTRL +539 0x0000 //TX_WIND_SUPRTO +540 0x0000 //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x0000 //TX_RATIOMICH_TH +543 0x0000 //TX_WIND_INBEAM_L_TH +544 0x0000 //TX_WIND_INBEAM_H_TH +545 0x0000 //TX_WNS_RESRV_0 +546 0x0000 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0000 //TX_BF_LESSCUT_BBIN +554 0x0000 //TX_BF_LESSCUT_EBIN +555 0x0000 //TX_POSTBFB0 +556 0x0000 //TX_POSTBFB +557 0x0000 //TX_POSTBFE +558 0x0000 //TX_SPEECH_SNR_TH +559 0x0000 //TX_PB_MAX_PRI_SNR_TH +560 0x0000 //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0020 //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4848 //TX_FDEQ_GAIN_5 +573 0x4848 //TX_FDEQ_GAIN_6 +574 0x4848 //TX_FDEQ_GAIN_7 +575 0x4848 //TX_FDEQ_GAIN_8 +576 0x4848 //TX_FDEQ_GAIN_9 +577 0x4848 //TX_FDEQ_GAIN_10 +578 0x4848 //TX_FDEQ_GAIN_11 +579 0x4848 //TX_FDEQ_GAIN_12 +580 0x4848 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0000 //TX_FDEQ_BIN_0 +592 0x0000 //TX_FDEQ_BIN_1 +593 0x0000 //TX_FDEQ_BIN_2 +594 0x0000 //TX_FDEQ_BIN_3 +595 0x0000 //TX_FDEQ_BIN_4 +596 0x0000 //TX_FDEQ_BIN_5 +597 0x0000 //TX_FDEQ_BIN_6 +598 0x0000 //TX_FDEQ_BIN_7 +599 0x0000 //TX_FDEQ_BIN_8 +600 0x0000 //TX_FDEQ_BIN_9 +601 0x0000 //TX_FDEQ_BIN_10 +602 0x0000 //TX_FDEQ_BIN_11 +603 0x0000 //TX_FDEQ_BIN_12 +604 0x0000 //TX_FDEQ_BIN_13 +605 0x0000 //TX_FDEQ_BIN_14 +606 0x0000 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4848 //TX_PREEQ_GAIN_MIC0_8 +626 0x4848 //TX_PREEQ_GAIN_MIC0_9 +627 0x4848 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0000 //TX_PREEQ_BIN_MIC0_0 +642 0x0000 //TX_PREEQ_BIN_MIC0_1 +643 0x0000 //TX_PREEQ_BIN_MIC0_2 +644 0x0000 //TX_PREEQ_BIN_MIC0_3 +645 0x0000 //TX_PREEQ_BIN_MIC0_4 +646 0x0000 //TX_PREEQ_BIN_MIC0_5 +647 0x0000 //TX_PREEQ_BIN_MIC0_6 +648 0x0000 //TX_PREEQ_BIN_MIC0_7 +649 0x0000 //TX_PREEQ_BIN_MIC0_8 +650 0x0000 //TX_PREEQ_BIN_MIC0_9 +651 0x0000 //TX_PREEQ_BIN_MIC0_10 +652 0x0000 //TX_PREEQ_BIN_MIC0_11 +653 0x0000 //TX_PREEQ_BIN_MIC0_12 +654 0x0000 //TX_PREEQ_BIN_MIC0_13 +655 0x0000 //TX_PREEQ_BIN_MIC0_14 +656 0x0000 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0000 //TX_PREEQ_BIN_MIC1_0 +691 0x0000 //TX_PREEQ_BIN_MIC1_1 +692 0x0000 //TX_PREEQ_BIN_MIC1_2 +693 0x0000 //TX_PREEQ_BIN_MIC1_3 +694 0x0000 //TX_PREEQ_BIN_MIC1_4 +695 0x0000 //TX_PREEQ_BIN_MIC1_5 +696 0x0000 //TX_PREEQ_BIN_MIC1_6 +697 0x0000 //TX_PREEQ_BIN_MIC1_7 +698 0x0000 //TX_PREEQ_BIN_MIC1_8 +699 0x0000 //TX_PREEQ_BIN_MIC1_9 +700 0x0000 //TX_PREEQ_BIN_MIC1_10 +701 0x0000 //TX_PREEQ_BIN_MIC1_11 +702 0x0000 //TX_PREEQ_BIN_MIC1_12 +703 0x0000 //TX_PREEQ_BIN_MIC1_13 +704 0x0000 //TX_PREEQ_BIN_MIC1_14 +705 0x0000 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0000 //TX_PREEQ_BIN_MIC2_0 +740 0x0000 //TX_PREEQ_BIN_MIC2_1 +741 0x0000 //TX_PREEQ_BIN_MIC2_2 +742 0x0000 //TX_PREEQ_BIN_MIC2_3 +743 0x0000 //TX_PREEQ_BIN_MIC2_4 +744 0x0000 //TX_PREEQ_BIN_MIC2_5 +745 0x0000 //TX_PREEQ_BIN_MIC2_6 +746 0x0000 //TX_PREEQ_BIN_MIC2_7 +747 0x0000 //TX_PREEQ_BIN_MIC2_8 +748 0x0000 //TX_PREEQ_BIN_MIC2_9 +749 0x0000 //TX_PREEQ_BIN_MIC2_10 +750 0x0000 //TX_PREEQ_BIN_MIC2_11 +751 0x0000 //TX_PREEQ_BIN_MIC2_12 +752 0x0000 //TX_PREEQ_BIN_MIC2_13 +753 0x0000 //TX_PREEQ_BIN_MIC2_14 +754 0x0000 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x2000 //TX_NND_WEIGHT +765 0x0064 //TX_MIC_CALIBRATION_0 +766 0x006A //TX_MIC_CALIBRATION_1 +767 0x006A //TX_MIC_CALIBRATION_2 +768 0x006B //TX_MIC_CALIBRATION_3 +769 0x0048 //TX_MIC_PWR_BIAS_0 +770 0x003C //TX_MIC_PWR_BIAS_1 +771 0x003C //TX_MIC_PWR_BIAS_2 +772 0x003C //TX_MIC_PWR_BIAS_3 +773 0x0000 //TX_GAIN_LIMIT_0 +774 0x0009 //TX_GAIN_LIMIT_1 +775 0x000C //TX_GAIN_LIMIT_2 +776 0x000F //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F3D //TX_BVE_NOVAD0_ALPHAUP +783 0x3000 //TX_TDDRC_ALPHA_UP_01 +784 0x3000 //TX_TDDRC_ALPHA_UP_02 +785 0x3000 //TX_TDDRC_ALPHA_UP_03 +786 0x3000 //TX_TDDRC_ALPHA_UP_04 +787 0x7FB0 //TX_TDDRC_ALPHA_DWN_01 +788 0x7FB0 //TX_TDDRC_ALPHA_DWN_02 +789 0x7FB0 //TX_TDDRC_ALPHA_DWN_03 +790 0x7FB0 //TX_TDDRC_ALPHA_DWN_04 +791 0x65AD //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0002 //TX_DEADMIC_SILENCE_TH +817 0x0147 //TX_MIC_DEGRADE_TH +818 0x0078 //TX_DEADMIC_CNT +819 0x0078 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x0000 //TX_KS_NOISEPASTE_FACTOR +824 0x0000 //TX_KS_CONFIG +825 0x0000 //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x0000 //TX_FFP_FP_K_METAL +834 0x0000 //TX_A_POST_FLT_FP +835 0x0000 //TX_RTO_OUTBEAM_TH +836 0x0000 //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0000 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0000 //TX_FFP_RESRV_2 +849 0x0000 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0002 //TX_FILTINDX +854 0x0000 //TX_TDDRC_THRD_0 +855 0x0000 //TX_TDDRC_THRD_1 +856 0x0E80 //TX_TDDRC_THRD_2 +857 0x3800 //TX_TDDRC_THRD_3 +858 0x2A00 //TX_TDDRC_SLANT_0 +859 0x6E00 //TX_TDDRC_SLANT_1 +860 0x3000 //TX_TDDRC_ALPHA_UP_00 +861 0x7FB0 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x0000 //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0000 //TX_TDDRC_SMT_W +866 0x0100 //TX_TDDRC_DRC_GAIN +867 0x0000 //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x1EB8 //TX_TFMASKLTH +870 0x170A //TX_TFMASKLTHL +871 0x7FFF //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0x0CCD //TX_TFMASKTH_BLESSCUT +876 0x4000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x0000 //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x0000 //TX_FASTNS_OUTIN_TH +884 0x0000 //TX_FASTNS_TFMASK_TH +885 0x0000 //TX_FASTNS_TFMASKBIN_TH1 +886 0x0000 //TX_FASTNS_TFMASKBIN_TH2 +887 0x0000 //TX_FASTNS_TFMASKBIN_TH3 +888 0x00C8 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x051F //TX_POSTSSA_MIN_G_VR_MASK +891 0x4000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x2339 //TX_SENDFUNC_REG_MICMUTE +898 0x0021 //TX_SENDFUNC_REG_MICMUTE1 +899 0x02BC //TX_MICMUTE_RATIO_THR +900 0x0140 //TX_MICMUTE_AMP_THR +901 0x0004 //TX_MICMUTE_HPF_IND +902 0x00C0 //TX_MICMUTE_LOG_EYR_TH +903 0x0008 //TX_MICMUTE_CVG_TIME +904 0x0008 //TX_MICMUTE_RELEASE_TIME +905 0x01FE //TX_MIC_VOLUME_MIC0MUTE +906 0x0020 //TX_MICMUTE_EPD_OFFSET_0 +907 0x001E //TX_MICMUTE_FRQ_AEC_L +908 0x7999 //TX_MICMUTE_EAD_THR +909 0x7FFF //TX_MICMUTE_LAMBDA_CB_NLE +910 0x7FFF //TX_MICMUTE_LAMBDA_RE_EST +911 0x4000 //TX_DTD_THR1_MICMUTE_0 +912 0x7000 //TX_DTD_THR1_MICMUTE_1 +913 0x7FFF //TX_DTD_THR1_MICMUTE_2 +914 0x7FFF //TX_DTD_THR1_MICMUTE_3 +915 0x6CCC //TX_DTD_THR2_MICMUTE_0 +916 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x1000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x4000 //TX_MICMUTE_C_POST_FLT +922 0x03E8 //TX_MICMUTE_DT_CUT_K +923 0x0001 //TX_MICMUTE_DT_CUT_THR +924 0x03E8 //TX_MICMUTE_DT_CUT_K2 +925 0x0001 //TX_MICMUTE_DT_CUT_THR2 +926 0x0064 //TX_MICMUTE_DT2_HOLD_N +927 0x1000 //TX_MICMUTE_RATIODTH_THCUT +928 0x1000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x7FFF //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0400 //TX_MICMUTE_C_POST_FLT_MASK +931 0x7999 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0258 //TX_MICMUTE_DT_CUT_K1 +933 0x0800 //TX_MICMUTE_N2_SN_EST +934 0xFC00 //TX_MICMUTE_THR_SN_EST_0 +935 0x001C //TX_MICMUTE_MIN_G_CTRL_0 +936 0x6000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x7000 //TX_MICMUTE_B_POST_FILT_0 +938 0x2710 //TX_MIC1RUB_AMP_THR +939 0x0010 //TX_MIC1MUTE_RATIO_THR +940 0x0450 //TX_MIC1MUTE_AMP_THR +941 0x0008 //TX_MIC1MUTE_CVG_TIME +942 0x0008 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x2040 //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0000 //RX_SAMPLINGFREQ_SIG +3 0x0000 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +10 0x050D //RX_PGA +11 0x7652 //RX_A_HP +12 0x4000 //RX_B_PE +13 0x7800 //RX_THR_PITCH_DET_0 +14 0x7000 //RX_THR_PITCH_DET_1 +15 0x6000 //RX_THR_PITCH_DET_2 +16 0x0000 //RX_PITCH_BFR_LEN +17 0x0000 //RX_SBD_PITCH_DET +18 0x0000 //RX_PP_RESRV_0 +19 0x0000 //RX_PP_RESRV_1 +20 0xF800 //RX_N_SN_EST +21 0x0000 //RX_N2_SN_EST +22 0x000F //RX_NS_LVL_CTRL +23 0xF800 //RX_THR_SN_EST +24 0x7E00 //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0000 //RX_FENS_RESRV_1 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +30 0x0000 //RX_EXTRA_NS_L +31 0x0000 //RX_EXTRA_NS_A +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x0000 //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0003 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x0080 //RX_MIN_G_FP +128 0x2000 //RX_MAX_G_FP +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0010 //RX_MAXLEVEL_CNG +132 0x0000 //RX_BWE_UV_TH +133 0x0000 //RX_BWE_UV_TH2 +134 0x0000 //RX_BWE_UV_TH3 +135 0x0000 //RX_BWE_V_TH +136 0x0000 //RX_BWE_GAIN1_V_TH1 +137 0x0000 //RX_BWE_GAIN1_V_TH2 +138 0x0000 //RX_BWE_UV_EQ +139 0x0000 //RX_BWE_V_EQ +140 0x0000 //RX_BWE_TONE_TH +141 0x0000 //RX_BWE_UV_HOLD_T +142 0x0000 //RX_BWE_GAIN2_ALPHA +143 0x0000 //RX_BWE_GAIN3_ALPHA +144 0x0000 //RX_BWE_CUTOFF +145 0x0000 //RX_BWE_GAINFILL +146 0x0000 //RX_BWE_MAXTH_TONE +147 0x0000 //RX_BWE_EQ_0 +148 0x0000 //RX_BWE_EQ_1 +149 0x0000 //RX_BWE_EQ_2 +150 0x0000 //RX_BWE_EQ_3 +151 0x0000 //RX_BWE_EQ_4 +152 0x0000 //RX_BWE_EQ_5 +153 0x0000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x2040 //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0000 //RX_SAMPLINGFREQ_SIG +160 0x0000 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +167 0x050D //RX_PGA +168 0x7652 //RX_A_HP +169 0x4000 //RX_B_PE +170 0x7800 //RX_THR_PITCH_DET_0 +171 0x7000 //RX_THR_PITCH_DET_1 +172 0x6000 //RX_THR_PITCH_DET_2 +173 0x0000 //RX_PITCH_BFR_LEN +174 0x0000 //RX_SBD_PITCH_DET +175 0x0000 //RX_PP_RESRV_0 +176 0x0000 //RX_PP_RESRV_1 +177 0xF800 //RX_N_SN_EST +178 0x0000 //RX_N2_SN_EST +179 0x000F //RX_NS_LVL_CTRL +180 0xF800 //RX_THR_SN_EST +181 0x7E00 //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0000 //RX_FENS_RESRV_1 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +187 0x0000 //RX_EXTRA_NS_L +188 0x0000 //RX_EXTRA_NS_A +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x0000 //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0003 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x0080 //RX_MIN_G_FP +285 0x2000 //RX_MAX_G_FP +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0010 //RX_MAXLEVEL_CNG +289 0x0000 //RX_BWE_UV_TH +290 0x0000 //RX_BWE_UV_TH2 +291 0x0000 //RX_BWE_UV_TH3 +292 0x0000 //RX_BWE_V_TH +293 0x0000 //RX_BWE_GAIN1_V_TH1 +294 0x0000 //RX_BWE_GAIN1_V_TH2 +295 0x0000 //RX_BWE_UV_EQ +296 0x0000 //RX_BWE_V_EQ +297 0x0000 //RX_BWE_TONE_TH +298 0x0000 //RX_BWE_UV_HOLD_T +299 0x0000 //RX_BWE_GAIN2_ALPHA +300 0x0000 //RX_BWE_GAIN3_ALPHA +301 0x0000 //RX_BWE_CUTOFF +302 0x0000 //RX_BWE_GAINFILL +303 0x0000 //RX_BWE_MAXTH_TONE +304 0x0000 //RX_BWE_EQ_0 +305 0x0000 //RX_BWE_EQ_1 +306 0x0000 //RX_BWE_EQ_2 +307 0x0000 //RX_BWE_EQ_3 +308 0x0000 //RX_BWE_EQ_4 +309 0x0000 //RX_BWE_EQ_5 +310 0x0000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME HEADSET-TTY_FULL-VOICE_GENERIC-SWB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0001 //TX_OPERATION_MODE_0 +1 0x0000 //TX_OPERATION_MODE_1 +2 0x0000 //TX_PATCH_REG +3 0x0200 //TX_SENDFUNC_MODE_0 +4 0x0000 //TX_SENDFUNC_MODE_1 +5 0x0001 //TX_NUM_MIC +6 0x0000 //TX_SAMPLINGFREQ_SIG +7 0x0000 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x0078 //TX_DIST2REF1 +22 0x0000 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0302 //TX_PGA_0 +28 0x0800 //TX_PGA_1 +29 0x0800 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0000 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0000 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0000 //TX_MICS_OF_PAIR0 +38 0x0000 //TX_MICS_OF_PAIR1 +39 0x0000 //TX_MICS_OF_PAIR2 +40 0x0000 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0001 //TX_MIC_DATA_SRC1 +43 0x0002 //TX_MIC_DATA_SRC2 +44 0x0003 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x0000 //TX_HD_BIN_MASK +53 0x0000 //TX_HD_SUBAND_MASK +54 0x0000 //TX_HD_FRAME_AVG_MASK +55 0x0000 //TX_HD_MIN_FRQ +56 0x0000 //TX_HD_ALPHA_PSD +57 0x0000 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0x0000 //TX_T_PSDVAT +63 0x0000 //TX_CNT +64 0x0000 //TX_ANTI_HOWL_GAIN +65 0x0000 //TX_MICFORBFMARK_0 +66 0x0000 //TX_MICFORBFMARK_1 +67 0x0000 //TX_MICFORBFMARK_2 +68 0x0000 //TX_MICFORBFMARK_3 +69 0x0000 //TX_MICFORBFMARK_4 +70 0x0000 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x0000 //TX_DIST2REF_11 +73 0x0000 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0800 //TX_MIC_REFBLK_VOLUME +108 0x0800 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x0000 //TX_ADCS_GAIN +112 0x0000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x7FFF //TX_BLMIC_BLKFACTOR +116 0x7FFF //TX_BRMIC_BLKFACTOR +117 0x000A //TX_MICBLK_START_BIN +118 0x0041 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0015 //TX_FENE_HOLD +123 0x0000 //TX_FE_ENER_TH_MTS +124 0x0000 //TX_FE_ENER_TH_EXP +125 0x0000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x0000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0020 //TX_MIC_BLOCK_N +128 0x7652 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x7800 //TX_THR_PITCH_DET_0 +131 0x7000 //TX_THR_PITCH_DET_1 +132 0x6000 //TX_THR_PITCH_DET_2 +133 0x0000 //TX_PITCH_BFR_LEN +134 0x0000 //TX_SBD_PITCH_DET +135 0x0000 //TX_TD_AEC_L +136 0x0000 //TX_MU0_UNP_TD_AEC +137 0x0000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x0028 //TX_TAIL_LENGTH +147 0x2000 //TX_AEC_REF_GAIN_0 +148 0x2000 //TX_AEC_REF_GAIN_1 +149 0x2000 //TX_AEC_REF_GAIN_2 +150 0x4000 //TX_EAD_THR +151 0x0200 //TX_THR_RE_EST +152 0x0100 //TX_MIN_EQ_RE_EST_0 +153 0x0100 //TX_MIN_EQ_RE_EST_1 +154 0x0100 //TX_MIN_EQ_RE_EST_2 +155 0x0100 //TX_MIN_EQ_RE_EST_3 +156 0x0100 //TX_MIN_EQ_RE_EST_4 +157 0x0100 //TX_MIN_EQ_RE_EST_5 +158 0x0100 //TX_MIN_EQ_RE_EST_6 +159 0x0100 //TX_MIN_EQ_RE_EST_7 +160 0x0100 //TX_MIN_EQ_RE_EST_8 +161 0x0100 //TX_MIN_EQ_RE_EST_9 +162 0x0100 //TX_MIN_EQ_RE_EST_10 +163 0x0100 //TX_MIN_EQ_RE_EST_11 +164 0x0100 //TX_MIN_EQ_RE_EST_12 +165 0x4000 //TX_LAMBDA_RE_EST +166 0x0000 //TX_LAMBDA_CB_NLE +167 0x0000 //TX_C_POST_FLT +168 0x4000 //TX_GAIN_NP +169 0x0008 //TX_SE_HOLD_N +170 0x0050 //TX_DT_HOLD_N +171 0x03E8 //TX_DT2_HOLD_N +172 0x0000 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x0000 //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0000 //TX_FRQ_LIN_LEN +184 0x0000 //TX_FRQ_AEC_LEN_RHO +185 0x0000 //TX_MU0_UNP_FRQ_AEC +186 0x0000 //TX_MU0_PTD_FRQ_AEC +187 0x0000 //TX_MINENOISETH +188 0x0000 //TX_MU0_RE_EST +189 0x0000 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x0000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x7333 //TX_DTD_THR1_0 +198 0x7333 //TX_DTD_THR1_1 +199 0x7333 //TX_DTD_THR1_2 +200 0x7333 //TX_DTD_THR1_3 +201 0x7333 //TX_DTD_THR1_4 +202 0x7333 //TX_DTD_THR1_5 +203 0x7333 //TX_DTD_THR1_6 +204 0x0CCD //TX_DTD_THR2_0 +205 0x0CCD //TX_DTD_THR2_1 +206 0x0CCD //TX_DTD_THR2_2 +207 0x0CCD //TX_DTD_THR2_3 +208 0x0CCD //TX_DTD_THR2_4 +209 0x0CCD //TX_DTD_THR2_5 +210 0x0CCD //TX_DTD_THR2_6 +211 0x7FFF //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x0400 //TX_DT_CUT_K +214 0x0000 //TX_DT_CUT_THR +215 0x0000 //TX_COMFORT_G +216 0x0000 //TX_POWER_YOUT_TH +217 0x0000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x0400 //TX_ADPT_STRICT_L +222 0x0200 //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x0800 //TX_B_POST_FILT_ECHO_L +229 0x0800 //TX_B_POST_FILT_ECHO_H +230 0x0000 //TX_MIN_G_CTRL_ECHO +231 0x7FFF //TX_B_LESSCUT_RTO_ECHO +232 0x0000 //TX_EPD_OFFSET_00 +233 0x0000 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x0000 //TX_MIN_EQ_RE_EST_13 +237 0x0000 //TX_DTD_THR1_7 +238 0x0000 //TX_DTD_THR2_7 +239 0x0000 //TX_DT_RESRV_7 +240 0x0000 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xFA00 //TX_THR_SN_EST_0 +243 0xF400 //TX_THR_SN_EST_1 +244 0xF800 //TX_THR_SN_EST_2 +245 0xF600 //TX_THR_SN_EST_3 +246 0xF800 //TX_THR_SN_EST_4 +247 0xF800 //TX_THR_SN_EST_5 +248 0xF800 //TX_THR_SN_EST_6 +249 0xF800 //TX_THR_SN_EST_7 +250 0x0100 //TX_DELTA_THR_SN_EST_0 +251 0x0100 //TX_DELTA_THR_SN_EST_1 +252 0x0100 //TX_DELTA_THR_SN_EST_2 +253 0x0200 //TX_DELTA_THR_SN_EST_3 +254 0x0200 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0000 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x4000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x4000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0A00 //TX_N_SN_EST +267 0x0000 //TX_INBEAM_T +268 0x0000 //TX_INBEAMHOLDT +269 0x1FFF //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x1000 //TX_NE_RTO_TH_L +274 0x1000 //TX_MAINREFRTOH_TH_H +275 0x1000 //TX_MAINREFRTOH_TH_L +276 0x2000 //TX_MAINREFRTO_TH_H +277 0x1400 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x0000 //TX_B_POST_FLT_0 +280 0x0000 //TX_B_POST_FLT_1 +281 0x001A //TX_NS_LVL_CTRL_0 +282 0x0014 //TX_NS_LVL_CTRL_1 +283 0x0014 //TX_NS_LVL_CTRL_2 +284 0x000C //TX_NS_LVL_CTRL_3 +285 0x000C //TX_NS_LVL_CTRL_4 +286 0x000C //TX_NS_LVL_CTRL_5 +287 0x001A //TX_NS_LVL_CTRL_6 +288 0x000C //TX_NS_LVL_CTRL_7 +289 0x000E //TX_MIN_GAIN_S_0 +290 0x0014 //TX_MIN_GAIN_S_1 +291 0x0014 //TX_MIN_GAIN_S_2 +292 0x0014 //TX_MIN_GAIN_S_3 +293 0x0014 //TX_MIN_GAIN_S_4 +294 0x0014 //TX_MIN_GAIN_S_5 +295 0x0014 //TX_MIN_GAIN_S_6 +296 0x0014 //TX_MIN_GAIN_S_7 +297 0x0000 //TX_NMOS_SUP +298 0x0064 //TX_NS_MAX_PRI_SNR_TH +299 0x7FFF //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x7FFF //TX_SNRI_SUP_1 +302 0x7FFF //TX_SNRI_SUP_2 +303 0x4000 //TX_SNRI_SUP_3 +304 0x4000 //TX_SNRI_SUP_4 +305 0x4000 //TX_SNRI_SUP_5 +306 0x7FFF //TX_SNRI_SUP_6 +307 0x4000 //TX_SNRI_SUP_7 +308 0x1200 //TX_THR_LFNS +309 0x0147 //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x7FFF //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x7FFF //TX_A_POST_FILT_1 +314 0x4000 //TX_A_POST_FILT_S_0 +315 0x1000 //TX_A_POST_FILT_S_1 +316 0x1000 //TX_A_POST_FILT_S_2 +317 0x6666 //TX_A_POST_FILT_S_3 +318 0x6666 //TX_A_POST_FILT_S_4 +319 0x6666 //TX_A_POST_FILT_S_5 +320 0x199A //TX_A_POST_FILT_S_6 +321 0x6666 //TX_A_POST_FILT_S_7 +322 0x2000 //TX_B_POST_FILT_0 +323 0x2000 //TX_B_POST_FILT_1 +324 0x2000 //TX_B_POST_FILT_2 +325 0x2000 //TX_B_POST_FILT_3 +326 0x2000 //TX_B_POST_FILT_4 +327 0x2000 //TX_B_POST_FILT_5 +328 0x2000 //TX_B_POST_FILT_6 +329 0x2000 //TX_B_POST_FILT_7 +330 0x7FFF //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x7FFF //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7E00 //TX_LAMBDA_PFILT +339 0x7E00 //TX_LAMBDA_PFILT_S_0 +340 0x7E00 //TX_LAMBDA_PFILT_S_1 +341 0x7E00 //TX_LAMBDA_PFILT_S_2 +342 0x7E00 //TX_LAMBDA_PFILT_S_3 +343 0x7E00 //TX_LAMBDA_PFILT_S_4 +344 0x7E00 //TX_LAMBDA_PFILT_S_5 +345 0x7E00 //TX_LAMBDA_PFILT_S_6 +346 0x7E00 //TX_LAMBDA_PFILT_S_7 +347 0x0010 //TX_K_PEPPER +348 0x0400 //TX_A_PEPPER +349 0x0000 //TX_K_PEPPER_HF +350 0x0000 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x4000 //TX_HMNC_BST_THR +353 0x0000 //TX_DT_BINVAD_TH_0 +354 0x0000 //TX_DT_BINVAD_TH_1 +355 0x0000 //TX_DT_BINVAD_TH_2 +356 0x0000 //TX_DT_BINVAD_TH_3 +357 0x0000 //TX_DT_BINVAD_ENDF +358 0x0000 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0001 //TX_BF_SGRAD_FLG +362 0x0000 //TX_BF_DVG_TH +363 0x0000 //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x05A0 //TX_NDETCT +367 0x0383 //TX_NOISE_TH_0 +368 0x1388 //TX_NOISE_TH_0_2 +369 0x3A98 //TX_NOISE_TH_0_3 +370 0x0C80 //TX_NOISE_TH_1 +371 0x0032 //TX_NOISE_TH_2 +372 0x3D54 //TX_NOISE_TH_3 +373 0x012C //TX_NOISE_TH_4 +374 0x07D0 //TX_NOISE_TH_5 +375 0x6590 //TX_NOISE_TH_5_2 +376 0x7FFF //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x00C8 //TX_NOISE_TH_6 +379 0x044C //TX_MINENOISE_TH +380 0xD508 //TX_MORENS_TFMASK_TH +381 0x0001 //TX_DRC_QUIET_FLOOR +382 0x3A98 //TX_RATIODTL_CUT_TH +383 0x0DAC //TX_DT_CUT_K1 +384 0x6400 //TX_OUT_ENER_S_TH_CLEAN +385 0x6400 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x6400 //TX_OUT_ENER_S_TH_NOISY +387 0x6400 //TX_OUT_ENER_TH_NOISE +388 0x7D00 //TX_OUT_ENER_TH_SPEECH +389 0x0000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x7FFF //TX_POST_MASK_SUP_HSNE +392 0x1388 //TX_TAIL_DET_TH +393 0x4000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0080 //TX_SUPHIGH_TH +396 0x0000 //TX_MASK_G_R +397 0x0000 //TX_EXTRA_NS_L +398 0x1800 //TX_C_POST_FLT_MASK +399 0x7FFF //TX_A_POST_FLT_WNS +400 0x0000 //TX_MIN_G_LOW300HZ +401 0x0010 //TX_MAXLEVEL_CNG +402 0x0000 //TX_STN_NOISE_TH +403 0x0000 //TX_POST_MASK_SUP +404 0x0000 //TX_POST_MASK_ADJUST +405 0x0014 //TX_NS_ENOISE_MIC0_TH +406 0x02F3 //TX_MINENOISE_MIC0_TH +407 0x0226 //TX_MINENOISE_MIC0_S_TH +408 0x2879 //TX_MIN_G_CTRL_SSNS +409 0x0400 //TX_METAL_RTO_THR +410 0x0080 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x2000 //TX_RHO_UPB +415 0x0020 //TX_N_HOLD_HS +416 0x0009 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0000 //TX_EXTRA_GAIN_MICBLOCK +419 0x0333 //TX_THR_STD_NSR +420 0x0219 //TX_THR_STD_PLH +421 0x09C4 //TX_N_HOLD_STD +422 0x0166 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0800 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x0000 //TX_SB_RTO_MEAN_TH_RUB +428 0x2000 //TX_WTA_EN_RTO_TH +429 0x1400 //TX_TOP_ENER_TH_F +430 0x0064 //TX_DESIRED_TALK_HOLDT +431 0x1000 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0000 //TX_HS_VAD_BIN +435 0x0000 //TX_THR_VAD_HS +436 0x0000 //TX_MEAN_RTO_MIN_TH2 +437 0x0000 //TX_SILENCE_T +438 0x4000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x099A //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x001E //TX_DOA_VAD_THR_1 +445 0x001E //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x00B4 //TX_SRC_DOA_RNG_HIGH_0B +453 0x005A //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x00B4 //TX_SRC_DOA_RNG_HIGH_0C +456 0x005A //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x00B4 //TX_SRC_DOA_RNG_HIGH_0D +459 0x005A //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0172 //TX_BF_HOLDOFF_T +473 0x8000 //TX_DOA_COST_FACTOR +474 0x0D9A //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x071C //TX_DOA_TRACK_HT +477 0x0280 //TX_N1_HOLD_HF +478 0x0140 //TX_N2_HOLD_HF +479 0x2AAB //TX_BF_RESET_THR_HF +480 0x4000 //TX_DOA_SMOOTH +481 0x0000 //TX_MU_BF +482 0x0200 //TX_BF_MU_LF_B2 +483 0x0000 //TX_BF_FC_END_BIN_B2 +484 0x0000 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0000 //TX_N_DOA_SEED +488 0x0000 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x0000 //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x0000 //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x0000 //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x0168 //TX_NOR_OFF_THR +498 0x0CCD //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0004 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0230 //TX_NOR_OFF_TH1 +503 0xD333 //TX_WIDE_MASK_TH +504 0x4650 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x6000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x000A //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x6666 //TX_MICTOBFGAIN0 +513 0x0014 //TX_FASTMUE_TH +514 0xC000 //TX_DEREVERB_LF_MU +515 0xC000 //TX_DEREVERB_HF_MU +516 0xCCCC //TX_DEREVERB_DELAY +517 0xD999 //TX_DEREVERB_COEF_LEN +518 0x1F40 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x7000 //TX_GSC_RTOH_TH +523 0x0064 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x0000 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0028 //TX_SNR_THR +531 0x03E8 //TX_ENGY_THR +532 0x0000 //TX_CORR_HIGH_TH +533 0x0000 //TX_ENGY_THR_2 +534 0x0000 //TX_MEAN_RTO_THR +535 0x0000 //TX_WNS_ENOISE_MIC0_TH +536 0x0000 //TX_RATIOMICL_TH +537 0x0000 //TX_CALIG_HS +538 0x000A //TX_LVL_CTRL +539 0x0000 //TX_WIND_SUPRTO +540 0x0000 //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x0000 //TX_RATIOMICH_TH +543 0x0000 //TX_WIND_INBEAM_L_TH +544 0x0000 //TX_WIND_INBEAM_H_TH +545 0x0000 //TX_WNS_RESRV_0 +546 0x0000 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0000 //TX_BF_LESSCUT_BBIN +554 0x0000 //TX_BF_LESSCUT_EBIN +555 0x0000 //TX_POSTBFB0 +556 0x0000 //TX_POSTBFB +557 0x0000 //TX_POSTBFE +558 0x0000 //TX_SPEECH_SNR_TH +559 0x0000 //TX_PB_MAX_PRI_SNR_TH +560 0x0000 //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0020 //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4848 //TX_FDEQ_GAIN_5 +573 0x4848 //TX_FDEQ_GAIN_6 +574 0x4848 //TX_FDEQ_GAIN_7 +575 0x4848 //TX_FDEQ_GAIN_8 +576 0x4848 //TX_FDEQ_GAIN_9 +577 0x4848 //TX_FDEQ_GAIN_10 +578 0x4848 //TX_FDEQ_GAIN_11 +579 0x4848 //TX_FDEQ_GAIN_12 +580 0x4848 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0000 //TX_FDEQ_BIN_0 +592 0x0000 //TX_FDEQ_BIN_1 +593 0x0000 //TX_FDEQ_BIN_2 +594 0x0000 //TX_FDEQ_BIN_3 +595 0x0000 //TX_FDEQ_BIN_4 +596 0x0000 //TX_FDEQ_BIN_5 +597 0x0000 //TX_FDEQ_BIN_6 +598 0x0000 //TX_FDEQ_BIN_7 +599 0x0000 //TX_FDEQ_BIN_8 +600 0x0000 //TX_FDEQ_BIN_9 +601 0x0000 //TX_FDEQ_BIN_10 +602 0x0000 //TX_FDEQ_BIN_11 +603 0x0000 //TX_FDEQ_BIN_12 +604 0x0000 //TX_FDEQ_BIN_13 +605 0x0000 //TX_FDEQ_BIN_14 +606 0x0000 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4848 //TX_PREEQ_GAIN_MIC0_8 +626 0x4848 //TX_PREEQ_GAIN_MIC0_9 +627 0x4848 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0000 //TX_PREEQ_BIN_MIC0_0 +642 0x0000 //TX_PREEQ_BIN_MIC0_1 +643 0x0000 //TX_PREEQ_BIN_MIC0_2 +644 0x0000 //TX_PREEQ_BIN_MIC0_3 +645 0x0000 //TX_PREEQ_BIN_MIC0_4 +646 0x0000 //TX_PREEQ_BIN_MIC0_5 +647 0x0000 //TX_PREEQ_BIN_MIC0_6 +648 0x0000 //TX_PREEQ_BIN_MIC0_7 +649 0x0000 //TX_PREEQ_BIN_MIC0_8 +650 0x0000 //TX_PREEQ_BIN_MIC0_9 +651 0x0000 //TX_PREEQ_BIN_MIC0_10 +652 0x0000 //TX_PREEQ_BIN_MIC0_11 +653 0x0000 //TX_PREEQ_BIN_MIC0_12 +654 0x0000 //TX_PREEQ_BIN_MIC0_13 +655 0x0000 //TX_PREEQ_BIN_MIC0_14 +656 0x0000 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0000 //TX_PREEQ_BIN_MIC1_0 +691 0x0000 //TX_PREEQ_BIN_MIC1_1 +692 0x0000 //TX_PREEQ_BIN_MIC1_2 +693 0x0000 //TX_PREEQ_BIN_MIC1_3 +694 0x0000 //TX_PREEQ_BIN_MIC1_4 +695 0x0000 //TX_PREEQ_BIN_MIC1_5 +696 0x0000 //TX_PREEQ_BIN_MIC1_6 +697 0x0000 //TX_PREEQ_BIN_MIC1_7 +698 0x0000 //TX_PREEQ_BIN_MIC1_8 +699 0x0000 //TX_PREEQ_BIN_MIC1_9 +700 0x0000 //TX_PREEQ_BIN_MIC1_10 +701 0x0000 //TX_PREEQ_BIN_MIC1_11 +702 0x0000 //TX_PREEQ_BIN_MIC1_12 +703 0x0000 //TX_PREEQ_BIN_MIC1_13 +704 0x0000 //TX_PREEQ_BIN_MIC1_14 +705 0x0000 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0000 //TX_PREEQ_BIN_MIC2_0 +740 0x0000 //TX_PREEQ_BIN_MIC2_1 +741 0x0000 //TX_PREEQ_BIN_MIC2_2 +742 0x0000 //TX_PREEQ_BIN_MIC2_3 +743 0x0000 //TX_PREEQ_BIN_MIC2_4 +744 0x0000 //TX_PREEQ_BIN_MIC2_5 +745 0x0000 //TX_PREEQ_BIN_MIC2_6 +746 0x0000 //TX_PREEQ_BIN_MIC2_7 +747 0x0000 //TX_PREEQ_BIN_MIC2_8 +748 0x0000 //TX_PREEQ_BIN_MIC2_9 +749 0x0000 //TX_PREEQ_BIN_MIC2_10 +750 0x0000 //TX_PREEQ_BIN_MIC2_11 +751 0x0000 //TX_PREEQ_BIN_MIC2_12 +752 0x0000 //TX_PREEQ_BIN_MIC2_13 +753 0x0000 //TX_PREEQ_BIN_MIC2_14 +754 0x0000 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x2000 //TX_NND_WEIGHT +765 0x0064 //TX_MIC_CALIBRATION_0 +766 0x006A //TX_MIC_CALIBRATION_1 +767 0x006A //TX_MIC_CALIBRATION_2 +768 0x006B //TX_MIC_CALIBRATION_3 +769 0x0048 //TX_MIC_PWR_BIAS_0 +770 0x003C //TX_MIC_PWR_BIAS_1 +771 0x003C //TX_MIC_PWR_BIAS_2 +772 0x003C //TX_MIC_PWR_BIAS_3 +773 0x0000 //TX_GAIN_LIMIT_0 +774 0x0009 //TX_GAIN_LIMIT_1 +775 0x000C //TX_GAIN_LIMIT_2 +776 0x000F //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F3D //TX_BVE_NOVAD0_ALPHAUP +783 0x3000 //TX_TDDRC_ALPHA_UP_01 +784 0x3000 //TX_TDDRC_ALPHA_UP_02 +785 0x3000 //TX_TDDRC_ALPHA_UP_03 +786 0x3000 //TX_TDDRC_ALPHA_UP_04 +787 0x7FB0 //TX_TDDRC_ALPHA_DWN_01 +788 0x7FB0 //TX_TDDRC_ALPHA_DWN_02 +789 0x7FB0 //TX_TDDRC_ALPHA_DWN_03 +790 0x7FB0 //TX_TDDRC_ALPHA_DWN_04 +791 0x65AD //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0002 //TX_DEADMIC_SILENCE_TH +817 0x0147 //TX_MIC_DEGRADE_TH +818 0x0078 //TX_DEADMIC_CNT +819 0x0078 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x0000 //TX_KS_NOISEPASTE_FACTOR +824 0x0000 //TX_KS_CONFIG +825 0x0000 //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x0000 //TX_FFP_FP_K_METAL +834 0x0000 //TX_A_POST_FLT_FP +835 0x0000 //TX_RTO_OUTBEAM_TH +836 0x0000 //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0000 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0000 //TX_FFP_RESRV_2 +849 0x0000 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0002 //TX_FILTINDX +854 0x0000 //TX_TDDRC_THRD_0 +855 0x0000 //TX_TDDRC_THRD_1 +856 0x0E80 //TX_TDDRC_THRD_2 +857 0x3800 //TX_TDDRC_THRD_3 +858 0x2A00 //TX_TDDRC_SLANT_0 +859 0x6E00 //TX_TDDRC_SLANT_1 +860 0x3000 //TX_TDDRC_ALPHA_UP_00 +861 0x7FB0 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x0000 //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0000 //TX_TDDRC_SMT_W +866 0x0100 //TX_TDDRC_DRC_GAIN +867 0x0000 //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x1EB8 //TX_TFMASKLTH +870 0x170A //TX_TFMASKLTHL +871 0x7FFF //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0x0CCD //TX_TFMASKTH_BLESSCUT +876 0x4000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x0000 //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x0000 //TX_FASTNS_OUTIN_TH +884 0x0000 //TX_FASTNS_TFMASK_TH +885 0x0000 //TX_FASTNS_TFMASKBIN_TH1 +886 0x0000 //TX_FASTNS_TFMASKBIN_TH2 +887 0x0000 //TX_FASTNS_TFMASKBIN_TH3 +888 0x00C8 //TX_FASTNS_ARSPC_TH +889 0x8000 //TX_FASTNS_MASK5_TH +890 0x051F //TX_POSTSSA_MIN_G_VR_MASK +891 0x4000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x2339 //TX_SENDFUNC_REG_MICMUTE +898 0x0021 //TX_SENDFUNC_REG_MICMUTE1 +899 0x02BC //TX_MICMUTE_RATIO_THR +900 0x0140 //TX_MICMUTE_AMP_THR +901 0x0004 //TX_MICMUTE_HPF_IND +902 0x00C0 //TX_MICMUTE_LOG_EYR_TH +903 0x0008 //TX_MICMUTE_CVG_TIME +904 0x0008 //TX_MICMUTE_RELEASE_TIME +905 0x01FE //TX_MIC_VOLUME_MIC0MUTE +906 0x0020 //TX_MICMUTE_EPD_OFFSET_0 +907 0x001E //TX_MICMUTE_FRQ_AEC_L +908 0x7999 //TX_MICMUTE_EAD_THR +909 0x7FFF //TX_MICMUTE_LAMBDA_CB_NLE +910 0x7FFF //TX_MICMUTE_LAMBDA_RE_EST +911 0x4000 //TX_DTD_THR1_MICMUTE_0 +912 0x7000 //TX_DTD_THR1_MICMUTE_1 +913 0x7FFF //TX_DTD_THR1_MICMUTE_2 +914 0x7FFF //TX_DTD_THR1_MICMUTE_3 +915 0x6CCC //TX_DTD_THR2_MICMUTE_0 +916 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x1000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x4000 //TX_MICMUTE_C_POST_FLT +922 0x03E8 //TX_MICMUTE_DT_CUT_K +923 0x0001 //TX_MICMUTE_DT_CUT_THR +924 0x03E8 //TX_MICMUTE_DT_CUT_K2 +925 0x0001 //TX_MICMUTE_DT_CUT_THR2 +926 0x0064 //TX_MICMUTE_DT2_HOLD_N +927 0x1000 //TX_MICMUTE_RATIODTH_THCUT +928 0x1000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x7FFF //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0400 //TX_MICMUTE_C_POST_FLT_MASK +931 0x7999 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0258 //TX_MICMUTE_DT_CUT_K1 +933 0x0800 //TX_MICMUTE_N2_SN_EST +934 0xFC00 //TX_MICMUTE_THR_SN_EST_0 +935 0x001C //TX_MICMUTE_MIN_G_CTRL_0 +936 0x6000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x7000 //TX_MICMUTE_B_POST_FILT_0 +938 0x2710 //TX_MIC1RUB_AMP_THR +939 0x0010 //TX_MIC1MUTE_RATIO_THR +940 0x0450 //TX_MIC1MUTE_AMP_THR +941 0x0008 //TX_MIC1MUTE_CVG_TIME +942 0x0008 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x2040 //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0000 //RX_SAMPLINGFREQ_SIG +3 0x0000 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +10 0x050D //RX_PGA +11 0x7652 //RX_A_HP +12 0x4000 //RX_B_PE +13 0x7800 //RX_THR_PITCH_DET_0 +14 0x7000 //RX_THR_PITCH_DET_1 +15 0x6000 //RX_THR_PITCH_DET_2 +16 0x0000 //RX_PITCH_BFR_LEN +17 0x0000 //RX_SBD_PITCH_DET +18 0x0000 //RX_PP_RESRV_0 +19 0x0000 //RX_PP_RESRV_1 +20 0xF800 //RX_N_SN_EST +21 0x0000 //RX_N2_SN_EST +22 0x000F //RX_NS_LVL_CTRL +23 0xF800 //RX_THR_SN_EST +24 0x7E00 //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0000 //RX_FENS_RESRV_1 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +30 0x0000 //RX_EXTRA_NS_L +31 0x0000 //RX_EXTRA_NS_A +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x0000 //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0003 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x0080 //RX_MIN_G_FP +128 0x2000 //RX_MAX_G_FP +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0010 //RX_MAXLEVEL_CNG +132 0x0000 //RX_BWE_UV_TH +133 0x0000 //RX_BWE_UV_TH2 +134 0x0000 //RX_BWE_UV_TH3 +135 0x0000 //RX_BWE_V_TH +136 0x0000 //RX_BWE_GAIN1_V_TH1 +137 0x0000 //RX_BWE_GAIN1_V_TH2 +138 0x0000 //RX_BWE_UV_EQ +139 0x0000 //RX_BWE_V_EQ +140 0x0000 //RX_BWE_TONE_TH +141 0x0000 //RX_BWE_UV_HOLD_T +142 0x0000 //RX_BWE_GAIN2_ALPHA +143 0x0000 //RX_BWE_GAIN3_ALPHA +144 0x0000 //RX_BWE_CUTOFF +145 0x0000 //RX_BWE_GAINFILL +146 0x0000 //RX_BWE_MAXTH_TONE +147 0x0000 //RX_BWE_EQ_0 +148 0x0000 //RX_BWE_EQ_1 +149 0x0000 //RX_BWE_EQ_2 +150 0x0000 //RX_BWE_EQ_3 +151 0x0000 //RX_BWE_EQ_4 +152 0x0000 //RX_BWE_EQ_5 +153 0x0000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x2040 //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0000 //RX_SAMPLINGFREQ_SIG +160 0x0000 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +167 0x050D //RX_PGA +168 0x7652 //RX_A_HP +169 0x4000 //RX_B_PE +170 0x7800 //RX_THR_PITCH_DET_0 +171 0x7000 //RX_THR_PITCH_DET_1 +172 0x6000 //RX_THR_PITCH_DET_2 +173 0x0000 //RX_PITCH_BFR_LEN +174 0x0000 //RX_SBD_PITCH_DET +175 0x0000 //RX_PP_RESRV_0 +176 0x0000 //RX_PP_RESRV_1 +177 0xF800 //RX_N_SN_EST +178 0x0000 //RX_N2_SN_EST +179 0x000F //RX_NS_LVL_CTRL +180 0xF800 //RX_THR_SN_EST +181 0x7E00 //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0000 //RX_FENS_RESRV_1 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +187 0x0000 //RX_EXTRA_NS_L +188 0x0000 //RX_EXTRA_NS_A +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x0000 //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0003 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x0080 //RX_MIN_G_FP +285 0x2000 //RX_MAX_G_FP +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0010 //RX_MAXLEVEL_CNG +289 0x0000 //RX_BWE_UV_TH +290 0x0000 //RX_BWE_UV_TH2 +291 0x0000 //RX_BWE_UV_TH3 +292 0x0000 //RX_BWE_V_TH +293 0x0000 //RX_BWE_GAIN1_V_TH1 +294 0x0000 //RX_BWE_GAIN1_V_TH2 +295 0x0000 //RX_BWE_UV_EQ +296 0x0000 //RX_BWE_V_EQ +297 0x0000 //RX_BWE_TONE_TH +298 0x0000 //RX_BWE_UV_HOLD_T +299 0x0000 //RX_BWE_GAIN2_ALPHA +300 0x0000 //RX_BWE_GAIN3_ALPHA +301 0x0000 //RX_BWE_CUTOFF +302 0x0000 //RX_BWE_GAINFILL +303 0x0000 //RX_BWE_MAXTH_TONE +304 0x0000 //RX_BWE_EQ_0 +305 0x0000 //RX_BWE_EQ_1 +306 0x0000 //RX_BWE_EQ_2 +307 0x0000 //RX_BWE_EQ_3 +308 0x0000 //RX_BWE_EQ_4 +309 0x0000 //RX_BWE_EQ_5 +310 0x0000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + +#CASE_NAME HEADSET-TTY_FULL-VOICE_GENERIC-FB +#PARAM_MODE Full +#PARAM_TYPE TX+2RX +#TOTAL_CUSTOM_STEP 7+7 +#TX +0 0x0001 //TX_OPERATION_MODE_0 +1 0x0000 //TX_OPERATION_MODE_1 +2 0x0000 //TX_PATCH_REG +3 0x0200 //TX_SENDFUNC_MODE_0 +4 0x0000 //TX_SENDFUNC_MODE_1 +5 0x0001 //TX_NUM_MIC +6 0x0000 //TX_SAMPLINGFREQ_SIG +7 0x0000 //TX_SAMPLINGFREQ_PROC +8 0x000A //TX_FRAME_SZ_SIG +9 0x000A //TX_FRAME_SZ +10 0x0000 //TX_DELAY_OPT +11 0x0028 //TX_MAX_TAIL_LENGTH +12 0x0001 //TX_NUM_LOUTCHN +13 0x0001 //TX_MAXNUM_AECREF +14 0x0000 //TX_DBG_FUNC_REG +15 0x0000 //TX_DBG_FUNC_REG1 +16 0x0000 //TX_SYS_RESRV_0 +17 0x0000 //TX_SYS_RESRV_1 +18 0x0000 //TX_SYS_RESRV_2 +19 0x0000 //TX_SYS_RESRV_3 +20 0x0000 //TX_DIST2REF0 +21 0x0078 //TX_DIST2REF1 +22 0x0000 //TX_DIST2REF_02 +23 0x0000 //TX_DIST2REF_03 +24 0x0000 //TX_DIST2REF_04 +25 0x0000 //TX_DIST2REF_05 +26 0x0000 //TX_MMIC +27 0x0302 //TX_PGA_0 +28 0x0800 //TX_PGA_1 +29 0x0800 //TX_PGA_2 +30 0x0000 //TX_PGA_3 +31 0x0000 //TX_PGA_4 +32 0x0000 //TX_PGA_5 +33 0x0000 //TX_MIC_PAIRS +34 0x0000 //TX_MIC_PAIRS_HS +35 0x0000 //TX_MICS_FOR_BF +36 0x0000 //TX_MIC_PAIRS_FORL1 +37 0x0000 //TX_MICS_OF_PAIR0 +38 0x0000 //TX_MICS_OF_PAIR1 +39 0x0000 //TX_MICS_OF_PAIR2 +40 0x0000 //TX_MICS_OF_PAIR3 +41 0x0000 //TX_MIC_DATA_SRC0 +42 0x0001 //TX_MIC_DATA_SRC1 +43 0x0002 //TX_MIC_DATA_SRC2 +44 0x0003 //TX_MIC_DATA_SRC3 +45 0x0000 //TX_MIC_PAIR_CH_04 +46 0x0000 //TX_MIC_PAIR_CH_05 +47 0x0000 //TX_MIC_PAIR_CH_10 +48 0x0000 //TX_MIC_PAIR_CH_11 +49 0x0000 //TX_MIC_PAIR_CH_12 +50 0x0000 //TX_MIC_PAIR_CH_13 +51 0x0000 //TX_MIC_PAIR_CH_14 +52 0x0000 //TX_HD_BIN_MASK +53 0x0000 //TX_HD_SUBAND_MASK +54 0x0000 //TX_HD_FRAME_AVG_MASK +55 0x0000 //TX_HD_MIN_FRQ +56 0x0000 //TX_HD_ALPHA_PSD +57 0x0000 //TX_T_PHPR1 +58 0x0000 //TX_T_PHPR2 +59 0x0000 //TX_T_PTPR +60 0x0000 //TX_T_PNPR +61 0x0000 //TX_T_PAPR1 +62 0x0000 //TX_T_PSDVAT +63 0x0000 //TX_CNT +64 0x0000 //TX_ANTI_HOWL_GAIN +65 0x0000 //TX_MICFORBFMARK_0 +66 0x0000 //TX_MICFORBFMARK_1 +67 0x0000 //TX_MICFORBFMARK_2 +68 0x0000 //TX_MICFORBFMARK_3 +69 0x0000 //TX_MICFORBFMARK_4 +70 0x0000 //TX_MICFORBFMARK_5 +71 0x0000 //TX_DIST2REF_10 +72 0x0000 //TX_DIST2REF_11 +73 0x0000 //TX_DIST2REF2 +74 0x0000 //TX_DIST2REF_13 +75 0x0000 //TX_DIST2REF_14 +76 0x0000 //TX_DIST2REF_15 +77 0x0000 //TX_DIST2REF_20 +78 0x0000 //TX_DIST2REF_21 +79 0x0000 //TX_DIST2REF_22 +80 0x0000 //TX_DIST2REF_23 +81 0x0000 //TX_DIST2REF_24 +82 0x0000 //TX_DIST2REF_25 +83 0x0000 //TX_DIST2REF_30 +84 0x0000 //TX_DIST2REF_31 +85 0x0000 //TX_DIST2REF_32 +86 0x0000 //TX_DIST2REF_33 +87 0x0000 //TX_DIST2REF_34 +88 0x0000 //TX_DIST2REF_35 +89 0x0000 //TX_MIC_LOC_00 +90 0x0000 //TX_MIC_LOC_01 +91 0x0000 //TX_MIC_LOC_02 +92 0x0000 //TX_MIC_LOC_03 +93 0x0000 //TX_MIC_LOC_04 +94 0x0000 //TX_MIC_LOC_05 +95 0x0000 //TX_MIC_LOC_10 +96 0x0000 //TX_MIC_LOC_11 +97 0x0000 //TX_MIC_LOC_12 +98 0x0000 //TX_MIC_LOC_13 +99 0x0000 //TX_MIC_LOC_14 +100 0x0000 //TX_MIC_LOC_15 +101 0x0000 //TX_MIC_LOC_20 +102 0x0000 //TX_MIC_LOC_21 +103 0x0000 //TX_MIC_LOC_22 +104 0x0000 //TX_MIC_LOC_23 +105 0x0000 //TX_MIC_LOC_24 +106 0x0000 //TX_MIC_LOC_25 +107 0x0800 //TX_MIC_REFBLK_VOLUME +108 0x0800 //TX_MIC_BLOCK_VOLUME +109 0x0000 //TX_INVERSE_MASK +110 0x0000 //TX_ADCS_MASK +111 0x0000 //TX_ADCS_GAIN +112 0x0000 //TX_NFC_GAINFAC +113 0x0000 //TX_MAINMIC_BLKFACTOR +114 0x0000 //TX_REFMIC_BLKFACTOR +115 0x7FFF //TX_BLMIC_BLKFACTOR +116 0x7FFF //TX_BRMIC_BLKFACTOR +117 0x000A //TX_MICBLK_START_BIN +118 0x0041 //TX_MICBLK_END_BIN +119 0x0015 //TX_MICBLK_FE_HOLD +120 0xFFF2 //TX_MICBLK_MR_EXP_TH +121 0xFFF2 //TX_MICBLK_LR_EXP_TH +122 0x0015 //TX_FENE_HOLD +123 0x0000 //TX_FE_ENER_TH_MTS +124 0x0000 //TX_FE_ENER_TH_EXP +125 0x0000 //TX_C_POST_FLT_MIC_MAINBLK +126 0x0000 //TX_C_POST_FLT_MIC_REFBLK +127 0x0020 //TX_MIC_BLOCK_N +128 0x7652 //TX_A_HP +129 0x4000 //TX_B_PE +130 0x7800 //TX_THR_PITCH_DET_0 +131 0x7000 //TX_THR_PITCH_DET_1 +132 0x6000 //TX_THR_PITCH_DET_2 +133 0x0000 //TX_PITCH_BFR_LEN +134 0x0000 //TX_SBD_PITCH_DET +135 0x0000 //TX_TD_AEC_L +136 0x0000 //TX_MU0_UNP_TD_AEC +137 0x0000 //TX_MU0_PTD_TD_AEC +138 0x0000 //TX_PP_RESRV_0 +139 0x2A94 //TX_PP_RESRV_1 +140 0x55F0 //TX_PP_RESRV_2 +141 0x0000 //TX_PP_RESRV_3 +142 0x0000 //TX_PP_RESRV_4 +143 0x0000 //TX_PP_RESRV_5 +144 0x0000 //TX_PP_RESRV_6 +145 0x0000 //TX_PP_RESRV_7 +146 0x0028 //TX_TAIL_LENGTH +147 0x2000 //TX_AEC_REF_GAIN_0 +148 0x2000 //TX_AEC_REF_GAIN_1 +149 0x2000 //TX_AEC_REF_GAIN_2 +150 0x4000 //TX_EAD_THR +151 0x0200 //TX_THR_RE_EST +152 0x0100 //TX_MIN_EQ_RE_EST_0 +153 0x0100 //TX_MIN_EQ_RE_EST_1 +154 0x0100 //TX_MIN_EQ_RE_EST_2 +155 0x0100 //TX_MIN_EQ_RE_EST_3 +156 0x0100 //TX_MIN_EQ_RE_EST_4 +157 0x0100 //TX_MIN_EQ_RE_EST_5 +158 0x0100 //TX_MIN_EQ_RE_EST_6 +159 0x0100 //TX_MIN_EQ_RE_EST_7 +160 0x0100 //TX_MIN_EQ_RE_EST_8 +161 0x0100 //TX_MIN_EQ_RE_EST_9 +162 0x0100 //TX_MIN_EQ_RE_EST_10 +163 0x0100 //TX_MIN_EQ_RE_EST_11 +164 0x0100 //TX_MIN_EQ_RE_EST_12 +165 0x4000 //TX_LAMBDA_RE_EST +166 0x0000 //TX_LAMBDA_CB_NLE +167 0x0000 //TX_C_POST_FLT +168 0x4000 //TX_GAIN_NP +169 0x0008 //TX_SE_HOLD_N +170 0x0050 //TX_DT_HOLD_N +171 0x03E8 //TX_DT2_HOLD_N +172 0x0000 //TX_AEC_RESRV_0 +173 0x0000 //TX_AEC_RESRV_1 +174 0x0014 //TX_AEC_RESRV_2 +175 0x0000 //TX_MIC_DELAY_LENGTH +176 0x0000 //TX_REF_DELAY_LENGTH +177 0x0000 //TX_ADD_LINEIN_GAINL +178 0x0000 //TX_ADD_LINEIN_GAINH +179 0x0000 //TX_MIN_EQ_RE_EST_14 +180 0x0000 //TX_DTD_THR1_8 +181 0x0000 //TX_DTD_THR2_8 +182 0x0000 //TX_DTD_MIC_BLK2 +183 0x0000 //TX_FRQ_LIN_LEN +184 0x0000 //TX_FRQ_AEC_LEN_RHO +185 0x0000 //TX_MU0_UNP_FRQ_AEC +186 0x0000 //TX_MU0_PTD_FRQ_AEC +187 0x0000 //TX_MINENOISETH +188 0x0000 //TX_MU0_RE_EST +189 0x0000 //TX_AEC_NUM_CH +190 0x0000 //TX_BIGECHOATTENUATION_MAX +191 0x0000 //TX_A_POST_FLT_MICBLK +192 0x0000 //TX_BLKENERTH +193 0x0000 //TX_BLKENERHIGHTH +194 0x0000 //TX_NORMENERTH +195 0x0000 //TX_NORMENERHIGHTH +196 0x0000 //TX_NORMENERHIGHTHL +197 0x7333 //TX_DTD_THR1_0 +198 0x7333 //TX_DTD_THR1_1 +199 0x7333 //TX_DTD_THR1_2 +200 0x7333 //TX_DTD_THR1_3 +201 0x7333 //TX_DTD_THR1_4 +202 0x7333 //TX_DTD_THR1_5 +203 0x7333 //TX_DTD_THR1_6 +204 0x0CCD //TX_DTD_THR2_0 +205 0x0CCD //TX_DTD_THR2_1 +206 0x0CCD //TX_DTD_THR2_2 +207 0x0CCD //TX_DTD_THR2_3 +208 0x0CCD //TX_DTD_THR2_4 +209 0x0CCD //TX_DTD_THR2_5 +210 0x0CCD //TX_DTD_THR2_6 +211 0x7FFF //TX_DTD_THR3 +212 0x0000 //TX_SPK_CUT_K +213 0x0400 //TX_DT_CUT_K +214 0x0000 //TX_DT_CUT_THR +215 0x0000 //TX_COMFORT_G +216 0x0000 //TX_POWER_YOUT_TH +217 0x0000 //TX_FDPFGAINECHO +218 0x0000 //TX_DTD_HD_THR +219 0x0000 //TX_SPK_CUT_K_S +220 0x0000 //TX_DTD_MIC_BLK +221 0x0400 //TX_ADPT_STRICT_L +222 0x0200 //TX_ADPT_STRICT_H +223 0x0BB8 //TX_RATIO_DT_L_TH_LOW +224 0x3A98 //TX_RATIO_DT_H_TH_LOW +225 0x1770 //TX_RATIO_DT_L_TH_HIGH +226 0x4E20 //TX_RATIO_DT_H_TH_HIGH +227 0x09C4 //TX_RATIO_DT_L0_TH +228 0x0800 //TX_B_POST_FILT_ECHO_L +229 0x0800 //TX_B_POST_FILT_ECHO_H +230 0x0000 //TX_MIN_G_CTRL_ECHO +231 0x7FFF //TX_B_LESSCUT_RTO_ECHO +232 0x0000 //TX_EPD_OFFSET_00 +233 0x0000 //TX_EPD_OFFST_01 +234 0x1388 //TX_RATIO_DT_L0_TH_HIGH +235 0x3A98 //TX_RATIO_DT_H_TH_CUT +236 0x0000 //TX_MIN_EQ_RE_EST_13 +237 0x0000 //TX_DTD_THR1_7 +238 0x0000 //TX_DTD_THR2_7 +239 0x0000 //TX_DT_RESRV_7 +240 0x0000 //TX_DT_RESRV_8 +241 0x0000 //TX_DT_RESRV_9 +242 0xF700 //TX_THR_SN_EST_0 +243 0xF400 //TX_THR_SN_EST_1 +244 0xF800 //TX_THR_SN_EST_2 +245 0xF600 //TX_THR_SN_EST_3 +246 0xF800 //TX_THR_SN_EST_4 +247 0xF800 //TX_THR_SN_EST_5 +248 0xF800 //TX_THR_SN_EST_6 +249 0xF800 //TX_THR_SN_EST_7 +250 0x0100 //TX_DELTA_THR_SN_EST_0 +251 0x0100 //TX_DELTA_THR_SN_EST_1 +252 0x0100 //TX_DELTA_THR_SN_EST_2 +253 0x0200 //TX_DELTA_THR_SN_EST_3 +254 0x0200 //TX_DELTA_THR_SN_EST_4 +255 0x0200 //TX_DELTA_THR_SN_EST_5 +256 0x0000 //TX_DELTA_THR_SN_EST_6 +257 0x0200 //TX_DELTA_THR_SN_EST_7 +258 0x4000 //TX_LAMBDA_NN_EST_0 +259 0x4000 //TX_LAMBDA_NN_EST_1 +260 0x4000 //TX_LAMBDA_NN_EST_2 +261 0x4000 //TX_LAMBDA_NN_EST_3 +262 0x4000 //TX_LAMBDA_NN_EST_4 +263 0x4000 //TX_LAMBDA_NN_EST_5 +264 0x4000 //TX_LAMBDA_NN_EST_6 +265 0x4000 //TX_LAMBDA_NN_EST_7 +266 0x0A00 //TX_N_SN_EST +267 0x0000 //TX_INBEAM_T +268 0x0000 //TX_INBEAMHOLDT +269 0x1FFF //TX_G_STRICT +270 0x2000 //TX_EQ_THR_BF +271 0x799A //TX_LAMBDA_EQ_BF +272 0x1000 //TX_NE_RTO_TH +273 0x1000 //TX_NE_RTO_TH_L +274 0x1000 //TX_MAINREFRTOH_TH_H +275 0x1000 //TX_MAINREFRTOH_TH_L +276 0x2000 //TX_MAINREFRTO_TH_H +277 0x1400 //TX_MAINREFRTO_TH_L +278 0x0200 //TX_MAINREFRTO_TH_EQ +279 0x0000 //TX_B_POST_FLT_0 +280 0x0000 //TX_B_POST_FLT_1 +281 0x001A //TX_NS_LVL_CTRL_0 +282 0x0014 //TX_NS_LVL_CTRL_1 +283 0x0014 //TX_NS_LVL_CTRL_2 +284 0x000C //TX_NS_LVL_CTRL_3 +285 0x000C //TX_NS_LVL_CTRL_4 +286 0x000C //TX_NS_LVL_CTRL_5 +287 0x001A //TX_NS_LVL_CTRL_6 +288 0x000C //TX_NS_LVL_CTRL_7 +289 0x000E //TX_MIN_GAIN_S_0 +290 0x0014 //TX_MIN_GAIN_S_1 +291 0x0014 //TX_MIN_GAIN_S_2 +292 0x0014 //TX_MIN_GAIN_S_3 +293 0x0014 //TX_MIN_GAIN_S_4 +294 0x0014 //TX_MIN_GAIN_S_5 +295 0x0014 //TX_MIN_GAIN_S_6 +296 0x0014 //TX_MIN_GAIN_S_7 +297 0x0000 //TX_NMOS_SUP +298 0x0064 //TX_NS_MAX_PRI_SNR_TH +299 0x7FFF //TX_NMOS_SUP_MENSA +300 0x7FFF //TX_SNRI_SUP_0 +301 0x7FFF //TX_SNRI_SUP_1 +302 0x7FFF //TX_SNRI_SUP_2 +303 0x4000 //TX_SNRI_SUP_3 +304 0x4000 //TX_SNRI_SUP_4 +305 0x4000 //TX_SNRI_SUP_5 +306 0x7FFF //TX_SNRI_SUP_6 +307 0x4000 //TX_SNRI_SUP_7 +308 0x1200 //TX_THR_LFNS +309 0x0147 //TX_G_LFNS +310 0x09C4 //TX_GAIN0_NTH +311 0x7FFF //TX_MUSIC_MORENS +312 0x7FFF //TX_A_POST_FILT_0 +313 0x7FFF //TX_A_POST_FILT_1 +314 0x4000 //TX_A_POST_FILT_S_0 +315 0x1000 //TX_A_POST_FILT_S_1 +316 0x1000 //TX_A_POST_FILT_S_2 +317 0x6666 //TX_A_POST_FILT_S_3 +318 0x6666 //TX_A_POST_FILT_S_4 +319 0x6666 //TX_A_POST_FILT_S_5 +320 0x199A //TX_A_POST_FILT_S_6 +321 0x6666 //TX_A_POST_FILT_S_7 +322 0x2000 //TX_B_POST_FILT_0 +323 0x2000 //TX_B_POST_FILT_1 +324 0x2000 //TX_B_POST_FILT_2 +325 0x2000 //TX_B_POST_FILT_3 +326 0x2000 //TX_B_POST_FILT_4 +327 0x2000 //TX_B_POST_FILT_5 +328 0x2000 //TX_B_POST_FILT_6 +329 0x2000 //TX_B_POST_FILT_7 +330 0x7FFF //TX_B_LESSCUT_RTO_S_0 +331 0x7FFF //TX_B_LESSCUT_RTO_S_1 +332 0x7FFF //TX_B_LESSCUT_RTO_S_2 +333 0x7FFF //TX_B_LESSCUT_RTO_S_3 +334 0x7FFF //TX_B_LESSCUT_RTO_S_4 +335 0x7FFF //TX_B_LESSCUT_RTO_S_5 +336 0x7FFF //TX_B_LESSCUT_RTO_S_6 +337 0x7FFF //TX_B_LESSCUT_RTO_S_7 +338 0x7E00 //TX_LAMBDA_PFILT +339 0x7E00 //TX_LAMBDA_PFILT_S_0 +340 0x7E00 //TX_LAMBDA_PFILT_S_1 +341 0x7E00 //TX_LAMBDA_PFILT_S_2 +342 0x7E00 //TX_LAMBDA_PFILT_S_3 +343 0x7E00 //TX_LAMBDA_PFILT_S_4 +344 0x7E00 //TX_LAMBDA_PFILT_S_5 +345 0x7E00 //TX_LAMBDA_PFILT_S_6 +346 0x7E00 //TX_LAMBDA_PFILT_S_7 +347 0x0010 //TX_K_PEPPER +348 0x0400 //TX_A_PEPPER +349 0x0000 //TX_K_PEPPER_HF +350 0x0000 //TX_A_PEPPER_HF +351 0x0001 //TX_HMNC_BST_FLG +352 0x4000 //TX_HMNC_BST_THR +353 0x0000 //TX_DT_BINVAD_TH_0 +354 0x0000 //TX_DT_BINVAD_TH_1 +355 0x0000 //TX_DT_BINVAD_TH_2 +356 0x0000 //TX_DT_BINVAD_TH_3 +357 0x0000 //TX_DT_BINVAD_ENDF +358 0x0000 //TX_C_POST_FLT_DT +359 0x0CCD //TX_NS_B_POST_FLT_LESSCUT +360 0x0100 //TX_DT_BOOST +361 0x0001 //TX_BF_SGRAD_FLG +362 0x0000 //TX_BF_DVG_TH +363 0x0000 //TX_SN_C_F +364 0x0000 //TX_K_APT +365 0x0001 //TX_NOISEDET +366 0x05A0 //TX_NDETCT +367 0x04E8 //TX_NOISE_TH_0 +368 0x1388 //TX_NOISE_TH_0_2 +369 0x3A98 //TX_NOISE_TH_0_3 +370 0x0C80 //TX_NOISE_TH_1 +371 0x0032 //TX_NOISE_TH_2 +372 0x3D54 //TX_NOISE_TH_3 +373 0x012C //TX_NOISE_TH_4 +374 0x07D0 //TX_NOISE_TH_5 +375 0x6590 //TX_NOISE_TH_5_2 +376 0x7FFF //TX_NOISE_TH_5_3 +377 0x7FFF //TX_NOISE_TH_5_4 +378 0x00C8 //TX_NOISE_TH_6 +379 0x02BC //TX_MINENOISE_TH +380 0xD508 //TX_MORENS_TFMASK_TH +381 0x0001 //TX_DRC_QUIET_FLOOR +382 0x3A98 //TX_RATIODTL_CUT_TH +383 0x1482 //TX_DT_CUT_K1 +384 0x6400 //TX_OUT_ENER_S_TH_CLEAN +385 0x6400 //TX_OUT_ENER_S_TH_LESSCLEAN +386 0x6400 //TX_OUT_ENER_S_TH_NOISY +387 0x6400 //TX_OUT_ENER_TH_NOISE +388 0x7D00 //TX_OUT_ENER_TH_SPEECH +389 0x0000 //TX_SN_NPB_GAIN +390 0x0000 //TX_NN_NPB_GAIN +391 0x7FFF //TX_POST_MASK_SUP_HSNE +392 0x1388 //TX_TAIL_DET_TH +393 0x4000 //TX_B_LESSCUT_RTO_WTA +394 0x0000 //TX_MEL_G_R +395 0x0080 //TX_SUPHIGH_TH +396 0x0000 //TX_MASK_G_R +397 0x0000 //TX_EXTRA_NS_L +398 0x1800 //TX_C_POST_FLT_MASK +399 0x7FFF //TX_A_POST_FLT_WNS +400 0x0000 //TX_MIN_G_LOW300HZ +401 0x0010 //TX_MAXLEVEL_CNG +402 0x0000 //TX_STN_NOISE_TH +403 0x0000 //TX_POST_MASK_SUP +404 0x0000 //TX_POST_MASK_ADJUST +405 0x0014 //TX_NS_ENOISE_MIC0_TH +406 0x04E7 //TX_MINENOISE_MIC0_TH +407 0x0226 //TX_MINENOISE_MIC0_S_TH +408 0x2879 //TX_MIN_G_CTRL_SSNS +409 0x0400 //TX_METAL_RTO_THR +410 0x0080 //TX_NS_FP_K_METAL +411 0x3A98 //TX_NOISEDET_BOOST_TH +412 0x0FA0 //TX_NSMOOTH_TH +413 0x0000 //TX_NS_RESRV_8 +414 0x2000 //TX_RHO_UPB +415 0x0020 //TX_N_HOLD_HS +416 0x0009 //TX_N_RHO_BFR0 +417 0x7FFF //TX_LAMBDA_ARSP_EST +418 0x0000 //TX_EXTRA_GAIN_MICBLOCK +419 0x0333 //TX_THR_STD_NSR +420 0x0219 //TX_THR_STD_PLH +421 0x09C4 //TX_N_HOLD_STD +422 0x0166 //TX_THR_STD_RHO +423 0x2000 //TX_BF_RESET_THR_HS +424 0x09C4 //TX_SB_RTO_MEAN_TH +425 0x0800 //TX_SB_RHO_MEAN_TH_NTALK +426 0x3800 //TX_SB_RTO_MEAN_TH_ABN +427 0x0000 //TX_SB_RTO_MEAN_TH_RUB +428 0x2000 //TX_WTA_EN_RTO_TH +429 0x1400 //TX_TOP_ENER_TH_F +430 0x0064 //TX_DESIRED_TALK_HOLDT +431 0x1000 //TX_MIC_BLOCK_FACTOR +432 0x0000 //TX_NSEST_BFRLRNRDC +433 0x0000 //TX_THR_POST_FLT_HS +434 0x0000 //TX_HS_VAD_BIN +435 0x0000 //TX_THR_VAD_HS +436 0x0000 //TX_MEAN_RTO_MIN_TH2 +437 0x0000 //TX_SILENCE_T +438 0x4000 //TX_A_POST_FLT_WTA +439 0x799A //TX_LAMBDA_PFLT_WTA +440 0x099A //TX_SB_RHO_MEAN2_TH +441 0x0190 //TX_SB_RHO_MEAN3_TH +442 0x0000 //TX_HS_RESRV_4 +443 0x0000 //TX_HS_RESRV_5 +444 0x001E //TX_DOA_VAD_THR_1 +445 0x001E //TX_DOA_VAD_THR_2 +446 0x0028 //TX_DOA_VAD_THR1_0 +447 0x0028 //TX_DOA_VAD_THR1_1 +448 0x0000 //TX_SRC_DOA_RNG_LOW_0A +449 0x00B4 //TX_SRC_DOA_RNG_HIGH_0A +450 0x005A //TX_DFLT_SRC_DOA_0A +451 0x0000 //TX_SRC_DOA_RNG_LOW_0B +452 0x00B4 //TX_SRC_DOA_RNG_HIGH_0B +453 0x005A //TX_DFLT_SRC_DOA_0B +454 0x0000 //TX_SRC_DOA_RNG_LOW_0C +455 0x00B4 //TX_SRC_DOA_RNG_HIGH_0C +456 0x005A //TX_DFLT_SRC_DOA_0C +457 0x0000 //TX_SRC_DOA_RNG_LOW_0D +458 0x00B4 //TX_SRC_DOA_RNG_HIGH_0D +459 0x005A //TX_DFLT_SRC_DOA_0D +460 0x0000 //TX_SRC_DOA_RNG_LOW_1A +461 0x00B4 //TX_SRC_DOA_RNG_HIGH_1A +462 0x005A //TX_DFLT_SRC_DOA_1A +463 0x0000 //TX_SRC_DOA_RNG_LOW_1B +464 0x00B4 //TX_SRC_DOA_RNG_HIGH_1B +465 0x005A //TX_DFLT_SRC_DOA_1B +466 0x0000 //TX_SRC_DOA_RNG_LOW_1C +467 0x00B4 //TX_SRC_DOA_RNG_HIGH_1C +468 0x005A //TX_DFLT_SRC_DOA_1C +469 0x0000 //TX_SRC_DOA_RNG_LOW_1D +470 0x00B4 //TX_SRC_DOA_RNG_HIGH_1D +471 0x005A //TX_DFLT_SRC_DOA_1D +472 0x0172 //TX_BF_HOLDOFF_T +473 0x8000 //TX_DOA_COST_FACTOR +474 0x0D9A //TX_MAINTOREFR_TH0 +475 0x071C //TX_DOA_TRK_THR +476 0x071C //TX_DOA_TRACK_HT +477 0x0280 //TX_N1_HOLD_HF +478 0x0140 //TX_N2_HOLD_HF +479 0x2AAB //TX_BF_RESET_THR_HF +480 0x4000 //TX_DOA_SMOOTH +481 0x0000 //TX_MU_BF +482 0x0200 //TX_BF_MU_LF_B2 +483 0x0000 //TX_BF_FC_END_BIN_B2 +484 0x0000 //TX_BF_FC_END_BIN +485 0x0000 //TX_HF_RESRV_25 +486 0x0000 //TX_HF_RESRV_26 +487 0x0000 //TX_N_DOA_SEED +488 0x0000 //TX_FINE_DOA_SEARCH_FLG +489 0x0000 //TX_HF_RESRV_27 +490 0x0000 //TX_DLT_SRC_DOA_RNG +491 0x0200 //TX_BF_MU_LF +492 0x0000 //TX_DFLT_SRC_LOC_0 +493 0x0000 //TX_DFLT_SRC_LOC_1 +494 0x0000 //TX_DFLT_SRC_LOC_2 +495 0x0000 //TX_DOA_TRACK_VADTH +496 0x0000 //TX_DOA_TRACK_NEW +497 0x0168 //TX_NOR_OFF_THR +498 0x0CCD //TX_MORE_ON_700HZ_THR +499 0x2000 //TX_MU_BF_ADPT_NS +500 0x0004 //TX_ADAPT_LEN +501 0x6666 //TX_MORE_SNS +502 0x0230 //TX_NOR_OFF_TH1 +503 0xD333 //TX_WIDE_MASK_TH +504 0x4650 //TX_SUBSNRATIOHIGH4MEANBCK_THR +505 0x6000 //TX_C_POST_FLT_CUT +506 0x2000 //TX_RADIODTLV +507 0x0320 //TX_POWER_LINEIN_TH +508 0x0014 //TX_FE_VADCOUNT_TH_FC +509 0x000A //TX_ECHO_SUPP_FC +510 0x0C80 //TX_ECHO_TH +511 0x6666 //TX_MIC_TO_BFGAIN +512 0x6666 //TX_MICTOBFGAIN0 +513 0x0014 //TX_FASTMUE_TH +514 0xC000 //TX_DEREVERB_LF_MU +515 0xC000 //TX_DEREVERB_HF_MU +516 0xCCCC //TX_DEREVERB_DELAY +517 0xD999 //TX_DEREVERB_COEF_LEN +518 0x1F40 //TX_DEREVERB_DNR +519 0x0000 //TX_DEREVERB_ALPHA +520 0x0000 //TX_DEREVERB_BETA +521 0x0000 //TX_GSC_RTOL_TH +522 0x7000 //TX_GSC_RTOH_TH +523 0x0064 //TX_WIDE2_MEANHTH +524 0x0000 //TX_DR_RESRV_5 +525 0x0000 //TX_DR_RESRV_6 +526 0x0000 //TX_DR_RESRV_7 +527 0x0000 //TX_DR_RESRV_8 +528 0x0000 //TX_WIND_MARK_TH +529 0x399A //TX_CORR_THR +530 0x0028 //TX_SNR_THR +531 0x03E8 //TX_ENGY_THR +532 0x0000 //TX_CORR_HIGH_TH +533 0x0000 //TX_ENGY_THR_2 +534 0x0000 //TX_MEAN_RTO_THR +535 0x0000 //TX_WNS_ENOISE_MIC0_TH +536 0x0000 //TX_RATIOMICL_TH +537 0x0000 //TX_CALIG_HS +538 0x000A //TX_LVL_CTRL +539 0x0000 //TX_WIND_SUPRTO +540 0x0000 //TX_WNS_MIN_G +541 0x0000 //TX_WNS_B_POST_FLT +542 0x0000 //TX_RATIOMICH_TH +543 0x0000 //TX_WIND_INBEAM_L_TH +544 0x0000 //TX_WIND_INBEAM_H_TH +545 0x0000 //TX_WNS_RESRV_0 +546 0x0000 //TX_WNS_RESRV_1 +547 0x0000 //TX_WNS_RESRV_2 +548 0x0000 //TX_WNS_RESRV_3 +549 0x0000 //TX_WNS_RESRV_4 +550 0x0000 //TX_WNS_RESRV_5 +551 0x0000 //TX_WNS_RESRV_6 +552 0x0000 //TX_PB_B_POST_FLT_LESSCUT +553 0x0000 //TX_BF_LESSCUT_BBIN +554 0x0000 //TX_BF_LESSCUT_EBIN +555 0x0000 //TX_POSTBFB0 +556 0x0000 //TX_POSTBFB +557 0x0000 //TX_POSTBFE +558 0x0000 //TX_SPEECH_SNR_TH +559 0x0000 //TX_PB_MAX_PRI_SNR_TH +560 0x0000 //TX_MAX_PRI_SNR_TH_L +561 0x0000 //TX_PFGAIN +562 0x0000 //TX_MAINTOREFR_TH +563 0x0000 //TX_SAM_MARK +564 0x0000 //TX_PB_RESRV_0 +565 0x0000 //TX_PB_RESRV_1 +566 0x0020 //TX_FDEQ_SUBNUM +567 0x4848 //TX_FDEQ_GAIN_0 +568 0x4848 //TX_FDEQ_GAIN_1 +569 0x4848 //TX_FDEQ_GAIN_2 +570 0x4848 //TX_FDEQ_GAIN_3 +571 0x4848 //TX_FDEQ_GAIN_4 +572 0x4848 //TX_FDEQ_GAIN_5 +573 0x4848 //TX_FDEQ_GAIN_6 +574 0x4848 //TX_FDEQ_GAIN_7 +575 0x4848 //TX_FDEQ_GAIN_8 +576 0x4848 //TX_FDEQ_GAIN_9 +577 0x4848 //TX_FDEQ_GAIN_10 +578 0x4848 //TX_FDEQ_GAIN_11 +579 0x4848 //TX_FDEQ_GAIN_12 +580 0x4848 //TX_FDEQ_GAIN_13 +581 0x4848 //TX_FDEQ_GAIN_14 +582 0x4848 //TX_FDEQ_GAIN_15 +583 0x4848 //TX_FDEQ_GAIN_16 +584 0x4848 //TX_FDEQ_GAIN_17 +585 0x4848 //TX_FDEQ_GAIN_18 +586 0x4848 //TX_FDEQ_GAIN_19 +587 0x4848 //TX_FDEQ_GAIN_20 +588 0x4848 //TX_FDEQ_GAIN_21 +589 0x4848 //TX_FDEQ_GAIN_22 +590 0x4848 //TX_FDEQ_GAIN_23 +591 0x0000 //TX_FDEQ_BIN_0 +592 0x0000 //TX_FDEQ_BIN_1 +593 0x0000 //TX_FDEQ_BIN_2 +594 0x0000 //TX_FDEQ_BIN_3 +595 0x0000 //TX_FDEQ_BIN_4 +596 0x0000 //TX_FDEQ_BIN_5 +597 0x0000 //TX_FDEQ_BIN_6 +598 0x0000 //TX_FDEQ_BIN_7 +599 0x0000 //TX_FDEQ_BIN_8 +600 0x0000 //TX_FDEQ_BIN_9 +601 0x0000 //TX_FDEQ_BIN_10 +602 0x0000 //TX_FDEQ_BIN_11 +603 0x0000 //TX_FDEQ_BIN_12 +604 0x0000 //TX_FDEQ_BIN_13 +605 0x0000 //TX_FDEQ_BIN_14 +606 0x0000 //TX_FDEQ_BIN_15 +607 0x0000 //TX_FDEQ_BIN_16 +608 0x0000 //TX_FDEQ_BIN_17 +609 0x0000 //TX_FDEQ_BIN_18 +610 0x0000 //TX_FDEQ_BIN_19 +611 0x0000 //TX_FDEQ_BIN_20 +612 0x0000 //TX_FDEQ_BIN_21 +613 0x0000 //TX_FDEQ_BIN_22 +614 0x0000 //TX_FDEQ_BIN_23 +615 0x0000 //TX_FDEQ_PADDING +616 0x0020 //TX_PREEQ_SUBNUM_MIC0 +617 0x4848 //TX_PREEQ_GAIN_MIC0_0 +618 0x4848 //TX_PREEQ_GAIN_MIC0_1 +619 0x4848 //TX_PREEQ_GAIN_MIC0_2 +620 0x4848 //TX_PREEQ_GAIN_MIC0_3 +621 0x4848 //TX_PREEQ_GAIN_MIC0_4 +622 0x4848 //TX_PREEQ_GAIN_MIC0_5 +623 0x4848 //TX_PREEQ_GAIN_MIC0_6 +624 0x4848 //TX_PREEQ_GAIN_MIC0_7 +625 0x4848 //TX_PREEQ_GAIN_MIC0_8 +626 0x4848 //TX_PREEQ_GAIN_MIC0_9 +627 0x4848 //TX_PREEQ_GAIN_MIC0_10 +628 0x4848 //TX_PREEQ_GAIN_MIC0_11 +629 0x4848 //TX_PREEQ_GAIN_MIC0_12 +630 0x4848 //TX_PREEQ_GAIN_MIC0_13 +631 0x4848 //TX_PREEQ_GAIN_MIC0_14 +632 0x4848 //TX_PREEQ_GAIN_MIC0_15 +633 0x4848 //TX_PREEQ_GAIN_MIC0_16 +634 0x4848 //TX_PREEQ_GAIN_MIC0_17 +635 0x4848 //TX_PREEQ_GAIN_MIC0_18 +636 0x4848 //TX_PREEQ_GAIN_MIC0_19 +637 0x4848 //TX_PREEQ_GAIN_MIC0_20 +638 0x4848 //TX_PREEQ_GAIN_MIC0_21 +639 0x4848 //TX_PREEQ_GAIN_MIC0_22 +640 0x4848 //TX_PREEQ_GAIN_MIC0_23 +641 0x0000 //TX_PREEQ_BIN_MIC0_0 +642 0x0000 //TX_PREEQ_BIN_MIC0_1 +643 0x0000 //TX_PREEQ_BIN_MIC0_2 +644 0x0000 //TX_PREEQ_BIN_MIC0_3 +645 0x0000 //TX_PREEQ_BIN_MIC0_4 +646 0x0000 //TX_PREEQ_BIN_MIC0_5 +647 0x0000 //TX_PREEQ_BIN_MIC0_6 +648 0x0000 //TX_PREEQ_BIN_MIC0_7 +649 0x0000 //TX_PREEQ_BIN_MIC0_8 +650 0x0000 //TX_PREEQ_BIN_MIC0_9 +651 0x0000 //TX_PREEQ_BIN_MIC0_10 +652 0x0000 //TX_PREEQ_BIN_MIC0_11 +653 0x0000 //TX_PREEQ_BIN_MIC0_12 +654 0x0000 //TX_PREEQ_BIN_MIC0_13 +655 0x0000 //TX_PREEQ_BIN_MIC0_14 +656 0x0000 //TX_PREEQ_BIN_MIC0_15 +657 0x0000 //TX_PREEQ_BIN_MIC0_16 +658 0x0000 //TX_PREEQ_BIN_MIC0_17 +659 0x0000 //TX_PREEQ_BIN_MIC0_18 +660 0x0000 //TX_PREEQ_BIN_MIC0_19 +661 0x0000 //TX_PREEQ_BIN_MIC0_20 +662 0x0000 //TX_PREEQ_BIN_MIC0_21 +663 0x0000 //TX_PREEQ_BIN_MIC0_22 +664 0x0000 //TX_PREEQ_BIN_MIC0_23 +665 0x0020 //TX_PREEQ_SUBNUM_MIC1 +666 0x4848 //TX_PREEQ_GAIN_MIC1_0 +667 0x4848 //TX_PREEQ_GAIN_MIC1_1 +668 0x4848 //TX_PREEQ_GAIN_MIC1_2 +669 0x4848 //TX_PREEQ_GAIN_MIC1_3 +670 0x4848 //TX_PREEQ_GAIN_MIC1_4 +671 0x4848 //TX_PREEQ_GAIN_MIC1_5 +672 0x4848 //TX_PREEQ_GAIN_MIC1_6 +673 0x4848 //TX_PREEQ_GAIN_MIC1_7 +674 0x4848 //TX_PREEQ_GAIN_MIC1_8 +675 0x4848 //TX_PREEQ_GAIN_MIC1_9 +676 0x4848 //TX_PREEQ_GAIN_MIC1_10 +677 0x4848 //TX_PREEQ_GAIN_MIC1_11 +678 0x4848 //TX_PREEQ_GAIN_MIC1_12 +679 0x4848 //TX_PREEQ_GAIN_MIC1_13 +680 0x4848 //TX_PREEQ_GAIN_MIC1_14 +681 0x4848 //TX_PREEQ_GAIN_MIC1_15 +682 0x4848 //TX_PREEQ_GAIN_MIC1_16 +683 0x4848 //TX_PREEQ_GAIN_MIC1_17 +684 0x4848 //TX_PREEQ_GAIN_MIC1_18 +685 0x4848 //TX_PREEQ_GAIN_MIC1_19 +686 0x4848 //TX_PREEQ_GAIN_MIC1_20 +687 0x4848 //TX_PREEQ_GAIN_MIC1_21 +688 0x4848 //TX_PREEQ_GAIN_MIC1_22 +689 0x4848 //TX_PREEQ_GAIN_MIC1_23 +690 0x0000 //TX_PREEQ_BIN_MIC1_0 +691 0x0000 //TX_PREEQ_BIN_MIC1_1 +692 0x0000 //TX_PREEQ_BIN_MIC1_2 +693 0x0000 //TX_PREEQ_BIN_MIC1_3 +694 0x0000 //TX_PREEQ_BIN_MIC1_4 +695 0x0000 //TX_PREEQ_BIN_MIC1_5 +696 0x0000 //TX_PREEQ_BIN_MIC1_6 +697 0x0000 //TX_PREEQ_BIN_MIC1_7 +698 0x0000 //TX_PREEQ_BIN_MIC1_8 +699 0x0000 //TX_PREEQ_BIN_MIC1_9 +700 0x0000 //TX_PREEQ_BIN_MIC1_10 +701 0x0000 //TX_PREEQ_BIN_MIC1_11 +702 0x0000 //TX_PREEQ_BIN_MIC1_12 +703 0x0000 //TX_PREEQ_BIN_MIC1_13 +704 0x0000 //TX_PREEQ_BIN_MIC1_14 +705 0x0000 //TX_PREEQ_BIN_MIC1_15 +706 0x0000 //TX_PREEQ_BIN_MIC1_16 +707 0x0000 //TX_PREEQ_BIN_MIC1_17 +708 0x0000 //TX_PREEQ_BIN_MIC1_18 +709 0x0000 //TX_PREEQ_BIN_MIC1_19 +710 0x0000 //TX_PREEQ_BIN_MIC1_20 +711 0x0000 //TX_PREEQ_BIN_MIC1_21 +712 0x0000 //TX_PREEQ_BIN_MIC1_22 +713 0x0000 //TX_PREEQ_BIN_MIC1_23 +714 0x0020 //TX_PREEQ_SUBNUM_MIC2 +715 0x4848 //TX_PREEQ_GAIN_MIC2_0 +716 0x4848 //TX_PREEQ_GAIN_MIC2_1 +717 0x4848 //TX_PREEQ_GAIN_MIC2_2 +718 0x4848 //TX_PREEQ_GAIN_MIC2_3 +719 0x4848 //TX_PREEQ_GAIN_MIC2_4 +720 0x4848 //TX_PREEQ_GAIN_MIC2_5 +721 0x4848 //TX_PREEQ_GAIN_MIC2_6 +722 0x4848 //TX_PREEQ_GAIN_MIC2_7 +723 0x4848 //TX_PREEQ_GAIN_MIC2_8 +724 0x4848 //TX_PREEQ_GAIN_MIC2_9 +725 0x4848 //TX_PREEQ_GAIN_MIC2_10 +726 0x4848 //TX_PREEQ_GAIN_MIC2_11 +727 0x4848 //TX_PREEQ_GAIN_MIC2_12 +728 0x4848 //TX_PREEQ_GAIN_MIC2_13 +729 0x4848 //TX_PREEQ_GAIN_MIC2_14 +730 0x4848 //TX_PREEQ_GAIN_MIC2_15 +731 0x4848 //TX_PREEQ_GAIN_MIC2_16 +732 0x4848 //TX_PREEQ_GAIN_MIC2_17 +733 0x4848 //TX_PREEQ_GAIN_MIC2_18 +734 0x4848 //TX_PREEQ_GAIN_MIC2_19 +735 0x4848 //TX_PREEQ_GAIN_MIC2_20 +736 0x4848 //TX_PREEQ_GAIN_MIC2_21 +737 0x4848 //TX_PREEQ_GAIN_MIC2_22 +738 0x4848 //TX_PREEQ_GAIN_MIC2_23 +739 0x0000 //TX_PREEQ_BIN_MIC2_0 +740 0x0000 //TX_PREEQ_BIN_MIC2_1 +741 0x0000 //TX_PREEQ_BIN_MIC2_2 +742 0x0000 //TX_PREEQ_BIN_MIC2_3 +743 0x0000 //TX_PREEQ_BIN_MIC2_4 +744 0x0000 //TX_PREEQ_BIN_MIC2_5 +745 0x0000 //TX_PREEQ_BIN_MIC2_6 +746 0x0000 //TX_PREEQ_BIN_MIC2_7 +747 0x0000 //TX_PREEQ_BIN_MIC2_8 +748 0x0000 //TX_PREEQ_BIN_MIC2_9 +749 0x0000 //TX_PREEQ_BIN_MIC2_10 +750 0x0000 //TX_PREEQ_BIN_MIC2_11 +751 0x0000 //TX_PREEQ_BIN_MIC2_12 +752 0x0000 //TX_PREEQ_BIN_MIC2_13 +753 0x0000 //TX_PREEQ_BIN_MIC2_14 +754 0x0000 //TX_PREEQ_BIN_MIC2_15 +755 0x0000 //TX_PREEQ_BIN_MIC2_16 +756 0x0000 //TX_PREEQ_BIN_MIC2_17 +757 0x0000 //TX_PREEQ_BIN_MIC2_18 +758 0x0000 //TX_PREEQ_BIN_MIC2_19 +759 0x0000 //TX_PREEQ_BIN_MIC2_20 +760 0x0000 //TX_PREEQ_BIN_MIC2_21 +761 0x0000 //TX_PREEQ_BIN_MIC2_22 +762 0x0000 //TX_PREEQ_BIN_MIC2_23 +763 0x0006 //TX_MASKING_ABILITY +764 0x2000 //TX_NND_WEIGHT +765 0x0064 //TX_MIC_CALIBRATION_0 +766 0x006A //TX_MIC_CALIBRATION_1 +767 0x006A //TX_MIC_CALIBRATION_2 +768 0x006B //TX_MIC_CALIBRATION_3 +769 0x0048 //TX_MIC_PWR_BIAS_0 +770 0x003C //TX_MIC_PWR_BIAS_1 +771 0x003C //TX_MIC_PWR_BIAS_2 +772 0x003C //TX_MIC_PWR_BIAS_3 +773 0x0000 //TX_GAIN_LIMIT_0 +774 0x0009 //TX_GAIN_LIMIT_1 +775 0x000C //TX_GAIN_LIMIT_2 +776 0x000F //TX_GAIN_LIMIT_3 +777 0x7F5B //TX_BVE_NOVAD0_ALPHADOWN +778 0x7FDE //TX_BVE_VAD0_ALPHAUP +779 0x7F3A //TX_BVE_VAD0_ALPHADOWN +780 0x2000 //TX_BVE_GAINWEIGHT_NOFEVADLI +781 0x7F5B //TX_BVE_FEVADLI_ALPHA +782 0x7F3D //TX_BVE_NOVAD0_ALPHAUP +783 0x3000 //TX_TDDRC_ALPHA_UP_01 +784 0x3000 //TX_TDDRC_ALPHA_UP_02 +785 0x3000 //TX_TDDRC_ALPHA_UP_03 +786 0x3000 //TX_TDDRC_ALPHA_UP_04 +787 0x7FB0 //TX_TDDRC_ALPHA_DWN_01 +788 0x7FB0 //TX_TDDRC_ALPHA_DWN_02 +789 0x7FB0 //TX_TDDRC_ALPHA_DWN_03 +790 0x7FB0 //TX_TDDRC_ALPHA_DWN_04 +791 0x65AD //TX_TDDRC_TD_DRC_LIMIT +792 0x0800 //TX_TDDRC_POST_LIMIT_GAIN +793 0x0000 //TX_TDDRC_RESRV_0 +794 0x0000 //TX_TDDRC_RESRV_1 +795 0x0018 //TX_FDDRC_BAND_MARGIN_0 +796 0x0030 //TX_FDDRC_BAND_MARGIN_1 +797 0x0050 //TX_FDDRC_BAND_MARGIN_2 +798 0x0080 //TX_FDDRC_BAND_MARGIN_3 +799 0x0007 //TX_FDDRC_BLOCK_EXP +800 0x5000 //TX_FDDRC_THRD_2_0 +801 0x5000 //TX_FDDRC_THRD_2_1 +802 0x5000 //TX_FDDRC_THRD_2_2 +803 0x5000 //TX_FDDRC_THRD_2_3 +804 0x6400 //TX_FDDRC_THRD_3_0 +805 0x6400 //TX_FDDRC_THRD_3_1 +806 0x6400 //TX_FDDRC_THRD_3_2 +807 0x6400 //TX_FDDRC_THRD_3_3 +808 0x2000 //TX_FDDRC_SLANT_0_0 +809 0x2000 //TX_FDDRC_SLANT_0_1 +810 0x2000 //TX_FDDRC_SLANT_0_2 +811 0x2000 //TX_FDDRC_SLANT_0_3 +812 0x5333 //TX_FDDRC_SLANT_1_0 +813 0x5333 //TX_FDDRC_SLANT_1_1 +814 0x5333 //TX_FDDRC_SLANT_1_2 +815 0x5333 //TX_FDDRC_SLANT_1_3 +816 0x0002 //TX_DEADMIC_SILENCE_TH +817 0x0147 //TX_MIC_DEGRADE_TH +818 0x0078 //TX_DEADMIC_CNT +819 0x0078 //TX_MIC_DEGRADE_CNT +820 0x0000 //TX_FDDRC_RESRV_4 +821 0x0000 //TX_FDDRC_RESRV_5 +822 0x0000 //TX_FDDRC_RESRV_6 +823 0x0000 //TX_KS_NOISEPASTE_FACTOR +824 0x0000 //TX_KS_CONFIG +825 0x0000 //TX_KS_GAIN_MIN +826 0x0000 //TX_KS_RESRV_0 +827 0x0000 //TX_KS_RESRV_1 +828 0x0000 //TX_KS_RESRV_2 +829 0x7C00 //TX_LAMBDA_PKA_FP +830 0x2000 //TX_TPKA_FP +831 0x0080 //TX_MIN_G_FP +832 0x2000 //TX_MAX_G_FP +833 0x0000 //TX_FFP_FP_K_METAL +834 0x0000 //TX_A_POST_FLT_FP +835 0x0000 //TX_RTO_OUTBEAM_TH +836 0x0000 //TX_TPKA_FP_THD +837 0x0000 //TX_MAX_G_FP_BLK +838 0x0000 //TX_FFP_FADEIN +839 0x0000 //TX_FFP_FADEOUT +840 0x0000 //TX_WHISPERCTH +841 0x0000 //TX_WHISPERHOLDT +842 0x0000 //TX_WHISP_ENTHH +843 0x0000 //TX_WHISP_ENTHL +844 0x0000 //TX_WHISP_RTOTH +845 0x0000 //TX_WHISP_RTOTH2 +846 0x0000 //TX_MUTE_PERIOD +847 0x0000 //TX_FADE_IN_PERIOD +848 0x0000 //TX_FFP_RESRV_2 +849 0x0000 //TX_FFP_RESRV_3 +850 0x0000 //TX_FFP_RESRV_4 +851 0x0000 //TX_FFP_RESRV_5 +852 0x0000 //TX_FFP_RESRV_6 +853 0x0002 //TX_FILTINDX +854 0x0000 //TX_TDDRC_THRD_0 +855 0x0000 //TX_TDDRC_THRD_1 +856 0x0E80 //TX_TDDRC_THRD_2 +857 0x3800 //TX_TDDRC_THRD_3 +858 0x2A00 //TX_TDDRC_SLANT_0 +859 0x6E00 //TX_TDDRC_SLANT_1 +860 0x3000 //TX_TDDRC_ALPHA_UP_00 +861 0x7FB0 //TX_TDDRC_ALPHA_DWN_00 +862 0x0000 //TX_TDDRC_HMNC_FLAG +863 0x0000 //TX_TDDRC_HMNC_GAIN +864 0x0000 //TX_TDDRC_SMT_FLAG +865 0x0000 //TX_TDDRC_SMT_W +866 0x0100 //TX_TDDRC_DRC_GAIN +867 0x0000 //TX_TDDRC_LMT_THRD +868 0x0000 //TX_TDDRC_LMT_ALPHA +869 0x1EB8 //TX_TFMASKLTH +870 0x170A //TX_TFMASKLTHL +871 0x7FFF //TX_TFMASKHTH +872 0x0CCD //TX_TFMASKLTH_BINVAD +873 0xF333 //TX_TFMASKLTH_NS_EST +874 0x2CCD //TX_TFMASKLTH_DOA +875 0x0CCD //TX_TFMASKTH_BLESSCUT +876 0x4000 //TX_B_LESSCUT_RTO_MASK +877 0x3800 //TX_SB_RHO_MEAN_TH_ABN +878 0x2000 //TX_B_POST_FLT_MASK +879 0x0000 //TX_B_POST_FLT_MASK1 +880 0x5333 //TX_GAIN_WIND_MASK +881 0x0000 //TX_TFMASK_BFSTRICT_MUSIC +882 0x0000 //TX_TFMASK_BFSTRICT_NOMUSIC +883 0x0000 //TX_FASTNS_OUTIN_TH +884 0x0000 //TX_FASTNS_TFMASK_TH +885 0x0000 //TX_FASTNS_TFMASKBIN_TH1 +886 0x0000 //TX_FASTNS_TFMASKBIN_TH2 +887 0x0000 //TX_FASTNS_TFMASKBIN_TH3 +888 0x00C8 //TX_FASTNS_ARSPC_TH +889 0xC000 //TX_FASTNS_MASK5_TH +890 0x051F //TX_POSTSSA_MIN_G_VR_MASK +891 0x7000 //TX_A_LESSCUT_RTO_MASK +892 0x1770 //TX_FASTNS_NOISETH +893 0xC000 //TX_FASTNS_SSA_THLFL +894 0xC000 //TX_FASTNS_SSA_THHFL +895 0xCCCC //TX_FASTNS_SSA_THLFH +896 0xD999 //TX_FASTNS_SSA_THHFH +897 0x2339 //TX_SENDFUNC_REG_MICMUTE +898 0x0021 //TX_SENDFUNC_REG_MICMUTE1 +899 0x02BC //TX_MICMUTE_RATIO_THR +900 0x0140 //TX_MICMUTE_AMP_THR +901 0x0004 //TX_MICMUTE_HPF_IND +902 0x00C0 //TX_MICMUTE_LOG_EYR_TH +903 0x0008 //TX_MICMUTE_CVG_TIME +904 0x0008 //TX_MICMUTE_RELEASE_TIME +905 0x01FE //TX_MIC_VOLUME_MIC0MUTE +906 0x0020 //TX_MICMUTE_EPD_OFFSET_0 +907 0x001E //TX_MICMUTE_FRQ_AEC_L +908 0x7999 //TX_MICMUTE_EAD_THR +909 0x7FFF //TX_MICMUTE_LAMBDA_CB_NLE +910 0x7FFF //TX_MICMUTE_LAMBDA_RE_EST +911 0x4000 //TX_DTD_THR1_MICMUTE_0 +912 0x7000 //TX_DTD_THR1_MICMUTE_1 +913 0x7FFF //TX_DTD_THR1_MICMUTE_2 +914 0x7FFF //TX_DTD_THR1_MICMUTE_3 +915 0x6CCC //TX_DTD_THR2_MICMUTE_0 +916 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_0 +917 0x0400 //TX_MICMUTE_MIN_EQ_RE_EST_1 +918 0x1000 //TX_MICMUTE_MIN_EQ_RE_EST_2 +919 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_3 +920 0x7FFF //TX_MICMUTE_MIN_EQ_RE_EST_4 +921 0x4000 //TX_MICMUTE_C_POST_FLT +922 0x03E8 //TX_MICMUTE_DT_CUT_K +923 0x0001 //TX_MICMUTE_DT_CUT_THR +924 0x03E8 //TX_MICMUTE_DT_CUT_K2 +925 0x0001 //TX_MICMUTE_DT_CUT_THR2 +926 0x0064 //TX_MICMUTE_DT2_HOLD_N +927 0x1000 //TX_MICMUTE_RATIODTH_THCUT +928 0x1000 //TX_MICMUTE_B_POST_FLT_ECHOL +929 0x7FFF //TX_MICMUTE_B_POST_FLT_ECHOH +930 0x0400 //TX_MICMUTE_C_POST_FLT_MASK +931 0x7999 //TX_MICMUTE_RATIODTL_CUT_TH +932 0x0258 //TX_MICMUTE_DT_CUT_K1 +933 0x0800 //TX_MICMUTE_N2_SN_EST +934 0xFC00 //TX_MICMUTE_THR_SN_EST_0 +935 0x001C //TX_MICMUTE_MIN_G_CTRL_0 +936 0x6000 //TX_MICMUTE_A_POST_FILT_S_0 +937 0x7000 //TX_MICMUTE_B_POST_FILT_0 +938 0x2710 //TX_MIC1RUB_AMP_THR +939 0x0010 //TX_MIC1MUTE_RATIO_THR +940 0x0450 //TX_MIC1MUTE_AMP_THR +941 0x0008 //TX_MIC1MUTE_CVG_TIME +942 0x0008 //TX_MIC1MUTE_RELEASE_TIME +943 0x0000 //TX_AMS_RESRV_01 +944 0x0000 //TX_AMS_RESRV_02 +945 0x0000 //TX_AMS_RESRV_03 +946 0x0000 //TX_AMS_RESRV_04 +947 0x0000 //TX_AMS_RESRV_05 +948 0x0000 //TX_AMS_RESRV_06 +949 0x0000 //TX_AMS_RESRV_07 +950 0x0000 //TX_AMS_RESRV_08 +951 0x0000 //TX_AMS_RESRV_09 +952 0x0000 //TX_AMS_RESRV_10 +953 0x0000 //TX_AMS_RESRV_11 +954 0x0000 //TX_AMS_RESRV_12 +955 0x0000 //TX_AMS_RESRV_13 +956 0x0000 //TX_AMS_RESRV_14 +957 0x0000 //TX_AMS_RESRV_15 +958 0x0000 //TX_AMS_RESRV_16 +959 0x0000 //TX_AMS_RESRV_17 +960 0x0000 //TX_AMS_RESRV_18 +961 0x0000 //TX_AMS_RESRV_19 +#RX +0 0x2040 //RX_RECVFUNC_MODE_0 +1 0x0000 //RX_RECVFUNC_MODE_1 +2 0x0000 //RX_SAMPLINGFREQ_SIG +3 0x0000 //RX_SAMPLINGFREQ_PROC +4 0x000A //RX_FRAME_SZ +5 0x0000 //RX_DELAY_OPT +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +10 0x050D //RX_PGA +11 0x7652 //RX_A_HP +12 0x4000 //RX_B_PE +13 0x7800 //RX_THR_PITCH_DET_0 +14 0x7000 //RX_THR_PITCH_DET_1 +15 0x6000 //RX_THR_PITCH_DET_2 +16 0x0000 //RX_PITCH_BFR_LEN +17 0x0000 //RX_SBD_PITCH_DET +18 0x0000 //RX_PP_RESRV_0 +19 0x0000 //RX_PP_RESRV_1 +20 0xF800 //RX_N_SN_EST +21 0x0000 //RX_N2_SN_EST +22 0x000F //RX_NS_LVL_CTRL +23 0xF800 //RX_THR_SN_EST +24 0x7E00 //RX_LAMBDA_PFILT +25 0x000A //RX_FENS_RESRV_0 +26 0x0000 //RX_FENS_RESRV_1 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +30 0x0000 //RX_EXTRA_NS_L +31 0x0000 //RX_EXTRA_NS_A +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +35 0x0000 //RX_A_POST_FLT +36 0x0000 //RX_LMT_THRD +37 0x4000 //RX_LMT_ALPHA +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +111 0x0003 //RX_FILTINDX +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +125 0x7C00 //RX_LAMBDA_PKA_FP +126 0x2000 //RX_TPKA_FP +127 0x0080 //RX_MIN_G_FP +128 0x2000 //RX_MAX_G_FP +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +131 0x0010 //RX_MAXLEVEL_CNG +132 0x0000 //RX_BWE_UV_TH +133 0x0000 //RX_BWE_UV_TH2 +134 0x0000 //RX_BWE_UV_TH3 +135 0x0000 //RX_BWE_V_TH +136 0x0000 //RX_BWE_GAIN1_V_TH1 +137 0x0000 //RX_BWE_GAIN1_V_TH2 +138 0x0000 //RX_BWE_UV_EQ +139 0x0000 //RX_BWE_V_EQ +140 0x0000 //RX_BWE_TONE_TH +141 0x0000 //RX_BWE_UV_HOLD_T +142 0x0000 //RX_BWE_GAIN2_ALPHA +143 0x0000 //RX_BWE_GAIN3_ALPHA +144 0x0000 //RX_BWE_CUTOFF +145 0x0000 //RX_BWE_GAINFILL +146 0x0000 //RX_BWE_MAXTH_TONE +147 0x0000 //RX_BWE_EQ_0 +148 0x0000 //RX_BWE_EQ_1 +149 0x0000 //RX_BWE_EQ_2 +150 0x0000 //RX_BWE_EQ_3 +151 0x0000 //RX_BWE_EQ_4 +152 0x0000 //RX_BWE_EQ_5 +153 0x0000 //RX_BWE_EQ_6 +154 0x0000 //RX_BWE_RESRV_0 +155 0x0000 //RX_BWE_RESRV_1 +156 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +6 0x3000 //RX_TDDRC_ALPHA_UP_1 +7 0x3000 //RX_TDDRC_ALPHA_UP_2 +8 0x3000 //RX_TDDRC_ALPHA_UP_3 +9 0x3000 //RX_TDDRC_ALPHA_UP_4 +27 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +28 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +29 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +32 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +33 0xDA9E //RX_TDDRC_LIMITER_THRD +34 0x0800 //RX_TDDRC_LIMITER_GAIN +112 0x0000 //RX_TDDRC_THRD_0 +113 0x0000 //RX_TDDRC_THRD_1 +114 0x0E80 //RX_TDDRC_THRD_2 +115 0x3800 //RX_TDDRC_THRD_3 +116 0x2A00 //RX_TDDRC_SLANT_0 +117 0x6E00 //RX_TDDRC_SLANT_1 +118 0x3000 //RX_TDDRC_ALPHA_UP_0 +119 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +120 0x0000 //RX_TDDRC_HMNC_FLAG +121 0x0000 //RX_TDDRC_HMNC_GAIN +122 0x0000 //RX_TDDRC_SMT_FLAG +123 0x0000 //RX_TDDRC_SMT_W +124 0x0100 //RX_TDDRC_DRC_GAIN +38 0x0020 //RX_FDEQ_SUBNUM +39 0x4848 //RX_FDEQ_GAIN_0 +40 0x4848 //RX_FDEQ_GAIN_1 +41 0x4848 //RX_FDEQ_GAIN_2 +42 0x4848 //RX_FDEQ_GAIN_3 +43 0x4848 //RX_FDEQ_GAIN_4 +44 0x4848 //RX_FDEQ_GAIN_5 +45 0x4848 //RX_FDEQ_GAIN_6 +46 0x4848 //RX_FDEQ_GAIN_7 +47 0x4848 //RX_FDEQ_GAIN_8 +48 0x4848 //RX_FDEQ_GAIN_9 +49 0x4848 //RX_FDEQ_GAIN_10 +50 0x4848 //RX_FDEQ_GAIN_11 +51 0x4848 //RX_FDEQ_GAIN_12 +52 0x4848 //RX_FDEQ_GAIN_13 +53 0x4848 //RX_FDEQ_GAIN_14 +54 0x4848 //RX_FDEQ_GAIN_15 +55 0x4848 //RX_FDEQ_GAIN_16 +56 0x4848 //RX_FDEQ_GAIN_17 +57 0x4848 //RX_FDEQ_GAIN_18 +58 0x4848 //RX_FDEQ_GAIN_19 +59 0x4848 //RX_FDEQ_GAIN_20 +60 0x4848 //RX_FDEQ_GAIN_21 +61 0x4848 //RX_FDEQ_GAIN_22 +62 0x4848 //RX_FDEQ_GAIN_23 +63 0x0000 //RX_FDEQ_BIN_0 +64 0x0000 //RX_FDEQ_BIN_1 +65 0x0000 //RX_FDEQ_BIN_2 +66 0x0000 //RX_FDEQ_BIN_3 +67 0x0000 //RX_FDEQ_BIN_4 +68 0x0000 //RX_FDEQ_BIN_5 +69 0x0000 //RX_FDEQ_BIN_6 +70 0x0000 //RX_FDEQ_BIN_7 +71 0x0000 //RX_FDEQ_BIN_8 +72 0x0000 //RX_FDEQ_BIN_9 +73 0x0000 //RX_FDEQ_BIN_10 +74 0x0000 //RX_FDEQ_BIN_11 +75 0x0000 //RX_FDEQ_BIN_12 +76 0x0000 //RX_FDEQ_BIN_13 +77 0x0000 //RX_FDEQ_BIN_14 +78 0x0000 //RX_FDEQ_BIN_15 +79 0x0000 //RX_FDEQ_BIN_16 +80 0x0000 //RX_FDEQ_BIN_17 +81 0x0000 //RX_FDEQ_BIN_18 +82 0x0000 //RX_FDEQ_BIN_19 +83 0x0000 //RX_FDEQ_BIN_20 +84 0x0000 //RX_FDEQ_BIN_21 +85 0x0000 //RX_FDEQ_BIN_22 +86 0x0000 //RX_FDEQ_BIN_23 +87 0x0000 //RX_FDEQ_RESRV_0 +88 0x0000 //RX_FDEQ_RESRV_1 +89 0x0018 //RX_FDDRC_BAND_MARGIN_0 +90 0x0030 //RX_FDDRC_BAND_MARGIN_1 +91 0x0050 //RX_FDDRC_BAND_MARGIN_2 +92 0x0080 //RX_FDDRC_BAND_MARGIN_3 +93 0x0004 //RX_FDDRC_BLOCK_EXP +94 0x5000 //RX_FDDRC_THRD_2_0 +95 0x5000 //RX_FDDRC_THRD_2_1 +96 0x5000 //RX_FDDRC_THRD_2_2 +97 0x5000 //RX_FDDRC_THRD_2_3 +98 0x6400 //RX_FDDRC_THRD_3_0 +99 0x6400 //RX_FDDRC_THRD_3_1 +100 0x6400 //RX_FDDRC_THRD_3_2 +101 0x6400 //RX_FDDRC_THRD_3_3 +102 0x2000 //RX_FDDRC_SLANT_0_0 +103 0x2000 //RX_FDDRC_SLANT_0_1 +104 0x2000 //RX_FDDRC_SLANT_0_2 +105 0x2000 //RX_FDDRC_SLANT_0_3 +106 0x2000 //RX_FDDRC_SLANT_1_0 +107 0x2000 //RX_FDDRC_SLANT_1_1 +108 0x2000 //RX_FDDRC_SLANT_1_2 +109 0x2000 //RX_FDDRC_SLANT_1_3 +110 0x0000 //RX_FDDRC_RESRV_0 +129 0x0100 //RX_SPK_VOL +130 0x0000 //RX_VOL_RESRV_0 +#RX 2 +157 0x2040 //RX_RECVFUNC_MODE_0 +158 0x0000 //RX_RECVFUNC_MODE_1 +159 0x0000 //RX_SAMPLINGFREQ_SIG +160 0x0000 //RX_SAMPLINGFREQ_PROC +161 0x000A //RX_FRAME_SZ +162 0x0000 //RX_DELAY_OPT +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +167 0x050D //RX_PGA +168 0x7652 //RX_A_HP +169 0x4000 //RX_B_PE +170 0x7800 //RX_THR_PITCH_DET_0 +171 0x7000 //RX_THR_PITCH_DET_1 +172 0x6000 //RX_THR_PITCH_DET_2 +173 0x0000 //RX_PITCH_BFR_LEN +174 0x0000 //RX_SBD_PITCH_DET +175 0x0000 //RX_PP_RESRV_0 +176 0x0000 //RX_PP_RESRV_1 +177 0xF800 //RX_N_SN_EST +178 0x0000 //RX_N2_SN_EST +179 0x000F //RX_NS_LVL_CTRL +180 0xF800 //RX_THR_SN_EST +181 0x7E00 //RX_LAMBDA_PFILT +182 0x000A //RX_FENS_RESRV_0 +183 0x0000 //RX_FENS_RESRV_1 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +187 0x0000 //RX_EXTRA_NS_L +188 0x0000 //RX_EXTRA_NS_A +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +192 0x0000 //RX_A_POST_FLT +193 0x0000 //RX_LMT_THRD +194 0x4000 //RX_LMT_ALPHA +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +268 0x0003 //RX_FILTINDX +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +282 0x7C00 //RX_LAMBDA_PKA_FP +283 0x2000 //RX_TPKA_FP +284 0x0080 //RX_MIN_G_FP +285 0x2000 //RX_MAX_G_FP +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +288 0x0010 //RX_MAXLEVEL_CNG +289 0x0000 //RX_BWE_UV_TH +290 0x0000 //RX_BWE_UV_TH2 +291 0x0000 //RX_BWE_UV_TH3 +292 0x0000 //RX_BWE_V_TH +293 0x0000 //RX_BWE_GAIN1_V_TH1 +294 0x0000 //RX_BWE_GAIN1_V_TH2 +295 0x0000 //RX_BWE_UV_EQ +296 0x0000 //RX_BWE_V_EQ +297 0x0000 //RX_BWE_TONE_TH +298 0x0000 //RX_BWE_UV_HOLD_T +299 0x0000 //RX_BWE_GAIN2_ALPHA +300 0x0000 //RX_BWE_GAIN3_ALPHA +301 0x0000 //RX_BWE_CUTOFF +302 0x0000 //RX_BWE_GAINFILL +303 0x0000 //RX_BWE_MAXTH_TONE +304 0x0000 //RX_BWE_EQ_0 +305 0x0000 //RX_BWE_EQ_1 +306 0x0000 //RX_BWE_EQ_2 +307 0x0000 //RX_BWE_EQ_3 +308 0x0000 //RX_BWE_EQ_4 +309 0x0000 //RX_BWE_EQ_5 +310 0x0000 //RX_BWE_EQ_6 +311 0x0000 //RX_BWE_RESRV_0 +312 0x0000 //RX_BWE_RESRV_1 +313 0x0000 //RX_BWE_RESRV_2 +#VOL 0 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 1 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 2 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 3 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 4 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 5 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 +#VOL 6 +163 0x3000 //RX_TDDRC_ALPHA_UP_1 +164 0x3000 //RX_TDDRC_ALPHA_UP_2 +165 0x3000 //RX_TDDRC_ALPHA_UP_3 +166 0x3000 //RX_TDDRC_ALPHA_UP_4 +184 0x7FB0 //RX_TDDRC_ALPHA_DWN_1 +185 0x7FB0 //RX_TDDRC_ALPHA_DWN_2 +186 0x7FB0 //RX_TDDRC_ALPHA_DWN_3 +189 0x7FB0 //RX_TDDRC_ALPHA_DWN_4 +190 0xDA9E //RX_TDDRC_LIMITER_THRD +191 0x0800 //RX_TDDRC_LIMITER_GAIN +269 0x0000 //RX_TDDRC_THRD_0 +270 0x0000 //RX_TDDRC_THRD_1 +271 0x0E80 //RX_TDDRC_THRD_2 +272 0x3800 //RX_TDDRC_THRD_3 +273 0x2A00 //RX_TDDRC_SLANT_0 +274 0x6E00 //RX_TDDRC_SLANT_1 +275 0x3000 //RX_TDDRC_ALPHA_UP_0 +276 0x7FB0 //RX_TDDRC_ALPHA_DWN_0 +277 0x0000 //RX_TDDRC_HMNC_FLAG +278 0x0000 //RX_TDDRC_HMNC_GAIN +279 0x0000 //RX_TDDRC_SMT_FLAG +280 0x0000 //RX_TDDRC_SMT_W +281 0x0100 //RX_TDDRC_DRC_GAIN +195 0x0020 //RX_FDEQ_SUBNUM +196 0x4848 //RX_FDEQ_GAIN_0 +197 0x4848 //RX_FDEQ_GAIN_1 +198 0x4848 //RX_FDEQ_GAIN_2 +199 0x4848 //RX_FDEQ_GAIN_3 +200 0x4848 //RX_FDEQ_GAIN_4 +201 0x4848 //RX_FDEQ_GAIN_5 +202 0x4848 //RX_FDEQ_GAIN_6 +203 0x4848 //RX_FDEQ_GAIN_7 +204 0x4848 //RX_FDEQ_GAIN_8 +205 0x4848 //RX_FDEQ_GAIN_9 +206 0x4848 //RX_FDEQ_GAIN_10 +207 0x4848 //RX_FDEQ_GAIN_11 +208 0x4848 //RX_FDEQ_GAIN_12 +209 0x4848 //RX_FDEQ_GAIN_13 +210 0x4848 //RX_FDEQ_GAIN_14 +211 0x4848 //RX_FDEQ_GAIN_15 +212 0x4848 //RX_FDEQ_GAIN_16 +213 0x4848 //RX_FDEQ_GAIN_17 +214 0x4848 //RX_FDEQ_GAIN_18 +215 0x4848 //RX_FDEQ_GAIN_19 +216 0x4848 //RX_FDEQ_GAIN_20 +217 0x4848 //RX_FDEQ_GAIN_21 +218 0x4848 //RX_FDEQ_GAIN_22 +219 0x4848 //RX_FDEQ_GAIN_23 +220 0x0000 //RX_FDEQ_BIN_0 +221 0x0000 //RX_FDEQ_BIN_1 +222 0x0000 //RX_FDEQ_BIN_2 +223 0x0000 //RX_FDEQ_BIN_3 +224 0x0000 //RX_FDEQ_BIN_4 +225 0x0000 //RX_FDEQ_BIN_5 +226 0x0000 //RX_FDEQ_BIN_6 +227 0x0000 //RX_FDEQ_BIN_7 +228 0x0000 //RX_FDEQ_BIN_8 +229 0x0000 //RX_FDEQ_BIN_9 +230 0x0000 //RX_FDEQ_BIN_10 +231 0x0000 //RX_FDEQ_BIN_11 +232 0x0000 //RX_FDEQ_BIN_12 +233 0x0000 //RX_FDEQ_BIN_13 +234 0x0000 //RX_FDEQ_BIN_14 +235 0x0000 //RX_FDEQ_BIN_15 +236 0x0000 //RX_FDEQ_BIN_16 +237 0x0000 //RX_FDEQ_BIN_17 +238 0x0000 //RX_FDEQ_BIN_18 +239 0x0000 //RX_FDEQ_BIN_19 +240 0x0000 //RX_FDEQ_BIN_20 +241 0x0000 //RX_FDEQ_BIN_21 +242 0x0000 //RX_FDEQ_BIN_22 +243 0x0000 //RX_FDEQ_BIN_23 +244 0x0000 //RX_FDEQ_RESRV_0 +245 0x0000 //RX_FDEQ_RESRV_1 +246 0x0018 //RX_FDDRC_BAND_MARGIN_0 +247 0x0030 //RX_FDDRC_BAND_MARGIN_1 +248 0x0050 //RX_FDDRC_BAND_MARGIN_2 +249 0x0080 //RX_FDDRC_BAND_MARGIN_3 +250 0x0004 //RX_FDDRC_BLOCK_EXP +251 0x5000 //RX_FDDRC_THRD_2_0 +252 0x5000 //RX_FDDRC_THRD_2_1 +253 0x5000 //RX_FDDRC_THRD_2_2 +254 0x5000 //RX_FDDRC_THRD_2_3 +255 0x6400 //RX_FDDRC_THRD_3_0 +256 0x6400 //RX_FDDRC_THRD_3_1 +257 0x6400 //RX_FDDRC_THRD_3_2 +258 0x6400 //RX_FDDRC_THRD_3_3 +259 0x2000 //RX_FDDRC_SLANT_0_0 +260 0x2000 //RX_FDDRC_SLANT_0_1 +261 0x2000 //RX_FDDRC_SLANT_0_2 +262 0x2000 //RX_FDDRC_SLANT_0_3 +263 0x2000 //RX_FDDRC_SLANT_1_0 +264 0x2000 //RX_FDDRC_SLANT_1_1 +265 0x2000 //RX_FDDRC_SLANT_1_2 +266 0x2000 //RX_FDDRC_SLANT_1_3 +267 0x0000 //RX_FDDRC_RESRV_0 +286 0x0100 //RX_SPK_VOL +287 0x0000 //RX_VOL_RESRV_0 + diff --git a/audio/tegu/tuning/fortemedia/mcps.dat b/audio/tegu/tuning/fortemedia/mcps.dat new file mode 100644 index 0000000000000000000000000000000000000000..04fc10042f748224f321473096600a6543c89b95 GIT binary patch literal 292 zcmY+{j{f~n};4u>Ch2$bG g>&Q@r{Wd@i56k%A@fF|CkxV}bW zK1Eb;Kqc;A68B}=B?}2ejERcbFh+!EOe=z0l<(B->3Yrp_sy^ji0|nicZUB|cirmh z>h9{Qr=QcWr0)s+Uu!`75>Y`D`9TdEP{E!=d;9;(@-z7~*po5?%cfRNC?8W^P&jzf z^zx~b$|e>Mt1K@&r+jLI7AFtu*S~mBdD+;?@slT&Pixq;-^BCEr%#?deSD)9H7gZQ zm{dGq@|bfPH!GR&-SUaW{mvUZt;^ounKZm?^u+SwZXTFPPMd~cZzm*NB(O2n`wgnCRF3*sk1+?ejVWS3>O&U9>eBxOD*Np#>TM9JD zx=3lLp%I`rHx5uTp7#hqv6D(qGw9CpzZw`(%}oQy*ER!mW;s6THbl)e>;;IO9K&?A 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maxxaudio_qdsp_is_feature_supported with a string to query from the list. +# This config has no effect in the MaxxAudioQdspHalController. It's only meaningful for platform vendors. +# Putting any value other than 1 would be equivalent to not supported. +######################################################################################################## +[HAL_SUPPORTED_FEATURES] +CUSTOM_ACTION_258=1 + +######################################################################################################## +# This defined the options of supported sample rates. +# This can be configured by Waves or platform vendor. +######################################################################################################## +[HAL_SUPPORTED_SAMPLE_RATES] +SR_COMMON = 48000 + +######################################################################################################## +# (Optional) The subtypes that applies to different angles(0, 90, 180, 270). Can be empty if not applicable. +# This can be configured by Waves or platform vendor. +######################################################################################################## +[HAL_ORIENTATION_SUBTYPES] +OST_SPEAKER = 0:12,90:13,180:12,270:0|13 + +######################################################################################################## +# This defines available preset configurations. +# This should be configured by Waves only unless platform vendor is familiar with MPS structure. +######################################################################################################## +[HAL_SUPPORTED_PRESETS] +SPEAKER_MUSIC_THROTTLE= OM:1,SM:2,OST:OST_SPEAKER +SPEAKER_SAFE_MUSIC_THROTTLE = OM:10,SM:2,OST:OST_SPEAKER +SPEAKER_SAFE_CALL_THROTTLE = OM:10,SM:2,OST:OST_SPEAKER +SPEAKER_MUSIC = OM:1,SM:2,OST:OST_SPEAKER +SPEAKER_SAFE_MUSIC = OM:10,SM:2,OST:OST_SPEAKER +SPEAKER_SAFE_CALL = OM:10,SM:2,OST:OST_SPEAKER +HEADSET_MUSIC = OM:2,SM:2 + +######################################################################################################## +# This defines available CONTROL configurations. Only define the CONTROL if you need it. +# The numbers could vary from device to device. +# This can be configured by Waves or platform vendor. +######################################################################################################## +[HAL_SUPPORTED_CONTROLS] +SPEAKER_INSTANCE = INSTANCE:1,DEV:0,SR:SR_COMMON,PRESET:SPEAKER_MUSIC|SPEAKER_SAFE_MUSIC|SPEAKER_SAFE_CALL|SPEAKER_MUSIC_THROTTLE|SPEAKER_SAFE_MUSIC_THROTTLE|SPEAKER_SAFE_CALL_THROTTLE +A2DP_INSTANCE = INSTANCE:2,DEV:0,SR:SR_COMMON,PRESET:HEADSET_MUSIC +USB_HEADPHONE_INSTANCE = INSTANCE:4,DEV:0,SR:SR_COMMON,PRESET:HEADSET_MUSIC + +[COEFS_CONVERTER_SETTING] +AlgFxPath=/vendor/lib/libAlgFx_HiFi3z.so +AlgFxPath64=/vendor/lib64/libAlgFx_HiFi3z.so +# do not modify the following if not necessary +#AudioFormatType=0 +#AudioFormatChannels=2 +#AudioFormatSampleRate=48000 +#AudioFormatBitsPerSample=32 +#AudioFormatSampleSize=4 +#AudioFormatIncrement=8 + +[CUSTOM_ACTION_258] +CASE_1=PRIORITY:0,NUMBERS:2:0|1:0,PRESET:SPEAKER_MUSIC +CASE_2=PRIORITY:1,NUMBERS:1|2|4194304:2|3|4:0,PRESET:SPEAKER_SAFE_CALL +CASE_3=PRIORITY:2,NUMBERS:1|4194304:0|1:0,PRESET:SPEAKER_SAFE_MUSIC +CASE_4=PRIORITY:3,NUMBERS:2:0|1:4,PRESET:SPEAKER_MUSIC_THROTTLE +CASE_5=PRIORITY:4,NUMBERS:1|2|4194304:2|3|4:4,PRESET:SPEAKER_SAFE_CALL_THROTTLE +CASE_6=PRIORITY:5,NUMBERS:1|4194304:0|1:4,PRESET:SPEAKER_SAFE_MUSIC_THROTTLE diff --git a/audio/tegu/tuning/waves/waves_preset.mps b/audio/tegu/tuning/waves/waves_preset.mps new file mode 100644 index 0000000000000000000000000000000000000000..9e463931068b7701a28ab2c212252f1e54d8aadd GIT binary patch literal 192460 zcmeI537i$hwZ;#t7bH5!5>S*$f{Ka=44|k`2ZR6#Dk`Ezlo?<~P=w2-5sh9&)VM*C zr-%y-VsMvviQ*EG2A4#G5#ttoF~O)9guiP>+cL0-v8(){@Re*5K)6&mjmq16>W_BI1EkoE_8;D(d+~_!v$GS+rk5WwqI}x);-iP3P<&AFQA3U& zRD5u8k8VA>ckA7w3;gjm>j!Q2X%uOtOjfhKTm2y+878_~wG=pv||L36esGoDQ6o_Ke9MGNR z_@vv!rUiiPE|4O}Fhi0{w7g+6-W@3;q9O}_t*&0N@`L@jrBBI~MXfx@PFrh`E`qH0 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zC`bw9!l4@^ND21fgU}$IqAmcUg8{MW3LrYfLI`k>zEK8Og5XMEA6j!fOP?i|0x~=s zKy;ag%K>xw3INd$0U5p$Ky;Ocs{wQQ8bFW|*n<+J1Vqbhr+EH|iz*gWt~U?r9p;7Smr1on~|qy+Ln8&%`P zkT$_oL68#IJ`!9BiueHEDa2UeKnu=TAxH^`LVyE#aOX3950O*mEI@`Q0*KC5z>_?L z00+`)K}tYW$@6@tkS4hSAmiTvq8l~b1gPSh0YtX|GQ0plv`|AOpo$j(f|NiGLXZ;V zD)?4>VokI}!ySM=d?z4C34)Zso;@MJ0ZFie;7Smr1QL;#M`7MNND1u4VKy2h!Q=vqy0I_KU7|QJcK}ry$1k!PWlt3C`TT2Q4A0IE^ AzyJUM literal 0 HcmV?d00001 diff --git a/bluetooth/bt_vendor_overlay.conf b/bluetooth/bt_vendor_overlay.conf new file mode 100644 index 0000000..dd9f118 --- /dev/null +++ b/bluetooth/bt_vendor_overlay.conf @@ -0,0 +1,22 @@ +# This is BTBCM HAL overlay configuration file. + +# Uart port name +UartPort = /dev/ttySAC18 + +# Userial type +# UserialType = 2 + +# Enable check whether let aoc controls power pin +AocPowerPinCtrlCheckEnable = true + +# Sar backOff high resolution support +SarBackOffHighResolution = true + +# Update BQR Event Mask property value +BqrEventMaskValueUpdate = 262238 + +BtA2dpOffloadCap = sbc-aac-aptx-aptxhd-ldac-opus + +BtOpusEnabled = true + +AccelBtDisable = false diff --git a/bluetooth/bt_vendor_overlay_komodo.conf b/bluetooth/bt_vendor_overlay_komodo.conf new file mode 100644 index 0000000..19388fc --- /dev/null +++ b/bluetooth/bt_vendor_overlay_komodo.conf @@ -0,0 +1,19 @@ +# This is BTBCM HAL overlay configuration file. + +# Uart port name +UartPort = /dev/ttySAC18 + +# Userial type +# UserialType = 2 + +# Sar backOff high resolution support +SarBackOffHighResolution = true + +# Update BQR Event Mask property value +BqrEventMaskValueUpdate = 262238 + +BtA2dpOffloadCap = sbc-aac-aptx-aptxhd-ldac-opus + +BtOpusEnabled = true + +AccelBtDisable = false diff --git a/bluetooth/bt_vendor_overlay_tegu.conf b/bluetooth/bt_vendor_overlay_tegu.conf new file mode 100644 index 0000000..19388fc --- /dev/null +++ b/bluetooth/bt_vendor_overlay_tegu.conf @@ -0,0 +1,19 @@ +# This is BTBCM HAL overlay configuration file. + +# Uart port name +UartPort = /dev/ttySAC18 + +# Userial type +# UserialType = 2 + +# Sar backOff high resolution support +SarBackOffHighResolution = true + +# Update BQR Event Mask property value +BqrEventMaskValueUpdate = 262238 + +BtA2dpOffloadCap = sbc-aac-aptx-aptxhd-ldac-opus + +BtOpusEnabled = true + +AccelBtDisable = false diff --git a/bluetooth/le_audio_codec_capabilities.xml b/bluetooth/le_audio_codec_capabilities.xml new file mode 100644 index 0000000..baadb81 --- /dev/null +++ b/bluetooth/le_audio_codec_capabilities.xml @@ -0,0 +1,91 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/board-info.txt b/board-info.txt new file mode 100644 index 0000000..639bfb1 --- /dev/null +++ b/board-info.txt @@ -0,0 +1 @@ +require board=tegu diff --git a/conf/init.recovery.device.rc b/conf/init.recovery.device.rc new file mode 100644 index 0000000..c76e45f --- /dev/null +++ b/conf/init.recovery.device.rc @@ -0,0 +1 @@ +import /init.recovery.${ro.board.platform}.rc diff --git a/conf/init.tegu.rc b/conf/init.tegu.rc new file mode 100644 index 0000000..7308db9 --- /dev/null +++ b/conf/init.tegu.rc @@ -0,0 +1,37 @@ +# Tegu specific init.rc +import /vendor/etc/init/hw/init.zumapro.rc + +on init && property:ro.vendor.factory=1 + import /vendor/etc/init/hw/init.factory.rc + +on init + # eSE streset tool name + setprop persist.vendor.se.streset libstreset24 + +on early-boot + # Wait for insmod_sh to finish all common modules + wait_for_prop vendor.common.modules.ready 1 + start insmod_sh_tegu + +service insmod_sh_tegu /vendor/bin/insmod.sh /vendor_dlkm/etc/init.insmod.${ro.hardware}.cfg + class main + user root + group root system + disabled + oneshot + +on property:vendor.mfgapi.touchpanel.permission=1 + chmod 0600 /sys/devices/virtual/sec/tsp/cmd + chown system system /sys/devices/virtual/sec/tsp/cmd + +# WiFi +on post-fs-data + setprop wifi.direct.interface p2p-dev-wlan0 + setprop wifi.aware.interface aware_nmi0 + + # Speaker amp permission + chmod 644 /mnt/vendor/persist/audio/speaker.cal + +# Bluetooth +on post-fs-data + chown bluetooth system /proc/bluetooth/timesync diff --git a/device-tegu-common.mk b/device-tegu-common.mk new file mode 100644 index 0000000..28dd9a7 --- /dev/null +++ b/device-tegu-common.mk @@ -0,0 +1,33 @@ +# +# Copyright (C) 2023 The Android Open-Source Project +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + + +# Thermal Config +ifeq (,$(TARGET_VENDOR_THERMAL_CONFIG_PATH)) +TARGET_VENDOR_THERMAL_CONFIG_PATH := device/google/tegu/thermal +endif + +PRODUCT_COPY_FILES += \ + $(TARGET_VENDOR_THERMAL_CONFIG_PATH)/thermal_info_config_$(TARGET_DEVICE).json:$(TARGET_COPY_OUT_VENDOR)/etc/thermal_info_config.json \ + $(TARGET_VENDOR_THERMAL_CONFIG_PATH)/thermal_info_config_charge_$(TARGET_DEVICE).json:$(TARGET_COPY_OUT_VENDOR)/etc/thermal_info_config_charge.json + +# Power HAL config +ifeq (,$(TARGET_VENDOR_PERF_CONFIG_PATH)) +TARGET_VENDOR_PERF_CONFIG_PATH := device/google/tegu/perf +endif + +PRODUCT_COPY_FILES += \ + $(TARGET_VENDOR_PERF_CONFIG_PATH)/powerhint-$(TARGET_DEVICE).json:$(TARGET_COPY_OUT_VENDOR)/etc/powerhint.json diff --git a/device-tegu.mk b/device-tegu.mk new file mode 100644 index 0000000..056a6a9 --- /dev/null +++ b/device-tegu.mk @@ -0,0 +1,251 @@ +# +# Copyright (C) 2021 The Android Open-Source Project +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +TARGET_KERNEL_DIR ?= device/google/tegu-kernel +TARGET_BOARD_KERNEL_HEADERS := device/google/tegu-kernel/kernel-headers + +ifneq (,$(filter userdebug eng, $(TARGET_BUILD_VARIANT))) + USE_UWBFIELDTESTQM := true +endif +ifeq ($(filter factory_tegu, $(TARGET_PRODUCT)),) + include device/google/tegu/uwb/uwb_calibration.mk +endif + +$(call inherit-product-if-exists, vendor/google_devices/tegu/prebuilts/device-vendor-tegu.mk) +$(call inherit-product-if-exists, vendor/google_devices/zumapro/prebuilts/device-vendor.mk) +$(call inherit-product-if-exists, vendor/google_devices/zumapro/proprietary/device-vendor.mk) +$(call inherit-product-if-exists, vendor/google_devices/tegu/proprietary/tegu/device-vendor-tegu.mk) +$(call inherit-product-if-exists, vendor/qorvo/uwb/qm35-hal/Device.mk) + +# Disable modem until b/291009607 is fixed +BOARD_WITHOUT_RADIO := true + +include device/google/tegu/audio/tegu/audio-tables.mk +include device/google/zumapro/device-shipping-common.mk +include hardware/google/pixel/vibrator/cs40l26/device.mk +include device/google/gs-common/bcmbt/bluetooth.mk +include device/google/gs-common/touch/syna/syna20.mk +include device/google/tegu/fingerprint/ultrasonic_udfps.mk + +# go/lyric-soong-variables +$(call soong_config_set,lyric,camera_hardware,tegu) +$(call soong_config_set,lyric,tuning_product,tegu) +$(call soong_config_set,google3a_config,target_device,tegu) + +# display +DEVICE_PACKAGE_OVERLAYS += device/google/tegu/tegu/overlay + +# Init files +PRODUCT_COPY_FILES += \ + device/google/tegu/conf/init.tegu.rc:$(TARGET_COPY_OUT_VENDOR)/etc/init/hw/init.tegu.rc + +# Recovery files +PRODUCT_COPY_FILES += \ + device/google/tegu/conf/init.recovery.device.rc:$(TARGET_COPY_OUT_RECOVERY)/root/init.recovery.tegu.rc + +# Camera +PRODUCT_COPY_FILES += \ + device/google/tegu/media_profiles_tegu.xml:$(TARGET_COPY_OUT_VENDOR)/etc/media_profiles_V1_0.xml + +# NFC +PRODUCT_COPY_FILES += \ + frameworks/native/data/etc/android.hardware.nfc.xml:$(TARGET_COPY_OUT_VENDOR)/etc/permissions/android.hardware.nfc.xml \ + frameworks/native/data/etc/android.hardware.nfc.hce.xml:$(TARGET_COPY_OUT_VENDOR)/etc/permissions/android.hardware.nfc.hce.xml \ + frameworks/native/data/etc/android.hardware.nfc.hcef.xml:$(TARGET_COPY_OUT_VENDOR)/etc/permissions/android.hardware.nfc.hcef.xml \ + frameworks/native/data/etc/com.nxp.mifare.xml:$(TARGET_COPY_OUT_VENDOR)/etc/permissions/com.nxp.mifare.xml \ + frameworks/native/data/etc/android.hardware.nfc.ese.xml:$(TARGET_COPY_OUT_VENDOR)/etc/permissions/android.hardware.nfc.ese.xml \ + device/google/tegu/nfc/libnfc-hal-st.conf:$(TARGET_COPY_OUT_VENDOR)/etc/libnfc-hal-st.conf \ + device/google/tegu/nfc/libnfc-nci.conf:$(TARGET_COPY_OUT_PRODUCT)/etc/libnfc-nci.conf + +PRODUCT_PACKAGES += \ + NfcNci \ + Tag \ + android.hardware.nfc-service.st + +# SecureElement +PRODUCT_PACKAGES += \ + android.hardware.secure_element-service.thales + +PRODUCT_COPY_FILES += \ + frameworks/native/data/etc/android.hardware.se.omapi.ese.xml:$(TARGET_COPY_OUT_VENDOR)/etc/permissions/android.hardware.se.omapi.ese.xml \ + frameworks/native/data/etc/android.hardware.se.omapi.uicc.xml:$(TARGET_COPY_OUT_VENDOR)/etc/permissions/android.hardware.se.omapi.uicc.xml \ + device/google/tegu/nfc/libse-gto-hal.conf:$(TARGET_COPY_OUT_VENDOR)/etc/libse-gto-hal.conf + +# Bluetooth HAL +PRODUCT_COPY_FILES += \ + device/google/tegu/bluetooth/bt_vendor_overlay_tegu.conf:$(TARGET_COPY_OUT_VENDOR)/etc/bluetooth/bt_vendor_overlay.conf +PRODUCT_PROPERTY_OVERRIDES += \ + ro.bluetooth.a2dp_offload.supported=true \ + persist.bluetooth.a2dp_offload.disabled=false \ + persist.bluetooth.a2dp_offload.cap=sbc-aac-aptx-aptxhd-ldac-opus + +# Spatial Audio +PRODUCT_PACKAGES += \ + libspatialaudio + +# declare use of spatial audio +PRODUCT_PROPERTY_OVERRIDES += \ + ro.audio.spatializer_enabled=true + +# Bluetooth hci_inject test tool +PRODUCT_PACKAGES_DEBUG += \ + hci_inject + +# Bluetooth OPUS codec +PRODUCT_PRODUCT_PROPERTIES += \ + persist.bluetooth.opus.enabled=true + +# Bluetooth SAR test tool +PRODUCT_PACKAGES_DEBUG += \ + sar_test + +# Bluetooth EWP test tool +PRODUCT_PACKAGES_DEBUG += \ + ewp_tool + +# Bluetooth AAC VBR +PRODUCT_PRODUCT_PROPERTIES += \ + persist.bluetooth.a2dp_aac.vbr_supported=true + +# Override BQR mask to enable LE Audio Choppy report, remove BTRT logging +ifneq (,$(filter userdebug eng, $(TARGET_BUILD_VARIANT))) +PRODUCT_PRODUCT_PROPERTIES += \ + persist.bluetooth.bqr.event_mask=262238 +else +PRODUCT_PRODUCT_PROPERTIES += \ + persist.bluetooth.bqr.event_mask=94 +endif + +# default BDADDR for EVB only +PRODUCT_PROPERTY_OVERRIDES += \ + ro.vendor.bluetooth.evb_bdaddr="22:22:22:33:44:55" + +# Spatial Audio +PRODUCT_PACKAGES += \ + libspatialaudio \ + librondo + +# Bluetooth LE Audio +PRODUCT_PRODUCT_PROPERTIES += \ + ro.bluetooth.leaudio_switcher.supported=true \ + bluetooth.profile.bap.unicast.client.enabled=true \ + bluetooth.profile.csip.set_coordinator.enabled=true \ + bluetooth.profile.hap.client.enabled=true \ + bluetooth.profile.mcp.server.enabled=true \ + bluetooth.profile.ccp.server.enabled=true \ + bluetooth.profile.vcp.controller.enabled=true \ + bluetooth.profile.bap.broadcast.assist.enabled=true \ + bluetooth.profile.bap.broadcast.source.enabled=true + +# Bluetooth LE Audio enable hardware offloading +PRODUCT_PRODUCT_PROPERTIES += \ + ro.bluetooth.leaudio_offload.supported=true \ + persist.bluetooth.leaudio_offload.disabled=false \ + ro.bluetooth.leaudio_broadcast_switcher.supported=true + +# Bluetooth LE Auido offload capabilities setting +PRODUCT_COPY_FILES += \ + device/google/tegu/bluetooth/le_audio_codec_capabilities.xml:$(TARGET_COPY_OUT_VENDOR)/etc/le_audio_codec_capabilities.xml + +# Keymaster HAL +#LOCAL_KEYMASTER_PRODUCT_PACKAGE ?= android.hardware.keymaster@4.1-service + +# Gatekeeper HAL +#LOCAL_GATEKEEPER_PRODUCT_PACKAGE ?= android.hardware.gatekeeper@1.0-service.software + + +# Gatekeeper +# PRODUCT_PACKAGES += \ +# android.hardware.gatekeeper@1.0-service.software + +# Keymint replaces Keymaster +# PRODUCT_PACKAGES += \ +# android.hardware.security.keymint-service + +# Keymaster +#PRODUCT_PACKAGES += \ +# android.hardware.keymaster@4.0-impl \ +# android.hardware.keymaster@4.0-service + +#PRODUCT_PACKAGES += android.hardware.keymaster@4.0-service.remote +#PRODUCT_PACKAGES += android.hardware.keymaster@4.1-service.remote +#LOCAL_KEYMASTER_PRODUCT_PACKAGE := android.hardware.keymaster@4.1-service +#LOCAL_KEYMASTER_PRODUCT_PACKAGE ?= android.hardware.keymaster@4.1-service + +# PRODUCT_PROPERTY_OVERRIDES += \ +# ro.hardware.keystore_desede=true \ +# ro.hardware.keystore=software \ +# ro.hardware.gatekeeper=software + +# PowerStats HAL +PRODUCT_SOONG_NAMESPACES += \ + device/google/tegu/powerstats/tegu + +# WiFi Overlay +PRODUCT_PACKAGES += \ + WifiOverlay2024 + +# Trusty liboemcrypto.so +PRODUCT_SOONG_NAMESPACES += vendor/google_devices/tegu/prebuilts + +# UWB +PRODUCT_SOONG_NAMESPACES += \ + device/google/tegu/uwb + +# Location +# SDK build system +$(call soong_config_set, include_libsitril-gps-wifi, board_without_radio, $(BOARD_WITHOUT_RADIO)) +include device/google/gs-common/gps/brcm/device.mk + +PRODUCT_COPY_FILES += \ + device/google/tegu/location/gps.cer:$(TARGET_COPY_OUT_VENDOR)/etc/gnss/gps.cer + +ifneq (,$(filter userdebug eng, $(TARGET_BUILD_VARIANT))) + PRODUCT_COPY_FILES += \ + device/google/tegu/location/lhd.conf:$(TARGET_COPY_OUT_VENDOR)/etc/gnss/lhd.conf \ + device/google/tegu/location/scd.conf:$(TARGET_COPY_OUT_VENDOR)/etc/gnss/scd.conf \ + device/google/tegu/location/gps.xml:$(TARGET_COPY_OUT_VENDOR)/etc/gnss/gps.xml +else + PRODUCT_COPY_FILES += \ + device/google/tegu/location/lhd_user.conf:$(TARGET_COPY_OUT_VENDOR)/etc/gnss/lhd.conf \ + device/google/tegu/location/scd_user.conf:$(TARGET_COPY_OUT_VENDOR)/etc/gnss/scd.conf \ + device/google/tegu/location/gps_user.xml:$(TARGET_COPY_OUT_VENDOR)/etc/gnss/gps.xml +endif + +# Set zram size +PRODUCT_VENDOR_PROPERTIES += \ + vendor.zram.size=3g \ + persist.device_config.configuration.disable_rescue_party=true + +PRODUCT_VENDOR_PROPERTIES += \ + persist.vendor.udfps.als_feed_forward_supported=true \ + persist.vendor.udfps.lhbm_controlled_in_hal_supported=true + +# Display RRS default Config +PRODUCT_DEFAULT_PROPERTY_OVERRIDES += persist.vendor.display.primary.boot_config=960x2142@120 +# TODO: b/250788756 - the property will be phased out after HWC loads user-preferred mode +PRODUCT_DEFAULT_PROPERTY_OVERRIDES += vendor.display.preferred_mode=960x2142@120 + +# Vibrator HAL +ACTUATOR_MODEL := luxshare_ict_081545 +PRODUCT_VENDOR_PROPERTIES += \ + ro.vendor.vibrator.hal.chirp.enabled=1 \ + ro.vendor.vibrator.hal.device.mass=0.222 \ + ro.vendor.vibrator.hal.loc.coeff=2.8 + +# PKVM Memory Reclaim +PRODUCT_VENDOR_PROPERTIES += \ + hypervisor.memory_reclaim.supported=1 diff --git a/factory_tegu.mk b/factory_tegu.mk new file mode 100644 index 0000000..3778263 --- /dev/null +++ b/factory_tegu.mk @@ -0,0 +1,38 @@ +# +# Copyright 2021 The Android Open-Source Project +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +TARGET_LINUX_KERNEL_VERSION := 6.1 + +$(call inherit-product, device/google/zumapro/factory_common.mk) +$(call inherit-product, device/google/tegu/device-tegu.mk) +include device/google/tegu/audio/tegu/factory-audio-tables.mk + +PRODUCT_NAME := factory_tegu +PRODUCT_DEVICE := tegu +PRODUCT_MODEL := Factory build on Tegu +PRODUCT_BRAND := Android +PRODUCT_MANUFACTURER := Google + +# default BDADDR for EVB only +PRODUCT_PROPERTY_OVERRIDES += \ + ro.vendor.bluetooth.evb_bdaddr="22:22:22:33:44:55" + +# Override to factory SDK +$(call soong_config_set, gpssdk, sdkv1, True) +$(call soong_config_set, gpssdk, gpsmcuversion, gpsv1_$(TARGET_BUILD_VARIANT)) + +# Factory binaries of camera +PRODUCT_PACKAGES += fatp_km4cm4tk4_wide_hat_tool fatp_km4cm4_tele_hat_tool fatp_km4cm4tk4_ultrawide_hat_tool fatp_km4cm4_front_hat_tool diff --git a/fingerprint/device_framework_matrix_product.xml b/fingerprint/device_framework_matrix_product.xml new file mode 100644 index 0000000..8e0a33c --- /dev/null +++ b/fingerprint/device_framework_matrix_product.xml @@ -0,0 +1,17 @@ + + + android.hardware.biometrics.fingerprint + + IFingerprint + default + + + + vendor.qti.hardware.fingerprint + 1.0 + + IQtiExtendedFingerprint + default + + + diff --git a/fingerprint/ultrasonic_udfps.mk b/fingerprint/ultrasonic_udfps.mk new file mode 100644 index 0000000..7d86e21 --- /dev/null +++ b/fingerprint/ultrasonic_udfps.mk @@ -0,0 +1,39 @@ +# +# Copyright 2021 The Android Open-Source Project +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +PRODUCT_SOONG_NAMESPACES += \ + vendor/qcom/fingerprint/qfp-service \ + vendor/qcom/fingerprint/QFPCalibration \ + +PRODUCT_PACKAGES += \ + qfp-daemon \ + QFPCalibration \ + +PRODUCT_COPY_FILES += \ + frameworks/native/data/etc/android.hardware.fingerprint.xml:$(TARGET_COPY_OUT_VENDOR)/etc/permissions/android.hardware.fingerprint.xml + +DEVICE_PRODUCT_COMPATIBILITY_MATRIX_FILE += device/google/tegu/fingerprint/device_framework_matrix_product.xml + +$(call soong_config_set,fp_hal_feature,biometric_suez_support,true) + +PRODUCT_PROPERTY_OVERRIDES += \ + persist.vendor.qfp.update_vfs_calib=1 + persist.vendor.qfp.enable_setprop=0 \ + log.tag.QFP=3 + +ifneq (,$(findstring factory, $(TARGET_PRODUCT))) +PRODUCT_PACKAGES += QfsFactoryTest +endif diff --git a/fullmte-common.mk b/fullmte-common.mk new file mode 100644 index 0000000..1591a33 --- /dev/null +++ b/fullmte-common.mk @@ -0,0 +1,2 @@ +BOARD_KERNEL_CMDLINE += bootloader.pixel.MTE_FORCE_ON +PRODUCT_PRODUCT_PROPERTIES += persist.arm64.memtag.default=sync diff --git a/fullmte-vars.mk b/fullmte-vars.mk new file mode 100644 index 0000000..c8c87ff --- /dev/null +++ b/fullmte-vars.mk @@ -0,0 +1,4 @@ +ifeq ($(filter memtag_heap,$(SANITIZE_TARGET)),) + SANITIZE_TARGET := $(strip $(SANITIZE_TARGET) memtag_heap memtag_stack) + SANITIZE_TARGET_DIAG := $(strip $(SANITIZE_TARGET_DIAG) memtag_heap) +endif diff --git a/location/gps.cer b/location/gps.cer new file mode 100644 index 0000000..934e0c5 --- /dev/null +++ b/location/gps.cer @@ -0,0 +1,161 @@ +-----BEGIN CERTIFICATE----- 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0000000..015ea13 --- /dev/null +++ b/location/gps_user.xml.hk3 @@ -0,0 +1,100 @@ + + + + + + + + + + diff --git a/location/gps_user.xml.sb3 b/location/gps_user.xml.sb3 new file mode 100644 index 0000000..f12eecc --- /dev/null +++ b/location/gps_user.xml.sb3 @@ -0,0 +1,100 @@ + + + + + + + + + + diff --git a/location/lhd.conf b/location/lhd.conf new file mode 100644 index 0000000..c430b93 --- /dev/null +++ b/location/lhd.conf @@ -0,0 +1,33 @@ +LheName=bbd + +LheRsmResetTimeoutMS=10000 +GpioNStdbyPath=/sys/devices/platform/111e0000.spi/spi_master/spi21/spi21.0/nstandby + +LhePatch=/vendor/firmware/SensorHub.patch +Lhe477xDebugFlags=RPC:FACILITY=65535-dKP+CUST+LHE:STDOUT_PUTS:STDOUT_LOG +LheConsole=/data/vendor/gps/LheConsole + +LogEnabled=true +Log=JAVA +LogDirectory=/sdcard/gps/broadcom/storage + +LheBbdPacket=/dev/ttyBCM + +LheBbdControl=/dev/bbd_control + +# LheBbdSensor=/dev/bbd_sensor + +LheFailSafe=/data/vendor/gps/logs/esw-crash-dump.txt +LogLevel=*:I + +NvStorageDir=/data/vendor/gps/ + +# Enable BBD debugging at these stages: +# LheDriverDebugFlags=PATCH_BBD:LHE_BBD:FSC_BBD + +LheAutoBaudDelayMS=10 +TrafficLogEnabled=false +SecondaryConfigPath=/data/vendor/gps/overlay/lhd_overlay.conf + +SkipSensorWakeLock=true +LoggerWakeLockEnable=false diff --git a/location/lhd_user.conf b/location/lhd_user.conf new file mode 100644 index 0000000..73e03bc --- /dev/null +++ b/location/lhd_user.conf @@ -0,0 +1,31 @@ +LheName=bbd + +LheRsmResetTimeoutMS=10000 +GpioNStdbyPath=/sys/devices/platform/111e0000.spi/spi_master/spi21/spi21.0/nstandby + +LhePatch=/vendor/firmware/SensorHub.patch +Lhe477xDebugFlags=RPC:FACILITY=65535-dKP+CUST+LHE:STDOUT_PUTS:STDOUT_LOG +# LheConsole=/data/vendor/gps/LheConsole + +LogEnabled=false +Log=JAVA +LogDirectory=/sdcard/gps/broadcom/storage + +LheBbdPacket=/dev/ttyBCM + +LheBbdControl=/dev/bbd_control + +# LheBbdSensor=/dev/bbd_sensor + +# LheFailSafe=/data/vendor/gps/esw-crash-dump.txt + +NvStorageDir=/data/vendor/gps/ + +# Enable BBD debugging at these stages: +# LheDriverDebugFlags=PATCH_BBD:LHE_BBD:FSC_BBD + +LheAutoBaudDelayMS=10 +TrafficLogEnabled=false + +SkipSensorWakeLock=true +LoggerWakeLockEnable=false diff --git a/location/scd.conf b/location/scd.conf new file mode 100644 index 0000000..43f9cd2 --- /dev/null +++ b/location/scd.conf @@ -0,0 +1,6 @@ +LogEnabled=true +Log=JAVA +LogDirectory=/sdcard/gps/broadcom/storage +NvStorageDir=/data/vendor/gps/ +TcpConnectionTimeout=20 +SecondaryConfigPath=/data/vendor/gps/overlay/scd_overlay.conf diff --git a/location/scd_user.conf b/location/scd_user.conf new file mode 100644 index 0000000..e75f209 --- /dev/null +++ b/location/scd_user.conf @@ -0,0 +1,5 @@ +LogEnabled=false +Log=JAVA +LogDirectory=/sdcard/gps/broadcom/storage +NvStorageDir=/data/vendor/gps/ +TcpConnectionTimeout=20 diff --git a/manifest.xml b/manifest.xml new file mode 100644 index 0000000..e01d156 --- /dev/null +++ b/manifest.xml @@ -0,0 +1,125 @@ + + + android.hardware.audio + hwbinder + 7.1 + + IDevicesFactory + default + + + + android.hardware.audio.effect + hwbinder + 7.0 + + IEffectsFactory + default + + + + android.hardware.soundtrigger + hwbinder + 2.3 + + ISoundTriggerHw + default + + + + android.hardware.media.omx + hwbinder + 1.0 + + IOmx + default + + + IOmxStore + default + + + + android.hardware.graphics.allocator + hwbinder + 4.0 + + IAllocator + default + + + + android.hardware.graphics.mapper + passthrough + 4.0 + + IMapper + default + + + + android.hardware.graphics.composer + hwbinder + 2.4 + + IComposer + default + + + + android.hardware.renderscript + passthrough + 1.0 + + IDevice + default + + + + android.hardware.dumpstate + hwbinder + 1.1 + + IDumpstateDevice + default + + + + android.hardware.bluetooth.audio + hwbinder + 2.1 + + IBluetoothAudioProvidersFactory + default + + + + android.hardware.boot + hwbinder + @1.2::IBootControl/default + + + android.hardware.neuralnetworks + hwbinder + @1.3::IDevice/google-edgetpu + + + android.hardware.health + hwbinder + 2.1 + + IHealth + default + + + + vendor.google.whitechapel.audio.audioext + hwbinder + 4.0 + + IAudioExt + default + + + + diff --git a/media_profiles_tegu.xml b/media_profiles_tegu.xml new file mode 100644 index 0000000..20e20ee --- /dev/null +++ b/media_profiles_tegu.xml @@ -0,0 +1,1821 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +]> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/nfc/libnfc-hal-st-disable.conf b/nfc/libnfc-hal-st-disable.conf new file mode 100644 index 0000000..7801d1b --- /dev/null +++ b/nfc/libnfc-hal-st-disable.conf @@ -0,0 +1,152 @@ +########################### Start of libnf-hal-st_aosp.conf ########################### + +############################################################################### +############################################################################### +# ST HAL trace log level +STNFC_HAL_LOGLEVEL=4 +NFC_DEBUG_ENABLED=1 + +############################################################################### +# Vendor specific mode to enable FW (RF & SWP) traces. +STNFC_FW_DEBUG_ENABLED=0 + +############################################################################### +# File used for NFA storage +NFA_STORAGE="/data/nfc" + +############################################################################### +# Dev Node used for ST HAL +ST_NFC_DEV_NODE="/dev/st_no_such_device" + +############################################################################### +# Keep the nfa storage file. +PRESERVE_STORAGE=1 + +############################################################################### +# In Switch OFF mode (phone switched-off), specify the desired CE mode to +# the controller. +# 0: No card-emulation; DEFAULT +# 1: Switch-off card-emulation enabled +CE_ON_SWITCH_OFF_STATE=1 + +############################################################################### +# Vendor specific mode to support the USB charging mode if VPSIO=1 in switch off. +STNFC_USB_CHARGING_MODE=1 + +############################################################################### +# Vendor Specific Proprietary Protocol & Discovery Configuration +# Set to 0xFF if unsupported +# byte[0] NCI_PROTOCOL_18092_ACTIVE +# byte[1] NCI_PROTOCOL_B_PRIME +# byte[2] NCI_PROTOCOL_DUAL +# byte[3] NCI_PROTOCOL_15693 +# byte[4] NCI_PROTOCOL_KOVIO +# byte[5] NCI_PROTOCOL_MIFARE +# byte[6] NCI_DISCOVERY_TYPE_POLL_KOVIO +# byte[7] NCI_DISCOVERY_TYPE_POLL_B_PRIME +# byte[8] NCI_DISCOVERY_TYPE_LISTEN_B_PRIME +NFA_PROPRIETARY_CFG={05:FF:FF:06:8A:90:77:FF:FF} + +############################################################################### +# Choose the presence-check algorithm for type-4 tag. If not defined, +# the default value is 1. +# 0 NFA_RW_PRES_CHK_DEFAULT; Let stack selects an algorithm +# 1 NFA_RW_PRES_CHK_I_BLOCK; ISO-DEP protocol's empty I-block +# 2 NFA_RW_PRES_CHK_RESET; Deactivate to Sleep, then re-activate +# 3 NFA_RW_PRES_CHK_RB_CH0; Type-4 tag protocol's ReadBinary command on channel 0 +# 4 NFA_RW_PRES_CHK_RB_CH3; Type-4 tag protocol's ReadBinary command on channel 3 +# 5 NFA_RW_PRES_CHK_ISO_DEP_NAK; presence check command ISO-DEP NAK as per NCI2.0 +PRESENCE_CHECK_ALGORITHM=5 + +############################################################################### +# Name of the NCI HAL module to use +# If unset, falls back to nfc_nci.bcm2079x +NCI_HAL_MODULE="nfc_nci.st21nfc.default" + +############################################################################### +# Allow list to be set at startup. +DEVICE_HOST_ALLOW_LIST={02:C0} + +############################################################################### +# BAIL OUT value for P2P +# Implements algorithm for NFC-DEP protocol priority over ISO-DEP protocol. +POLL_BAIL_OUT_MODE=1 + +############################################################################### +# Extended APDU length for ISO_DEP +ISO_DEP_MAX_TRANSCEIVE=0xFEFF + +############################################################################### +# Configure the NFC Extras to open and use a static pipe. If the value is +# not set or set to 0, then the default is use a dynamic pipe based on a +# destination gate (see NFA_HCI_DEFAULT_DEST_GATE). Note there is a value +# for each EE (ESE/SIM) +OFF_HOST_ESE_PIPE_ID=0x5E +OFF_HOST_SIM_PIPE_ID=0x3E + +############################################################################### +#Set the default Felica T3T System Code OffHost route Location : +#This settings will be used when application does not set this parameter +# host 0x00 +# eSE 0x82 (eSE), 0x86 (eUICC/SPI-SE) +# UICC 0x81 (UICC_1), 0x85 (UICC_2) +DEFAULT_SYS_CODE_ROUTE=0x86 + +############################################################################### +#Set the Felica T3T System Code supported power state: +DEFAULT_SYS_CODE_PWR_STATE=0x3B + +############################################################################### +# Path and Files used for FW update binaries storage +STNFC_FW_PATH_STORAGE="/vendor/firmware" +STNFC_FW_BIN_NAME="/st54l_fw.bin" +STNFC_FW_CONF_NAME="/st54l_conf.bin" + +############################################################################### +# Default off-host route for Felica. +# This settings will be used when application does not set this parameter +# host 0x00 +# eSE 0x82 (eSE), 0x86 (eUICC/SPI-SE) +# UICC 0x81 (UICC_1), 0x85 (UICC_2) +DEFAULT_NFCF_ROUTE=0x86 + +############################################################################### +# Configure the default off-host route. +# used for technology A and B routing +# eSE 0x82 (eSE), 0x86 (eUICC/SPI-SE) +# UICC 0x81 (UICC_1), 0x85 (UICC_2) +DEFAULT_OFFHOST_ROUTE=0x81 + +############################################################################### +# Configure the default AID route. +# host 0x00 +# eSE 0x82 (eSE), 0x86 (eUICC/SPI-SE) +# UICC 0x81 (UICC_1), 0x85 (UICC_2) +DEFAULT_ROUTE=0x00 + +############################################################################### +# Configure the NFCEEIDs of offhost UICC. +# UICC 0x81 (UICC_1), 0x85 (UICC_2) +OFFHOST_ROUTE_UICC={81} + +############################################################################### +# Configure the NFCEEIDs of offhost eSEs. +# eSE 0x82 (eSE), 0x86 (eUICC/SPI-SE) +OFFHOST_ROUTE_ESE={86} + +############################################################################### +# Configure the list of NFCEE for the ISO-DEP routing. +# host 0x00 +# eSE 0x82 (eSE), 0x86 (eUICC/SPI-SE) +# UICC 0x81 (UICC_1), 0x85 (UICC_2) +DEFAULT_ISODEP_ROUTE=0x81 + +############################################################################### +# Core configuration settings +CORE_CONF_PROP={ 20, 02, 0a, 03, + a1, 01, 1e, + a2, 01, 19, + 80, 01, 01 +} + + diff --git a/nfc/libnfc-hal-st.conf b/nfc/libnfc-hal-st.conf new file mode 100644 index 0000000..442e785 --- /dev/null +++ b/nfc/libnfc-hal-st.conf @@ -0,0 +1,169 @@ +########################### Start of libnf-hal-st_aosp.conf ########################### + +############################################################################### +############################################################################### +# ST HAL trace log level +STNFC_HAL_LOGLEVEL=1 +NFC_DEBUG_ENABLED=0 + +############################################################################### +# Vendor specific mode to enable FW (RF & SWP) traces. +STNFC_FW_DEBUG_ENABLED=0 + +############################################################################### +# File used for NFA storage +NFA_STORAGE="/data/nfc" + +############################################################################### +# Dev Node used for ST HAL +ST_NFC_DEV_NODE="/dev/st21nfc" + +############################################################################### +# Keep the nfa storage file. +PRESERVE_STORAGE=1 + +############################################################################### +# In Switch OFF mode (phone switched-off), specify the desired CE mode to +# the controller. +# 0: No card-emulation; DEFAULT +# 1: Switch-off card-emulation enabled +CE_ON_SWITCH_OFF_STATE=1 + +############################################################################### +# Vendor specific mode to support the USB charging mode if VPSIO=1 in switch off. +STNFC_USB_CHARGING_MODE=1 + +############################################################################### +# Vendor Specific Proprietary Protocol & Discovery Configuration +# Set to 0xFF if unsupported +# byte[0] NCI_PROTOCOL_18092_ACTIVE +# byte[1] NCI_PROTOCOL_B_PRIME +# byte[2] NCI_PROTOCOL_DUAL +# byte[3] NCI_PROTOCOL_15693 +# byte[4] NCI_PROTOCOL_KOVIO +# byte[5] NCI_PROTOCOL_MIFARE +# byte[6] NCI_DISCOVERY_TYPE_POLL_KOVIO +# byte[7] NCI_DISCOVERY_TYPE_POLL_B_PRIME +# byte[8] NCI_DISCOVERY_TYPE_LISTEN_B_PRIME +NFA_PROPRIETARY_CFG={05:FF:FF:06:8A:90:77:FF:FF} + +############################################################################### +# Choose the presence-check algorithm for type-4 tag. If not defined, +# the default value is 1. +# 0 NFA_RW_PRES_CHK_DEFAULT; Let stack selects an algorithm +# 1 NFA_RW_PRES_CHK_I_BLOCK; ISO-DEP protocol's empty I-block +# 2 NFA_RW_PRES_CHK_RESET; Deactivate to Sleep, then re-activate +# 3 NFA_RW_PRES_CHK_RB_CH0; Type-4 tag protocol's ReadBinary command on channel 0 +# 4 NFA_RW_PRES_CHK_RB_CH3; Type-4 tag protocol's ReadBinary command on channel 3 +# 5 NFA_RW_PRES_CHK_ISO_DEP_NAK; presence check command ISO-DEP NAK as per NCI2.0 +PRESENCE_CHECK_ALGORITHM=5 + +############################################################################### +# Name of the NCI HAL module to use +# If unset, falls back to nfc_nci.bcm2079x +NCI_HAL_MODULE="nfc_nci.st21nfc.default" + +############################################################################### +# Allow list to be set at startup. +DEVICE_HOST_ALLOW_LIST={02:C0} + +############################################################################### +# BAIL OUT value for P2P +# Implements algorithm for NFC-DEP protocol priority over ISO-DEP protocol. +POLL_BAIL_OUT_MODE=1 + +############################################################################### +# Extended APDU length for ISO_DEP +ISO_DEP_MAX_TRANSCEIVE=0xFEFF + +############################################################################### +# Configure the NFC Extras to open and use a static pipe. If the value is +# not set or set to 0, then the default is use a dynamic pipe based on a +# destination gate (see NFA_HCI_DEFAULT_DEST_GATE). Note there is a value +# for each EE (ESE/SIM) +OFF_HOST_ESE_PIPE_ID=0x5E +OFF_HOST_SIM_PIPE_ID=0x3E + +############################################################################### +#Set the default Felica T3T System Code OffHost route Location : +#This settings will be used when application does not set this parameter +# host 0x00 +# eSE 0x82 (eSE), 0x86 (eUICC/SPI-SE) +# UICC 0x81 (UICC_1), 0x85 (UICC_2) +DEFAULT_SYS_CODE_ROUTE=0x86 + +############################################################################### +#Set the Felica T3T System Code supported power state: +DEFAULT_SYS_CODE_PWR_STATE=0x3B + +############################################################################### +# Path and Files used for FW update binaries storage +STNFC_FW_PATH_STORAGE="/vendor/firmware" +STNFC_FW_BIN_NAME="/st54l_fw.bin" +STNFC_FW_CONF_NAME="/st54l_conf.bin" + +############################################################################### +# Default off-host route for Felica. +# This settings will be used when application does not set this parameter +# host 0x00 +# eSE 0x82 (eSE), 0x86 (eUICC/SPI-SE) +# UICC 0x81 (UICC_1), 0x85 (UICC_2) +DEFAULT_NFCF_ROUTE=0x86 + +############################################################################### +# Configure the default off-host route. +# used for technology A and B routing +# eSE 0x82 (eSE), 0x86 (eUICC/SPI-SE) +# UICC 0x81 (UICC_1), 0x85 (UICC_2) +DEFAULT_OFFHOST_ROUTE=0x81 + +############################################################################### +# Configure the default AID route. +# host 0x00 +# eSE 0x82 (eSE), 0x86 (eUICC/SPI-SE) +# UICC 0x81 (UICC_1), 0x85 (UICC_2) +DEFAULT_ROUTE=0x00 + +############################################################################### +# Configure the NFCEEIDs of offhost UICC. +# UICC 0x81 (UICC_1), 0x85 (UICC_2) +OFFHOST_ROUTE_UICC={81} + +############################################################################### +# Configure the NFCEEIDs of offhost eSEs. +# eSE 0x82 (eSE), 0x86 (eUICC/SPI-SE) +OFFHOST_ROUTE_ESE={86} + +############################################################################### +# Configure the list of NFCEE for the ISO-DEP routing. +# host 0x00 +# eSE 0x82 (eSE), 0x86 (eUICC/SPI-SE) +# UICC 0x81 (UICC_1), 0x85 (UICC_2) +DEFAULT_ISODEP_ROUTE=0x00 + +############################################################################### +# Configure the HAL Clock control +# enable 0x01 +# disable 0x00 default value +STNFC_CONTROL_CLK=0x00 + +############################################################################### +# Configure the Field on timer +# enable 0x01 +# disable 0x00 default value +STNFC_REMOTE_FIELD_TIMER=0x01 + +############################################################################### +# Configure the ACTIVE_RW timer +# Default 0x00, set 0x01 to enable it +# STNFC_ACTIVERW_TIMER=0x01 + +############################################################################### +# Core configuration settings +CORE_CONF_PROP={ 20, 02, 0a, 03, + a1, 01, 1e, + a2, 01, 19, + 80, 01, 01 +} + + diff --git a/nfc/libnfc-nci.conf b/nfc/libnfc-nci.conf new file mode 100644 index 0000000..be65f66 --- /dev/null +++ b/nfc/libnfc-nci.conf @@ -0,0 +1,121 @@ +############################################################################### +# Application options +NFC_DEBUG_ENABLED=0 + +############################################################################### +# File used for NFA storage +NFA_STORAGE="/data/nfc" + +############################################################################### +# Force UICC to only listen to the following technology(s). +# The bits are defined as tNFA_TECHNOLOGY_MASK in nfa_api.h. +# Default is NFA_TECHNOLOGY_MASK_A | NFA_TECHNOLOGY_MASK_B | NFA_TECHNOLOGY_MASK_F +UICC_LISTEN_TECH_MASK=0x07 + +############################################################################### +# Set HOST default listen to the following technology(s). +# The bits are defined as tNFA_TECHNOLOGY_MASK in nfa_api.h. +# Default is NFA_TECHNOLOGY_MASK_A | NFA_TECHNOLOGY_MASK_F +# 0x07 = A + B + F +HOST_LISTEN_TECH_MASK=0x07 + +############################################################################### +# AID for Empty Select command +# If specified, this AID will be substituted when an Empty SELECT command is +# detected. The first byte is the length of the AID. Maximum length is 16. +AID_FOR_EMPTY_SELECT={08:A0:00:00:01:51:00:00:00} + +############################################################################### +# When screen is turned off, specify the desired power state of the controller. +# 0: power-off-sleep state; DEFAULT +# 1: full-power state +# 2: screen-off card-emulation (CE4/CE3/CE1 modes are used) +SCREEN_OFF_POWER_STATE=1 + +############################################################################### +# Force tag polling for the following technology(s). +# The bits are defined as tNFA_TECHNOLOGY_MASK in nfa_api.h. +# Default is NFA_TECHNOLOGY_MASK_A | NFA_TECHNOLOGY_MASK_B | +# NFA_TECHNOLOGY_MASK_F | NFA_TECHNOLOGY_MASK_ISO15693 | +# NFA_TECHNOLOGY_MASK_B_PRIME | NFA_TECHNOLOGY_MASK_KOVIO | +# NFA_TECHNOLOGY_MASK_ACTIVE +# +# Notable bits: +# NFA_TECHNOLOGY_MASK_A 0x01 /* NFC Technology A */ +# NFA_TECHNOLOGY_MASK_B 0x02 /* NFC Technology B */ +# NFA_TECHNOLOGY_MASK_F 0x04 /* NFC Technology F */ +# NFA_TECHNOLOGY_MASK_ISO15693 0x08 /* Proprietary Technology */ +# NFA_TECHNOLOGY_MASK_KOVIO 0x20 /* Proprietary Technology */ +# NFA_TECHNOLOGY_MASK_ACTIVE 0x40 /* NFC Technology Active */ +POLLING_TECH_MASK=0x2F + +############################################################################### +# Force P2P to only listen for the following technology(s). +# The bits are defined as tNFA_TECHNOLOGY_MASK in nfa_api.h. +# Default is NFA_TECHNOLOGY_MASK_A | NFA_TECHNOLOGY_MASK_F | +# NFA_TECHNOLOGY_MASK_ACTIVE +# +# Notable bits: +# NFA_TECHNOLOGY_MASK_A 0x01 /* NFC Technology A */ +# NFA_TECHNOLOGY_MASK_F 0x04 /* NFC Technology F */ +# NFA_TECHNOLOGY_MASK_ACTIVE 0x40 /* NFC Technology Active */ +P2P_LISTEN_TECH_MASK=0x00 + +PRESERVE_STORAGE=0x01 + +############################################################################### +# Override the stack default for NFA_EE_MAX_EE_SUPPORTED set in nfc_target.h. +# The value is set to 3 by default as it assumes we will discover 0xF2, +# 0xF3, and 0xF4. If a platform will exclude and SE, this value can be reduced +# so that the stack will not wait any longer than necessary. +# Maximum EE supported number +# NXP PN547C2 0x02 +# NXP PN65T 0x03 +# NXP PN548C2 0x02 +# NXP PN66T 0x03 +NFA_MAX_EE_SUPPORTED=0x02 + +############################################################################### +# AID_MATCHING constants +# AID_MATCHING_EXACT_ONLY 0x00 +# AID_MATCHING_EXACT_OR_PREFIX 0x01 +# AID_MATCHING_PREFIX_ONLY 0x02 +# AID_MATCHING_EXACT_OR_SUBSET_OR_PREFIX 0x03 +AID_MATCHING_MODE=0x03 + +############################################################################### +#Set the default Felica T3T System Code : +#This settings will be used when application does not set this parameter +DEFAULT_SYS_CODE={FE:FE} + +############################################################################### +# Value of NIC parameter NFCC_COFNIG_CONTROL +# 0x00 NFCC is not allowed to manage RF configuration +# 0x01 NFCC is allowed to manage RF configuration +NFCC_CONFIG_CONTROL=0x01 + +############################################################################### +#Set if the AID routing should be blocked for the power modes not supported. +NFA_AID_BLOCK_ROUTE=1 + +############################################################################### +#Set the OffHost AID supported power state: +OFFHOST_AID_ROUTE_PWR_STATE=0x3B + +############################################################################### +# Mifare Tag implementation +# 0: General implementation +# 1: Legacy implementation +LEGACY_MIFARE_READER=0 + +############################################################################### +# Nfc recovery implementation +# 0: Crash Nfc Service +# 1: Toggle Nfc state +RECOVERY_OPTION=1 + +############################################################################### +# NFCEE Power Supply and Communication Link Control Configuration +# Set when SetAlwaysOn enabled +# Default 0x00 when SetAlways on disabled +ALWAYS_ON_SET_EE_POWER_AND_LINK_CONF=0x00 diff --git a/nfc/libse-gto-hal-disable.conf b/nfc/libse-gto-hal-disable.conf new file mode 100644 index 0000000..50e925c --- /dev/null +++ b/nfc/libse-gto-hal-disable.conf @@ -0,0 +1,2 @@ +#Gemalto SPI devnode +GTO_DEV=/dev/nothing; diff --git a/nfc/libse-gto-hal.conf b/nfc/libse-gto-hal.conf new file mode 100644 index 0000000..f4e443d --- /dev/null +++ b/nfc/libse-gto-hal.conf @@ -0,0 +1,2 @@ +#Gemalto SPI devnode +GTO_DEV=/dev/st54spi; diff --git a/nfc/manifest_se.xml b/nfc/manifest_se.xml new file mode 100644 index 0000000..39fe63e --- /dev/null +++ b/nfc/manifest_se.xml @@ -0,0 +1,7 @@ + + + android.hardware.secure_element + hwbinder + @1.2::ISecureElement/eSE1 + + diff --git a/perf/powerhint-tegu.json b/perf/powerhint-tegu.json new file mode 100644 index 0000000..18198d6 --- /dev/null +++ b/perf/powerhint-tegu.json @@ -0,0 +1,2387 @@ +{ + "Nodes": [ + { + "Name": "MemFreq", + "Path": "/sys/devices/platform/17000010.devfreq_mif/devfreq/17000010.devfreq_mif/min_freq", + "Values": [ + "3744000", + "1352000", + "1014000", + "421000" + ], + "ResetOnInit": true + }, + { + "Name": "IntFreq", + "Path": "/sys/devices/platform/17000020.devfreq_int/devfreq/17000020.devfreq_int/min_freq", + "Values": [ + "533000", + "100000" + ], + "ResetOnInit": true + }, + { + "Name": "DsuFreq", + "Path": "/sys/devices/platform/17000090.devfreq_dsu/devfreq/17000090.devfreq_dsu/min_freq", + "Values": [ + "2150000", + "1328000", + "820000", + "324000" + ], + "ResetOnInit": true + }, + { + "Name": "BCIFreq", + "Path": "/sys/devices/platform/170000a0.devfreq_bci/devfreq/170000a0.devfreq_bci/min_freq", + "Values": [ + "1850000", + "1205000", + "840000", + "315000" + ], + "ResetOnInit": true + }, + { + "Name": "CPULittleClusterMaxFreq", + "Path": "/sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq", + "Values": [ + "9999999", + "1098000", + "1475000", + "975000", + "1197000", + "1328000", + "1548000", + "1844000" + ], + "DefaultIndex": 0, + "ResetOnInit": true + }, + { + "Name": "CPULittleClusterMinFreq", + "Path": "/sys/devices/system/cpu/cpu0/cpufreq/scaling_min_freq", + "Values": [ + "9999999", + "1475000", + "1197000", + "0" + ], + "ResetOnInit": true + }, + { + "Name": "CPUMidClusterMaxFreq", + "Path": "/sys/devices/system/cpu/cpu4/cpufreq/scaling_max_freq", + "Values": [ + "9999999", + "1082000", + "1221000", + "1418000", + "910000", + "1328000", + "1622000", + "1836000", + "1999000" + ], + "DefaultIndex": 0, + "ResetOnInit": true + }, + { + "Name": "CPUMidClusterMinFreq", + "Path": "/sys/devices/system/cpu/cpu4/cpufreq/scaling_min_freq", + "Values": [ + "9999999", + "1836000", + "1221000", + "0" + ], + "ResetOnInit": true + }, + { + "Name": "CPUBigClusterMaxFreq", + "Path": "/sys/devices/system/cpu/cpu8/cpufreq/scaling_max_freq", + "Values": [ + "9999999", + "893000", + "1328000", + "1852000", + "1164000", + "1557000", + "1745000", + "2049000", + "2409000" + ], + "DefaultIndex": 0, + "ResetOnInit": true + }, + { + "Name": "CPUBigClusterMinFreq", + "Path": "/sys/devices/system/cpu/cpu8/cpufreq/scaling_min_freq", + "Values": [ + "9999999", + "1852000", + "1164000", + "0" + ], + "ResetOnInit": true + }, + { + "Name": "GPUMinFreq", + "Path": "/sys/devices/platform/1f000000.mali/hint_min_freq", + "Values": [ + "649000", + "580000", + "521000", + "467000", + "376000", + "302000", + "150000" + ], + "ResetOnInit": true + }, + { + "Name": "ReducePreferIdle", + "Path": "/proc/vendor_sched/reduce_prefer_idle", + "Values": [ + "0", + "1" + ], + "ResetOnInit": true + }, + { + "Name": "CPUUtilThreshold", + "Path": "/proc/vendor_sched/util_threshold", + "Values": [ + "1280", + "1100" + ], + "DefaultIndex": 0, + "ResetOnInit": true + }, + { + "Name": "CAMUClampBoost", + "Path": "/proc/vendor_sched/cam_uclamp_min", + "Values": [ + "612", + "0" + ], + "ResetOnInit": true + }, + { + "Name": "TAUClampBoost", + "Path": "/proc/vendor_sched/ta_uclamp_min", + "Values": [ + "612", + "1" + ], + "ResetOnInit": true + }, + { + "Name": "FGUClampBoost", + "Path": "/proc/vendor_sched/fg_uclamp_min", + "Values": [ + "159", + "0" + ], + "ResetOnInit": true + }, + { + "Name": "MLUclampBoost", + "Path": "/proc/vendor_sched/nnapi_uclamp_min", + "Values": [ + "180", + "650" + ], + "DefaultIndex": 0, + "ResetOnInit": true + }, + { + "Name": "PMQoSCpuDmaLatency", + "Path": "/dev/cpu_dma_latency", + "Values": [ + "44", + "1000" + ], + "HoldFd": true + }, + { + "Name": "CDPreferIdle", + "Path": "/proc/vendor_sched/cam_prefer_idle", + "Values": [ + "0", + "1" + ], + "ResetOnInit": true + }, + { + "Name": "CDCpuset", + "Path": "/dev/cpuset/camera-daemon/cpus", + "Values": [ + "0-3", + "4-8", + "0-7", + "0-8" + ], + "ResetOnInit": true + }, + { + "Name": "CDHighCpusetCpus", + "Path": "/dev/cpuset/camera-daemon-high-group/cpus", + "Values": [ + "0-3", + "8", + "0-8" + ], + "ResetOnInit": true + }, + { + "Name": "CDMidCpusetCpus", + "Path": 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"THERMAL_VIRTUAL-SKIN-HINT_EMERGENCY", + "Node": "MidSwitchOnTempSet", + "Duration": 0, + "Value": "60000" + }, + { + "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_EMERGENCY", + "Node": "LittleSwitchOnTempSet", + "Duration": 0, + "Value": "60000" + }, + { + "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_EMERGENCY", + "Node": "G3dSwitchOnTempSet", + "Duration": 0, + "Value": "60000" + }, + { + "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_EMERGENCY", + "Node": "TpuSwitchOnTempSet", + "Duration": 0, + "Value": "60000" + }, + { + "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_EMERGENCY", + "Node": "AurSwitchOnTempSet", + "Duration": 0, + "Value": "60000" + }, + { + "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_EMERGENCY", + "Node": "Dex2oatThreads", + "Duration": 0, + "Value": "1" + }, + { + "PowerHint": "THERMAL_VIRTUAL-SKIN-HINT_EMERGENCY", + "Node": "Dex2oatCPUSet", + "Duration": 0, + "Value": "0,1,2,3" + }, + { + "PowerHint": "FACE_UNLOCK_BOOST", + "Node": "CPUBigClusterMaxFreq", + "Duration": 1000, + "Value": "9999999" + }, + { + "PowerHint": "FACE_UNLOCK_BOOST", + "Node": "CPU_LITTLE_TSKIN_BYPASS", + "Duration": 1000, + "Value": "1" + }, + { + "PowerHint": "FACE_UNLOCK_BOOST", + "Node": "CPU_MID_TSKIN_BYPASS", + "Duration": 1000, + "Value": "1" + }, + { + "PowerHint": "FACE_UNLOCK_BOOST", + "Node": "CPU_BIG_TSKIN_BYPASS", + "Duration": 1000, + "Value": "1" + }, + { + "PowerHint": "FP_BOOST", + "Node": "CPUBigClusterMaxFreq", + "Duration": 1000, + "Value": "9999999" + }, + { + "PowerHint": "FP_BOOST", + "Node": "CPUBigClusterMinFreq", + "Duration": 1000, + "Value": "9999999" + }, + { + "PowerHint": "FP_BOOST", + "Node": "CPU_LITTLE_TSKIN_BYPASS", + "Duration": 1000, + "Value": "1" + }, + { + "PowerHint": "FP_BOOST", + "Node": "CPU_MID_TSKIN_BYPASS", + "Duration": 1000, + "Value": "1" + }, + { + "PowerHint": "FP_BOOST", + "Node": "CPU_BIG_TSKIN_BYPASS", + "Duration": 1000, + "Value": "1" + }, + { + "PowerHint": "FP_BOOST", + "Node": "TRUSTY_VIRTIO_HIGH", + "Duration": 1000, + "Value": "1" + }, + { + "PowerHint": "FP_BOOST", + "Node": "TRUSTY_HIGH", + "Duration": 1000, + "Value": "1" + }, + { + "PowerHint": "ML_ACC", + "Node": "MLUclampBoost", + "Duration": 2000, + "Value": "650" + }, + { + "PowerHint": "ML_ACC", + "Node": "PMQoSCpuDmaLatency", + "Duration": 2000, + "Value": "44" + } + ], + "AdpfConfig": [ + { + "Name": "REFRESH_120FPS", + "PID_On": true, + "PID_Po": 2.0, + "PID_Pu": 1.0, + "PID_I": 0.0, + "PID_I_Init": 200, + "PID_I_High": 512, + "PID_I_Low": -30, + "PID_Do": 500.0, + "PID_Du": 0.0, + "UclampMin_On": true, + "UclampMin_Init": 185, + "UclampMin_High": 384, + "UclampMin_Low": 2, + "SamplingWindow_P": 1, + "SamplingWindow_I": 0, + "SamplingWindow_D": 1, + "ReportingRateLimitNs": 83333330, + "EarlyBoost_On": false, + "EarlyBoost_TimeFactor": 0.0, + "TargetTimeFactor": 1.0, + "StaleTimeFactor": 20.0 + }, + { + "Name": "REFRESH_90FPS", + "PID_On": true, + "PID_Po": 2.0, + "PID_Pu": 1.0, + "PID_I": 0.0, + "PID_I_Init": 200, + "PID_I_High": 512, + "PID_I_Low": -30, + "PID_Do": 500.0, + "PID_Du": 0.0, + "UclampMin_On": true, + "UclampMin_Init": 129, + "UclampMin_High": 384, + "UclampMin_Low": 2, + "SamplingWindow_P": 1, + "SamplingWindow_I": 0, + "SamplingWindow_D": 1, + "ReportingRateLimitNs": 111111110, + "EarlyBoost_On": false, + "EarlyBoost_TimeFactor": 0.0, + "TargetTimeFactor": 1.0, + "StaleTimeFactor": 20.0 + }, + { + "Name": "REFRESH_60FPS", + "PID_On": true, + "PID_Po": 2.0, + "PID_Pu": 1.0, + "PID_I": 0.0, + "PID_I_Init": 200, + "PID_I_High": 512, + "PID_I_Low": -30, + "PID_Do": 500.0, + "PID_Du": 0.0, + "UclampMin_On": true, + "UclampMin_Init": 129, + "UclampMin_High": 384, + "UclampMin_Low": 2, + "SamplingWindow_P": 1, + "SamplingWindow_I": 0, + "SamplingWindow_D": 1, + "ReportingRateLimitNs": 166666660, + "EarlyBoost_On": false, + "EarlyBoost_TimeFactor": 0.0, + "TargetTimeFactor": 1.0, + "StaleTimeFactor": 20.0 + }, + { + "Name": "UiHighBoostWithoutPid", + "PID_On": false, + "PID_Po": 0, + "PID_Pu": 0, + "PID_I": 0, + "PID_I_Init": 0, + "PID_I_High": 0, + "PID_I_Low": 0, + "PID_Do": 0, + "PID_Du": 0, + "SamplingWindow_P": 1, + "SamplingWindow_I": 1, + "SamplingWindow_D": 1, + "UclampMin_On": true, + "UclampMin_Init": 200, + "UclampMin_High": 157, + "UclampMin_Low": 157, + "ReportingRateLimitNs": 1, + "EarlyBoost_On": false, + "EarlyBoost_TimeFactor": 0.0, + "TargetTimeFactor": 1.0, + "StaleTimeFactor": 5.0 + }, + { + "Name": "UiLowBoostWithoutPid", + "PID_On": false, + "PID_Po": 0, + "PID_Pu": 0, + "PID_I": 0, + "PID_I_Init": 0, + "PID_I_High": 0, + "PID_I_Low": 0, + "PID_Do": 0, + "PID_Du": 0, + "SamplingWindow_P": 1, + "SamplingWindow_I": 1, + "SamplingWindow_D": 1, + "UclampMin_On": true, + "UclampMin_Init": 200, + "UclampMin_High": 42, + "UclampMin_Low": 42, + "ReportingRateLimitNs": 1, + "EarlyBoost_On": false, + "EarlyBoost_TimeFactor": 0.0, + "TargetTimeFactor": 1.0, + "StaleTimeFactor": 5.0 + }, + { + "Name": "UiLowNoneBoost", + "PID_On": false, + "PID_Po": 0, + "PID_Pu": 0, + "PID_I": 0, + "PID_I_Init": 0, + "PID_I_High": 0, + "PID_I_Low": 0, + "PID_Do": 0, + "PID_Du": 0, + "SamplingWindow_P": 1, + "SamplingWindow_I": 1, + "SamplingWindow_D": 1, + "UclampMin_On": true, + "UclampMin_Init": 200, + "UclampMin_High": 0, + "UclampMin_Low": 0, + "ReportingRateLimitNs": 1, + "EarlyBoost_On": false, + "EarlyBoost_TimeFactor": 0.0, + "TargetTimeFactor": 1.0, + "StaleTimeFactor": 5.0 + } + ] +} diff --git a/powerstats/tegu/Android.bp b/powerstats/tegu/Android.bp new file mode 100644 index 0000000..f80f09f --- /dev/null +++ b/powerstats/tegu/Android.bp @@ -0,0 +1,42 @@ +// Copyright (C) 2021 The Android Open Source Project +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +soong_namespace { + imports: [ + "hardware/google/pixel", + "device/google/zumapro/powerstats", + ] +} + +package { + // See: http://go/android-license-faq + // A large-scale-change added 'default_applicable_licenses' to import + // all of the 'license_kinds' from "device_google_tegu_license" + // to get the below license kinds: + // SPDX-license-identifier-Apache-2.0 + default_applicable_licenses: ["device_google_tegu_license"], +} + +cc_binary { + name: "android.hardware.power.stats-service.pixel", + defaults: ["powerstats_pixel_binary_defaults"], + + srcs: [ + "*.cpp", + ], + + shared_libs: [ + "android.hardware.power.stats-impl.zumapro", + ], +} diff --git a/powerstats/tegu/service.cpp b/powerstats/tegu/service.cpp new file mode 100644 index 0000000..2cbcca3 --- /dev/null +++ b/powerstats/tegu/service.cpp @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2021 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#define LOG_TAG "android.hardware.power.stats-service.pixel" + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +using aidl::android::hardware::power::stats::DisplayStateResidencyDataProvider; +using aidl::android::hardware::power::stats::EnergyConsumerType; +using aidl::android::hardware::power::stats::PowerStatsEnergyConsumer; + +void addDisplay(std::shared_ptr p) { + // Add display residency stats + std::vector states = { + "Off", + "LP: 1440x3120@30", + "On: 1440x3120@60", + "On: 1440x3120@90", + "HBM: 1440x3120@60", + "HBM: 1440x3120@90"}; + + p->addStateResidencyDataProvider(std::make_unique( + "Display", + "/sys/class/backlight/panel0-backlight/state", + states)); + + // Add display energy consumer + p->addEnergyConsumer(PowerStatsEnergyConsumer::createMeterConsumer( + p, + EnergyConsumerType::DISPLAY, + "Display", + {"VSYS_PWR_DISPLAY"})); +} + +int main() { + LOG(INFO) << "Pixel PowerStats HAL AIDL Service is starting."; + + // single thread + ABinderProcess_setThreadPoolMaxThreadCount(0); + + std::shared_ptr p = ndk::SharedRefBase::make(); + + addZumaProCommonDataProviders(p); + addDisplay(p); + + const std::string instance = std::string() + PowerStats::descriptor + "/default"; + binder_status_t status = AServiceManager_addService(p->asBinder().get(), instance.c_str()); + LOG_ALWAYS_FATAL_IF(status != STATUS_OK); + + ABinderProcess_joinThreadPool(); + return EXIT_FAILURE; // should not reach +} diff --git a/rro_overlays/WifiOverlay/Android.bp b/rro_overlays/WifiOverlay/Android.bp new file mode 100644 index 0000000..79a8d9c --- /dev/null +++ b/rro_overlays/WifiOverlay/Android.bp @@ -0,0 +1,18 @@ +package { + // See: http://go/android-license-faq + // A large-scale-change added 'default_applicable_licenses' to import + // all of the 'license_kinds' from "//device/google/tegu:device_google_tegu_license" + // to get the below license kinds: + // SPDX-license-identifier-Apache-2.0 + default_applicable_licenses: [ + "//device/google/tegu:device_google_tegu_license", + ], +} + +runtime_resource_overlay { + name: "WifiOverlay2024", + theme: "WifiOverlay2024", + certificate: "platform", + sdk_version: "current", + product_specific: true +} diff --git a/rro_overlays/WifiOverlay/AndroidManifest.xml b/rro_overlays/WifiOverlay/AndroidManifest.xml new file mode 100644 index 0000000..632ac6a --- /dev/null +++ b/rro_overlays/WifiOverlay/AndroidManifest.xml @@ -0,0 +1,27 @@ + + + + + + + diff --git a/rro_overlays/WifiOverlay/OWNERS b/rro_overlays/WifiOverlay/OWNERS new file mode 100644 index 0000000..8b6c5a7 --- /dev/null +++ b/rro_overlays/WifiOverlay/OWNERS @@ -0,0 +1,4 @@ +# People who can approve changes for submission +kumachang@google.com +wangroger@google.com +hsuvictor@google.com diff --git a/rro_overlays/WifiOverlay/res/values/config.xml b/rro_overlays/WifiOverlay/res/values/config.xml new file mode 100644 index 0000000..dc3055a --- /dev/null +++ b/rro_overlays/WifiOverlay/res/values/config.xml @@ -0,0 +1,166 @@ + + + + + + true + + + true + + + true + + + true + + + -77 + -80 + + -80 + -83 + + + false + + + true + + + 524288,2097152,8388608,262144,524288,4194304 + + + true + + + true + + + true + true + + + true + + + true + + + true + + + true + + + Pixel + + + 32 + + + + 1 + 2 + 3 + 8 + + + + 3000 + + + 10 + + + true + + + true + + + true + + + true + + + false + + + true + + + true + + + true + + + true + + + true + + + true + + + true + + + true + + + false + + + true + + + + 1 + + true + + + true + + true + + + true + + false + diff --git a/tegu/BoardConfig.mk b/tegu/BoardConfig.mk new file mode 100644 index 0000000..adb6485 --- /dev/null +++ b/tegu/BoardConfig.mk @@ -0,0 +1,28 @@ +# +# Copyright (C) 2020 The Android Open-Source Project +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +TARGET_BOARD_INFO_FILE := device/google/tegu/board-info.txt +TARGET_BOOTLOADER_BOARD_NAME := tegu +TARGET_SCREEN_DENSITY := 480 +BOARD_USES_GENERIC_AUDIO := true +USES_DEVICE_GOOGLE_TEGU := true + +include device/google/tegu/device-tegu-common.mk + +include device/google/zumapro/BoardConfig-common.mk +-include vendor/google_devices/zumapro/prebuilts/BoardConfigVendor.mk +include device/google/tegu-sepolicy/tegu-sepolicy.mk +include device/google/tegu/wifi/BoardConfig-wifi.mk diff --git a/tegu/overlay/frameworks/base/core/res/res/values/config.xml b/tegu/overlay/frameworks/base/core/res/res/values/config.xml new file mode 100644 index 0000000..88809ba --- /dev/null +++ b/tegu/overlay/frameworks/base/core/res/res/values/config.xml @@ -0,0 +1,259 @@ + + + + + + true + + + true + + + 6 + + + 0.0 + + + 1.0 + + + + 0.075192308 + + + 0 + + + 120 + + + + 2 + + + 5 + + + + 120 + + + 60 + + + + 1 + 2 + 3 + 4 + 8 + 12 + 15 + 20 + 33 + 55 + 90 + 148 + 245 + 403 + 665 + 1097 + 1808 + 3000 + 6000 + 9000 + 10000 + 14000 + 20000 + 25000 + 31000 + 51000 + 81000 + 100000 + + + + + 5.139055 + 9.962018965 + 18.34822964 + 21.55068128 + 24.0167788 + 32.5 + 46 + 53.26923077 + 54.61538462 + 58.11538462 + 62.1394 + 67.13133333 + 79.67614115 + 98.04727274 + 125.1221991 + 161.6875093 + 208.4885553 + 264.8221315 + 328.5869521 + 627.4315413 + 826.8584866 + 867.85582302 + 1041.39662279 + 1227.52633489 + 1331.28933608 + 1414.57566867 + 1553.22826182 + 1614.01031782 + 1850 + + + + 1000 + 4000 + + + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 20 + 30 + 40 + 50 + 60 + 70 + 80 + 90 + 100 + 200 + 300 + 400 + 500 + 1000 + 2000 + 3000 + 4000 + + + + 5186 + 4333 + 3666 + 2999 + 2759 + 2519 + 2279 + 2039 + 1799 + 799 + 527 + 499 + 470 + 517 + 565 + 612 + 660 + 708 + 742 + 636 + 582 + 549 + 369 + 294 + 269 + 220 + 220 + + + + 525 + 683 + 666 + 650 + 640 + 630 + 620 + 610 + 600 + 500 + 500 + 440 + 385 + 382 + 379 + 376 + 373 + 371 + 367 + 387 + 397 + 403 + 380 + 345 + 333 + 283 + 283 + + + + 1280 + 2856 + + + 0.335 + diff --git a/tegu/overlay/frameworks/base/packages/SystemUI/res/values/config.xml b/tegu/overlay/frameworks/base/packages/SystemUI/res/values/config.xml new file mode 100644 index 0000000..21942ac --- /dev/null +++ b/tegu/overlay/frameworks/base/packages/SystemUI/res/values/config.xml @@ -0,0 +1,66 @@ + + + + + + + + m 585.74,68.4 a 49.16,60.6 0 0 0 -91.47,0 49.16,60.6 0 0 0 91.47,0 Z + + + + 1 + + + com.google.android.as + + true + + + com.google.sensor.binned_brightness + + + + -1 + 2 + 2 + 8 + 8 + + + + + -1 + 133 + 0 + 0 + 0 + + + + 100 + diff --git a/tegu/overlay/packages/apps/Nfc/res/values/config.xml b/tegu/overlay/packages/apps/Nfc/res/values/config.xml new file mode 100644 index 0000000..5058cfa --- /dev/null +++ b/tegu/overlay/packages/apps/Nfc/res/values/config.xml @@ -0,0 +1,25 @@ + + + + false + true + + GR83Y + GEC77 + GWVK6 + + true + diff --git a/thermal/thermal_info_config_charge_komodo.json b/thermal/thermal_info_config_charge_komodo.json new file mode 100644 index 0000000..111db7a --- /dev/null +++ b/thermal/thermal_info_config_charge_komodo.json @@ -0,0 +1,197 @@ +{ + "Sensors":[ + { + "Name":"north_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 42.1, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "TempPath":"/dev/thermal/tz-by-name/north_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"rfpa_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 43.7, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "TempPath":"/dev/thermal/tz-by-name/rfpa_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"soc_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 57.2, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "TempPath":"/dev/thermal/tz-by-name/soc_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"charging_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 58.4, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "TempPath":"/dev/thermal/tz-by-name/charging_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"disp_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 41.7, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "TempPath":"/dev/thermal/tz-by-name/disp_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"battery", + "Type":"BATTERY", + "HotThreshold":["NAN", "NAN", "NAN", "NAN", "NAN", "NAN", 60.0], + "Multiplier":0.001 + }, + { + "Name":"btmspkr_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 54.1, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "TempPath":"/dev/thermal/tz-by-name/btmspkr_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"quiet_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 44.6, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "TempPath":"/dev/thermal/tz-by-name/quiet_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"usb_pwr_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 45.0, "NAN", "NAN", "NAN", "NAN", "NAN"], + "TempPath":"/dev/thermal/tz-by-name/usb_pwr_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"VIRTUAL-SKIN-CHARGE-SUB-0", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0.04, 0.16, 0.19, 0.16, 0.17, 0, 0.01, 0.24, 0], + "Offset":-820, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-CHARGE-SUB-1", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0.02, 0.01, 0.04, 0.04, 0.4, 0.14, 0.1, 0.02, 0.12], + "Offset":1840, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-CHARGE-SUB-2", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0.18, 0.1, 0.15, 0.13, 0.22, 0.16, 0.02, 0.04, 0.01], + "Offset":-2810, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-CHARGE-SUB-3", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0.1, 0.16, 0.11, 0.19, 0.26, 0, 0, 0.11, 0], + "Offset":1140, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-CHARGE", + "Type":"UNKNOWN", + "Version":"4.0", + "VirtualSensor":true, + "TriggerSensor":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "quiet_therm", "usb_pwr_therm"], + "Formula":"MAXIMUM", + "Combination":["VIRTUAL-SKIN-CHARGE-SUB-0", "VIRTUAL-SKIN-CHARGE-SUB-1", "VIRTUAL-SKIN-CHARGE-SUB-2", "VIRTUAL-SKIN-CHARGE-SUB-3"], + "Coefficient":[1.0, 1.0, 1.0, 1.0], + "HotThreshold":["NAN", 44.0, 48.0, 51.0, 55.0, 57.0, 75.0], + "HotHysteresis":[0.0, 1.9, 3.9, 2.9, 3.9, 1.9, 1.9], + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000, + "PIDInfo": { + "K_Po":["NAN", "NAN", 119, "NAN", "NAN", "NAN", "NAN"], + "K_Pu":["NAN", "NAN", 119, "NAN", "NAN", "NAN", "NAN"], + "K_I":["NAN", "NAN", 25, "NAN", "NAN", "NAN", "NAN"], + "K_D":["NAN", "NAN", 0, "NAN", "NAN", "NAN", "NAN"], + "I_Max":["NAN", "NAN", 1302, "NAN", "NAN", "NAN", "NAN"], + "S_Power":["NAN", "NAN", 2527, "NAN", "NAN", "NAN", "NAN"], + "MinAllocPower":["NAN", "NAN", 0, "NAN", "NAN", "NAN", "NAN"], + "MaxAllocPower":["NAN", "NAN", 6219, "NAN", "NAN", "NAN", "NAN"], + "I_Cutoff":["NAN", "NAN", 6, "NAN", "NAN", "NAN", "NAN"], + "I_Default":1302 + }, + "ExcludedPowerInfo": [ + { + "PowerRail": "PARTIAL_SYSTEM_POWER", + "PowerWeight": [0.12, 0.12, 0.06, 0.06, 0.24, 0.24, 0.24] + } + ], + "BindedCdevInfo": [ + { + "CdevRequest": "chg_mdis", + "CdevWeightForPID": [1, 1, 1, 1, 1, 1, 1], + "MaxReleaseStep": 1, + "MaxThrottleStep": 1, + "CdevCeiling": [0, 25, 25, 25, 26, 26, 26], + "LimitInfo": [0, 0, 1, 1, 1, 26, 26] + } + ] + } + ], + "CoolingDevices":[ + { + "Name":"chg_mdis", + "Type":"BATTERY" + }, + { + "Name":"usbc-port", + "Type":"BATTERY" + } + ], + "PowerRails":[ + { + "Name":"PARTIAL_SYSTEM_POWER", + "VirtualRails":true, + "Formula":"WEIGHTED_AVG", + "Combination":["S1S_VDD_CAM", "S4S_VDD2H_MEM", "S5S_VDDQ_MEM", "S8S_VDD_G3D_L2", "S9S_VDD_AOC", "L2S_PLL_MIPI_UFS", "L9S_GNSS_CORE", "L21S_VDD2L_MEM", "VSYS_PWR_DISPLAY", "VSYS_PWR_WLAN_BT", "S1M_VDD_MIF", "S5M_VDD_INT", "S6M_LLDO1", "S7M_VDD_TPU", "S8M_LLDO2", "VSYS_PWR_MODEM"], + "Coefficient":[1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0], + "PowerSampleDelay":7000, + "PowerSampleCount":5 + } + ] +} diff --git a/thermal/thermal_info_config_charge_ripcurrent24.json b/thermal/thermal_info_config_charge_ripcurrent24.json new file mode 100644 index 0000000..4e7eecb --- /dev/null +++ b/thermal/thermal_info_config_charge_ripcurrent24.json @@ -0,0 +1,19 @@ +{ + "Sensors":[ + { + "Name":"battery", + "Type":"BATTERY", + "HotThreshold":[ + "NAN", + "NAN", + "NAN", + "NAN", + "NAN", + "NAN", + "60.0" + ], + "VrThreshold":"NAN", + "Multiplier":0.001 + } + ] +} diff --git a/thermal/thermal_info_config_charge_ripcurrentpro.json b/thermal/thermal_info_config_charge_ripcurrentpro.json new file mode 100644 index 0000000..4e7eecb --- /dev/null +++ b/thermal/thermal_info_config_charge_ripcurrentpro.json @@ -0,0 +1,19 @@ +{ + "Sensors":[ + { + "Name":"battery", + "Type":"BATTERY", + "HotThreshold":[ + "NAN", + "NAN", + "NAN", + "NAN", + "NAN", + "NAN", + "60.0" + ], + "VrThreshold":"NAN", + "Multiplier":0.001 + } + ] +} diff --git a/thermal/thermal_info_config_charge_tegu.json b/thermal/thermal_info_config_charge_tegu.json new file mode 100644 index 0000000..642c942 --- /dev/null +++ b/thermal/thermal_info_config_charge_tegu.json @@ -0,0 +1,197 @@ +{ + "Sensors":[ + { + "Name":"north_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 42.1, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "TempPath":"/dev/thermal/tz-by-name/north_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"rfpa_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 43.7, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "TempPath":"/dev/thermal/tz-by-name/rfpa_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"soc_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 57.2, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "TempPath":"/dev/thermal/tz-by-name/soc_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"charging_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 58.4, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "TempPath":"/dev/thermal/tz-by-name/charging_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"disp_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 41.7, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "TempPath":"/dev/thermal/tz-by-name/disp_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"battery", + "Type":"BATTERY", + "HotThreshold":["NAN", "NAN", "NAN", "NAN", "NAN", "NAN", 60.0], + "Multiplier":0.001 + }, + { + "Name":"btmspkr_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 54.1, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "TempPath":"/dev/thermal/tz-by-name/btmspkr_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"quiet_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 44.6, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "TempPath":"/dev/thermal/tz-by-name/quiet_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"usb_pwr_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 45.0, "NAN", "NAN", "NAN", "NAN", "NAN"], + "TempPath":"/dev/thermal/tz-by-name/usb_pwr_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"VIRTUAL-SKIN-CHARGE-SUB-0", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0.04, 0.16, 0.19, 0.16, 0.17, 0, 0.01, 0.24, 0], + "Offset":-820, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-CHARGE-SUB-1", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0.02, 0.01, 0.04, 0.04, 0.4, 0.14, 0.1, 0.02, 0.12], + "Offset":1840, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-CHARGE-SUB-2", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0.18, 0.1, 0.15, 0.13, 0.22, 0.16, 0.02, 0.04, 0.01], + "Offset":-2810, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-CHARGE-SUB-3", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0.1, 0.16, 0.11, 0.19, 0.26, 0, 0, 0.11, 0], + "Offset":1140, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-CHARGE", + "Type":"UNKNOWN", + "Version":"4.0", + "VirtualSensor":true, + "TriggerSensor":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "quiet_therm", "usb_pwr_therm"], + "Formula":"MAXIMUM", + "Combination":["VIRTUAL-SKIN-CHARGE-SUB-0", "VIRTUAL-SKIN-CHARGE-SUB-1", "VIRTUAL-SKIN-CHARGE-SUB-2", "VIRTUAL-SKIN-CHARGE-SUB-3"], + "Coefficient":[1.0, 1.0, 1.0, 1.0], + "HotThreshold":["NAN", 44.0, 48.0, 51.0, 55.0, 57.0, 75.0], + "HotHysteresis":[0.0, 1.9, 3.9, 2.9, 3.9, 1.9, 1.9], + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000, + "PIDInfo": { + "K_Po":["NAN", "NAN", 119, "NAN", "NAN", "NAN", "NAN"], + "K_Pu":["NAN", "NAN", 119, "NAN", "NAN", "NAN", "NAN"], + "K_I":["NAN", "NAN", 25, "NAN", "NAN", "NAN", "NAN"], + "K_D":["NAN", "NAN", 0, "NAN", "NAN", "NAN", "NAN"], + "I_Max":["NAN", "NAN", 1302, "NAN", "NAN", "NAN", "NAN"], + "S_Power":["NAN", "NAN", 2527, "NAN", "NAN", "NAN", "NAN"], + "MinAllocPower":["NAN", "NAN", 0, "NAN", "NAN", "NAN", "NAN"], + "MaxAllocPower":["NAN", "NAN", 6219, "NAN", "NAN", "NAN", "NAN"], + "I_Cutoff":["NAN", "NAN", 6, "NAN", "NAN", "NAN", "NAN"], + "I_Default":1302 + }, + "ExcludedPowerInfo": [ + { + "PowerRail": "PARTIAL_SYSTEM_POWER", + "PowerWeight": [0.12, 0.12, 0.06, 0.06, 0.24, 0.24, 0.24] + } + ], + "BindedCdevInfo": [ + { + "CdevRequest": "chg_mdis", + "CdevWeightForPID": [1, 1, 1, 1, 1, 1, 1], + "MaxReleaseStep": 1, + "MaxThrottleStep": 1, + "CdevCeiling": [0, 25, 25, 25, 26, 26, 26], + "LimitInfo": [0, 0, 1, 1, 1, 26, 26] + } + ] + } + ], + "CoolingDevices":[ + { + "Name":"chg_mdis", + "Type":"BATTERY" + }, + { + "Name":"usbc-port", + "Type":"BATTERY" + } + ], + "PowerRails":[ + { + "Name":"PARTIAL_SYSTEM_POWER", + "VirtualRails":true, + "Formula":"WEIGHTED_AVG", + "Combination":["S1S_VDD_CAM", "S4S_VDD2H_MEM", "S5S_VDDQ_MEM", "S8S_VDD_G3D_L2", "S9S_VDD_AOC", "L2S_PLL_MIPI_UFS", "L9S_GNSS_CORE", "L21S_VDD2L_MEM", "VSYS_PWR_DISPLAY", "VSYS_PWR_WLAN_BT", "S1M_VDD_MIF", "S5M_VDD_INT", "S6M_LLDO1", "S7M_VDD_TPU", "S8M_LLDO2", "VSYS_PWR_MODEM"], + "Coefficient":[1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0], + "PowerSampleDelay":7000, + "PowerSampleCount":5 + } + ] +} diff --git a/thermal/thermal_info_config_charge_tokay.json b/thermal/thermal_info_config_charge_tokay.json new file mode 100644 index 0000000..642c942 --- /dev/null +++ b/thermal/thermal_info_config_charge_tokay.json @@ -0,0 +1,197 @@ +{ + "Sensors":[ + { + "Name":"north_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 42.1, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "TempPath":"/dev/thermal/tz-by-name/north_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"rfpa_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 43.7, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "TempPath":"/dev/thermal/tz-by-name/rfpa_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"soc_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 57.2, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "TempPath":"/dev/thermal/tz-by-name/soc_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"charging_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 58.4, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "TempPath":"/dev/thermal/tz-by-name/charging_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"disp_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 41.7, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "TempPath":"/dev/thermal/tz-by-name/disp_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"battery", + "Type":"BATTERY", + "HotThreshold":["NAN", "NAN", "NAN", "NAN", "NAN", "NAN", 60.0], + "Multiplier":0.001 + }, + { + "Name":"btmspkr_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 54.1, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "TempPath":"/dev/thermal/tz-by-name/btmspkr_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"quiet_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 44.6, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "TempPath":"/dev/thermal/tz-by-name/quiet_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"usb_pwr_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 45.0, "NAN", "NAN", "NAN", "NAN", "NAN"], + "TempPath":"/dev/thermal/tz-by-name/usb_pwr_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"VIRTUAL-SKIN-CHARGE-SUB-0", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0.04, 0.16, 0.19, 0.16, 0.17, 0, 0.01, 0.24, 0], + "Offset":-820, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-CHARGE-SUB-1", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0.02, 0.01, 0.04, 0.04, 0.4, 0.14, 0.1, 0.02, 0.12], + "Offset":1840, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-CHARGE-SUB-2", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0.18, 0.1, 0.15, 0.13, 0.22, 0.16, 0.02, 0.04, 0.01], + "Offset":-2810, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-CHARGE-SUB-3", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0.1, 0.16, 0.11, 0.19, 0.26, 0, 0, 0.11, 0], + "Offset":1140, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-CHARGE", + "Type":"UNKNOWN", + "Version":"4.0", + "VirtualSensor":true, + "TriggerSensor":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "quiet_therm", "usb_pwr_therm"], + "Formula":"MAXIMUM", + "Combination":["VIRTUAL-SKIN-CHARGE-SUB-0", "VIRTUAL-SKIN-CHARGE-SUB-1", "VIRTUAL-SKIN-CHARGE-SUB-2", "VIRTUAL-SKIN-CHARGE-SUB-3"], + "Coefficient":[1.0, 1.0, 1.0, 1.0], + "HotThreshold":["NAN", 44.0, 48.0, 51.0, 55.0, 57.0, 75.0], + "HotHysteresis":[0.0, 1.9, 3.9, 2.9, 3.9, 1.9, 1.9], + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000, + "PIDInfo": { + "K_Po":["NAN", "NAN", 119, "NAN", "NAN", "NAN", "NAN"], + "K_Pu":["NAN", "NAN", 119, "NAN", "NAN", "NAN", "NAN"], + "K_I":["NAN", "NAN", 25, "NAN", "NAN", "NAN", "NAN"], + "K_D":["NAN", "NAN", 0, "NAN", "NAN", "NAN", "NAN"], + "I_Max":["NAN", "NAN", 1302, "NAN", "NAN", "NAN", "NAN"], + "S_Power":["NAN", "NAN", 2527, "NAN", "NAN", "NAN", "NAN"], + "MinAllocPower":["NAN", "NAN", 0, "NAN", "NAN", "NAN", "NAN"], + "MaxAllocPower":["NAN", "NAN", 6219, "NAN", "NAN", "NAN", "NAN"], + "I_Cutoff":["NAN", "NAN", 6, "NAN", "NAN", "NAN", "NAN"], + "I_Default":1302 + }, + "ExcludedPowerInfo": [ + { + "PowerRail": "PARTIAL_SYSTEM_POWER", + "PowerWeight": [0.12, 0.12, 0.06, 0.06, 0.24, 0.24, 0.24] + } + ], + "BindedCdevInfo": [ + { + "CdevRequest": "chg_mdis", + "CdevWeightForPID": [1, 1, 1, 1, 1, 1, 1], + "MaxReleaseStep": 1, + "MaxThrottleStep": 1, + "CdevCeiling": [0, 25, 25, 25, 26, 26, 26], + "LimitInfo": [0, 0, 1, 1, 1, 26, 26] + } + ] + } + ], + "CoolingDevices":[ + { + "Name":"chg_mdis", + "Type":"BATTERY" + }, + { + "Name":"usbc-port", + "Type":"BATTERY" + } + ], + "PowerRails":[ + { + "Name":"PARTIAL_SYSTEM_POWER", + "VirtualRails":true, + "Formula":"WEIGHTED_AVG", + "Combination":["S1S_VDD_CAM", "S4S_VDD2H_MEM", "S5S_VDDQ_MEM", "S8S_VDD_G3D_L2", "S9S_VDD_AOC", "L2S_PLL_MIPI_UFS", "L9S_GNSS_CORE", "L21S_VDD2L_MEM", "VSYS_PWR_DISPLAY", "VSYS_PWR_WLAN_BT", "S1M_VDD_MIF", "S5M_VDD_INT", "S6M_LLDO1", "S7M_VDD_TPU", "S8M_LLDO2", "VSYS_PWR_MODEM"], + "Coefficient":[1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0], + "PowerSampleDelay":7000, + "PowerSampleCount":5 + } + ] +} diff --git a/thermal/thermal_info_config_komodo.json b/thermal/thermal_info_config_komodo.json new file mode 100644 index 0000000..0b06f84 --- /dev/null +++ b/thermal/thermal_info_config_komodo.json @@ -0,0 +1,926 @@ +{ + "Sensors":[ + { + "Name":"north_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 42.1, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "TempPath":"/dev/thermal/tz-by-name/north_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"rfpa_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 43.7, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "TempPath":"/dev/thermal/tz-by-name/rfpa_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"soc_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 57.2, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "TempPath":"/dev/thermal/tz-by-name/soc_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"charging_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 58.4, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "TempPath":"/dev/thermal/tz-by-name/charging_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"disp_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 41.7, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "TempPath":"/dev/thermal/tz-by-name/disp_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"battery", + "Type":"BATTERY", + "HotThreshold":["NAN", "NAN", "NAN", "NAN", "NAN", "NAN", 60.0], + "Multiplier":0.001 + }, + { + "Name":"btmspkr_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 54.1, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "TempPath":"/dev/thermal/tz-by-name/btmspkr_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"quiet_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 44.6, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "TempPath":"/dev/thermal/tz-by-name/quiet_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"usb_pwr_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 45.0, "NAN", "NAN", "NAN", "NAN", "NAN"], + "TempPath":"/dev/thermal/tz-by-name/usb_pwr_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"battery_cycle", + "Type":"BCL_VOLTAGE" + }, + { + "Name":"critical-battery-cell", + "Type":"BCL_VOLTAGE", + "VirtualSensor":true, + "Formula":"COUNT_THRESHOLD", + "TriggerSensor": "vdroop1", + "Combination":["battery", "battery_cycle", "vdroop1"], + "Coefficient":[-10000, 400, 1000], + "HotThreshold":["NAN", "NAN", "NAN", "NAN", "NAN", 3.00, "NAN"], + "Multiplier":1, + "PollingDelay":0, + "PassiveDelay":1000, + "SendCallback":true + }, + { + "Name":"FLASH_LED_REDUCE", + "Type":"UNKNOWN", + "VirtualSensor":true, + "Formula":"COUNT_THRESHOLD", + "TriggerSensor": "vdroop1", + "Combination":["battery", "battery_cycle", "vdroop1"], + "Coefficient":[-10000, 400, 1000], + "HotThreshold":["NAN", "NAN", "NAN", "NAN", 3.00, "NAN", "NAN"], + "Multiplier":1, + "PollingDelay":0, + "PassiveDelay":1000, + "SendCallback":true, + "SendPowerHint":true + }, + { + "Name":"soc", + "Type":"BCL_PERCENTAGE", + "HotThreshold":["NAN", "NAN", 80, "NAN", "NAN", "NAN", "NAN"], + "Multiplier":1 + }, + { + "Name":"batoilo", + "Type":"BCL_CURRENT", + "HotThreshold":["NAN", "NAN", "NAN", "NAN", 5000, "NAN", "NAN"], + "HotHysteresis":[0.0, 0.0, 0.0, 0.0, 100, 0.0, 0.0], + "Multiplier":1, + "SendCallback":true, + "PollingDelay":0, + "PassiveDelay":1000 + }, + { + "Name":"BCL_AUDIO_BAACL", + "Type":"BCL_VOLTAGE", + "VirtualSensor":true, + "Formula":"COUNT_THRESHOLD", + "TriggerSensor": "soc", + "Combination":["battery", "soc"], + "Coefficient":[-25000, 80], + "HotThreshold":["NAN", "NAN", "NAN", "NAN", 2.0, "NAN", "NAN"], + "PollingDelay":0, + "PassiveDelay":1000, + "Multiplier":1, + "SendCallback":true + }, + { + "Name":"vdroop1", + "Type":"BCL_VOLTAGE", + "HotThreshold":["NAN", "NAN", "NAN", "NAN", 1000, "NAN", "NAN"], + "HotHysteresis":[0.0, 0.0, 0.0, 0.0, 100, 0.0, 0.0], + "Multiplier":1, + "SendCallback":true, + "PollingDelay":0, + "PassiveDelay":1000 + }, + { + "Name":"vdroop2", + "Type":"BCL_VOLTAGE", + "HotThreshold":["NAN", "NAN", "NAN", "NAN", 1200, "NAN", "NAN"], + "HotHysteresis":[0.0, 0.0, 0.0, 0.0, 100, 0.0, 0.0], + "Multiplier":1, + "SendCallback":true, + "PollingDelay":0, + "PassiveDelay":1000 + }, + { + "Name":"smpl_gm", + "Type":"BCL_VOLTAGE", + "HotThreshold":["NAN", "NAN", "NAN", "NAN", 1100, "NAN", "NAN"], + "HotHysteresis":[0.0, 0.0, 0.0, 0.0, 100, 0.0, 0.0], + "Multiplier":1, + "SendCallback":true, + "PollingDelay":0, + "PassiveDelay":1000 + }, + { + "Name":"VIRTUAL-BTS-WINDOW-PARTIAL", + "Type":"UNKNOWN", + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["rfpa_therm", "north_therm"], + "Coefficient":[0.05, 0.14], + "Offset":560, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-SUB-0", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0, 0.27, 0.17, 0.11, 0, 0.2, 0.01, 0.06, 0.08], + "Offset":2110, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-SUB-1", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0.46, 0, 0.14, 0.28, 0, 0.06, 0.02, 0.14, 0], + "Offset":-7280, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-SUB-2", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0.07, 0, 0, 0, 0, 0.28, 0.15, 0.02, 0.3], + "Offset":4010, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-SUB-3", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0.27, 0.06, 0.3, 0, 0, 0.2, 0.03, 0.02, 0.04], + "Offset":10, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-SUB-4", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0.9, 0, 0.05, 0, 0, 0, 0.01, 0, 0], + "Offset":730, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-SUB-5", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0.08, 0.02, 0.24, 0.23, 0, 0.29, 0.01, 0, 0], + "Offset":1870, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-SUB-6", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0, 0, 0, 0.04, 0.2, 0.07, 0.15, 0.3, 0.16], + "Offset":-440, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-SUB-7", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0, 0.01, 0, 0, 0.07, 0.28, 0.25, 0.02, 0.08], + "Offset":9170, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-SUB-8", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0.1, 0.16, 0.11, 0.19, 0.26, 0, 0, 0.11, 0], + "Offset":1140, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-SUB-9", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0.02, 0.05, 0.21, 0.13, 0.02, 0.29, 0.09, 0, 0], + "Offset":5160, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-SUB-10", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0, 0, 0.16, 0, 0.49, 0.35, 0, 0, 0], + "Offset":-1500, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN", + "Type":"SKIN", + "Version":"5.0", + "VirtualSensor":true, + "TriggerSensor":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "quiet_therm", "usb_pwr_therm"], + "Formula":"MAXIMUM", + "Combination":["VIRTUAL-SKIN-SUB-0", "VIRTUAL-SKIN-SUB-1", "VIRTUAL-SKIN-SUB-2", + "VIRTUAL-SKIN-SUB-3", "VIRTUAL-SKIN-SUB-4", "VIRTUAL-SKIN-SUB-5", + "VIRTUAL-SKIN-SUB-6", "VIRTUAL-SKIN-SUB-7", "VIRTUAL-SKIN-SUB-8", "VIRTUAL-SKIN-SUB-9", "VIRTUAL-SKIN-SUB-10"], + "Coefficient":[1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0], + "HotThreshold":["NAN", 49.0, 53.0, 55.0, 56.5, 62.0, 75.0], + "HotHysteresis":[0.0, 1.9, 1.9, 1.9, 1.4, 1.9, 1.9], + "Multiplier":0.001, + "SendCallback":true, + "PollingDelay":300000, + "PassiveDelay":7000, + "BindedCdevInfo": [ + { + "CdevRequest": "tpu_cooling", + "LimitInfo": [0, 2, 3, 4, 5, 5, 5] + }, + { + "CdevRequest": "gxp-cooling", + "LimitInfo": [0, 0, 0, 0, 0, 6, 6] + } + ] + }, + { + "Name":"VIRTUAL-SKIN-HINT", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "TriggerSensor":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "quiet_therm", "usb_pwr_therm"], + "Formula":"MAXIMUM", + "Combination":["VIRTUAL-SKIN"], + "Coefficient":[1.0], + "HotThreshold":["NAN", 47.0, 53.0, 55.0, 56.5, 62.0, 75.0], + "HotHysteresis":[0.0, 1.9, 1.9, 1.9, 1.4, 1.9, 1.9], + "Multiplier":0.001, + "SendPowerHint":true, + "PollingDelay":300000, + "PassiveDelay":7000 + }, + { + "Name":"VIRTUAL-SKIN-CPU-LIGHT-ODPM", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "TriggerSensor":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "quiet_therm", "usb_pwr_therm"], + "Formula":"MAXIMUM", + "Combination":["VIRTUAL-SKIN"], + "Coefficient":[1.0], + "HotThreshold":["NAN", 47.0, 49.0, "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 1.9, 1.9, 0.0, 0.0, 0.0, 0.0], + "Multiplier":0.001, + "PollingDelay":300000, + "PassiveDelay":7000, + "PIDInfo": { + "K_Po":["NAN", "NAN", 400, "NAN", "NAN", "NAN", "NAN"], + "K_Pu":["NAN", "NAN", 400, "NAN", "NAN", "NAN", "NAN"], + "K_I":["NAN", "NAN", 5, "NAN", "NAN", "NAN", "NAN"], + "K_D":["NAN", "NAN", 0, "NAN", "NAN", "NAN", "NAN"], + "I_Max":["NAN", "NAN", 2200, "NAN", "NAN", "NAN", "NAN"], + "S_Power":["NAN", "NAN", 800, "NAN", "NAN", "NAN", "NAN"], + "MinAllocPower":["NAN", "NAN", 800, "NAN", "NAN", "NAN", "NAN"], + "MaxAllocPower":["NAN", "NAN", 4600, "NAN", "NAN", "NAN", "NAN"], + "I_Cutoff":["NAN", "NAN", 4, "NAN", "NAN", "NAN", "NAN"] + }, + "BindedCdevInfo": [ + { + "CdevRequest": "thermal-cpufreq-0", + "CdevWeightForPID": [1, 1, 1, 1, 1, 1, 1], + "MaxReleaseStep": 1, + "MaxThrottleStep": 1, + "BindedPowerRail": "S4M_VDD_CPUCL0", + "CdevCeiling": [0, 2, 2, 2, 2, 2, 2] + }, + { + "CdevRequest": "thermal-cpufreq-1", + "CdevWeightForPID": [1, 1, 1, 1, 1, 1, 1], + "MaxReleaseStep": 1, + "MaxThrottleStep": 2, + "BindedPowerRail": "S3M_VDD_CPUCL1", + "CdevCeiling": [0, 6, 6, 6, 6, 6, 6] + }, + { + "CdevRequest": "thermal-cpufreq-2", + "CdevWeightForPID": [1, 1, 1, 1, 1, 1, 1], + "MaxReleaseStep": 1, + "MaxThrottleStep": 2, + "BindedPowerRail": "S2M_VDD_CPUCL2", + "CdevCeiling": [0, 8, 8, 8, 8, 8, 8] + } + ] + }, + { + "Name":"VIRTUAL-SKIN-CPU-MID", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "TriggerSensor":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "quiet_therm", "usb_pwr_therm"], + "Formula":"MAXIMUM", + "Combination":["VIRTUAL-SKIN"], + "Coefficient":[1.0], + "HotThreshold":["NAN", 49.0, 51.0, "NAN", "NAN", "NAN", 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"thermal-cpufreq-2", + "MaxReleaseStep": 1, + "Disabled":true + } + ] + } + ] + }, + { + "Name":"VIRTUAL-SKIN-CPU-GPU", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "TriggerSensor":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "quiet_therm", "usb_pwr_therm"], + "Formula":"MAXIMUM", + "Combination":["VIRTUAL-SKIN"], + "Coefficient":[1.0], + "HotThreshold":["NAN", 47.0, 53.0, 55.0, 56.5, 62.0, 75.0], + "HotHysteresis":[0.0, 1.9, 1.9, 1.9, 1.4, 1.9, 1.9], + "Multiplier":0.001, + "PollingDelay":300000, + "PassiveDelay":7000, + "PIDInfo": { + "K_Po":["NAN", "NAN", "NAN", 300, "NAN", "NAN", "NAN"], + "K_Pu":["NAN", "NAN", "NAN", 300, "NAN", "NAN", "NAN"], + "K_I":["NAN", "NAN", "NAN", 5, "NAN", "NAN", "NAN"], + "K_D":["NAN", "NAN", "NAN", 0, "NAN", "NAN", "NAN"], + "I_Max":["NAN", "NAN", "NAN", 2600, "NAN", "NAN", "NAN"], + "S_Power":["NAN", "NAN", "NAN", 800, "NAN", "NAN", "NAN"], + "MinAllocPower":["NAN", "NAN", "NAN", 0, "NAN", "NAN", "NAN"], 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[1, 1, 1, 1, 1, 1, 1], + "MaxReleaseStep": 1, + "MaxThrottleStep": 1, + "BindedPowerRail": "S2S_VDD_G3D", + "CdevCeiling": [0, 8, 8, 8, 9, 11, 11], + "LimitInfo": [0, 0, 0, 0, 0, 11, 11] + } + ] + }, + { + "Name":"VIRTUAL-SKIN-GPU", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "TriggerSensor":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "quiet_therm", "usb_pwr_therm"], + "Formula":"MAXIMUM", + "Combination":["VIRTUAL-SKIN"], + "Coefficient":[1.0], + "HotThreshold":["NAN", 53.0, 55.0, 56.5, 62.0, "NAN", "NAN"], + "HotHysteresis":[0.0, 1.9, 1.9, 1.4, 1.9, 0.0, 0.0], + "Multiplier":0.001, + "PollingDelay":300000, + "PassiveDelay":7000, + "PIDInfo": { + "K_Po":["NAN", "NAN", 700, "NAN", "NAN", "NAN", "NAN"], + "K_Pu":["NAN", "NAN", 700, "NAN", "NAN", "NAN", "NAN"], + "K_I":["NAN", "NAN", 5, "NAN", "NAN", "NAN", "NAN"], + "K_D":["NAN", "NAN", 0, "NAN", "NAN", "NAN", "NAN"], + "I_Max":["NAN", "NAN", 1723, "NAN", "NAN", "NAN", "NAN"], + "S_Power":["NAN", "NAN", 473, "NAN", "NAN", "NAN", "NAN"], + "MinAllocPower":["NAN", "NAN", 0, "NAN", "NAN", "NAN", "NAN"], + "MaxAllocPower":["NAN", "NAN", 2500, "NAN", "NAN", "NAN", "NAN"], + "I_Cutoff":["NAN", "NAN", 4, "NAN", "NAN", "NAN", "NAN"] + }, + "BindedCdevInfo": [ + { + "CdevRequest": "thermal-gpufreq-0", + "CdevWeightForPID": [1, 1, 1, 1, 1, 1, 1], + "CdevCeiling": [0, 8, 8, 9, 11, 11, 11] + } + ] + }, + { + "Name":"cellular-emergency", + "Type":"POWER_AMPLIFIER", + "VirtualSensor":true, + "TriggerSensor":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "quiet_therm", "usb_pwr_therm"], + "Formula":"MAXIMUM", + "Combination":["VIRTUAL-SKIN"], + "Coefficient":[1.0], + "HotThreshold":["NAN", "NAN", "NAN", "NAN", "NAN", 64.0, "NAN"], + "HotHysteresis":[0.0, 0.0, 0.0, 0.0, 0.0, 1.9, 0.0], + "Multiplier":0.001, + "SendCallback":true, + "PollingDelay":300000, + "PassiveDelay":7000 + }, + { + "Name":"VIRTUAL-SKIN-SPEAKER-SUB-0", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0, 0.14, 0, 0.15, 0, 0, 0, 0.88, 0], + "Offset":-11750, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-SPEAKER-SUB-1", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0.01, 0.18, 0, 0, 0, 0.24, 0, 0.01, 0.35], + "Offset":3600, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-SPEAKER-SUB-2", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0, 0.01, 0, 0, 0.13, 0.31, 0.11, 0.18, 0.09], + "Offset":2140, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-SPEAKER", + "Type":"UNKNOWN", + "Version":"2.0", + "VirtualSensor":true, + "TriggerSensor":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "quiet_therm", "usb_pwr_therm"], + "Formula":"MAXIMUM", + "Combination":["VIRTUAL-SKIN-SPEAKER-SUB-0", "VIRTUAL-SKIN-SPEAKER-SUB-1", "VIRTUAL-SKIN-SPEAKER-SUB-2"], + "Coefficient":[1, 1, 1], + "HotThreshold":["NAN", 47.0, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 1.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "Multiplier":0.001, + "SendCallback":true + }, + { + "Name":"VIRTUAL-SKIN-FRONT-SUB-0", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0.04, 0.03, 0.1, 0.05, 0.35, 0.3, 0, 0, 0.04], + "Offset":1850, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-FRONT-SUB-1", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0, 0, 0.35, 0.22, 0.22, 0.07, 0.03, 0, 0], + "Offset":-560, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-FRONT-SUB-2", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0.05, 0.13, 0.12, 0.07, 0.37, 0.06, 0.01, 0.01, 0], + "Offset":5070, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-FRONT", + "Type":"UNKNOWN", + "Version":"1.0", + "VirtualSensor":true, + "TriggerSensor":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "quiet_therm", "usb_pwr_therm"], + "Formula":"MAXIMUM", + "Combination":["VIRTUAL-SKIN-FRONT-SUB-0", "VIRTUAL-SKIN-FRONT-SUB-1", "VIRTUAL-SKIN-FRONT-SUB-2"], + "Coefficient":[1, 1, 1], + "Multiplier":0.001 + }, + { + "Name":"LITTLE", + "Type":"CPU", + "Multiplier":0.001 + }, + { + "Name":"MID", + "Type":"CPU", + "Multiplier":0.001 + }, + { + "Name":"BIG", + "Type":"CPU", + "Multiplier":0.001 + }, + { + "Name":"G3D", + "Type":"GPU", + "Multiplier":0.001 + }, + { + "Name":"TPU", + "Type":"NPU", + "Multiplier":0.001 + } + ], + "CoolingDevices":[ + { + "Name":"thermal-cpufreq-0", + "Type":"CPU", + "WritePath":"/dev/thermal/cdev-by-name/thermal-cpufreq-0/user_vote" + }, + { + "Name":"thermal-cpufreq-1", + "Type":"CPU", + "WritePath":"/dev/thermal/cdev-by-name/thermal-cpufreq-1/user_vote" + }, + { + "Name":"thermal-cpufreq-2", + "Type":"CPU", + "WritePath":"/dev/thermal/cdev-by-name/thermal-cpufreq-2/user_vote" + }, + { + "Name":"thermal-gpufreq-0", + "Type":"GPU", + "WritePath":"/dev/thermal/cdev-by-name/thermal-gpufreq-0/user_vote" + }, + { + "Name":"chg_mdis", + "Type":"BATTERY" + }, + { + "Name":"usbc-port", + "Type":"BATTERY" + }, + { + "Name":"tpu_cooling", + "Type":"NPU", + "WritePath":"/dev/thermal/cdev-by-name/tpu_cooling/user_vote" + }, + { + "Name":"gxp-cooling", + "Type":"NPU", + "WritePath":"/dev/thermal/cdev-by-name/gxp-cooling/user_vote" + } + ], + "PowerRails":[ + { + "Name":"S2M_VDD_CPUCL2", + "PowerSampleDelay":7000, + "PowerSampleCount":1 + }, + { + "Name":"S3M_VDD_CPUCL1", + "PowerSampleDelay":7000, + "PowerSampleCount":1 + }, + { + "Name":"S4M_VDD_CPUCL0", + "PowerSampleDelay":7000, + "PowerSampleCount":1 + }, + { + "Name":"S2S_VDD_G3D", + "PowerSampleDelay":7000, + "PowerSampleCount":1 + }, + { + "Name":"PARTIAL_SYSTEM_POWER", + "VirtualRails":true, + "Formula":"WEIGHTED_AVG", + "Combination":["S1S_VDD_CAM", "S2S_VDD_G3D", "S4S_VDD2H_MEM", "S5S_VDDQ_MEM", "S8S_VDD_G3D_L2", "S9S_VDD_AOC", "L2S_PLL_MIPI_UFS", "L9S_GNSS_CORE", "L21S_VDD2L_MEM", "VSYS_PWR_DISPLAY", "VSYS_PWR_WLAN_BT", "S1M_VDD_MIF", "S2M_VDD_CPUCL2", "S3M_VDD_CPUCL1", "S4M_VDD_CPUCL0", "S5M_VDD_INT", "S6M_LLDO1", "S7M_VDD_TPU", "S8M_LLDO2", "VSYS_PWR_MODEM"], + "Coefficient":[1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0], + "PowerSampleDelay":7000, + "PowerSampleCount":5 + } + ], + "Stats": { + "Sensors": { + "RecordWithDefaultThreshold": ["VIRTUAL-SKIN"], + "RecordWithThreshold": [ + { + "Name": "VIRTUAL-BTS-WINDOW-PARTIAL", + "Thresholds": [41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 75] + }, + { + "Name": "VIRTUAL-SKIN-SPEAKER", + "Thresholds": [41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 75] + }, + { + "Name": "VIRTUAL-SKIN", + "Thresholds": [41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 75] + }, + { + "Name": "VIRTUAL-SKIN-SUB-0", + "Thresholds": [41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 75] + }, + { + "Name": "VIRTUAL-SKIN-SUB-1", + "Thresholds": [41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 75] + }, + { + "Name": "VIRTUAL-SKIN-SUB-2", + "Thresholds": [41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 75] + }, + { + "Name": "VIRTUAL-SKIN-SUB-3", + "Thresholds": [41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 75] + }, + { + "Name": "VIRTUAL-SKIN-SUB-4", + "Thresholds": [41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 75] + }, + { + "Name": "VIRTUAL-SKIN-SUB-5", + "Thresholds": [41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 75] + }, + { + "Name": "VIRTUAL-SKIN-SUB-6", + "Thresholds": [41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 75] + }, + { + "Name": "VIRTUAL-SKIN-SUB-7", + "Thresholds": [41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 75] + } + ] + }, + "CoolingDevices": { + "RecordVotePerSensor": { + "DefaultThresholdEnableAll": true + } + } + } +} diff --git a/thermal/thermal_info_config_ripcurrent24.json b/thermal/thermal_info_config_ripcurrent24.json new file mode 100644 index 0000000..72fb124 --- /dev/null +++ b/thermal/thermal_info_config_ripcurrent24.json @@ -0,0 +1,561 @@ +{ + "Sensors":[ + { + "Name":"battery", + "Type":"BATTERY", + "HotThreshold":[ + "NAN", + "NAN", + "NAN", + "NAN", + "NAN", + "NAN", + "60.0" + ], + "VrThreshold":"NAN", + "Multiplier":0.001 + }, + { + "Name":"LITTLE", + "Type":"CPU", + "HotThreshold":[ + "NAN", + "NAN", + "NAN", + "NAN", + "NAN", + "NAN", + 115.0 + ], + "VrThreshold":"NAN", + "Multiplier":0.001 + }, + { + "Name":"MID", + "Type":"CPU", + "HotThreshold":[ + "NAN", + "NAN", + "NAN", + "NAN", + "NAN", + "NAN", + 115.0 + ], + "VrThreshold":"NAN", + "Multiplier":0.001 + }, + { + "Name":"G3D", + "Type":"GPU", + "HotThreshold":[ + "NAN", + "NAN", + "NAN", + "NAN", + "NAN", + "NAN", + 115.0 + ], + "VrThreshold":"NAN", + "Multiplier":0.001 + }, + { + "Name":"battery_cycle", + "Type":"BCL_VOLTAGE", + "HotThreshold":[ + "NAN", + "NAN", + "NAN", + "NAN", + "NAN", + "NAN", + "NAN" + ], + "VrThreshold":"NAN", + "Multiplier":1, + "Monitor":false + }, + { + "Name":"critical-battery-cell", + "Type":"BCL_VOLTAGE", + "VirtualSensor":true, + "Formula":"COUNT_THRESHOLD", + "TriggerSensor": "vdroop1", + "Combination":[ + "battery", + "battery_cycle", + "vdroop1" + ], + "Coefficient":[ + "-10000", + "400", + "1000" + ], + "HotThreshold":[ + "NAN", + "NAN", + "NAN", + "NAN", + "NAN", + 3.00, + "NAN" + ], + "VrThreshold":"NAN", + "Multiplier":1, + "Monitor":true + }, + { + "Name":"FLASH_LED_REDUCE", + "Type":"UNKNOWN", + "VirtualSensor":true, + "Formula":"COUNT_THRESHOLD", + "TriggerSensor": "vdroop1", + "Combination":[ + "battery", + "battery_cycle", + "vdroop1" + ], + "Coefficient":[ + "-10000", + "400", + "1000" + ], + "HotThreshold":[ + "NAN", + "NAN", + "NAN", + "NAN", + 3.00, + "NAN", + "NAN" + ], + "VrThreshold":"NAN", + "Multiplier":1, + "Monitor":true, + "SendPowerHint":true + }, + { + "Name":"soc", + "Type":"BCL_PERCENTAGE", + "HotThreshold":[ + "NAN", + 80, + "NAN", + "NAN", + "NAN", + "NAN", + "NAN" + ], + "VrThreshold":"NAN", + "Multiplier":1 + }, + { + "Name":"batoilo", + "Type":"BCL_CURRENT", + "HotThreshold":[ + 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"HotHysteresis":[ + 0.0, + 0.0, + 0.0, + 0.0, + 100, + 0.0, + 0.0 + ], + "VrThreshold":"NAN", + "Multiplier":1 + }, + { + "Name":"soft_ocp_gpu", + "Type":"BCL_CURRENT", + "HotThreshold":[ + "NAN", + "NAN", + "NAN", + "NAN", + 9000, + "NAN", + "NAN" + ], + "HotHysteresis":[ + 0.0, + 0.0, + 0.0, + 0.0, + 100, + 0.0, + 0.0 + ], + "VrThreshold":"NAN", + "Multiplier":1 + }, + { + "Name":"TPU", + "Type":"NPU", + "HotThreshold":[ + "NAN", + "NAN", + "NAN", + "NAN", + "NAN", + "NAN", + 115.0 + ], + "VrThreshold":"NAN", + "Multiplier":0.001 + } + ], + "CoolingDevices":[ + { + "Name":"thermal-cpufreq-0", + "Type":"CPU", + "WritePath":"/dev/thermal/cdev-by-name/thermal-cpufreq-0/user_vote", + "State2Power":["1100", "1050", "1000", "950", "900", "850", "800", "750", "700", "650", "600"] + }, + { + "Name":"thermal-cpufreq-1", + "Type":"CPU", + "WritePath":"/dev/thermal/cdev-by-name/thermal-cpufreq-1/user_vote", + "State2Power":["1400", "1350", "1300", "1250", "1200", "1150", "1100", "1050", "1000", "950", "900", "850", "800", "750"] + }, + { + "Name":"thermal-cpufreq-2", + "Type":"CPU", + "WritePath":"/dev/thermal/cdev-by-name/thermal-cpufreq-2/user_vote", + "State2Power":["1450", "1400", "1350", "1300", "1250", "1200", "1150", "1100", "1050", "1000", "950", "900", "850", "800", "750"] + }, + { + "Name":"thermal-gpufreq-0", + "Type":"GPU", + "WritePath":"/dev/thermal/cdev-by-name/thermal-gpufreq-0/user_vote" + } + ] +} diff --git a/thermal/thermal_info_config_ripcurrentpro.json b/thermal/thermal_info_config_ripcurrentpro.json new file mode 100644 index 0000000..72fb124 --- /dev/null +++ b/thermal/thermal_info_config_ripcurrentpro.json @@ -0,0 +1,561 @@ +{ + "Sensors":[ + { + "Name":"battery", + "Type":"BATTERY", + "HotThreshold":[ + "NAN", + "NAN", + "NAN", + "NAN", + "NAN", + "NAN", + "60.0" + ], + "VrThreshold":"NAN", + "Multiplier":0.001 + }, + { + "Name":"LITTLE", + "Type":"CPU", + "HotThreshold":[ + "NAN", + "NAN", + "NAN", + "NAN", + "NAN", + "NAN", + 115.0 + ], + "VrThreshold":"NAN", + "Multiplier":0.001 + }, + { + "Name":"MID", + "Type":"CPU", + "HotThreshold":[ + "NAN", + "NAN", + "NAN", + "NAN", + "NAN", + "NAN", + 115.0 + ], + "VrThreshold":"NAN", + "Multiplier":0.001 + }, + { + "Name":"G3D", + "Type":"GPU", + "HotThreshold":[ + "NAN", + "NAN", + "NAN", + "NAN", + "NAN", + "NAN", + 115.0 + ], + "VrThreshold":"NAN", + "Multiplier":0.001 + }, + { + "Name":"battery_cycle", + "Type":"BCL_VOLTAGE", + "HotThreshold":[ + "NAN", + "NAN", + "NAN", + "NAN", + "NAN", + "NAN", + "NAN" + ], + "VrThreshold":"NAN", + "Multiplier":1, + "Monitor":false + }, + { + "Name":"critical-battery-cell", + "Type":"BCL_VOLTAGE", + "VirtualSensor":true, + "Formula":"COUNT_THRESHOLD", + "TriggerSensor": "vdroop1", + "Combination":[ + "battery", + "battery_cycle", + "vdroop1" + ], + "Coefficient":[ + "-10000", + "400", + "1000" + ], + "HotThreshold":[ + "NAN", + "NAN", + "NAN", + "NAN", + "NAN", + 3.00, + "NAN" + ], + "VrThreshold":"NAN", + "Multiplier":1, + "Monitor":true + }, + { + "Name":"FLASH_LED_REDUCE", + "Type":"UNKNOWN", + "VirtualSensor":true, + "Formula":"COUNT_THRESHOLD", + "TriggerSensor": "vdroop1", + "Combination":[ + "battery", + "battery_cycle", + "vdroop1" + ], + "Coefficient":[ + "-10000", + "400", + "1000" + ], + "HotThreshold":[ + "NAN", + "NAN", + "NAN", + "NAN", + 3.00, + "NAN", + "NAN" + ], + "VrThreshold":"NAN", + "Multiplier":1, + "Monitor":true, + "SendPowerHint":true + }, + { + "Name":"soc", + "Type":"BCL_PERCENTAGE", + "HotThreshold":[ + "NAN", + 80, + "NAN", + "NAN", + "NAN", + "NAN", + "NAN" + ], + "VrThreshold":"NAN", + "Multiplier":1 + }, + { + "Name":"batoilo", + "Type":"BCL_CURRENT", + "HotThreshold":[ + "NAN", + "NAN", + "NAN", + "NAN", + 5000, + "NAN", + "NAN" + ], + "HotHysteresis":[ + 0.0, + 0.0, + 0.0, + 0.0, + 100, + 0.0, + 0.0 + ], + "VrThreshold":"NAN", + "Multiplier":1, + "Monitor":true, + "PollingDelay":0, + "PassiveDelay":1000, + "BindedCdevInfo": [ + { + "CdevRequest": "thermal-cpufreq-2", + "LimitInfo": [0, 0, 0, 0, 7, 7, 7] + }, + { + "CdevRequest": "thermal-gpufreq-0", + "LimitInfo": [0, 0, 0, 0, 3, 3, 3] + } + ] + }, + { + "Name":"BCL_AUDIO_BAACL", + "Type":"BCL_VOLTAGE", + "VirtualSensor":true, + "Formula":"COUNT_THRESHOLD", + "TriggerSensor": "soc", + "Combination":[ + "battery", + "soc" + ], + "Coefficient":[ + "-25000", + "80" + ], + "HotThreshold":[ + "NAN", + "NAN", + "NAN", + "NAN", + 2.0, + "NAN", + "NAN" + ], + "VrThreshold":"NAN", + "Multiplier":1, + "Monitor":true + }, + { + "Name":"vdroop1", + "Type":"BCL_VOLTAGE", + "HotThreshold":[ + "NAN", + "NAN", + "NAN", + "NAN", + 1000, + "NAN", + "NAN" + ], + "HotHysteresis":[ + 0.0, + 0.0, + 0.0, + 0.0, + 100, + 0.0, + 0.0 + ], + "VrThreshold":"NAN", + "Multiplier":1, + "Monitor":true, + "PollingDelay":0, + "PassiveDelay":1000, + "BindedCdevInfo": [ + { + "CdevRequest": "thermal-cpufreq-2", + "LimitInfo": [0, 0, 0, 0, 7, 10, 10] + }, + { + "CdevRequest": "thermal-gpufreq-0", + "LimitInfo": [0, 0, 0, 0, 2, 2, 2] + } + ] + }, + { + "Name":"vdroop2", + "Type":"BCL_VOLTAGE", + "HotThreshold":[ + "NAN", + "NAN", + "NAN", + "NAN", + 1200, + "NAN", + "NAN" + ], + "HotHysteresis":[ + 0.0, + 0.0, + 0.0, + 0.0, + 100, + 0.0, + 0.0 + ], + "VrThreshold":"NAN", + "Multiplier":1, + "Monitor":true, + "PollingDelay":0, + "PassiveDelay":1000, + "BindedCdevInfo": [ + { + "CdevRequest": "thermal-cpufreq-2", + "LimitInfo": [0, 0, 0, 0, 7, 10, 10] + }, + { + "CdevRequest": "thermal-gpufreq-0", + "LimitInfo": [0, 0, 0, 0, 4, 4, 4] + } + ] + }, + { + "Name":"smpl_gm", + "Type":"BCL_VOLTAGE", + "HotThreshold":[ + "NAN", + "NAN", + "NAN", + "NAN", + 1100, + "NAN", + "NAN" + ], + "HotHysteresis":[ + 0.0, + 0.0, + 0.0, + 0.0, + 100, + 0.0, + 0.0 + ], + "VrThreshold":"NAN", + "Multiplier":1, + "Monitor":true, + "PollingDelay":0, + "PassiveDelay":1000, + "BindedCdevInfo": [ + { + "CdevRequest": "thermal-cpufreq-2", + "LimitInfo": [0, 0, 0, 0, 7, 10, 10] + }, + { + "CdevRequest": "thermal-gpufreq-0", + "LimitInfo": [0, 0, 0, 0, 3, 3, 3] + } + ] + }, + { + "Name":"ocp_cpu1", + "Type":"BCL_CURRENT", + "HotThreshold":[ + "NAN", + "NAN", + "NAN", + "NAN", + 7000, + "NAN", + "NAN" + ], + "HotHysteresis":[ + 0.0, + 0.0, + 0.0, + 0.0, + 100, + 0.0, + 0.0 + ], + "VrThreshold":"NAN", + "Multiplier":1 + }, + { + "Name":"ocp_cpu2", + "Type":"BCL_CURRENT", + "HotThreshold":[ + "NAN", + "NAN", + "NAN", + "NAN", + 12000, + "NAN", + "NAN" + ], + "HotHysteresis":[ + 0.0, + 0.0, + 0.0, + 0.0, + 100, + 0.0, + 0.0 + ], + "VrThreshold":"NAN", + "Multiplier":1 + }, + { + "Name":"ocp_tpu", + "Type":"BCL_CURRENT", + "HotThreshold":[ + "NAN", + "NAN", + "NAN", + "NAN", + 10500, + "NAN", + "NAN" + ], + "HotHysteresis":[ + 0.0, + 0.0, + 0.0, + 0.0, + 100, + 0.0, + 0.0 + ], + "VrThreshold":"NAN", + "Multiplier":1 + }, + { + "Name":"ocp_gpu", + "Type":"BCL_CURRENT", + "HotThreshold":[ + "NAN", + "NAN", + "NAN", + "NAN", + 12000, + "NAN", + "NAN" + ], + "HotHysteresis":[ + 0.0, + 0.0, + 0.0, + 0.0, + 100, + 0.0, + 0.0 + ], + "VrThreshold":"NAN", + "Multiplier":1 + }, + { + "Name":"soft_ocp_cpu2", + "Type":"BCL_CURRENT", + "HotThreshold":[ + "NAN", + "NAN", + "NAN", + "NAN", + 9000, + "NAN", + "NAN" + ], + "HotHysteresis":[ + 0.0, + 0.0, + 0.0, + 0.0, + 100, + 0.0, + 0.0 + ], + "VrThreshold":"NAN", + "Multiplier":1 + }, + { + "Name":"soft_ocp_cpu1", + "Type":"BCL_CURRENT", + "HotThreshold":[ + "NAN", + "NAN", + "NAN", + "NAN", + 7000, + "NAN", + "NAN" + ], + "HotHysteresis":[ + 0.0, + 0.0, + 0.0, + 0.0, + 100, + 0.0, + 0.0 + ], + "VrThreshold":"NAN", + "Multiplier":1 + }, + { + "Name":"soft_ocp_tpu", + "Type":"BCL_CURRENT", + "HotThreshold":[ + "NAN", + "NAN", + "NAN", + "NAN", + 8500, + "NAN", + "NAN" + ], + "HotHysteresis":[ + 0.0, + 0.0, + 0.0, + 0.0, + 100, + 0.0, + 0.0 + ], + "VrThreshold":"NAN", + "Multiplier":1 + }, + { + "Name":"soft_ocp_gpu", + "Type":"BCL_CURRENT", + "HotThreshold":[ + "NAN", + "NAN", + "NAN", + "NAN", + 9000, + "NAN", + "NAN" + ], + "HotHysteresis":[ + 0.0, + 0.0, + 0.0, + 0.0, + 100, + 0.0, + 0.0 + ], + "VrThreshold":"NAN", + "Multiplier":1 + }, + { + "Name":"TPU", + "Type":"NPU", + "HotThreshold":[ + "NAN", + "NAN", + "NAN", + "NAN", + "NAN", + "NAN", + 115.0 + ], + "VrThreshold":"NAN", + "Multiplier":0.001 + } + ], + "CoolingDevices":[ + { + "Name":"thermal-cpufreq-0", + "Type":"CPU", + "WritePath":"/dev/thermal/cdev-by-name/thermal-cpufreq-0/user_vote", + "State2Power":["1100", "1050", "1000", "950", "900", "850", "800", "750", "700", "650", "600"] + }, + { + "Name":"thermal-cpufreq-1", + "Type":"CPU", + "WritePath":"/dev/thermal/cdev-by-name/thermal-cpufreq-1/user_vote", + "State2Power":["1400", "1350", "1300", "1250", "1200", "1150", "1100", "1050", "1000", "950", "900", "850", "800", "750"] + }, + { + "Name":"thermal-cpufreq-2", + "Type":"CPU", + "WritePath":"/dev/thermal/cdev-by-name/thermal-cpufreq-2/user_vote", + "State2Power":["1450", "1400", "1350", "1300", "1250", "1200", "1150", "1100", "1050", "1000", "950", "900", "850", "800", "750"] + }, + { + "Name":"thermal-gpufreq-0", + "Type":"GPU", + "WritePath":"/dev/thermal/cdev-by-name/thermal-gpufreq-0/user_vote" + } + ] +} diff --git a/thermal/thermal_info_config_tegu.json b/thermal/thermal_info_config_tegu.json new file mode 100644 index 0000000..0b06f84 --- /dev/null +++ b/thermal/thermal_info_config_tegu.json @@ -0,0 +1,926 @@ +{ + "Sensors":[ + { + "Name":"north_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 42.1, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "TempPath":"/dev/thermal/tz-by-name/north_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"rfpa_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 43.7, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "TempPath":"/dev/thermal/tz-by-name/rfpa_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"soc_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 57.2, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "TempPath":"/dev/thermal/tz-by-name/soc_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"charging_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 58.4, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "TempPath":"/dev/thermal/tz-by-name/charging_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"disp_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 41.7, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "TempPath":"/dev/thermal/tz-by-name/disp_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"battery", + "Type":"BATTERY", + "HotThreshold":["NAN", "NAN", "NAN", "NAN", "NAN", "NAN", 60.0], + "Multiplier":0.001 + }, + { + "Name":"btmspkr_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 54.1, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "TempPath":"/dev/thermal/tz-by-name/btmspkr_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"quiet_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 44.6, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "TempPath":"/dev/thermal/tz-by-name/quiet_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"usb_pwr_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 45.0, "NAN", "NAN", "NAN", "NAN", "NAN"], + "TempPath":"/dev/thermal/tz-by-name/usb_pwr_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"battery_cycle", + "Type":"BCL_VOLTAGE" + }, + { + "Name":"critical-battery-cell", + "Type":"BCL_VOLTAGE", + "VirtualSensor":true, + "Formula":"COUNT_THRESHOLD", + "TriggerSensor": "vdroop1", + "Combination":["battery", "battery_cycle", "vdroop1"], + "Coefficient":[-10000, 400, 1000], + "HotThreshold":["NAN", "NAN", "NAN", "NAN", "NAN", 3.00, "NAN"], + "Multiplier":1, + "PollingDelay":0, + "PassiveDelay":1000, + "SendCallback":true + }, + { + "Name":"FLASH_LED_REDUCE", + "Type":"UNKNOWN", + "VirtualSensor":true, + "Formula":"COUNT_THRESHOLD", + "TriggerSensor": "vdroop1", + "Combination":["battery", "battery_cycle", "vdroop1"], + "Coefficient":[-10000, 400, 1000], + "HotThreshold":["NAN", "NAN", "NAN", "NAN", 3.00, "NAN", "NAN"], + "Multiplier":1, + "PollingDelay":0, + "PassiveDelay":1000, + "SendCallback":true, + "SendPowerHint":true + }, + { + "Name":"soc", + "Type":"BCL_PERCENTAGE", + "HotThreshold":["NAN", "NAN", 80, "NAN", "NAN", "NAN", "NAN"], + "Multiplier":1 + }, + { + "Name":"batoilo", + "Type":"BCL_CURRENT", + "HotThreshold":["NAN", "NAN", "NAN", "NAN", 5000, "NAN", "NAN"], + "HotHysteresis":[0.0, 0.0, 0.0, 0.0, 100, 0.0, 0.0], + "Multiplier":1, + "SendCallback":true, + "PollingDelay":0, + "PassiveDelay":1000 + }, + { + "Name":"BCL_AUDIO_BAACL", + "Type":"BCL_VOLTAGE", + "VirtualSensor":true, + "Formula":"COUNT_THRESHOLD", + "TriggerSensor": "soc", + "Combination":["battery", "soc"], + "Coefficient":[-25000, 80], + "HotThreshold":["NAN", "NAN", "NAN", "NAN", 2.0, "NAN", "NAN"], + "PollingDelay":0, + "PassiveDelay":1000, + "Multiplier":1, + "SendCallback":true + }, + { + "Name":"vdroop1", + "Type":"BCL_VOLTAGE", + "HotThreshold":["NAN", "NAN", "NAN", "NAN", 1000, "NAN", "NAN"], + "HotHysteresis":[0.0, 0.0, 0.0, 0.0, 100, 0.0, 0.0], + "Multiplier":1, + "SendCallback":true, + "PollingDelay":0, + "PassiveDelay":1000 + }, + { + "Name":"vdroop2", + "Type":"BCL_VOLTAGE", + "HotThreshold":["NAN", "NAN", "NAN", "NAN", 1200, "NAN", "NAN"], + "HotHysteresis":[0.0, 0.0, 0.0, 0.0, 100, 0.0, 0.0], + "Multiplier":1, + "SendCallback":true, + "PollingDelay":0, + "PassiveDelay":1000 + }, + { + "Name":"smpl_gm", + "Type":"BCL_VOLTAGE", + "HotThreshold":["NAN", "NAN", "NAN", "NAN", 1100, "NAN", "NAN"], + "HotHysteresis":[0.0, 0.0, 0.0, 0.0, 100, 0.0, 0.0], + "Multiplier":1, + "SendCallback":true, + "PollingDelay":0, + "PassiveDelay":1000 + }, + { + "Name":"VIRTUAL-BTS-WINDOW-PARTIAL", + "Type":"UNKNOWN", + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["rfpa_therm", "north_therm"], + "Coefficient":[0.05, 0.14], + "Offset":560, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-SUB-0", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0, 0.27, 0.17, 0.11, 0, 0.2, 0.01, 0.06, 0.08], + "Offset":2110, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-SUB-1", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0.46, 0, 0.14, 0.28, 0, 0.06, 0.02, 0.14, 0], + "Offset":-7280, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-SUB-2", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0.07, 0, 0, 0, 0, 0.28, 0.15, 0.02, 0.3], + "Offset":4010, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-SUB-3", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0.27, 0.06, 0.3, 0, 0, 0.2, 0.03, 0.02, 0.04], + "Offset":10, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-SUB-4", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0.9, 0, 0.05, 0, 0, 0, 0.01, 0, 0], + "Offset":730, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-SUB-5", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0.08, 0.02, 0.24, 0.23, 0, 0.29, 0.01, 0, 0], + "Offset":1870, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-SUB-6", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0, 0, 0, 0.04, 0.2, 0.07, 0.15, 0.3, 0.16], + "Offset":-440, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-SUB-7", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0, 0.01, 0, 0, 0.07, 0.28, 0.25, 0.02, 0.08], + "Offset":9170, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-SUB-8", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0.1, 0.16, 0.11, 0.19, 0.26, 0, 0, 0.11, 0], + "Offset":1140, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-SUB-9", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0.02, 0.05, 0.21, 0.13, 0.02, 0.29, 0.09, 0, 0], + "Offset":5160, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-SUB-10", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0, 0, 0.16, 0, 0.49, 0.35, 0, 0, 0], + "Offset":-1500, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN", + "Type":"SKIN", + "Version":"5.0", + "VirtualSensor":true, + "TriggerSensor":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "quiet_therm", "usb_pwr_therm"], + "Formula":"MAXIMUM", + "Combination":["VIRTUAL-SKIN-SUB-0", "VIRTUAL-SKIN-SUB-1", "VIRTUAL-SKIN-SUB-2", + "VIRTUAL-SKIN-SUB-3", "VIRTUAL-SKIN-SUB-4", "VIRTUAL-SKIN-SUB-5", + "VIRTUAL-SKIN-SUB-6", "VIRTUAL-SKIN-SUB-7", "VIRTUAL-SKIN-SUB-8", "VIRTUAL-SKIN-SUB-9", "VIRTUAL-SKIN-SUB-10"], + "Coefficient":[1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0], + "HotThreshold":["NAN", 49.0, 53.0, 55.0, 56.5, 62.0, 75.0], + "HotHysteresis":[0.0, 1.9, 1.9, 1.9, 1.4, 1.9, 1.9], + "Multiplier":0.001, + "SendCallback":true, + "PollingDelay":300000, + "PassiveDelay":7000, + "BindedCdevInfo": [ + { + "CdevRequest": "tpu_cooling", + "LimitInfo": [0, 2, 3, 4, 5, 5, 5] + }, + { + "CdevRequest": "gxp-cooling", + "LimitInfo": [0, 0, 0, 0, 0, 6, 6] + } + ] + }, + { + "Name":"VIRTUAL-SKIN-HINT", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "TriggerSensor":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "quiet_therm", "usb_pwr_therm"], + "Formula":"MAXIMUM", + "Combination":["VIRTUAL-SKIN"], + "Coefficient":[1.0], + "HotThreshold":["NAN", 47.0, 53.0, 55.0, 56.5, 62.0, 75.0], + "HotHysteresis":[0.0, 1.9, 1.9, 1.9, 1.4, 1.9, 1.9], + "Multiplier":0.001, + "SendPowerHint":true, + "PollingDelay":300000, + "PassiveDelay":7000 + }, + { + "Name":"VIRTUAL-SKIN-CPU-LIGHT-ODPM", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "TriggerSensor":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "quiet_therm", "usb_pwr_therm"], + "Formula":"MAXIMUM", + "Combination":["VIRTUAL-SKIN"], + "Coefficient":[1.0], + "HotThreshold":["NAN", 47.0, 49.0, "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 1.9, 1.9, 0.0, 0.0, 0.0, 0.0], + "Multiplier":0.001, + "PollingDelay":300000, + "PassiveDelay":7000, + "PIDInfo": { + "K_Po":["NAN", "NAN", 400, "NAN", "NAN", "NAN", "NAN"], + "K_Pu":["NAN", "NAN", 400, "NAN", "NAN", "NAN", "NAN"], + "K_I":["NAN", "NAN", 5, "NAN", "NAN", "NAN", "NAN"], + "K_D":["NAN", "NAN", 0, "NAN", "NAN", "NAN", "NAN"], + "I_Max":["NAN", "NAN", 2200, "NAN", "NAN", "NAN", "NAN"], + "S_Power":["NAN", "NAN", 800, "NAN", "NAN", "NAN", "NAN"], + "MinAllocPower":["NAN", "NAN", 800, "NAN", "NAN", "NAN", "NAN"], + "MaxAllocPower":["NAN", "NAN", 4600, "NAN", "NAN", "NAN", "NAN"], + "I_Cutoff":["NAN", "NAN", 4, "NAN", "NAN", "NAN", "NAN"] + }, + "BindedCdevInfo": [ + { + "CdevRequest": "thermal-cpufreq-0", + "CdevWeightForPID": [1, 1, 1, 1, 1, 1, 1], + "MaxReleaseStep": 1, + "MaxThrottleStep": 1, + "BindedPowerRail": "S4M_VDD_CPUCL0", + "CdevCeiling": [0, 2, 2, 2, 2, 2, 2] + }, + { + "CdevRequest": "thermal-cpufreq-1", + "CdevWeightForPID": [1, 1, 1, 1, 1, 1, 1], + "MaxReleaseStep": 1, + "MaxThrottleStep": 2, + "BindedPowerRail": "S3M_VDD_CPUCL1", + "CdevCeiling": [0, 6, 6, 6, 6, 6, 6] + }, + { + "CdevRequest": "thermal-cpufreq-2", + "CdevWeightForPID": [1, 1, 1, 1, 1, 1, 1], + "MaxReleaseStep": 1, + "MaxThrottleStep": 2, + "BindedPowerRail": "S2M_VDD_CPUCL2", + "CdevCeiling": [0, 8, 8, 8, 8, 8, 8] + } + ] + }, + { + "Name":"VIRTUAL-SKIN-CPU-MID", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "TriggerSensor":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "quiet_therm", "usb_pwr_therm"], + "Formula":"MAXIMUM", + "Combination":["VIRTUAL-SKIN"], + "Coefficient":[1.0], + "HotThreshold":["NAN", 49.0, 51.0, "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.0, 1.9, 0.0, 0.0, 0.0, 0.0], + "Multiplier":0.001, + "PollingDelay":300000, + "PassiveDelay":7000, + "PIDInfo": { + "K_Po":["NAN", "NAN", 400, "NAN", "NAN", "NAN", "NAN"], + "K_Pu":["NAN", "NAN", 400, "NAN", "NAN", "NAN", "NAN"], + "K_I":["NAN", "NAN", 5, "NAN", "NAN", "NAN", "NAN"], + "K_D":["NAN", "NAN", 0, "NAN", "NAN", "NAN", "NAN"], + "I_Max":["NAN", "NAN", 1500, "NAN", "NAN", "NAN", "NAN"], + "S_Power":["NAN", "NAN", 700, "NAN", "NAN", "NAN", "NAN"], + "MinAllocPower":["NAN", "NAN", 0, "NAN", "NAN", "NAN", "NAN"], + "MaxAllocPower":["NAN", "NAN", 2800, "NAN", "NAN", "NAN", "NAN"], + "I_Cutoff":["NAN", "NAN", 4, "NAN", "NAN", "NAN", "NAN"] + }, + "BindedCdevInfo": [ + { + "CdevRequest": "thermal-cpufreq-0", + "CdevWeightForPID": [0.292, 0.292, 0.292, 0.292, 0.292, 0.292, 0.292], + "MaxReleaseStep": 1, + "MaxThrottleStep": 1, + "CdevCeiling": [0, 6, 6, 6, 6, 6, 6] + }, + { + "CdevRequest": "thermal-cpufreq-1", + "CdevWeightForPID": [0.804, 0.804, 0.804, 0.804, 0.804, 0.804, 0.804], + "MaxReleaseStep": 1, + "MaxThrottleStep": 2, + "CdevCeiling": [0, 9, 9, 9, 9, 9, 9] + }, + { + "CdevRequest": "thermal-cpufreq-2", + "CdevWeightForPID": [0.342, 0.342, 0.342, 0.342, 0.342, 0.342, 0.342], + "MaxReleaseStep": 1, + "MaxThrottleStep": 2, + "CdevCeiling": [0, 12, 12, 12, 12, 12, 12] + } + ], + "Profile": [ + { + "Mode": "game", + "BindedCdevInfo": [ + { + "CdevRequest": "thermal-cpufreq-0", + "MaxReleaseStep": 1, + "Disabled":true + }, + { + "CdevRequest": "thermal-cpufreq-1", + "MaxReleaseStep": 1, + "Disabled":true + }, + { + "CdevRequest": "thermal-cpufreq-2", + "MaxReleaseStep": 1, + "Disabled":true + } + ] + } + ] + }, + { + "Name":"VIRTUAL-SKIN-CPU-HIGH", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "TriggerSensor":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "quiet_therm", "usb_pwr_therm"], + "Formula":"MAXIMUM", + "Combination":["VIRTUAL-SKIN"], + "Coefficient":[1.0], + "HotThreshold":["NAN", 51.0, 53.0, 62.0, "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.0, 1.9, 1.9, 0.0, 0.0, 0.0], + "Multiplier":0.001, + "PollingDelay":300000, + "PassiveDelay":7000, + "PIDInfo": { + "K_Po":["NAN", "NAN", 400, "NAN", "NAN", "NAN", "NAN"], + "K_Pu":["NAN", "NAN", 400, "NAN", "NAN", "NAN", "NAN"], + "K_I":["NAN", "NAN", 5, "NAN", "NAN", "NAN", "NAN"], + "K_D":["NAN", "NAN", 0, "NAN", "NAN", "NAN", "NAN"], + "I_Max":["NAN", "NAN", 1000, "NAN", "NAN", "NAN", "NAN"], + "S_Power":["NAN", "NAN", 600, "NAN", "NAN", "NAN", "NAN"], + "MinAllocPower":["NAN", "NAN", 0, "NAN", "NAN", "NAN", "NAN"], + "MaxAllocPower":["NAN", "NAN", 1600, "NAN", "NAN", "NAN", "NAN"], + "I_Cutoff":["NAN", "NAN", 4, "NAN", "NAN", "NAN", "NAN"] + }, + "BindedCdevInfo": [ + { + "CdevRequest": "thermal-cpufreq-0", + "CdevWeightForPID": [0.156, 0.156, 0.156, 0.156, 0.156, 0.156, 0.156], + "MaxReleaseStep": 1, + "MaxThrottleStep": 1, + "CdevCeiling": [0, 8, 8, 8, 8, 8, 8] + }, + { + "CdevRequest": "thermal-cpufreq-1", + "CdevWeightForPID": [0.428, 0.428, 0.428, 0.428, 0.428, 0.428, 0.428], + "MaxReleaseStep": 1, + "MaxThrottleStep": 2, + "CdevCeiling": [0, 11, 11, 11, 11, 11, 11] + }, + { + "CdevRequest": "thermal-cpufreq-2", + "CdevWeightForPID": [0.252, 0.225, 0.225, 0.225, 0.225, 0.225, 0.225], + "MaxReleaseStep": 1, + "MaxThrottleStep": 2, + "CdevCeiling": [0, 13, 13, 13, 13, 13, 13] + } + ], + "Profile": [ + { + "Mode": "game", + "BindedCdevInfo": [ + { + "CdevRequest": "thermal-cpufreq-0", + "MaxReleaseStep": 1, + "Disabled":true + }, + { + "CdevRequest": "thermal-cpufreq-1", + "MaxReleaseStep": 1, + "Disabled":true + }, + { + "CdevRequest": "thermal-cpufreq-2", + "MaxReleaseStep": 1, + "Disabled":true + } + ] + }, + { + "Mode": "camera", + "BindedCdevInfo": [ + { + "CdevRequest": "thermal-cpufreq-0", + "MaxReleaseStep": 1, + "Disabled":true + }, + { + "CdevRequest": "thermal-cpufreq-1", + "MaxReleaseStep": 1, + "Disabled":true + }, + { + "CdevRequest": "thermal-cpufreq-2", + "MaxReleaseStep": 1, + "Disabled":true + } + ] + } + ] + }, + { + "Name":"VIRTUAL-SKIN-CPU-GPU", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "TriggerSensor":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "quiet_therm", "usb_pwr_therm"], + "Formula":"MAXIMUM", + "Combination":["VIRTUAL-SKIN"], + "Coefficient":[1.0], + "HotThreshold":["NAN", 47.0, 53.0, 55.0, 56.5, 62.0, 75.0], + "HotHysteresis":[0.0, 1.9, 1.9, 1.9, 1.4, 1.9, 1.9], + "Multiplier":0.001, + "PollingDelay":300000, + "PassiveDelay":7000, + "PIDInfo": { + "K_Po":["NAN", "NAN", "NAN", 300, "NAN", "NAN", "NAN"], + "K_Pu":["NAN", "NAN", "NAN", 300, "NAN", "NAN", "NAN"], + "K_I":["NAN", "NAN", "NAN", 5, "NAN", "NAN", "NAN"], + "K_D":["NAN", "NAN", "NAN", 0, "NAN", "NAN", "NAN"], + "I_Max":["NAN", "NAN", "NAN", 2600, "NAN", "NAN", "NAN"], + "S_Power":["NAN", "NAN", "NAN", 800, "NAN", "NAN", "NAN"], + "MinAllocPower":["NAN", "NAN", "NAN", 0, "NAN", "NAN", "NAN"], + "MaxAllocPower":["NAN", "NAN", "NAN", 3900, "NAN", "NAN", "NAN"], + "I_Cutoff":["NAN", "NAN", "NAN", 8, "NAN", "NAN", "NAN"] + }, + "BindedCdevInfo": [ + { + "CdevRequest": "thermal-cpufreq-0", + "CdevWeightForPID": [1, 1, 1, 1, 1, 1, 1], + "MaxReleaseStep": 1, + "MaxThrottleStep": 1, + "BindedPowerRail": "S4M_VDD_CPUCL0", + "CdevCeiling": [0, 8, 8, 8, 8, 9, 9], + "LimitInfo": [0, 0, 0, 0, 0, 9, 9] + }, + { + "CdevRequest": "thermal-cpufreq-1", + "CdevWeightForPID": [1, 1, 1, 1, 1, 1, 1], + "MaxReleaseStep": 1, + "MaxThrottleStep": 2, + "BindedPowerRail": "S3M_VDD_CPUCL1", + "CdevCeiling": [0, 11, 11, 11, 11, 14, 14], + "LimitInfo": [0, 0, 0, 0, 0, 14, 14] + }, + { + "CdevRequest": "thermal-cpufreq-2", + "CdevWeightForPID": [1, 1, 1, 1, 1, 1, 1], + "MaxReleaseStep": 1, + "MaxThrottleStep": 2, + "BindedPowerRail": "S2M_VDD_CPUCL2", + "CdevCeiling": [0, 13, 13, 13, 13, 14, 14], + "LimitInfo": [0, 0, 0, 0, 0, 14, 14] + }, + { + "CdevRequest": "thermal-gpufreq-0", + "CdevWeightForPID": [1, 1, 1, 1, 1, 1, 1], + "MaxReleaseStep": 1, + "MaxThrottleStep": 1, + "BindedPowerRail": "S2S_VDD_G3D", + "CdevCeiling": [0, 8, 8, 8, 9, 11, 11], + "LimitInfo": [0, 0, 0, 0, 0, 11, 11] + } + ] + }, + { + "Name":"VIRTUAL-SKIN-GPU", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "TriggerSensor":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "quiet_therm", "usb_pwr_therm"], + "Formula":"MAXIMUM", + "Combination":["VIRTUAL-SKIN"], + "Coefficient":[1.0], + "HotThreshold":["NAN", 53.0, 55.0, 56.5, 62.0, "NAN", "NAN"], + "HotHysteresis":[0.0, 1.9, 1.9, 1.4, 1.9, 0.0, 0.0], + "Multiplier":0.001, + "PollingDelay":300000, + "PassiveDelay":7000, + "PIDInfo": { + "K_Po":["NAN", "NAN", 700, "NAN", "NAN", "NAN", "NAN"], + "K_Pu":["NAN", "NAN", 700, "NAN", "NAN", "NAN", "NAN"], + "K_I":["NAN", "NAN", 5, "NAN", "NAN", "NAN", "NAN"], + "K_D":["NAN", "NAN", 0, "NAN", "NAN", "NAN", "NAN"], + "I_Max":["NAN", "NAN", 1723, "NAN", "NAN", "NAN", "NAN"], + "S_Power":["NAN", "NAN", 473, "NAN", "NAN", "NAN", "NAN"], + "MinAllocPower":["NAN", "NAN", 0, "NAN", "NAN", "NAN", "NAN"], + "MaxAllocPower":["NAN", "NAN", 2500, "NAN", "NAN", "NAN", "NAN"], + "I_Cutoff":["NAN", "NAN", 4, "NAN", "NAN", "NAN", "NAN"] + }, + "BindedCdevInfo": [ + { + "CdevRequest": "thermal-gpufreq-0", + "CdevWeightForPID": [1, 1, 1, 1, 1, 1, 1], + "CdevCeiling": [0, 8, 8, 9, 11, 11, 11] + } + ] + }, + { + "Name":"cellular-emergency", + "Type":"POWER_AMPLIFIER", + "VirtualSensor":true, + "TriggerSensor":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "quiet_therm", "usb_pwr_therm"], + "Formula":"MAXIMUM", + "Combination":["VIRTUAL-SKIN"], + "Coefficient":[1.0], + "HotThreshold":["NAN", "NAN", "NAN", "NAN", "NAN", 64.0, "NAN"], + "HotHysteresis":[0.0, 0.0, 0.0, 0.0, 0.0, 1.9, 0.0], + "Multiplier":0.001, + "SendCallback":true, + "PollingDelay":300000, + "PassiveDelay":7000 + }, + { + "Name":"VIRTUAL-SKIN-SPEAKER-SUB-0", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0, 0.14, 0, 0.15, 0, 0, 0, 0.88, 0], + "Offset":-11750, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-SPEAKER-SUB-1", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0.01, 0.18, 0, 0, 0, 0.24, 0, 0.01, 0.35], + "Offset":3600, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-SPEAKER-SUB-2", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0, 0.01, 0, 0, 0.13, 0.31, 0.11, 0.18, 0.09], + "Offset":2140, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-SPEAKER", + "Type":"UNKNOWN", + "Version":"2.0", + "VirtualSensor":true, + "TriggerSensor":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "quiet_therm", "usb_pwr_therm"], + "Formula":"MAXIMUM", + "Combination":["VIRTUAL-SKIN-SPEAKER-SUB-0", "VIRTUAL-SKIN-SPEAKER-SUB-1", "VIRTUAL-SKIN-SPEAKER-SUB-2"], + "Coefficient":[1, 1, 1], + "HotThreshold":["NAN", 47.0, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 1.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "Multiplier":0.001, + "SendCallback":true + }, + { + "Name":"VIRTUAL-SKIN-FRONT-SUB-0", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0.04, 0.03, 0.1, 0.05, 0.35, 0.3, 0, 0, 0.04], + "Offset":1850, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-FRONT-SUB-1", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0, 0, 0.35, 0.22, 0.22, 0.07, 0.03, 0, 0], + "Offset":-560, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-FRONT-SUB-2", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0.05, 0.13, 0.12, 0.07, 0.37, 0.06, 0.01, 0.01, 0], + "Offset":5070, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-FRONT", + "Type":"UNKNOWN", + "Version":"1.0", + "VirtualSensor":true, + "TriggerSensor":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "quiet_therm", "usb_pwr_therm"], + "Formula":"MAXIMUM", + "Combination":["VIRTUAL-SKIN-FRONT-SUB-0", "VIRTUAL-SKIN-FRONT-SUB-1", "VIRTUAL-SKIN-FRONT-SUB-2"], + "Coefficient":[1, 1, 1], + "Multiplier":0.001 + }, + { + "Name":"LITTLE", + "Type":"CPU", + "Multiplier":0.001 + }, + { + "Name":"MID", + "Type":"CPU", + "Multiplier":0.001 + }, + { + "Name":"BIG", + "Type":"CPU", + "Multiplier":0.001 + }, + { + "Name":"G3D", + "Type":"GPU", + "Multiplier":0.001 + }, + { + "Name":"TPU", + "Type":"NPU", + "Multiplier":0.001 + } + ], + "CoolingDevices":[ + { + "Name":"thermal-cpufreq-0", + "Type":"CPU", + "WritePath":"/dev/thermal/cdev-by-name/thermal-cpufreq-0/user_vote" + }, + { + "Name":"thermal-cpufreq-1", + "Type":"CPU", + "WritePath":"/dev/thermal/cdev-by-name/thermal-cpufreq-1/user_vote" + }, + { + "Name":"thermal-cpufreq-2", + "Type":"CPU", + "WritePath":"/dev/thermal/cdev-by-name/thermal-cpufreq-2/user_vote" + }, + { + "Name":"thermal-gpufreq-0", + "Type":"GPU", + "WritePath":"/dev/thermal/cdev-by-name/thermal-gpufreq-0/user_vote" + }, + { + "Name":"chg_mdis", + "Type":"BATTERY" + }, + { + "Name":"usbc-port", + "Type":"BATTERY" + }, + { + "Name":"tpu_cooling", + "Type":"NPU", + "WritePath":"/dev/thermal/cdev-by-name/tpu_cooling/user_vote" + }, + { + "Name":"gxp-cooling", + "Type":"NPU", + "WritePath":"/dev/thermal/cdev-by-name/gxp-cooling/user_vote" + } + ], + "PowerRails":[ + { + "Name":"S2M_VDD_CPUCL2", + "PowerSampleDelay":7000, + "PowerSampleCount":1 + }, + { + "Name":"S3M_VDD_CPUCL1", + "PowerSampleDelay":7000, + "PowerSampleCount":1 + }, + { + "Name":"S4M_VDD_CPUCL0", + "PowerSampleDelay":7000, + "PowerSampleCount":1 + }, + { + "Name":"S2S_VDD_G3D", + "PowerSampleDelay":7000, + "PowerSampleCount":1 + }, + { + "Name":"PARTIAL_SYSTEM_POWER", + "VirtualRails":true, + "Formula":"WEIGHTED_AVG", + "Combination":["S1S_VDD_CAM", "S2S_VDD_G3D", "S4S_VDD2H_MEM", "S5S_VDDQ_MEM", "S8S_VDD_G3D_L2", "S9S_VDD_AOC", "L2S_PLL_MIPI_UFS", "L9S_GNSS_CORE", "L21S_VDD2L_MEM", "VSYS_PWR_DISPLAY", "VSYS_PWR_WLAN_BT", "S1M_VDD_MIF", "S2M_VDD_CPUCL2", "S3M_VDD_CPUCL1", "S4M_VDD_CPUCL0", "S5M_VDD_INT", "S6M_LLDO1", "S7M_VDD_TPU", "S8M_LLDO2", "VSYS_PWR_MODEM"], + "Coefficient":[1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0], + "PowerSampleDelay":7000, + "PowerSampleCount":5 + } + ], + "Stats": { + "Sensors": { + "RecordWithDefaultThreshold": ["VIRTUAL-SKIN"], + "RecordWithThreshold": [ + { + "Name": "VIRTUAL-BTS-WINDOW-PARTIAL", + "Thresholds": [41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 75] + }, + { + "Name": "VIRTUAL-SKIN-SPEAKER", + "Thresholds": [41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 75] + }, + { + "Name": "VIRTUAL-SKIN", + "Thresholds": [41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 75] + }, + { + "Name": "VIRTUAL-SKIN-SUB-0", + "Thresholds": [41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 75] + }, + { + "Name": "VIRTUAL-SKIN-SUB-1", + "Thresholds": [41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 75] + }, + { + "Name": "VIRTUAL-SKIN-SUB-2", + "Thresholds": [41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 75] + }, + { + "Name": "VIRTUAL-SKIN-SUB-3", + "Thresholds": [41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 75] + }, + { + "Name": "VIRTUAL-SKIN-SUB-4", + "Thresholds": [41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 75] + }, + { + "Name": "VIRTUAL-SKIN-SUB-5", + "Thresholds": [41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 75] + }, + { + "Name": "VIRTUAL-SKIN-SUB-6", + "Thresholds": [41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 75] + }, + { + "Name": "VIRTUAL-SKIN-SUB-7", + "Thresholds": [41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 75] + } + ] + }, + "CoolingDevices": { + "RecordVotePerSensor": { + "DefaultThresholdEnableAll": true + } + } + } +} diff --git a/thermal/thermal_info_config_tokay.json b/thermal/thermal_info_config_tokay.json new file mode 100644 index 0000000..4a4278a --- /dev/null +++ b/thermal/thermal_info_config_tokay.json @@ -0,0 +1,926 @@ +{ + "Sensors":[ + { + "Name":"north_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 42.1, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "TempPath":"/dev/thermal/tz-by-name/north_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"rfpa_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 43.7, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "TempPath":"/dev/thermal/tz-by-name/rfpa_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"soc_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 57.2, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "TempPath":"/dev/thermal/tz-by-name/soc_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"charging_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 58.4, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "TempPath":"/dev/thermal/tz-by-name/charging_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"disp_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 41.7, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "TempPath":"/dev/thermal/tz-by-name/disp_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"battery", + "Type":"BATTERY", + "HotThreshold":["NAN", "NAN", "NAN", "NAN", "NAN", "NAN", 60.0], + "Multiplier":0.001 + }, + { + "Name":"btmspkr_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 54.1, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "TempPath":"/dev/thermal/tz-by-name/btmspkr_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"quiet_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 44.6, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "TempPath":"/dev/thermal/tz-by-name/quiet_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"usb_pwr_therm", + "Type":"UNKNOWN", + "HotThreshold":["NAN", 45.0, "NAN", "NAN", "NAN", "NAN", "NAN"], + "TempPath":"/dev/thermal/tz-by-name/usb_pwr_therm/tz_temp", + "Multiplier":0.001, + "PollingDelay":60000, + "PassiveDelay":7000 + }, + { + "Name":"battery_cycle", + "Type":"BCL_VOLTAGE" + }, + { + "Name":"critical-battery-cell", + "Type":"BCL_VOLTAGE", + "VirtualSensor":true, + "Formula":"COUNT_THRESHOLD", + "TriggerSensor": "vdroop1", + "Combination":["battery", "battery_cycle", "vdroop1"], + "Coefficient":[-10000, 400, 1000], + "HotThreshold":["NAN", "NAN", "NAN", "NAN", "NAN", 3.00, "NAN"], + "Multiplier":1, + "PollingDelay":0, + "PassiveDelay":1000, + "SendCallback":true + }, + { + "Name":"FLASH_LED_REDUCE", + "Type":"UNKNOWN", + "VirtualSensor":true, + "Formula":"COUNT_THRESHOLD", + "TriggerSensor": "vdroop1", + "Combination":["battery", "battery_cycle", "vdroop1"], + "Coefficient":[-10000, 400, 1000], + "HotThreshold":["NAN", "NAN", "NAN", "NAN", 3.00, "NAN", "NAN"], + "Multiplier":1, + "PollingDelay":0, + "PassiveDelay":1000, + "SendCallback":true, + "SendPowerHint":true + }, + { + "Name":"soc", + "Type":"BCL_PERCENTAGE", + "HotThreshold":["NAN", "NAN", 80, "NAN", "NAN", "NAN", "NAN"], + "Multiplier":1 + }, + { + "Name":"batoilo", + "Type":"BCL_CURRENT", + "HotThreshold":["NAN", "NAN", "NAN", "NAN", 5000, "NAN", "NAN"], + "HotHysteresis":[0.0, 0.0, 0.0, 0.0, 100, 0.0, 0.0], + "Multiplier":1, + "SendCallback":true, + "PollingDelay":0, + "PassiveDelay":1000 + }, + { + "Name":"BCL_AUDIO_BAACL", + "Type":"BCL_VOLTAGE", + "VirtualSensor":true, + "Formula":"COUNT_THRESHOLD", + "TriggerSensor": "soc", + "Combination":["battery", "soc"], + "Coefficient":[-25000, 80], + "HotThreshold":["NAN", "NAN", "NAN", "NAN", 2.0, "NAN", "NAN"], + "PollingDelay":0, + "PassiveDelay":1000, + "Multiplier":1, + "SendCallback":true + }, + { + "Name":"vdroop1", + "Type":"BCL_VOLTAGE", + "HotThreshold":["NAN", "NAN", "NAN", "NAN", 1000, "NAN", "NAN"], + "HotHysteresis":[0.0, 0.0, 0.0, 0.0, 100, 0.0, 0.0], + "Multiplier":1, + "SendCallback":true, + "PollingDelay":0, + "PassiveDelay":1000 + }, + { + "Name":"vdroop2", + "Type":"BCL_VOLTAGE", + "HotThreshold":["NAN", "NAN", "NAN", "NAN", 1200, "NAN", "NAN"], + "HotHysteresis":[0.0, 0.0, 0.0, 0.0, 100, 0.0, 0.0], + "Multiplier":1, + "SendCallback":true, + "PollingDelay":0, + "PassiveDelay":1000 + }, + { + "Name":"smpl_gm", + "Type":"BCL_VOLTAGE", + "HotThreshold":["NAN", "NAN", "NAN", "NAN", 1100, "NAN", "NAN"], + "HotHysteresis":[0.0, 0.0, 0.0, 0.0, 100, 0.0, 0.0], + "Multiplier":1, + "SendCallback":true, + "PollingDelay":0, + "PassiveDelay":1000 + }, + { + "Name":"VIRTUAL-BTS-WINDOW-PARTIAL", + "Type":"UNKNOWN", + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["rfpa_therm", "north_therm"], + "Coefficient":[0.05, 0.14], + "Offset":560, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-SUB-0", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0, 0.27, 0.17, 0.11, 0, 0.2, 0.01, 0.06, 0.08], + "Offset":2110, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-SUB-1", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0.46, 0, 0.14, 0.28, 0, 0.06, 0.02, 0.14, 0], + "Offset":-7280, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-SUB-2", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0.07, 0, 0, 0, 0, 0.28, 0.15, 0.02, 0.3], + "Offset":4010, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-SUB-3", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0.27, 0.06, 0.3, 0, 0, 0.2, 0.03, 0.02, 0.04], + "Offset":10, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-SUB-4", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0.9, 0, 0.05, 0, 0, 0, 0.01, 0, 0], + "Offset":730, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-SUB-5", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0.08, 0.02, 0.24, 0.23, 0, 0.29, 0.01, 0, 0], + "Offset":1870, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-SUB-6", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0, 0, 0, 0.04, 0.2, 0.07, 0.15, 0.3, 0.16], + "Offset":-440, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-SUB-7", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0, 0.01, 0, 0, 0.07, 0.28, 0.25, 0.02, 0.08], + "Offset":9170, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-SUB-8", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0.1, 0.16, 0.11, 0.19, 0.26, 0, 0, 0.11, 0], + "Offset":1140, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-SUB-9", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0.02, 0.05, 0.21, 0.13, 0.02, 0.29, 0.09, 0, 0], + "Offset":5160, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-SUB-10", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0, 0, 0.16, 0, 0.49, 0.35, 0, 0, 0], + "Offset":-1500, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN", + "Type":"SKIN", + "Version":"5.0", + "VirtualSensor":true, + "TriggerSensor":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "quiet_therm", "usb_pwr_therm"], + "Formula":"MAXIMUM", + "Combination":["VIRTUAL-SKIN-SUB-0", "VIRTUAL-SKIN-SUB-1", "VIRTUAL-SKIN-SUB-2", + "VIRTUAL-SKIN-SUB-3", "VIRTUAL-SKIN-SUB-4", "VIRTUAL-SKIN-SUB-5", + "VIRTUAL-SKIN-SUB-6", "VIRTUAL-SKIN-SUB-7", "VIRTUAL-SKIN-SUB-8", "VIRTUAL-SKIN-SUB-9", "VIRTUAL-SKIN-SUB-10"], + "Coefficient":[1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0], + "HotThreshold":["NAN", 49.0, 53.0, 55.0, 56.5, 62.0, 75.0], + "HotHysteresis":[0.0, 1.9, 1.9, 1.9, 1.4, 1.9, 1.9], + "Multiplier":0.001, + "SendCallback":true, + "PollingDelay":300000, + "PassiveDelay":7000, + "BindedCdevInfo": [ + { + "CdevRequest": "tpu_cooling", + "LimitInfo": [0, 2, 3, 4, 5, 5, 5] + }, + { + "CdevRequest": "gxp-cooling", + "LimitInfo": [0, 0, 0, 0, 0, 6, 6] + } + ] + }, + { + "Name":"VIRTUAL-SKIN-HINT", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "TriggerSensor":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "quiet_therm", "usb_pwr_therm"], + "Formula":"MAXIMUM", + "Combination":["VIRTUAL-SKIN"], + "Coefficient":[1.0], + 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"NAN", "NAN"], + "S_Power":["NAN", "NAN", 800, "NAN", "NAN", "NAN", "NAN"], + "MinAllocPower":["NAN", "NAN", 800, "NAN", "NAN", "NAN", "NAN"], + "MaxAllocPower":["NAN", "NAN", 4600, "NAN", "NAN", "NAN", "NAN"], + "I_Cutoff":["NAN", "NAN", 4, "NAN", "NAN", "NAN", "NAN"] + }, + "BindedCdevInfo": [ + { + "CdevRequest": "thermal-cpufreq-0", + "CdevWeightForPID": [1, 1, 1, 1, 1, 1, 1], + "MaxReleaseStep": 1, + "MaxThrottleStep": 1, + "BindedPowerRail": "S4M_VDD_CPUCL0", + "CdevCeiling": [0, 2, 2, 2, 2, 2, 2] + }, + { + "CdevRequest": "thermal-cpufreq-1", + "CdevWeightForPID": [1, 1, 1, 1, 1, 1, 1], + "MaxReleaseStep": 1, + "MaxThrottleStep": 2, + "BindedPowerRail": "S3M_VDD_CPUCL1", + "CdevCeiling": [0, 6, 6, 6, 6, 6, 6] + }, + { + "CdevRequest": "thermal-cpufreq-2", + "CdevWeightForPID": [1, 1, 1, 1, 1, 1, 1], + "MaxReleaseStep": 1, + "MaxThrottleStep": 2, + "BindedPowerRail": "S2M_VDD_CPUCL2", + "CdevCeiling": [0, 8, 8, 8, 8, 8, 8] + } + ] + }, + { + "Name":"VIRTUAL-SKIN-CPU-MID", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "TriggerSensor":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "quiet_therm", "usb_pwr_therm"], + "Formula":"MAXIMUM", + "Combination":["VIRTUAL-SKIN"], + "Coefficient":[1.0], + "HotThreshold":["NAN", 49.0, 51.0, "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.0, 1.9, 0.0, 0.0, 0.0, 0.0], + "Multiplier":0.001, + "PollingDelay":300000, + "PassiveDelay":7000, + "PIDInfo": { + "K_Po":["NAN", "NAN", 400, "NAN", "NAN", "NAN", "NAN"], + "K_Pu":["NAN", "NAN", 400, "NAN", "NAN", "NAN", "NAN"], + "K_I":["NAN", "NAN", 5, "NAN", "NAN", "NAN", "NAN"], + "K_D":["NAN", "NAN", 0, "NAN", "NAN", "NAN", "NAN"], + "I_Max":["NAN", "NAN", 1500, "NAN", "NAN", "NAN", "NAN"], + "S_Power":["NAN", "NAN", 700, "NAN", "NAN", "NAN", "NAN"], + "MinAllocPower":["NAN", "NAN", 0, "NAN", "NAN", "NAN", "NAN"], + "MaxAllocPower":["NAN", "NAN", 2800, "NAN", "NAN", "NAN", "NAN"], + "I_Cutoff":["NAN", "NAN", 4, "NAN", "NAN", "NAN", "NAN"] + }, + "BindedCdevInfo": [ + { + "CdevRequest": "thermal-cpufreq-0", + "CdevWeightForPID": [0.292, 0.292, 0.292, 0.292, 0.292, 0.292, 0.292], + "MaxReleaseStep": 1, + "MaxThrottleStep": 1, + "CdevCeiling": [0, 6, 6, 6, 6, 6, 6] + }, + { + "CdevRequest": "thermal-cpufreq-1", + "CdevWeightForPID": [0.804, 0.804, 0.804, 0.804, 0.804, 0.804, 0.804], + "MaxReleaseStep": 1, + "MaxThrottleStep": 2, + "CdevCeiling": [0, 9, 9, 9, 9, 9, 9] + }, + { + "CdevRequest": "thermal-cpufreq-2", + "CdevWeightForPID": [0.342, 0.342, 0.342, 0.342, 0.342, 0.342, 0.342], + "MaxReleaseStep": 1, + "MaxThrottleStep": 2, + "CdevCeiling": [0, 12, 12, 12, 12, 12, 12] + } + ], + "Profile": [ + { + "Mode": "game", + "BindedCdevInfo": [ + { + "CdevRequest": "thermal-cpufreq-0", + "MaxReleaseStep": 1, + "Disabled":true + }, + { + "CdevRequest": "thermal-cpufreq-1", + "MaxReleaseStep": 1, + "Disabled":true + }, + { + "CdevRequest": "thermal-cpufreq-2", + "MaxReleaseStep": 1, + "Disabled":true + } + ] + } + ] + }, + { + "Name":"VIRTUAL-SKIN-CPU-HIGH", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "TriggerSensor":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "quiet_therm", "usb_pwr_therm"], + "Formula":"MAXIMUM", + "Combination":["VIRTUAL-SKIN"], + "Coefficient":[1.0], + "HotThreshold":["NAN", 51.0, 53.0, 62.0, "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 0.0, 1.9, 1.9, 0.0, 0.0, 0.0], + "Multiplier":0.001, + "PollingDelay":300000, + "PassiveDelay":7000, + "PIDInfo": { + "K_Po":["NAN", "NAN", 400, "NAN", "NAN", "NAN", "NAN"], + "K_Pu":["NAN", "NAN", 400, "NAN", "NAN", "NAN", "NAN"], + "K_I":["NAN", "NAN", 5, "NAN", "NAN", "NAN", "NAN"], + "K_D":["NAN", "NAN", 0, "NAN", "NAN", "NAN", "NAN"], + "I_Max":["NAN", "NAN", 1000, "NAN", "NAN", "NAN", "NAN"], + "S_Power":["NAN", "NAN", 600, "NAN", "NAN", "NAN", "NAN"], + "MinAllocPower":["NAN", "NAN", 0, "NAN", "NAN", "NAN", "NAN"], + "MaxAllocPower":["NAN", "NAN", 1600, "NAN", "NAN", "NAN", "NAN"], + "I_Cutoff":["NAN", "NAN", 4, "NAN", "NAN", "NAN", "NAN"] + }, + "BindedCdevInfo": [ + { + "CdevRequest": "thermal-cpufreq-0", + "CdevWeightForPID": [0.156, 0.156, 0.156, 0.156, 0.156, 0.156, 0.156], + "MaxReleaseStep": 1, + "MaxThrottleStep": 1, + "CdevCeiling": [0, 8, 8, 8, 8, 8, 8] + }, + { + "CdevRequest": "thermal-cpufreq-1", + "CdevWeightForPID": [0.428, 0.428, 0.428, 0.428, 0.428, 0.428, 0.428], + "MaxReleaseStep": 1, + "MaxThrottleStep": 2, + "CdevCeiling": [0, 11, 11, 11, 11, 11, 11] + }, + { + "CdevRequest": "thermal-cpufreq-2", + "CdevWeightForPID": [0.252, 0.225, 0.225, 0.225, 0.225, 0.225, 0.225], + "MaxReleaseStep": 1, + "MaxThrottleStep": 2, + "CdevCeiling": [0, 13, 13, 13, 13, 13, 13] + } + ], + "Profile": [ + { + "Mode": "game", + "BindedCdevInfo": [ + { + "CdevRequest": "thermal-cpufreq-0", + "MaxReleaseStep": 1, + "Disabled":true + }, + { + "CdevRequest": "thermal-cpufreq-1", + "MaxReleaseStep": 1, + "Disabled":true + }, + { + "CdevRequest": "thermal-cpufreq-2", + "MaxReleaseStep": 1, + "Disabled":true + } + ] + }, + { + "Mode": "camera", + "BindedCdevInfo": [ + { + "CdevRequest": "thermal-cpufreq-0", + "MaxReleaseStep": 1, + "Disabled":true + }, + { + "CdevRequest": "thermal-cpufreq-1", + "MaxReleaseStep": 1, + "Disabled":true + }, + { + "CdevRequest": "thermal-cpufreq-2", + "MaxReleaseStep": 1, + "Disabled":true + } + ] + } + ] + }, + { + "Name":"VIRTUAL-SKIN-CPU-GPU", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "TriggerSensor":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "quiet_therm", "usb_pwr_therm"], + "Formula":"MAXIMUM", + "Combination":["VIRTUAL-SKIN"], + "Coefficient":[1.0], + "HotThreshold":["NAN", 47.0, 53.0, 55.0, 56.5, 62.0, 75.0], + "HotHysteresis":[0.0, 1.9, 1.9, 1.9, 1.4, 1.9, 1.9], + "Multiplier":0.001, + "PollingDelay":300000, + "PassiveDelay":7000, + "PIDInfo": { + "K_Po":["NAN", "NAN", "NAN", 300, "NAN", "NAN", "NAN"], + "K_Pu":["NAN", "NAN", "NAN", 300, "NAN", "NAN", "NAN"], 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"PIDInfo": { + "K_Po":["NAN", "NAN", 700, "NAN", "NAN", "NAN", "NAN"], + "K_Pu":["NAN", "NAN", 700, "NAN", "NAN", "NAN", "NAN"], + "K_I":["NAN", "NAN", 5, "NAN", "NAN", "NAN", "NAN"], + "K_D":["NAN", "NAN", 0, "NAN", "NAN", "NAN", "NAN"], + "I_Max":["NAN", "NAN", 1723, "NAN", "NAN", "NAN", "NAN"], + "S_Power":["NAN", "NAN", 473, "NAN", "NAN", "NAN", "NAN"], + "MinAllocPower":["NAN", "NAN", 0, "NAN", "NAN", "NAN", "NAN"], + "MaxAllocPower":["NAN", "NAN", 2500, "NAN", "NAN", "NAN", "NAN"], + "I_Cutoff":["NAN", "NAN", 4, "NAN", "NAN", "NAN", "NAN"] + }, + "BindedCdevInfo": [ + { + "CdevRequest": "thermal-gpufreq-0", + "CdevWeightForPID": [1, 1, 1, 1, 1, 1, 1], + "CdevCeiling": [0, 8, 8, 9, 11, 11, 11] + } + ] + }, + { + "Name":"cellular-emergency", + "Type":"POWER_AMPLIFIER", + "VirtualSensor":true, + "TriggerSensor":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "quiet_therm", "usb_pwr_therm"], + "Formula":"MAXIMUM", + "Combination":["VIRTUAL-SKIN"], + "Coefficient":[1.0], + "HotThreshold":["NAN", "NAN", "NAN", "NAN", "NAN", 64.0, "NAN"], + "HotHysteresis":[0.0, 0.0, 0.0, 0.0, 0.0, 1.9, 0.0], + "Multiplier":0.001, + "SendCallback":true, + "PollingDelay":300000, + "PassiveDelay":7000 + }, + { + "Name":"VIRTUAL-SKIN-SPEAKER-SUB-0", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0, 0.14, 0, 0.15, 0, 0, 0, 0.88, 0], + "Offset":-11750, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-SPEAKER-SUB-1", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0.01, 0.18, 0, 0, 0, 0.24, 0, 0.01, 0.35], + "Offset":3600, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-SPEAKER-SUB-2", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0, 0.01, 0, 0, 0.13, 0.31, 0.11, 0.18, 0.09], + "Offset":2140, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-SPEAKER", + "Type":"UNKNOWN", + "Version":"2.0", + "VirtualSensor":true, + "TriggerSensor":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "quiet_therm", "usb_pwr_therm"], + "Formula":"MAXIMUM", + "Combination":["VIRTUAL-SKIN-SPEAKER-SUB-0", "VIRTUAL-SKIN-SPEAKER-SUB-1", "VIRTUAL-SKIN-SPEAKER-SUB-2"], + "Coefficient":[1, 1, 1], + "HotThreshold":["NAN", 47.0, "NAN", "NAN", "NAN", "NAN", "NAN"], + "HotHysteresis":[0.0, 1.9, 0.0, 0.0, 0.0, 0.0, 0.0], + "Multiplier":0.001, + "SendCallback":true + }, + { + "Name":"VIRTUAL-SKIN-FRONT-SUB-0", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0.04, 0.03, 0.1, 0.05, 0.35, 0.3, 0, 0, 0.04], + "Offset":1850, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-FRONT-SUB-1", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0, 0, 0.35, 0.22, 0.22, 0.07, 0.03, 0, 0], + "Offset":-560, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-FRONT-SUB-2", + "Type":"UNKNOWN", + "Hidden":true, + "VirtualSensor":true, + "Formula":"WEIGHTED_AVG", + "Combination":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "battery", "btmspkr_therm", "quiet_therm", "usb_pwr_therm"], + "Coefficient":[0.05, 0.13, 0.12, 0.07, 0.37, 0.06, 0.01, 0.01, 0], + "Offset":5070, + "Multiplier":0.001 + }, + { + "Name":"VIRTUAL-SKIN-FRONT", + "Type":"UNKNOWN", + "Version":"1.0", + "VirtualSensor":true, + "TriggerSensor":["north_therm", "rfpa_therm", "soc_therm", "charging_therm", "disp_therm", "quiet_therm", "usb_pwr_therm"], + "Formula":"MAXIMUM", + "Combination":["VIRTUAL-SKIN-FRONT-SUB-0", "VIRTUAL-SKIN-FRONT-SUB-1", "VIRTUAL-SKIN-FRONT-SUB-2"], + "Coefficient":[1, 1, 1], + "Multiplier":0.001 + }, + { + "Name":"LITTLE", + "Type":"CPU", + "Multiplier":0.001 + }, + { + "Name":"MID", + "Type":"CPU", + "Multiplier":0.001 + }, + { + "Name":"BIG", + "Type":"CPU", + "Multiplier":0.001 + }, + { + "Name":"G3D", + "Type":"GPU", + "Multiplier":0.001 + }, + { + "Name":"TPU", + "Type":"NPU", + "Multiplier":0.001 + } + ], + "CoolingDevices":[ + { + "Name":"thermal-cpufreq-0", + "Type":"CPU", + "WritePath":"/dev/thermal/cdev-by-name/thermal-cpufreq-0/user_vote" + }, + { + "Name":"thermal-cpufreq-1", + "Type":"CPU", + "WritePath":"/dev/thermal/cdev-by-name/thermal-cpufreq-1/user_vote" + }, + { + "Name":"thermal-cpufreq-2", + "Type":"CPU", + "WritePath":"/dev/thermal/cdev-by-name/thermal-cpufreq-2/user_vote" + }, + { + "Name":"thermal-gpufreq-0", + "Type":"GPU", + "WritePath":"/dev/thermal/cdev-by-name/thermal-gpufreq-0/user_vote" + }, + { + "Name":"chg_mdis", + "Type":"BATTERY" + }, + { + "Name":"usbc-port", + "Type":"BATTERY" + }, + { + "Name":"tpu_cooling", + "Type":"NPU", + "WritePath":"/dev/thermal/cdev-by-name/tpu_cooling/user_vote" + }, + { + "Name":"gxp-cooling", + "Type":"NPU", + "WritePath":"/dev/thermal/cdev-by-name/gxp-cooling/user_vote" + } + ], + "PowerRails":[ + { + "Name":"S2M_VDD_CPUCL2", + "PowerSampleDelay":7000, + "PowerSampleCount":1 + }, + { + "Name":"S3M_VDD_CPUCL1", + "PowerSampleDelay":7000, + "PowerSampleCount":1 + }, + { + "Name":"S4M_VDD_CPUCL0", + "PowerSampleDelay":7000, + "PowerSampleCount":1 + }, + { + "Name":"S2S_VDD_G3D", + "PowerSampleDelay":7000, + "PowerSampleCount":1 + }, + { + "Name":"PARTIAL_SYSTEM_POWER", + "VirtualRails":true, + "Formula":"WEIGHTED_AVG", + "Combination":["S1S_VDD_CAM", "S2S_VDD_G3D", "S4S_VDD2H_MEM", "S5S_VDDQ_MEM", "S8S_VDD_G3D_L2", "S9S_VDD_AOC", "L2S_PLL_MIPI_UFS", "L9S_GNSS_CORE", "L21S_VDD2L_MEM", "VSYS_PWR_DISPLAY", "VSYS_PWR_WLAN_BT", "S1M_VDD_MIF", "S2M_VDD_CPUCL2", "S3M_VDD_CPUCL1", "S4M_VDD_CPUCL0", "S5M_VDD_INT", "S6M_LLDO1", "S7M_VDD_TPU", "S8M_LLDO2", "VSYS_PWR_MODEM"], + "Coefficient":[1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0], + "PowerSampleDelay":7000, + "PowerSampleCount":5 + } + ], + "Stats": { + "Sensors": { + "RecordWithDefaultThreshold": ["VIRTUAL-SKIN"], + "RecordWithThreshold": [ + { + "Name": "VIRTUAL-BTS-WINDOW-PARTIAL", + "Thresholds": [41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 75] + }, + { + "Name": "VIRTUAL-SKIN-SPEAKER", + "Thresholds": [41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 75] + }, + { + "Name": "VIRTUAL-SKIN", + "Thresholds": [41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 75] + }, + { + "Name": "VIRTUAL-SKIN-SUB-0", + "Thresholds": [41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 75 + }, + { + "Name": "VIRTUAL-SKIN-SUB-1", + "Thresholds": [41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 75] + }, + { + "Name": "VIRTUAL-SKIN-SUB-2", + "Thresholds": [41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 75] + }, + { + "Name": "VIRTUAL-SKIN-SUB-3", + "Thresholds": [41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 75] + }, + { + "Name": "VIRTUAL-SKIN-SUB-4", + "Thresholds": [41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 75] + }, + { + "Name": "VIRTUAL-SKIN-SUB-5", + "Thresholds": [41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 75] + }, + { + "Name": "VIRTUAL-SKIN-SUB-6", + "Thresholds": [41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 75] + }, + { + "Name": "VIRTUAL-SKIN-SUB-7", + "Thresholds": [41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 75] + } + ] + }, + "CoolingDevices": { + "RecordVotePerSensor": { + "DefaultThresholdEnableAll": true + } + } + } +} diff --git a/uwb/Android.bp b/uwb/Android.bp new file mode 100644 index 0000000..de2da1f --- /dev/null +++ b/uwb/Android.bp @@ -0,0 +1,71 @@ +// +// Copyright (C) 2021 The Android Open-Source Project +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +soong_namespace {} + +prebuilt_defaults { + name: "conf_defaults", + vendor: true, + sub_dir: "uwb", +} + +prebuilt_etc { + name: "configuration.conf", + src: "configuration.conf", + defaults: ["conf_defaults"], +} + +prebuilt_etc { + name: "calibration.conf", + src: "calibration.conf", + defaults: ["conf_defaults"], +} + +prebuilt_etc { + name: "calibration-default.conf", + src: "calibration-default.conf", + defaults: ["conf_defaults"], +} + +prebuilt_etc { + name: "calibration-CE.conf", + src: "calibration-CE.conf", + defaults: ["conf_defaults"], +} + +prebuilt_etc { + name: "calibration-FCC.conf", + src: "calibration-FCC.conf", + defaults: ["conf_defaults"], +} + +prebuilt_etc { + name: "calibration-JP.conf", + src: "calibration-JP.conf", + defaults: ["conf_defaults"], +} + +prebuilt_etc { + name: "calibration-TW.conf", + src: "calibration-TW.conf", + defaults: ["conf_defaults"], +} + +prebuilt_etc { + name: "calibration-RESTRICTED.conf", + src: "calibration-RESTRICTED.conf", + defaults: ["conf_defaults"], +} + diff --git a/uwb/calibration-CE.conf b/uwb/calibration-CE.conf new file mode 100644 index 0000000..385bc55 --- /dev/null +++ b/uwb/calibration-CE.conf @@ -0,0 +1,73 @@ +# CE calibration file + +ant2.ch5.ref_frame0.tx_power_index=08:08:08:08 +ant2.ch5.ref_frame0.post_tx_power_index=0xff +ant2.ch5.ref_frame1.tx_power_index=08:08:08:08 +ant2.ch5.ref_frame1.post_tx_power_index=0xff +ant2.ch5.ref_frame2.tx_power_index=08:08:08:08 +ant2.ch5.ref_frame2.post_tx_power_index=0xff +ant2.ch5.ref_frame3.tx_power_index=08:08:08:08 +ant2.ch5.ref_frame3.post_tx_power_index=0xff +ant2.ch5.ref_frame4.tx_power_index=08:08:08:08 +ant2.ch5.ref_frame4.post_tx_power_index=0xff +ant2.ch5.ref_frame5.tx_power_index=08:08:08:08 +ant2.ch5.ref_frame5.post_tx_power_index=0xff +ant2.ch5.ref_frame6.tx_power_index=08:08:08:08 +ant2.ch5.ref_frame6.post_tx_power_index=0xff +ant2.ch5.ref_frame7.tx_power_index=08:08:08:08 +ant2.ch5.ref_frame7.post_tx_power_index=0xff + +ant2.ch9.ref_frame0.tx_power_index=08:08:08:08 +ant2.ch9.ref_frame0.post_tx_power_index=0xff +ant2.ch9.ref_frame1.tx_power_index=08:08:08:08 +ant2.ch9.ref_frame1.post_tx_power_index=0xff +ant2.ch9.ref_frame2.tx_power_index=08:08:08:08 +ant2.ch9.ref_frame2.post_tx_power_index=0xff +ant2.ch9.ref_frame3.tx_power_index=08:08:08:08 +ant2.ch9.ref_frame3.post_tx_power_index=0xff +ant2.ch9.ref_frame4.tx_power_index=08:08:08:08 +ant2.ch9.ref_frame4.post_tx_power_index=0xff +ant2.ch9.ref_frame5.tx_power_index=08:08:08:08 +ant2.ch9.ref_frame5.post_tx_power_index=0xff +ant2.ch9.ref_frame6.tx_power_index=08:08:08:08 +ant2.ch9.ref_frame6.post_tx_power_index=0xff +ant2.ch9.ref_frame7.tx_power_index=08:08:08:08 +ant2.ch9.ref_frame7.post_tx_power_index=0xff + +ant3.ch5.ref_frame0.tx_power_index=08:08:08:08 +ant3.ch5.ref_frame0.post_tx_power_index=0xff +ant3.ch5.ref_frame1.tx_power_index=08:08:08:08 +ant3.ch5.ref_frame1.post_tx_power_index=0xff +ant3.ch5.ref_frame2.tx_power_index=08:08:08:08 +ant3.ch5.ref_frame2.post_tx_power_index=0xff +ant3.ch5.ref_frame3.tx_power_index=08:08:08:08 +ant3.ch5.ref_frame3.post_tx_power_index=0xff +ant3.ch5.ref_frame4.tx_power_index=08:08:08:08 +ant3.ch5.ref_frame4.post_tx_power_index=0xff +ant3.ch5.ref_frame5.tx_power_index=08:08:08:08 +ant3.ch5.ref_frame5.post_tx_power_index=0xff +ant3.ch5.ref_frame6.tx_power_index=08:08:08:08 +ant3.ch5.ref_frame6.post_tx_power_index=0xff +ant3.ch5.ref_frame7.tx_power_index=08:08:08:08 +ant3.ch5.ref_frame7.post_tx_power_index=0xff + +ant3.ch9.ref_frame0.tx_power_index=08:08:08:08 +ant3.ch9.ref_frame0.post_tx_power_index=0xff +ant3.ch9.ref_frame1.tx_power_index=08:08:08:08 +ant3.ch9.ref_frame1.post_tx_power_index=0xff +ant3.ch9.ref_frame2.tx_power_index=08:08:08:08 +ant3.ch9.ref_frame2.post_tx_power_index=0xff +ant3.ch9.ref_frame3.tx_power_index=08:08:08:08 +ant3.ch9.ref_frame3.post_tx_power_index=0xff +ant3.ch9.ref_frame4.tx_power_index=08:08:08:08 +ant3.ch9.ref_frame4.post_tx_power_index=0xff +ant3.ch9.ref_frame5.tx_power_index=08:08:08:08 +ant3.ch9.ref_frame5.post_tx_power_index=0xff +ant3.ch9.ref_frame6.tx_power_index=08:08:08:08 +ant3.ch9.ref_frame6.post_tx_power_index=0xff +ant3.ch9.ref_frame7.tx_power_index=08:08:08:08 +ant3.ch9.ref_frame7.post_tx_power_index=0xff + + +restricted_channels=0x0000 +alternate_pulse_shape=0x00 diff --git a/uwb/calibration-FCC.conf b/uwb/calibration-FCC.conf new file mode 100644 index 0000000..616f91e --- /dev/null +++ b/uwb/calibration-FCC.conf @@ -0,0 +1,73 @@ +# FCC calibration file + +ant2.ch5.ref_frame0.tx_power_index=08:08:08:08 +ant2.ch5.ref_frame0.post_tx_power_index=0xff +ant2.ch5.ref_frame1.tx_power_index=08:08:08:08 +ant2.ch5.ref_frame1.post_tx_power_index=0xff +ant2.ch5.ref_frame2.tx_power_index=08:08:08:08 +ant2.ch5.ref_frame2.post_tx_power_index=0xff +ant2.ch5.ref_frame3.tx_power_index=08:08:08:08 +ant2.ch5.ref_frame3.post_tx_power_index=0xff +ant2.ch5.ref_frame4.tx_power_index=08:08:08:08 +ant2.ch5.ref_frame4.post_tx_power_index=0xff +ant2.ch5.ref_frame5.tx_power_index=08:08:08:08 +ant2.ch5.ref_frame5.post_tx_power_index=0xff +ant2.ch5.ref_frame6.tx_power_index=08:08:08:08 +ant2.ch5.ref_frame6.post_tx_power_index=0xff +ant2.ch5.ref_frame7.tx_power_index=08:08:08:08 +ant2.ch5.ref_frame7.post_tx_power_index=0xff + +ant2.ch9.ref_frame0.tx_power_index=08:08:08:08 +ant2.ch9.ref_frame0.post_tx_power_index=0xff +ant2.ch9.ref_frame1.tx_power_index=08:08:08:08 +ant2.ch9.ref_frame1.post_tx_power_index=0xff +ant2.ch9.ref_frame2.tx_power_index=08:08:08:08 +ant2.ch9.ref_frame2.post_tx_power_index=0xff +ant2.ch9.ref_frame3.tx_power_index=08:08:08:08 +ant2.ch9.ref_frame3.post_tx_power_index=0xff +ant2.ch9.ref_frame4.tx_power_index=08:08:08:08 +ant2.ch9.ref_frame4.post_tx_power_index=0xff +ant2.ch9.ref_frame5.tx_power_index=08:08:08:08 +ant2.ch9.ref_frame5.post_tx_power_index=0xff +ant2.ch9.ref_frame6.tx_power_index=08:08:08:08 +ant2.ch9.ref_frame6.post_tx_power_index=0xff +ant2.ch9.ref_frame7.tx_power_index=08:08:08:08 +ant2.ch9.ref_frame7.post_tx_power_index=0xff + +ant3.ch5.ref_frame0.tx_power_index=08:08:08:08 +ant3.ch5.ref_frame0.post_tx_power_index=0xff +ant3.ch5.ref_frame1.tx_power_index=08:08:08:08 +ant3.ch5.ref_frame1.post_tx_power_index=0xff +ant3.ch5.ref_frame2.tx_power_index=08:08:08:08 +ant3.ch5.ref_frame2.post_tx_power_index=0xff +ant3.ch5.ref_frame3.tx_power_index=08:08:08:08 +ant3.ch5.ref_frame3.post_tx_power_index=0xff +ant3.ch5.ref_frame4.tx_power_index=08:08:08:08 +ant3.ch5.ref_frame4.post_tx_power_index=0xff +ant3.ch5.ref_frame5.tx_power_index=08:08:08:08 +ant3.ch5.ref_frame5.post_tx_power_index=0xff +ant3.ch5.ref_frame6.tx_power_index=08:08:08:08 +ant3.ch5.ref_frame6.post_tx_power_index=0xff +ant3.ch5.ref_frame7.tx_power_index=08:08:08:08 +ant3.ch5.ref_frame7.post_tx_power_index=0xff + +ant3.ch9.ref_frame0.tx_power_index=08:08:08:08 +ant3.ch9.ref_frame0.post_tx_power_index=0xff +ant3.ch9.ref_frame1.tx_power_index=08:08:08:08 +ant3.ch9.ref_frame1.post_tx_power_index=0xff +ant3.ch9.ref_frame2.tx_power_index=08:08:08:08 +ant3.ch9.ref_frame2.post_tx_power_index=0xff +ant3.ch9.ref_frame3.tx_power_index=08:08:08:08 +ant3.ch9.ref_frame3.post_tx_power_index=0xff +ant3.ch9.ref_frame4.tx_power_index=08:08:08:08 +ant3.ch9.ref_frame4.post_tx_power_index=0xff +ant3.ch9.ref_frame5.tx_power_index=08:08:08:08 +ant3.ch9.ref_frame5.post_tx_power_index=0xff +ant3.ch9.ref_frame6.tx_power_index=08:08:08:08 +ant3.ch9.ref_frame6.post_tx_power_index=0xff +ant3.ch9.ref_frame7.tx_power_index=08:08:08:08 +ant3.ch9.ref_frame7.post_tx_power_index=0xff + + +restricted_channels=0x0000 +alternate_pulse_shape=0x00 diff --git a/uwb/calibration-JP.conf b/uwb/calibration-JP.conf new file mode 100644 index 0000000..c2ffed0 --- /dev/null +++ b/uwb/calibration-JP.conf @@ -0,0 +1,39 @@ +# JP calibration file + +ant2.ch9.ref_frame0.tx_power_index=08:08:08:08 +ant2.ch9.ref_frame0.post_tx_power_index=0xff +ant2.ch9.ref_frame1.tx_power_index=08:08:08:08 +ant2.ch9.ref_frame1.post_tx_power_index=0xff +ant2.ch9.ref_frame2.tx_power_index=08:08:08:08 +ant2.ch9.ref_frame2.post_tx_power_index=0xff +ant2.ch9.ref_frame3.tx_power_index=08:08:08:08 +ant2.ch9.ref_frame3.post_tx_power_index=0xff +ant2.ch9.ref_frame4.tx_power_index=08:08:08:08 +ant2.ch9.ref_frame4.post_tx_power_index=0xff +ant2.ch9.ref_frame5.tx_power_index=08:08:08:08 +ant2.ch9.ref_frame5.post_tx_power_index=0xff +ant2.ch9.ref_frame6.tx_power_index=08:08:08:08 +ant2.ch9.ref_frame6.post_tx_power_index=0xff +ant2.ch9.ref_frame7.tx_power_index=08:08:08:08 +ant2.ch9.ref_frame7.post_tx_power_index=0xff + +ant3.ch9.ref_frame0.tx_power_index=08:08:08:08 +ant3.ch9.ref_frame0.post_tx_power_index=0xff +ant3.ch9.ref_frame1.tx_power_index=08:08:08:08 +ant3.ch9.ref_frame1.post_tx_power_index=0xff +ant3.ch9.ref_frame2.tx_power_index=08:08:08:08 +ant3.ch9.ref_frame2.post_tx_power_index=0xff +ant3.ch9.ref_frame3.tx_power_index=08:08:08:08 +ant3.ch9.ref_frame3.post_tx_power_index=0xff +ant3.ch9.ref_frame4.tx_power_index=08:08:08:08 +ant3.ch9.ref_frame4.post_tx_power_index=0xff +ant3.ch9.ref_frame5.tx_power_index=08:08:08:08 +ant3.ch9.ref_frame5.post_tx_power_index=0xff +ant3.ch9.ref_frame6.tx_power_index=08:08:08:08 +ant3.ch9.ref_frame6.post_tx_power_index=0xff +ant3.ch9.ref_frame7.tx_power_index=08:08:08:08 +ant3.ch9.ref_frame7.post_tx_power_index=0xff + + +restricted_channels=0x0020 +alternate_pulse_shape=0x01 diff --git a/uwb/calibration-RESTRICTED.conf b/uwb/calibration-RESTRICTED.conf new file mode 100644 index 0000000..64363e5 --- /dev/null +++ b/uwb/calibration-RESTRICTED.conf @@ -0,0 +1,3 @@ +# RESTRICTED calibration file, UWB disabled + +restricted_channels=0xFFFF diff --git a/uwb/calibration-TW.conf b/uwb/calibration-TW.conf new file mode 100644 index 0000000..4036c35 --- /dev/null +++ b/uwb/calibration-TW.conf @@ -0,0 +1,39 @@ +# FCC calibration file + +ant2.ch9.ref_frame0.tx_power_index=08:08:08:08 +ant2.ch9.ref_frame0.post_tx_power_index=0xff +ant2.ch9.ref_frame1.tx_power_index=08:08:08:08 +ant2.ch9.ref_frame1.post_tx_power_index=0xff +ant2.ch9.ref_frame2.tx_power_index=08:08:08:08 +ant2.ch9.ref_frame2.post_tx_power_index=0xff +ant2.ch9.ref_frame3.tx_power_index=08:08:08:08 +ant2.ch9.ref_frame3.post_tx_power_index=0xff +ant2.ch9.ref_frame4.tx_power_index=08:08:08:08 +ant2.ch9.ref_frame4.post_tx_power_index=0xff +ant2.ch9.ref_frame5.tx_power_index=08:08:08:08 +ant2.ch9.ref_frame5.post_tx_power_index=0xff +ant2.ch9.ref_frame6.tx_power_index=08:08:08:08 +ant2.ch9.ref_frame6.post_tx_power_index=0xff +ant2.ch9.ref_frame7.tx_power_index=08:08:08:08 +ant2.ch9.ref_frame7.post_tx_power_index=0xff + +ant3.ch9.ref_frame0.tx_power_index=08:08:08:08 +ant3.ch9.ref_frame0.post_tx_power_index=0xff +ant3.ch9.ref_frame1.tx_power_index=08:08:08:08 +ant3.ch9.ref_frame1.post_tx_power_index=0xff +ant3.ch9.ref_frame2.tx_power_index=08:08:08:08 +ant3.ch9.ref_frame2.post_tx_power_index=0xff +ant3.ch9.ref_frame3.tx_power_index=08:08:08:08 +ant3.ch9.ref_frame3.post_tx_power_index=0xff +ant3.ch9.ref_frame4.tx_power_index=08:08:08:08 +ant3.ch9.ref_frame4.post_tx_power_index=0xff +ant3.ch9.ref_frame5.tx_power_index=08:08:08:08 +ant3.ch9.ref_frame5.post_tx_power_index=0xff +ant3.ch9.ref_frame6.tx_power_index=08:08:08:08 +ant3.ch9.ref_frame6.post_tx_power_index=0xff +ant3.ch9.ref_frame7.tx_power_index=08:08:08:08 +ant3.ch9.ref_frame7.post_tx_power_index=0xff + + +restricted_channels=0x0020 +alternate_pulse_shape=0x00 diff --git a/uwb/calibration-default.conf b/uwb/calibration-default.conf new file mode 100644 index 0000000..eb9d1af --- /dev/null +++ b/uwb/calibration-default.conf @@ -0,0 +1,72 @@ +# ROW (Rest Of World) calibration file + +ant2.ch5.ref_frame0.tx_power_index=08:08:08:08 +ant2.ch5.ref_frame0.post_tx_power_index=0xff +ant2.ch5.ref_frame1.tx_power_index=08:08:08:08 +ant2.ch5.ref_frame1.post_tx_power_index=0xff +ant2.ch5.ref_frame2.tx_power_index=08:08:08:08 +ant2.ch5.ref_frame2.post_tx_power_index=0xff +ant2.ch5.ref_frame3.tx_power_index=08:08:08:08 +ant2.ch5.ref_frame3.post_tx_power_index=0xff +ant2.ch5.ref_frame4.tx_power_index=08:08:08:08 +ant2.ch5.ref_frame4.post_tx_power_index=0xff +ant2.ch5.ref_frame5.tx_power_index=08:08:08:08 +ant2.ch5.ref_frame5.post_tx_power_index=0xff +ant2.ch5.ref_frame6.tx_power_index=08:08:08:08 +ant2.ch5.ref_frame6.post_tx_power_index=0xff +ant2.ch5.ref_frame7.tx_power_index=08:08:08:08 +ant2.ch5.ref_frame7.post_tx_power_index=0xff + +ant2.ch9.ref_frame0.tx_power_index=08:08:08:08 +ant2.ch9.ref_frame0.post_tx_power_index=0xff +ant2.ch9.ref_frame1.tx_power_index=08:08:08:08 +ant2.ch9.ref_frame1.post_tx_power_index=0xff +ant2.ch9.ref_frame2.tx_power_index=08:08:08:08 +ant2.ch9.ref_frame2.post_tx_power_index=0xff +ant2.ch9.ref_frame3.tx_power_index=08:08:08:08 +ant2.ch9.ref_frame3.post_tx_power_index=0xff +ant2.ch9.ref_frame4.tx_power_index=08:08:08:08 +ant2.ch9.ref_frame4.post_tx_power_index=0xff +ant2.ch9.ref_frame5.tx_power_index=08:08:08:08 +ant2.ch9.ref_frame5.post_tx_power_index=0xff +ant2.ch9.ref_frame6.tx_power_index=08:08:08:08 +ant2.ch9.ref_frame6.post_tx_power_index=0xff +ant2.ch9.ref_frame7.tx_power_index=08:08:08:08 +ant2.ch9.ref_frame7.post_tx_power_index=0xff + +ant3.ch5.ref_frame0.tx_power_index=08:08:08:08 +ant3.ch5.ref_frame0.post_tx_power_index=0xff +ant3.ch5.ref_frame1.tx_power_index=08:08:08:08 +ant3.ch5.ref_frame1.post_tx_power_index=0xff +ant3.ch5.ref_frame2.tx_power_index=08:08:08:08 +ant3.ch5.ref_frame2.post_tx_power_index=0xff +ant3.ch5.ref_frame3.tx_power_index=08:08:08:08 +ant3.ch5.ref_frame3.post_tx_power_index=0xff +ant3.ch5.ref_frame4.tx_power_index=08:08:08:08 +ant3.ch5.ref_frame4.post_tx_power_index=0xff +ant3.ch5.ref_frame5.tx_power_index=08:08:08:08 +ant3.ch5.ref_frame5.post_tx_power_index=0xff +ant3.ch5.ref_frame6.tx_power_index=08:08:08:08 +ant3.ch5.ref_frame6.post_tx_power_index=0xff +ant3.ch5.ref_frame7.tx_power_index=08:08:08:08 +ant3.ch5.ref_frame7.post_tx_power_index=0xff + +ant3.ch9.ref_frame0.tx_power_index=08:08:08:08 +ant3.ch9.ref_frame0.post_tx_power_index=0xff +ant3.ch9.ref_frame1.tx_power_index=08:08:08:08 +ant3.ch9.ref_frame1.post_tx_power_index=0xff +ant3.ch9.ref_frame2.tx_power_index=08:08:08:08 +ant3.ch9.ref_frame2.post_tx_power_index=0xff +ant3.ch9.ref_frame3.tx_power_index=08:08:08:08 +ant3.ch9.ref_frame3.post_tx_power_index=0xff +ant3.ch9.ref_frame4.tx_power_index=08:08:08:08 +ant3.ch9.ref_frame4.post_tx_power_index=0xff +ant3.ch9.ref_frame5.tx_power_index=08:08:08:08 +ant3.ch9.ref_frame5.post_tx_power_index=0xff +ant3.ch9.ref_frame6.tx_power_index=08:08:08:08 +ant3.ch9.ref_frame6.post_tx_power_index=0xff +ant3.ch9.ref_frame7.tx_power_index=08:08:08:08 +ant3.ch9.ref_frame7.post_tx_power_index=0xff + +restricted_channels=0x0000 +alternate_pulse_shape=0x00 diff --git a/uwb/calibration.conf b/uwb/calibration.conf new file mode 100644 index 0000000..df67d0c --- /dev/null +++ b/uwb/calibration.conf @@ -0,0 +1,33 @@ +# common calibration file +ant0.ch5.ant_delay=10:40:00:00 +ant0.ch9.ant_delay=10:40:00:00 + +ant1.ch5.ant_delay=10:40:00:00 +ant1.ch9.ant_delay=10:40:00:00 + +ant2.ch5.ant_delay=10:40:00:00 +ant2.ch9.ant_delay=10:40:00:00 + +ant3.ch5.ant_delay=10:40:00:00 +ant3.ch9.ant_delay=10:40:00:00 + +ant_grp1.ch5.pdoa.axisx.offset=00:00 +ant_grp1.ch9.pdoa.axisx.offset=00:00 + +xtal_trim=0x30 + +# Increase TX power of 0.25 dB +# ant0.ch5.pa_gain_offset=0x01 +# ant0.ch9.pa_gain_offset=0x01 + +# Decrease TX power of -0.25 dB +# ant1.ch5.pa_gain_offset=0xFF +# ant1.ch9.pa_gain_offset=0xFF + +# Increase TX power of 0.25 dB +# ant2.ch5.pa_gain_offset=0x01 +# ant2.ch9.pa_gain_offset=0x01 + +# Decrease TX power of -0.25 dB +# ant3.ch5.pa_gain_offset=0xFF +# ant3.ch9.pa_gain_offset=0xFF diff --git a/uwb/configuration.conf b/uwb/configuration.conf new file mode 100644 index 0000000..aabf5f0 --- /dev/null +++ b/uwb/configuration.conf @@ -0,0 +1,146 @@ +[FIRA]ant_sets.ch5.range.rx_ant_set_nonranging = 2 +[FIRA]ant_sets.ch5.range.rx_ant_set_ranging = 2 +[FIRA]ant_sets.ch5.range.tx_ant_set_nonranging = 2 +[FIRA]ant_sets.ch5.range.tx_ant_set_ranging = 2 +[FIRA]ant_sets.ch9.range.rx_ant_set_nonranging = 2 +[FIRA]ant_sets.ch9.range.rx_ant_set_ranging = 2 +[FIRA]ant_sets.ch9.range.tx_ant_set_nonranging = 2 +[FIRA]ant_sets.ch9.range.tx_ant_set_ranging = 2 +[FIRA]ant_sets.ch5.azimuth.rx_ant_set_nonranging = 1 +[FIRA]ant_sets.ch5.azimuth.rx_ant_set_ranging = 1 +[FIRA]ant_sets.ch5.azimuth.tx_ant_set_nonranging = 3 +[FIRA]ant_sets.ch5.azimuth.tx_ant_set_ranging = 3 +[FIRA]ant_sets.ch9.azimuth.rx_ant_set_nonranging = 1 +[FIRA]ant_sets.ch9.azimuth.rx_ant_set_ranging = 1 +[FIRA]ant_sets.ch9.azimuth.tx_ant_set_nonranging = 3 +[FIRA]ant_sets.ch9.azimuth.tx_ant_set_ranging = 3 +[FIRA]ant_sets.ch5.azimuth_elevation.rx_ant_set_nonranging = 1 +[FIRA]ant_sets.ch5.azimuth_elevation.rx_ant_set_ranging_azimuth = 1 +[FIRA]ant_sets.ch5.azimuth_elevation.rx_ant_set_ranging_elevation = 0 +[FIRA]ant_sets.ch5.azimuth_elevation.tx_ant_set_nonranging = 3 +[FIRA]ant_sets.ch5.azimuth_elevation.tx_ant_set_ranging = 3 +[FIRA]ant_sets.ch9.azimuth_elevation.rx_ant_set_nonranging = 1 +[FIRA]ant_sets.ch9.azimuth_elevation.rx_ant_set_ranging_azimuth = 1 +[FIRA]ant_sets.ch9.azimuth_elevation.rx_ant_set_ranging_elevation = 0 +[FIRA]ant_sets.ch9.azimuth_elevation.tx_ant_set_nonranging = 3 +[FIRA]ant_sets.ch9.azimuth_elevation.tx_ant_set_ranging = 3 + +[CCC]ant_sets.ch5.range.rx_ant_set_nonranging = 2 +[CCC]ant_sets.ch5.range.rx_ant_set_ranging = 2 +[CCC]ant_sets.ch5.range.tx_ant_set_nonranging = 2 +[CCC]ant_sets.ch5.range.tx_ant_set_ranging = 2 +[CCC]ant_sets.ch9.range.rx_ant_set_nonranging = 2 +[CCC]ant_sets.ch9.range.rx_ant_set_ranging = 2 +[CCC]ant_sets.ch9.range.tx_ant_set_nonranging = 2 +[CCC]ant_sets.ch9.range.tx_ant_set_ranging = 2 + +# Antenna Configuration +wifi_spdt=01 +ant0.config=03 +ant1.config=13 +ant2.config=02 +ant3.config=12 + +# Dual Rx (for Tx ANT3) +ant_grp0.rf_config.rfoff=00 +ant_grp0.rf_config.tx=03 +ant_grp0.rf_config.tx_aoa=03 +ant_grp0.rf_config.rx_ip=0e +ant_grp0.rf_config.rx_sts0=0e +ant_grp0.rf_config.rx_sts1=0e +ant_grp0.rf_config.rx_sts2=0e +ant_grp0.rf_config.rx_sts3=0e +ant_grp0.ext_sw_config=00 +ant_grp0.lna_rxa=01 +ant_grp0.lna_rxb=01 +ant_grp0.rx_config=04 +ant_grp0.pdoa_segments=02:07:00:00:00:00 +ant_grp0.pdoa_type=01:00:00 +ant_grp0.tx_power_control=00 +ant_grp0.ch5.pdoa.axisx.lut_id=00 +ant_grp0.ch9.pdoa.axisy.lut_id=01 + +# Dual Rx (for Tx ANT3) +ant_grp1.rf_config.rfoff=00 +ant_grp1.rf_config.tx=03 +ant_grp1.rf_config.tx_aoa=03 +ant_grp1.rf_config.rx_ip=0e +ant_grp1.rf_config.rx_sts0=0e +ant_grp1.rf_config.rx_sts1=0e +ant_grp1.rf_config.rx_sts2=0e +ant_grp1.rf_config.rx_sts3=0e +ant_grp1.ext_sw_config=00 +ant_grp1.lna_rxa=01 +ant_grp1.lna_rxb=01 +ant_grp1.rx_config=04 +ant_grp1.pdoa_segments=02:07:00:00:00:00 +ant_grp1.pdoa_type=00:00:00 +ant_grp1.tx_power_control=00 +ant_grp1.ch5.pdoa.axisx.lut_id=00 +ant_grp1.ch9.pdoa.axisy.lut_id=01 + +# Tx ANT2, Dual Rx (for Tx ANT2) +ant_grp2.rf_config.rfoff=00 +ant_grp2.rf_config.tx=03 +ant_grp2.rf_config.tx_aoa=03 +ant_grp2.rf_config.rx_ip=0e +ant_grp2.rf_config.rx_sts0=0e +ant_grp2.rf_config.rx_sts1=0e +ant_grp2.rf_config.rx_sts2=0e +ant_grp2.rf_config.rx_sts3=0e +ant_grp2.ext_sw_config=00 +ant_grp2.lna_rxa=01 +ant_grp2.lna_rxb=01 +ant_grp2.rx_config=05 +ant_grp2.pdoa_segments=02:07:00:00:00:00 +ant_grp2.pdoa_type=00:00:00 +ant_grp2.tx_power_control=00 + +# Tx ANT3, Dual Rx (for Tx ANT3) +ant_grp3.rf_config.rfoff=00 +ant_grp3.rf_config.tx=03 +ant_grp3.rf_config.tx_aoa=03 +ant_grp3.rf_config.rx_ip=0e +ant_grp3.rf_config.rx_sts0=0e +ant_grp3.rf_config.rx_sts1=0e +ant_grp3.rf_config.rx_sts2=0e +ant_grp3.rf_config.rx_sts3=0e +ant_grp3.ext_sw_config=01 +ant_grp3.lna_rxa=01 +ant_grp3.lna_rxb=01 +ant_grp3.rx_config=05 +ant_grp3.pdoa_segments=02:07:00:00:00:00 +ant_grp3.pdoa_type=00:00:00 +ant_grp3.tx_power_control=00 + +pdoa_lut0.data=de:e6:6f:f3:8b:e8:6f:f3:38:ea:6f:f3:e5:eb:6f:f3:92:ed:6f:f3:3f:ef:72:f6:ec:f0:11:f8:99:f2:4a:f9:45:f4:54:fa:f2:f5:44:fb:9f:f7:22:fc:4c:f9:f3:fc:f9:fa:bd:fd:a6:fc:81:fe:53:fe:41:ff:00:00:00:00:ad:01:bf:00:5a:03:7f:01:07:05:43:02:b4:06:0d:03:61:08:de:03:0e:0a:bc:04:bb:0b:ac:05:67:0d:b6:06:14:0f:ef:07:c1:10:8e:09:6e:12:91:0c:1b:14:91:0c:c8:15:91:0c:75:17:91:0c:22:19:91:0c +pdoa_lut1.data=de:e6:6f:f3:8b:e8:6f:f3:38:ea:6f:f3:e5:eb:6f:f3:92:ed:6f:f3:3f:ef:6f:f3:ec:f0:6f:f3:99:f2:6d:f6:45:f4:63:f8:f2:f5:d1:f9:9f:f7:08:fb:4c:f9:21:fc:f9:fa:26:fd:a6:fc:1f:fe:53:fe:11:ff:00:00:00:00:ad:01:ef:00:5a:03:e1:01:07:05:da:02:b4:06:df:03:61:08:f8:04:0e:0a:2f:06:bb:0b:9d:07:67:0d:93:09:14:0f:91:0c:c1:10:91:0c:6e:12:91:0c:1b:14:91:0c:c8:15:91:0c:75:17:91:0c:22:19:91:0c + +# Reference frames definition +ref_frame0.phy_cfg=44:21:07 # BPRF SET 3 +ref_frame0.payload_size=0x007f + +ref_frame1.phy_cfg=25:25:03 # HPRF SET 16 +ref_frame1.payload_size=0x0C68 + +ref_frame2.phy_cfg=44:31:07 # BPRF DRBM_HP SP1 +ref_frame2.payload_size=0x007f + +ref_frame3.phy_cfg=44:22:07 # BPRF SET 4 +ref_frame3.payload_size=0x0000 + +ref_frame4.phy_cfg=25:24:03 # HPRF DRHM_LR CL3 SP1 +ref_frame4.payload_size=0x0C68 + +ref_frame5.phy_cfg=25:2c:03 # HPRF DRHM_LR CL7 SP1 +ref_frame5.payload_size=0x0C68 + +ref_frame6.phy_cfg=25:2d:03 # HPRF DRHM_HR CL7 +ref_frame6.payload_size=0x0C68 + +ref_frame7.phy_cfg=45:22:07 # HPRF SET 24 +ref_frame7.payload_size=0x0000 + +# Post tones +post_tx.pattern_data=DD:DD:DD:DD:77:77:77:77 +post_tx.pattern_repetitions=0x0000 diff --git a/uwb/uwb_calibration.mk b/uwb/uwb_calibration.mk new file mode 100644 index 0000000..09c4f13 --- /dev/null +++ b/uwb/uwb_calibration.mk @@ -0,0 +1,24 @@ +# +# Copyright (C) 2021 The Android Open-Source Project +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +PRODUCT_PACKAGES += \ + configuration.conf \ + calibration.conf \ + calibration-default.conf \ + calibration-CE.conf \ + calibration-FCC.conf \ + calibration-JP.conf \ + calibration-TW.conf \ + calibration-RESTRICTED.conf diff --git a/wifi/BoardConfig-wifi.mk b/wifi/BoardConfig-wifi.mk new file mode 100644 index 0000000..7011ccf --- /dev/null +++ b/wifi/BoardConfig-wifi.mk @@ -0,0 +1,40 @@ +# +# Copyright (C) 2021 The Android Open-Source Project +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +# WiFi +BOARD_WLAN_DEVICE := bcmdhd +BOARD_WPA_SUPPLICANT_PRIVATE_LIB := lib_driver_cmd_bcmdhd +BOARD_HOSTAPD_PRIVATE_LIB := lib_driver_cmd_bcmdhd +WPA_SUPPLICANT_VERSION := VER_0_8_X +BOARD_WPA_SUPPLICANT_DRIVER := NL80211 +BOARD_HOSTAPD_DRIVER := NL80211 +# Wifi interface combination - {1 STA + 1 AP} or {1 STA + 1 AP_BRIDGED} or {1 STA + 1 P2P} +# or {1 STA + 1 NAN} or {2 STA} +WIFI_HAL_INTERFACE_COMBINATIONS := {{{STA}, 1}, {{P2P, NAN, AP, AP_BRIDGED}, 1}}, {{{STA}, 2}} +WIFI_FEATURE_WIFI_EXT_HAL := true +WIFI_FEATURE_IMU_DETECTION := true +# Avoid Wifi reset on MAC Address change +WIFI_AVOID_IFACE_RESET_MAC_CHANGE := true +WIFI_FEATURE_HOSTAPD_11AX := true +BOARD_HOSTAPD_CONFIG_80211W_MFP_OPTIONAL := true +WIFI_HIDL_UNIFIED_SUPPLICANT_SERVICE_RC_ENTRY := true + +PRODUCT_COPY_FILES += \ + device/google/tegu/wifi/p2p_supplicant_overlay.conf:$(TARGET_COPY_OUT_VENDOR)/etc/wifi/p2p_supplicant_overlay.conf \ + device/google/tegu/wifi/wpa_supplicant_overlay.conf:$(TARGET_COPY_OUT_VENDOR)/etc/wifi/wpa_supplicant_overlay.conf + +# Add WIFI_FEATURE_IMU_DETECTION to soong_config +$(call soong_config_set,wifi,feature_imu_detection,$(WIFI_FEATURE_IMU_DETECTION)) diff --git a/wifi/p2p_supplicant_overlay.conf b/wifi/p2p_supplicant_overlay.conf new file mode 100644 index 0000000..4ec8453 --- /dev/null +++ b/wifi/p2p_supplicant_overlay.conf @@ -0,0 +1,10 @@ +driver_param=use_p2p_group_interface=1p2p_device=1 +update_config=1 +eapol_version=1 +ap_scan=1 +fast_reauth=1 +pmf=1 +p2p_add_cli_chan=1 +disable_scan_offload=1 +p2p_go_vht=1 +p2p_pref_chan=124:149, 115:36 diff --git a/wifi/wpa_supplicant_overlay.conf b/wifi/wpa_supplicant_overlay.conf new file mode 100644 index 0000000..6f274c1 --- /dev/null +++ b/wifi/wpa_supplicant_overlay.conf @@ -0,0 +1,10 @@ +sae_pwe=2 +driver_param=use_p2p_group_interface=1p2p_device=1 +disable_scan_offload=1 +wowlan_triggers=any +bss_max_count=512 +interworking=1 +hs20=1 +auto_interworking=0 +bss_no_flush_when_down=1 +btm_offload=1