From 07a98e0fd5e46d10b25d5d593088ba7d00296883 Mon Sep 17 00:00:00 2001 From: Sophia Wang Date: Fri, 12 May 2023 15:42:21 -0700 Subject: [PATCH] Zuma:conf Add dsulat CPU idle awareness settings Test: cat /sys/class/devfreq/gs_dsulat_devfreq:devfreq_dsu_lat@17000090/dsu_latency/dsulat_cpuidle_state_aware Bug: 282103584 Change-Id: I78f0c2b69c93e482271241c2c801c0cf74018b76 Merged-In: I78f0c2b69c93e482271241c2c801c0cf74018b76 Signed-off-by: Sophia Wang --- conf/init.zuma.rc | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/conf/init.zuma.rc b/conf/init.zuma.rc index 508937ee..8b5bb422 100644 --- a/conf/init.zuma.rc +++ b/conf/init.zuma.rc @@ -350,6 +350,11 @@ on init write /sys/class/devfreq/gs_dsulat_devfreq:devfreq_dsu_lat@17000090/dsu_latency/ratio_ceil_cl1 1000 write /sys/class/devfreq/gs_dsulat_devfreq:devfreq_dsu_lat@17000090/dsu_latency/ratio_ceil_cl2 3000 + # Add dsulat governor settings + write /sys/class/devfreq/gs_dsulat_devfreq:devfreq_dsu_lat@17000090/dsu_latency/dsulat_cpuidle_state_aware_cl0 2 + write /sys/class/devfreq/gs_dsulat_devfreq:devfreq_dsu_lat@17000090/dsu_latency/dsulat_cpuidle_state_aware_cl1 2 + write /sys/class/devfreq/gs_dsulat_devfreq:devfreq_dsu_lat@17000090/dsu_latency/dsulat_cpuidle_state_aware_cl2 2 + # Give pixelstats group access to PCIe link statistics counters chown system system /sys/devices/platform/12100000.pcie/link_stats/complete_timeout_irqs chown system system /sys/devices/platform/12100000.pcie/link_stats/link_down_irqs