From 25367cdaadc1d76fcf7e32081c4c3422bace677b Mon Sep 17 00:00:00 2001 From: Ziyi Cui Date: Wed, 24 May 2023 21:20:43 +0000 Subject: [PATCH] init: fine tune dsulat parameter mem_stall_floor Bug: 279519442 Change-Id: I513e5f51928c089e2962c42670f1608f44cc1b56 Signed-off-by: Ziyi Cui --- conf/init.zuma.rc | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/conf/init.zuma.rc b/conf/init.zuma.rc index e01c79a3..a671d7c5 100644 --- a/conf/init.zuma.rc +++ b/conf/init.zuma.rc @@ -350,7 +350,10 @@ on init write /sys/class/devfreq/gs_dsulat_devfreq:devfreq_dsu_lat@17000090/dsu_latency/ratio_ceil_cl1 1000 write /sys/class/devfreq/gs_dsulat_devfreq:devfreq_dsu_lat@17000090/dsu_latency/ratio_ceil_cl2 3000 - # Add dsulat governor settings + write /sys/class/devfreq/gs_dsulat_devfreq:devfreq_dsu_lat@17000090/dsu_latency/mem_stall_floor_cl0 1750 + write /sys/class/devfreq/gs_dsulat_devfreq:devfreq_dsu_lat@17000090/dsu_latency/mem_stall_floor_cl1 1750 + write /sys/class/devfreq/gs_dsulat_devfreq:devfreq_dsu_lat@17000090/dsu_latency/mem_stall_floor_cl2 1750 + write /sys/class/devfreq/gs_dsulat_devfreq:devfreq_dsu_lat@17000090/dsu_latency/dsulat_cpuidle_state_aware_cl0 2 write /sys/class/devfreq/gs_dsulat_devfreq:devfreq_dsu_lat@17000090/dsu_latency/dsulat_cpuidle_state_aware_cl1 2 write /sys/class/devfreq/gs_dsulat_devfreq:devfreq_dsu_lat@17000090/dsu_latency/dsulat_cpuidle_state_aware_cl2 2