From fadc2aeb42c01c853a78d65a36e09fb505ad0b86 Mon Sep 17 00:00:00 2001 From: Sayanna Chandula Date: Wed, 22 Feb 2023 12:58:22 -0800 Subject: [PATCH] thermal: set dfs clock divider to 8 Increase the DFS clock divider to avoid thermal reset. Disable CPU cluster power down during clock settings. Bug: 268768104 Test: Build and boot on device. Check with geek bench test Change-Id: Ic4b959a7db0c5e903d617531d449b08cc5c81d0a Signed-off-by: Sayanna Chandula --- conf/init.zuma.rc | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/conf/init.zuma.rc b/conf/init.zuma.rc index 836eadee..a8829ef5 100644 --- a/conf/init.zuma.rc +++ b/conf/init.zuma.rc @@ -896,13 +896,15 @@ on post-fs-data on property:vendor.thermal.link_ready=1 # BCL - write /sys/devices/virtual/pmic/mitigation/clock_ratio/tpu_light_clk_ratio 0xfff041c1 #DFS - write /sys/devices/virtual/pmic/mitigation/clock_ratio/cpu1_heavy_clk_ratio 0xfff041c1 #DFS - write /sys/devices/virtual/pmic/mitigation/clock_ratio/cpu2_heavy_clk_ratio 0xfff041c1 #DFS - write /sys/devices/virtual/pmic/mitigation/clock_ratio/gpu_light_clk_ratio 0xfff041c1 #DFS + write /sys/devices/platform/cpupm/cpupm/cpd_cl1 0 #Disable power down + write /sys/devices/platform/cpupm/cpupm/cpd_cl2 0 #Disable power down + write /sys/devices/virtual/pmic/mitigation/clock_ratio/tpu_light_clk_ratio 0xfff041c1 #OCP + write /sys/devices/virtual/pmic/mitigation/clock_ratio/cpu1_heavy_clk_ratio 0xfff041c0 #DFS + write /sys/devices/virtual/pmic/mitigation/clock_ratio/cpu2_heavy_clk_ratio 0xfff041c0 #DFS + write /sys/devices/virtual/pmic/mitigation/clock_ratio/gpu_light_clk_ratio 0xfff041c1 #OCP write /sys/devices/virtual/pmic/mitigation/clock_ratio/cpu2_light_clk_ratio 0xfff041c3 #OCP - write /sys/devices/virtual/pmic/mitigation/clock_ratio/gpu_heavy_clk_ratio 0xfff04385 #OCP - write /sys/devices/virtual/pmic/mitigation/clock_ratio/tpu_heavy_clk_ratio 0xfff041c3 #OCP + write /sys/devices/virtual/pmic/mitigation/clock_ratio/gpu_heavy_clk_ratio 0xfff04380 #DFS + write /sys/devices/virtual/pmic/mitigation/clock_ratio/tpu_heavy_clk_ratio 0xfff041c0 #DFS write /sys/devices/virtual/pmic/mitigation/triggered_lvl/smpl_lvl 3100 write /sys/devices/virtual/pmic/mitigation/triggered_lvl/soft_ocp_cpu2_lvl 12000 write /sys/devices/virtual/pmic/mitigation/triggered_lvl/soft_ocp_gpu_lvl 9000 @@ -910,6 +912,8 @@ on property:vendor.thermal.link_ready=1 write /sys/devices/virtual/pmic/mitigation/clock_div/tpu_clk_div 0x1 write /sys/devices/virtual/pmic/mitigation/clock_div/gpu_clk_div 0x1 write /sys/devices/virtual/pmic/mitigation/clock_div/cpu2_clk_div 0x1 + write /sys/devices/platform/cpupm/cpupm/cpd_cl1 1 #Enable power down + write /sys/devices/platform/cpupm/cpupm/cpd_cl2 1 #Enable power down chown system system /dev/thermal/tz-by-name/soc/mode chown system system /dev/thermal/tz-by-name/vdroop2/trip_point_0_temp chown system system /dev/thermal/tz-by-name/vdroop2/trip_point_0_hyst