Evolution-X-Tensor/device_google_zumapro
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bcl: update heavy gpu and heavy tpu mitigation

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For tuning gpu and tpu heavy mitigation, update divider to /4 instead of
/8. For triggering level, update TPU to 13.5A from 12A and update GPU
from 8A to 9A.

Bug: 315520392
Bug: 315519863
Bug: 315522696
Test: build and readback changes
Change-Id: If0b459ccc071ee9d25884e0c830b829f12eca314
Signed-off-by: Hiroshi Akiyama <hiroshiakiyama@google.com>
This commit is contained in:
Hiroshi Akiyama 2023-12-11 19:21:32 +00:00
parent 17b40f0246
commit 5404418614
1 changed files with 4 additions and 2 deletions
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6
conf/init.zumapro.rc
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@ -936,12 +936,14 @@ on property:vendor.thermal.link_ready=1
write /sys/devices/virtual/pmic/mitigation/clock_ratio/cpu2_heavy_clk_ratio 0xfff041c0 #DFS write /sys/devices/virtual/pmic/mitigation/clock_ratio/cpu2_heavy_clk_ratio 0xfff041c0 #DFS
write /sys/devices/virtual/pmic/mitigation/clock_ratio/gpu_light_clk_ratio 0xfff041c1 #OCP write /sys/devices/virtual/pmic/mitigation/clock_ratio/gpu_light_clk_ratio 0xfff041c1 #OCP
write /sys/devices/virtual/pmic/mitigation/clock_ratio/cpu2_light_clk_ratio 0xfff041c3 #OCP write /sys/devices/virtual/pmic/mitigation/clock_ratio/cpu2_light_clk_ratio 0xfff041c3 #OCP
write /sys/devices/virtual/pmic/mitigation/clock_ratio/gpu_heavy_clk_ratio 0xfff04380 #DFS write /sys/devices/virtual/pmic/mitigation/clock_ratio/gpu_heavy_clk_ratio 0xfff04381 #DFS
write /sys/devices/virtual/pmic/mitigation/clock_ratio/tpu_heavy_clk_ratio 0xfff041c0 #DFS write /sys/devices/virtual/pmic/mitigation/clock_ratio/tpu_heavy_clk_ratio 0xfff041c1 #DFS
write /sys/devices/virtual/pmic/mitigation/triggered_lvl/smpl_lvl 3000 write /sys/devices/virtual/pmic/mitigation/triggered_lvl/smpl_lvl 3000
write /sys/devices/virtual/pmic/mitigation/triggered_lvl/soft_ocp_cpu2_lvl 12000 write /sys/devices/virtual/pmic/mitigation/triggered_lvl/soft_ocp_cpu2_lvl 12000
write /sys/devices/virtual/pmic/mitigation/triggered_lvl/soft_ocp_gpu_lvl 9000 write /sys/devices/virtual/pmic/mitigation/triggered_lvl/soft_ocp_gpu_lvl 9000
write /sys/devices/virtual/pmic/mitigation/triggered_lvl/soft_ocp_tpu_lvl 8500 write /sys/devices/virtual/pmic/mitigation/triggered_lvl/soft_ocp_tpu_lvl 8500
write /sys/devices/virtual/pmic/mitigation/triggered_lvl/ocp_tpu_lvl 13500
write /sys/devices/virtual/pmic/mitigation/triggered_lvl/ocp_gpu_lvl 9000
write /sys/devices/virtual/pmic/mitigation/clock_div/tpu_clk_div 0x1 write /sys/devices/virtual/pmic/mitigation/clock_div/tpu_clk_div 0x1
write /sys/devices/virtual/pmic/mitigation/clock_div/gpu_clk_div 0x1 write /sys/devices/virtual/pmic/mitigation/clock_div/gpu_clk_div 0x1
write /sys/devices/virtual/pmic/mitigation/clock_div/cpu2_clk_div 0x1 write /sys/devices/virtual/pmic/mitigation/clock_div/cpu2_clk_div 0x1