From d6fb8eead2283c8423b45103f278e8d3ca5eb311 Mon Sep 17 00:00:00 2001 From: Andhavarapu Karthik Date: Thu, 16 Feb 2023 14:01:37 +0530 Subject: [PATCH] disp: msm: sde: update qos cpu mask to avoid defective cores CPU qos_mask populated from devicetree can have defective cpu cores included. This change identifies and replaces the defective cores in the qos mask with the next possible working cpu cores. Change-Id: I0f32205e7f0abf0482d7dbbd288b7d7f3088726a Signed-off-by: Andhavarapu Karthik --- msm/sde/sde_hw_catalog.c | 45 +++++++++++++++++++++++++++++++++++----- 1 file changed, 40 insertions(+), 5 deletions(-) diff --git a/msm/sde/sde_hw_catalog.c b/msm/sde/sde_hw_catalog.c index f905d29c..f3d0085c 100644 --- a/msm/sde/sde_hw_catalog.c +++ b/msm/sde/sde_hw_catalog.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. */ @@ -4427,12 +4427,45 @@ static void _sde_perf_parse_dt_cfg_populate(struct sde_mdss_cfg *cfg, DEFAULT_AXI_BUS_WIDTH; } +/** + * _sde_set_possible_cpu_mask - checks defective cores in qos mask and update the + * mask to avoid defective cores and add next possible cores for pm qos vote. + * @qos_mask: qos_mask set from DT + */ +static int _sde_set_possible_cpu_mask(unsigned long qos_mask) +{ + int cpu = 0, defective_cores_count = 0; + struct cpumask *cpu_qos_mask = to_cpumask(&qos_mask); + unsigned long cpu_p_mask = cpu_possible_mask->bits[0]; + unsigned long cpu_defective_qos = qos_mask & (~cpu_p_mask); + + /* Count all the defective cores in cpu_defective_qos */ + defective_cores_count = cpumask_weight(to_cpumask(&cpu_defective_qos)); + + for_each_cpu(cpu, cpu_all_mask) { + if (cpu_possible(cpu) && !cpumask_test_cpu(cpu, cpu_qos_mask) && + defective_cores_count > 0) { + /* Set next possible cpu */ + cpumask_set_cpu(cpu, cpu_qos_mask); + defective_cores_count--; + } else if (cpumask_test_cpu(cpu, cpu_qos_mask) && !cpu_possible(cpu)) + /* Unset the defective core from qos mask */ + cpumask_clear_cpu(cpu, cpu_qos_mask); + } + + qos_mask = cpu_qos_mask->bits[0]; + return qos_mask; +} + + + static int _sde_perf_parse_dt_cfg(struct device_node *np, struct sde_mdss_cfg *cfg, int *prop_count, struct sde_prop_value *prop_value, bool *prop_exists) { int rc, j; const char *str = NULL; + unsigned long qos_mask = 0; /* * The following performance parameters (e.g. core_ib_ff) are @@ -4476,14 +4509,16 @@ static int _sde_perf_parse_dt_cfg(struct device_node *np, set_bit(SDE_FEATURE_CDP, cfg->features); } - cfg->perf.cpu_mask = - prop_exists[PERF_CPU_MASK] ? + qos_mask = prop_exists[PERF_CPU_MASK] ? PROP_VALUE_ACCESS(prop_value, PERF_CPU_MASK, 0) : DEFAULT_CPU_MASK; - cfg->perf.cpu_mask_perf = - prop_exists[CPU_MASK_PERF] ? + cfg->perf.cpu_mask = _sde_set_possible_cpu_mask(qos_mask); + + qos_mask = prop_exists[CPU_MASK_PERF] ? PROP_VALUE_ACCESS(prop_value, CPU_MASK_PERF, 0) : DEFAULT_CPU_MASK; + cfg->perf.cpu_mask_perf = _sde_set_possible_cpu_mask(qos_mask); + cfg->perf.cpu_dma_latency = prop_exists[PERF_CPU_DMA_LATENCY] ? PROP_VALUE_ACCESS(prop_value, PERF_CPU_DMA_LATENCY, 0) :