diff --git a/msm/dp/dp_ctrl.c b/msm/dp/dp_ctrl.c
index 58f14510..f3a403f8 100644
--- a/msm/dp/dp_ctrl.c
+++ b/msm/dp/dp_ctrl.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved.
  */
 
@@ -647,6 +647,9 @@ static void dp_ctrl_set_clock_rate(struct dp_ctrl_private *ctrl,
 	u32 num = ctrl->parser->mp[clk_type].num_clk;
 	struct dss_clk *cfg = ctrl->parser->mp[clk_type].clk_config;
 
+	/* convert to HZ for byte2 ops */
+	rate *= 1000;
+
 	while (num && strcmp(cfg->clk_name, name)) {
 		num--;
 		cfg++;
diff --git a/msm/dp/dp_pll_4nm.c b/msm/dp/dp_pll_4nm.c
index 46f15102..0f3dfb2e 100644
--- a/msm/dp/dp_pll_4nm.c
+++ b/msm/dp/dp_pll_4nm.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 /*
@@ -737,8 +737,7 @@ static unsigned long dp_pll_link_clk_recalc_rate(struct clk_hw *hw,
 	pll_link = to_dp_vco_hw(hw);
 	pll = pll_link->priv;
 
-	rate = pll->vco_rate;
-	rate = pll->vco_rate / 10;
+	rate = pll->vco_rate * 100;
 
 	return rate;
 }
@@ -757,7 +756,7 @@ static long dp_pll_link_clk_round(struct clk_hw *hw, unsigned long rate,
 	pll_link = to_dp_vco_hw(hw);
 	pll = pll_link->priv;
 
-	rate = pll->vco_rate / 10;
+	rate = pll->vco_rate * 100;
 
 	return rate;
 }
@@ -765,11 +764,11 @@ static long dp_pll_link_clk_round(struct clk_hw *hw, unsigned long rate,
 static unsigned long dp_pll_vco_div_clk_get_rate(struct dp_pll *pll)
 {
 	if (pll->vco_rate == DP_VCO_HSCLK_RATE_8100MHZDIV1000)
-		return (pll->vco_rate / 6);
+		return (pll->vco_rate / 6 * 1000);
 	else if (pll->vco_rate == DP_VCO_HSCLK_RATE_5400MHZDIV1000)
-		return (pll->vco_rate / 4);
+		return (pll->vco_rate / 4 * 1000);
 	else
-		return (pll->vco_rate / 2);
+		return (pll->vco_rate / 2 * 1000);
 }
 
 static unsigned long dp_pll_vco_div_clk_recalc_rate(struct clk_hw *hw,
diff --git a/msm/dp/dp_pll_5nm.c b/msm/dp/dp_pll_5nm.c
index 0af078d8..37899dd6 100644
--- a/msm/dp/dp_pll_5nm.c
+++ b/msm/dp/dp_pll_5nm.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  */
 
@@ -719,8 +719,7 @@ static unsigned long dp_pll_link_clk_recalc_rate(struct clk_hw *hw,
 	pll_link = to_dp_vco_hw(hw);
 	pll = pll_link->priv;
 
-	rate = pll->vco_rate;
-	rate = pll->vco_rate / 10;
+	rate = pll->vco_rate * 100;
 
 	return rate;
 }
@@ -739,7 +738,7 @@ static long dp_pll_link_clk_round(struct clk_hw *hw, unsigned long rate,
 	pll_link = to_dp_vco_hw(hw);
 	pll = pll_link->priv;
 
-	rate = pll->vco_rate / 10;
+	rate = pll->vco_rate * 100;
 
 	return rate;
 }
@@ -747,11 +746,11 @@ static long dp_pll_link_clk_round(struct clk_hw *hw, unsigned long rate,
 static unsigned long dp_pll_vco_div_clk_get_rate(struct dp_pll *pll)
 {
 	if (pll->vco_rate == DP_VCO_HSCLK_RATE_8100MHZDIV1000)
-		return (pll->vco_rate / 6);
+		return (pll->vco_rate / 6 * 1000);
 	else if (pll->vco_rate == DP_VCO_HSCLK_RATE_5400MHZDIV1000)
-		return (pll->vco_rate / 4);
+		return (pll->vco_rate / 4 * 1000);
 	else
-		return (pll->vco_rate / 2);
+		return (pll->vco_rate / 2 * 1000);
 }
 
 static unsigned long dp_pll_vco_div_clk_recalc_rate(struct clk_hw *hw,
diff --git a/msm/dp/dp_power.c b/msm/dp/dp_power.c
index de8ba05b..75f7001d 100644
--- a/msm/dp/dp_power.c
+++ b/msm/dp/dp_power.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2023, Qualcomm Innovation Center, Inc. All rights reserved.
  * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved.
  */
 
@@ -22,6 +22,8 @@ struct dp_power_private {
 	struct clk *pixel_parent;
 	struct clk *pixel1_clk_rcg;
 	struct clk *xo_clk;
+	struct clk *link_clk_rcg;
+	struct clk *link_parent;
 
 	struct dp_power dp_power;
 
@@ -245,6 +247,24 @@ static int dp_power_clk_init(struct dp_power_private *power, bool enable)
 				goto err_pixel1_clk_rcg;
 			}
 		}
+
+		power->link_clk_rcg = clk_get(dev, "link_clk_src");
+		if (IS_ERR(power->link_clk_rcg)) {
+			DP_DEBUG("Unable to get DP link clk RCG: %ld\n",
+					PTR_ERR(power->link_clk_rcg));
+			rc = PTR_ERR(power->link_clk_rcg);
+			power->link_clk_rcg = NULL;
+			goto err_link_clk_rcg;
+		}
+
+		power->link_parent = clk_get(dev, "link_parent");
+		if (IS_ERR(power->link_parent)) {
+			DP_DEBUG("Unable to get DP link parent: %ld\n",
+					PTR_ERR(power->link_parent));
+			rc = PTR_ERR(power->link_parent);
+			power->link_parent = NULL;
+			goto err_link_parent;
+		}
 	} else {
 		if (power->pixel1_clk_rcg)
 			clk_put(power->pixel1_clk_rcg);
@@ -255,10 +275,21 @@ static int dp_power_clk_init(struct dp_power_private *power, bool enable)
 		if (power->pixel_clk_rcg)
 			clk_put(power->pixel_clk_rcg);
 
+		if (power->link_parent)
+			clk_put(power->link_parent);
+
+		if (power->link_clk_rcg)
+			clk_put(power->link_clk_rcg);
+
 		dp_power_clk_put(power);
 	}
 
 	return rc;
+
+err_link_parent:
+	clk_put(power->link_clk_rcg);
+err_link_clk_rcg:
+	clk_put(power->pixel1_clk_rcg);
 err_pixel1_clk_rcg:
 	clk_put(power->xo_clk);
 err_xo_clk:
@@ -421,6 +452,14 @@ static int dp_power_clk_enable(struct dp_power *dp_power,
 		}
 	}
 
+	if (pm_type == DP_LINK_PM && enable && power->link_parent) {
+		rc = clk_set_parent(power->link_clk_rcg, power->link_parent);
+		if (rc) {
+			DP_ERR("failed to set link parent\n");
+			goto error;
+		}
+	}
+
 	rc = dp_power_clk_set_rate(power, pm_type, enable);
 	if (rc) {
 		DP_ERR("failed to '%s' clks for: %s. err=%d\n",