From 24aa389edcc365315b8b0ead4e582927960d2667 Mon Sep 17 00:00:00 2001 From: Jeykumar Sankaran Date: Mon, 30 Aug 2021 20:34:53 -0700 Subject: [PATCH] disp: msm: sde: separate out DSC 4HS config programming Dedicated registers are introduced for DSC 4HS merge block programming from MDSS.9.0. This change adds support in the driver to identify the change using a DSC feature flag and separates out 4HS merge block programming to use appropriate registers based on the DSC HW feature. Change-Id: Ia64a1ed4bc5f5f301ab422144916cdce2a1dadac Signed-off-by: Michael Ru Signed-off-by: Jeykumar Sankaran --- msm/sde/sde_hw_catalog.c | 3 ++- msm/sde/sde_hw_catalog.h | 2 ++ msm/sde/sde_hw_dsc_1_2.c | 45 +++++++++++++++++++++++++++++++++------- 3 files changed, 41 insertions(+), 9 deletions(-) diff --git a/msm/sde/sde_hw_catalog.c b/msm/sde/sde_hw_catalog.c index dae861c8..2a606a32 100644 --- a/msm/sde/sde_hw_catalog.c +++ b/msm/sde/sde_hw_catalog.c @@ -3295,7 +3295,8 @@ static int sde_dsc_parse_dt(struct device_node *np, if (PROP_VALUE_ACCESS(prop_value, DSC_422, i)) set_bit(SDE_DSC_NATIVE_422_EN, &dsc->features); - + if (SDE_HW_MAJOR(sde_cfg->hw_rev) >= SDE_HW_MAJOR(SDE_HW_VER_900)) + set_bit(SDE_DSC_4HS, &dsc->features); } else { set_bit(SDE_DSC_HW_REV_1_1, &dsc->features); } diff --git a/msm/sde/sde_hw_catalog.h b/msm/sde/sde_hw_catalog.h index 86f54685..8d6a2b5c 100644 --- a/msm/sde/sde_hw_catalog.h +++ b/msm/sde/sde_hw_catalog.h @@ -471,6 +471,7 @@ enum { * @SDE_DSC_NATIVE_422_EN, Supports native422 and native420 encoding * @SDE_DSC_ENC, DSC encoder sub block * @SDE_DSC_CTL, DSC ctl sub block + * @SDE_DSC_4HS, Dedicated DSC 4HS config registers * @SDE_DSC_MAX */ enum { @@ -480,6 +481,7 @@ enum { SDE_DSC_NATIVE_422_EN, SDE_DSC_ENC, SDE_DSC_CTL, + SDE_DSC_4HS, SDE_DSC_MAX }; diff --git a/msm/sde/sde_hw_dsc_1_2.c b/msm/sde/sde_hw_dsc_1_2.c index dee1efa3..b0aa994d 100644 --- a/msm/sde/sde_hw_dsc_1_2.c +++ b/msm/sde/sde_hw_dsc_1_2.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* + * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. */ @@ -55,7 +56,8 @@ #define DSC_CFG 0x04 #define DSC_DATA_IN_SWAP 0x08 #define DSC_CLK_CTRL 0x0C - +#define DSC_4HS_MERGE_EN 0x10 +#define DSC_4HS_MERGE_CFG 0x14 static int _dsc_calc_ob_max_addr(struct sde_hw_dsc *hw_dsc, int num_ss) { @@ -122,6 +124,36 @@ static void sde_hw_dsc_disable(struct sde_hw_dsc *hw_dsc) SDE_REG_WRITE(dsc_c, DSC_MAIN_CONF + idx, 0); } +static void sde_hw_dsc_4hs_config(struct sde_hw_dsc *hw_dsc, + struct msm_display_dsc_info *dsc, u32 mode, u32 idx) +{ + struct sde_hw_blk_reg_map *dsc_c; + u32 data = 0; + + if (!dsc->dsc_4hsmerge_en) + return; + + dsc_c = &hw_dsc->hw; + + if (test_bit(SDE_DSC_4HS, &hw_dsc->caps->features)) { + data = dsc->dsc_4hsmerge_alignment << 12; + data |= dsc->dsc_4hsmerge_padding << 8; + data |= ((mode & DSC_MODE_VIDEO) ? 1 : 0); + + SDE_REG_WRITE(dsc_c, DSC_4HS_MERGE_CFG + idx, data); + SDE_REG_WRITE(dsc_c, DSC_4HS_MERGE_EN + idx, BIT(0)); + } else { + data = SDE_REG_READ(dsc_c, DSC_CFG + idx); + + data |= dsc->dsc_4hsmerge_padding << 18; + data |= dsc->dsc_4hsmerge_alignment << 22; + data |= ((mode & DSC_MODE_VIDEO) ? 1 : 0) << 17; + data |= BIT(16); + + SDE_REG_WRITE(dsc_c, DSC_CFG + idx, data); + } +} + static void sde_hw_dsc_config(struct sde_hw_dsc *hw_dsc, struct msm_display_dsc_info *dsc, u32 mode, bool ich_reset_override) @@ -258,15 +290,12 @@ static void sde_hw_dsc_config(struct sde_hw_dsc *hw_dsc, data |= BIT(12); if (mode & DSC_MODE_MULTIPLEX) data |= BIT(13); - if (!(mode & DSC_MODE_VIDEO)) - data |= BIT(17); - if (dsc->dsc_4hsmerge_en) { - data |= dsc->dsc_4hsmerge_padding << 18; - data |= dsc->dsc_4hsmerge_alignment << 22; - data |= BIT(16); - } SDE_REG_WRITE(dsc_c, DSC_CFG + idx, data); + + wmb(); /* ensure the register is committed */ + + sde_hw_dsc_4hs_config(hw_dsc, dsc, mode, idx); } static void sde_hw_dsc_config_thresh(struct sde_hw_dsc *hw_dsc,