Merge ccedfd643a on remote branch

Change-Id: Ibc05d655d17bf432699d5fe1a888e0fda18ba917

msm/dp/dp_panel.c

@@ -1575,7 +1575,7 @@ static int dp_panel_dsc_prepare_basic_params(
 	comp_info->comp_type = MSM_DISPLAY_COMPRESSION_DSC;
 	comp_info->tgt_bpp = DSC_TGT_BPP;
 	comp_info->src_bpp = dp_mode->timing.bpp;
-	comp_info->comp_ratio = dp_mode->timing.bpp / DSC_TGT_BPP;
+	comp_info->comp_ratio = mult_frac(100, dp_mode->timing.bpp, DSC_TGT_BPP);
 	comp_info->enabled = true;
 
 	return 0;
@@ -3001,7 +3001,7 @@ static void dp_panel_convert_to_dp_mode(struct dp_panel *dp_panel,
 	comp_info->src_bpp = default_bpp;
 	comp_info->tgt_bpp = default_bpp;
 	comp_info->comp_type = MSM_DISPLAY_COMPRESSION_NONE;
-	comp_info->comp_ratio = 1;
+	comp_info->comp_ratio = MSM_DISPLAY_COMPRESSION_RATIO_NONE;
 	comp_info->enabled = false;
 
 	/* As YUV was not supported now, so set the default format to RGB */
@@ -3036,7 +3036,7 @@ static void dp_panel_convert_to_dp_mode(struct dp_panel *dp_panel,
 		}
 
 		rc = sde_dsc_populate_dsc_private_params(&comp_info->dsc_info,
-				dp_mode->timing.h_active);
+				dp_mode->timing.h_active, dp_mode->timing.widebus_en);
 		if (rc) {
 			DP_DEBUG("failed populating other dsc params\n");
 			return;

msm/dsi/dsi_ctrl_hw_cmn.c

@@ -567,7 +567,7 @@ void dsi_ctrl_hw_cmn_setup_cmd_stream(struct dsi_ctrl_hw *ctrl,
 		this_frame_slices = pic_width / dsc.config.slice_width;
 		intf_ip_w = this_frame_slices * dsc.config.slice_width;
 
-		sde_dsc_populate_dsc_private_params(&dsc, intf_ip_w);
+		sde_dsc_populate_dsc_private_params(&dsc, intf_ip_w, ctrl->widebus_support);
 
 		width_final = dsc.bytes_per_pkt * dsc.pkt_per_line;
 		stride_final = dsc.bytes_per_pkt;

msm/dsi/dsi_display.c

@@ -7090,27 +7090,27 @@ int dsi_display_get_modes_helper(struct dsi_display *display,
 
 		memset(&display_mode, 0, sizeof(display_mode));
 
+		display_mode.priv_info = kzalloc(sizeof(*display_mode.priv_info), GFP_KERNEL);
+		if (!display_mode.priv_info) {
+			rc = -ENOMEM;
+			return rc;
+		}
+
+		/* Setup widebus support */
+		display_mode.priv_info->widebus_support = ctrl->ctrl->hw.widebus_support;
+
 		rc = dsi_panel_get_mode(display->panel, mode_idx,
 						&display_mode,
 						topology_override);
 		if (rc) {
 			DSI_ERR("[%s] failed to get mode idx %d from panel\n",
 				   display->name, mode_idx);
+			kfree(display_mode.priv_info);
+			display_mode.priv_info = NULL;
 			rc = -EINVAL;
 			return rc;
 		}
 
-		/*
-		 * Update the host_config.dst_format for compressed RGB101010 pixel format.
-		 */
-		if (display->panel->host_config.dst_format == DSI_PIXEL_FORMAT_RGB101010 &&
-			display_mode.timing.dsc_enabled) {
-			display->panel->host_config.dst_format = DSI_PIXEL_FORMAT_RGB888;
-			DSI_DEBUG("updated dst_format from %d to %d\n",
-				DSI_PIXEL_FORMAT_RGB101010,
-				display->panel->host_config.dst_format);
-		}
-
 		if (display->cmdline_timing == display_mode.mode_idx) {
 			topology_override = display->cmdline_topology;
 			is_preferred = true;
@@ -7124,9 +7124,18 @@ int dsi_display_get_modes_helper(struct dsi_display *display,
 		else
 			nondsc_modes++;
 
-		/* Setup widebus support */
+		/*
-		display_mode.priv_info->widebus_support =
+		 * Update the host_config.dst_format for compressed RGB101010 pixel format
-				ctrl->ctrl->hw.widebus_support;
+		 * when there is no widebus support.
+		 */
+		if (host->dst_format == DSI_PIXEL_FORMAT_RGB101010 &&
+				display_mode.timing.dsc_enabled &&
+				!display_mode.priv_info->widebus_support) {
+			host->dst_format = DSI_PIXEL_FORMAT_RGB888;
+			DSI_DEBUG("updated dst_format from %d to %d\n",
+					DSI_PIXEL_FORMAT_RGB101010, host->dst_format);
+		}
+
 		num_dfps_rates = ((!dfps_caps.dfps_support ||
 			!support_video_mode) ? 1 : dfps_caps.dfps_list_len);
 

msm/dsi/dsi_drm.c

@@ -692,7 +692,7 @@ int dsi_conn_get_mode_info(struct drm_connector *connector,
 	if (mode_info->comp_info.comp_type) {
 		tar_bpp = dsi_mode->priv_info->pclk_scale.numer;
 		src_bpp = dsi_mode->priv_info->pclk_scale.denom;
-		mode_info->comp_info.comp_ratio = mult_frac(1, src_bpp,
+		mode_info->comp_info.comp_ratio = mult_frac(100, src_bpp,
 				tar_bpp);
 		mode_info->wide_bus_en = dsi_mode->priv_info->widebus_support;
 	}

msm/dsi/dsi_panel.c

@@ -2812,7 +2812,8 @@ static int dsi_panel_parse_dsc_params(struct dsi_display_mode *mode,
 		goto error;
 	}
 
-	rc = sde_dsc_populate_dsc_private_params(&priv_info->dsc, intf_width);
+	rc = sde_dsc_populate_dsc_private_params(&priv_info->dsc, intf_width,
+			priv_info->widebus_support);
 	if (rc) {
 		DSI_DEBUG("failed populating other dsc params\n");
 		rc = -EINVAL;
@@ -4173,12 +4174,6 @@ int dsi_panel_get_mode(struct dsi_panel *panel,
 	mutex_lock(&panel->panel_lock);
 	utils = &panel->utils;
 
-	mode->priv_info = kzalloc(sizeof(*mode->priv_info), GFP_KERNEL);
-	if (!mode->priv_info) {
-		rc = -ENOMEM;
-		goto done;
-	}
-
 	prv_info = mode->priv_info;
 
 	timings_np = utils->get_child_by_name(utils->data,
@@ -4272,12 +4267,8 @@ int dsi_panel_get_mode(struct dsi_panel *panel,
 		if (rc)
 			DSI_ERR("failed to partial update caps, rc=%d\n", rc);
 	}
-	goto done;
 
 parse_fail:
-	kfree(mode->priv_info);
-	mode->priv_info = NULL;
-done:
 	utils->data = utils_data;
 	mutex_unlock(&panel->panel_lock);
 	return rc;

msm/dsi/dsi_pll_4nm.c

@@ -123,23 +123,23 @@ static inline int dsi_pll_get_phy_post_div(struct dsi_pll_resource *pll)
 }
 
 
-static inline void dsi_pll_set_dsi_clk(struct dsi_pll_resource *pll, u32 dsi_clk)
+static inline void dsi_pll_set_dsiclk_sel(struct dsi_pll_resource *pll, u32 dsiclk_sel)
 {
 	u32 reg_val = 0;
 
 	reg_val = DSI_PLL_REG_R(pll->phy_base, PHY_CMN_CLK_CFG1);
 	reg_val &= ~0x3;
-	reg_val |= dsi_clk;
+	reg_val |= dsiclk_sel;
 	DSI_PLL_REG_W(pll->phy_base, PHY_CMN_CLK_CFG1, reg_val);
 	if (pll->slave) {
 		reg_val = DSI_PLL_REG_R(pll->slave->phy_base, PHY_CMN_CLK_CFG1);
 		reg_val &= ~0x3;
-		reg_val |= dsi_clk;
+		reg_val |= dsiclk_sel;
 		DSI_PLL_REG_W(pll->slave->phy_base, PHY_CMN_CLK_CFG1, reg_val);
 	}
 }
 
-static inline int dsi_pll_get_dsi_clk(struct dsi_pll_resource *pll)
+static inline int dsi_pll_get_dsiclk_sel(struct dsi_pll_resource *pll)
 {
 	u32 reg_val;
 
@@ -735,7 +735,7 @@ static unsigned long dsi_pll_pclk_recalc_rate(struct clk_hw *hw, unsigned long p
 	struct dsi_pll_resource *pll = NULL;
 	u64 vco_rate = 0;
 	u64 pclk_rate = 0;
-	u32 phy_post_div, pclk_div;
+	u32 phy_post_div, pclk_div, dsiclk_sel;
 
 	if (!pix_pll->priv) {
 		DSI_PLL_INFO(pll, "pll priv is null\n");
@@ -757,19 +757,22 @@ static unsigned long dsi_pll_pclk_recalc_rate(struct clk_hw *hw, unsigned long p
 
 	vco_rate = dsi_pll_vco_recalc_rate(pll);
 
-	if (pll->type == DSI_PHY_TYPE_DPHY) {
+	phy_post_div = dsi_pll_get_phy_post_div(pll);
-		phy_post_div = dsi_pll_get_phy_post_div(pll);
+	dsiclk_sel = dsi_pll_get_dsiclk_sel(pll);
+
+	if (dsiclk_sel == 0) {
+		pclk_rate = div_u64(vco_rate, phy_post_div);
+	} else if (dsiclk_sel == 1) {
 		pclk_rate = div_u64(vco_rate, phy_post_div);
 		pclk_rate = div_u64(pclk_rate, 2);
-		pclk_div = dsi_pll_get_pclk_div(pll);
+	} else if (dsiclk_sel == 3 && pll->type == DSI_PHY_TYPE_CPHY) {
-		pclk_rate = div_u64(pclk_rate, pclk_div);
-	} else {
 		pclk_rate = vco_rate * 2;
 		pclk_rate = div_u64(pclk_rate, 7);
-		pclk_div = dsi_pll_get_pclk_div(pll);
-		pclk_rate = div_u64(pclk_rate, pclk_div);
 	}
 
+	pclk_div = dsi_pll_get_pclk_div(pll);
+	pclk_rate = div_u64(pclk_rate, pclk_div);
+
 	return pclk_rate;
 }
 
@@ -982,7 +985,7 @@ static int dsi_pll_4nm_set_byteclk_div(struct dsi_pll_resource *pll, bool commit
 static int dsi_pll_calc_dphy_pclk_div(struct dsi_pll_resource *pll)
 {
 	u32 m_val, n_val; /* M and N values of MND trio */
-	u32 pclk_div;
+	u32 dsiclk_sel, pclk_div;
 
 	if (pll->bpp == 30 && pll->lanes == 4) {
 		/* RGB101010 */
@@ -1005,14 +1008,15 @@ static int dsi_pll_calc_dphy_pclk_div(struct dsi_pll_resource *pll)
 		n_val = 1;
 	}
 
-	/* Calculating pclk_div assuming dsiclk_sel to be 1 */
+	dsiclk_sel = dsi_pll_get_dsiclk_sel(pll);
 	pclk_div = pll->bpp;
 	pclk_div = mult_frac(pclk_div, m_val, n_val);
-	do_div(pclk_div, 2);
+	if (dsiclk_sel == 1)
+		do_div(pclk_div, 2);
 	do_div(pclk_div, pll->lanes);
 
-	DSI_PLL_DBG(pll, "bpp: %d, lanes: %d, m_val: %u, n_val: %u, pclk_div: %u\n",
+	DSI_PLL_DBG(pll, "bpp:%d lanes:%d m_val:%u n_val:%u dsiclk_sel:%u pclk_div: %u\n",
-                          pll->bpp, pll->lanes, m_val, n_val, pclk_div);
+			pll->bpp, pll->lanes, m_val, n_val, dsiclk_sel, pclk_div);
 
 	return pclk_div;
 }
@@ -1020,7 +1024,7 @@ static int dsi_pll_calc_dphy_pclk_div(struct dsi_pll_resource *pll)
 static int dsi_pll_calc_cphy_pclk_div(struct dsi_pll_resource *pll)
 {
 	u32 m_val, n_val; /* M and N values of MND trio */
-	u32 pclk_div;
+	u32 dsiclk_sel, pclk_div, num, den;
 	u32 phy_post_div = dsi_pll_get_phy_post_div(pll);
 
 	if (pll->bpp == 24 && pll->lanes == 2) {
@@ -1063,48 +1067,91 @@ static int dsi_pll_calc_cphy_pclk_div(struct dsi_pll_resource *pll)
 		n_val = 1;
 	}
 
-	/* Calculating pclk_div assuming dsiclk_sel to be 3 */
+	dsiclk_sel = dsi_pll_get_dsiclk_sel(pll);
-	pclk_div =  pll->bpp * phy_post_div;
+	num = m_val * pll->bpp;
-	pclk_div = mult_frac(pclk_div, m_val, n_val);
+	den = n_val * pll->lanes;
-	do_div(pclk_div, 8);
-	do_div(pclk_div, pll->lanes);
 
-	DSI_PLL_DBG(pll, "bpp: %d, lanes: %d, m_val: %u, n_val: %u, phy_post_div: %u pclk_div: %u\n",
+	if (dsiclk_sel == 3) {
-                          pll->bpp, pll->lanes, m_val, n_val, phy_post_div, pclk_div);
+		num *= phy_post_div;
+		den *= 8;
+	} else if (dsiclk_sel == 2) {
+		num *= (7 * phy_post_div);
+		den *= 16;
+	} else if (dsiclk_sel == 0) {
+		num *= 7;
+		den *= 16;
+	}
+
+	pclk_div = mult_frac(1, num, den);
+
+	DSI_PLL_DBG(pll,
+		"bpp:%d lanes:%d m_val:%u n_val:%u phy_post_div:%u dsiclk_sel:%u pclk_div:%u\n",
+		pll->bpp, pll->lanes, m_val, n_val, phy_post_div, dsiclk_sel, pclk_div);
 
 	return pclk_div;
 }
 
+static int dsi_pll_calc_dsiclk_sel(struct dsi_pll_resource *pll)
+{
+	u32 dsiclk_sel;
+
+	if (pll->type == DSI_PHY_TYPE_DPHY) {
+		if (pll->bpp == 30 && (pll->lanes == 2 || pll->lanes == 4))
+			dsiclk_sel = 0;
+		else if (pll->bpp == 3 && pll->lanes >= 3)
+			dsiclk_sel = 0;
+		else
+			dsiclk_sel = 1;
+	} else {
+		if (pll->bpp == 24 || (pll->bpp == 16 && pll->lanes == 2)
+				|| (pll->bpp == 30 && pll->lanes == 1))
+			dsiclk_sel = 3;
+		else if (pll->bpp == 3 && pll->lanes >= 2)
+			dsiclk_sel = 2;
+		else
+			dsiclk_sel = 0;
+	}
+
+	return dsiclk_sel;
+}
+
 static int dsi_pll_4nm_set_pclk_div(struct dsi_pll_resource *pll, bool commit)
 {
 
-	int dsi_clk = 0, pclk_div = 0;
+	int dsiclk_sel = 0, pclk_div = 0;
 	u64 pclk_src_rate;
 	u32 pll_post_div;
 	u32 phy_post_div;
 
 	pll_post_div = dsi_pll_get_pll_post_div(pll);
 	pclk_src_rate = div_u64(pll->vco_rate, pll_post_div);
-	if (pll->type == DSI_PHY_TYPE_DPHY) {
+
-		dsi_clk = 0x1;
+	phy_post_div = dsi_pll_get_phy_post_div(pll);
-		phy_post_div = dsi_pll_get_phy_post_div(pll);
+	dsiclk_sel = dsi_pll_calc_dsiclk_sel(pll);
+
+	dsi_pll_set_dsiclk_sel(pll, dsiclk_sel);
+
+	if (dsiclk_sel == 0) {
+		pclk_src_rate = div_u64(pclk_src_rate, phy_post_div);
+	} else if (dsiclk_sel == 1) {
 		pclk_src_rate = div_u64(pclk_src_rate, phy_post_div);
 		pclk_src_rate = div_u64(pclk_src_rate, 2);
-		pclk_div = dsi_pll_calc_dphy_pclk_div(pll);
+	} else if (dsiclk_sel == 3 && pll->type == DSI_PHY_TYPE_CPHY) {
-	} else {
-		dsi_clk = 0x3;
 		pclk_src_rate *= 2;
 		pclk_src_rate = div_u64(pclk_src_rate, 7);
-		pclk_div = dsi_pll_calc_cphy_pclk_div(pll);
 	}
 
+	if (pll->type == DSI_PHY_TYPE_DPHY)
+		pclk_div = dsi_pll_calc_dphy_pclk_div(pll);
+	else
+		pclk_div = dsi_pll_calc_cphy_pclk_div(pll);
+
 	pll->pclk_rate = div_u64(pclk_src_rate, pclk_div);
 
-	DSI_PLL_DBG(pll, "pclk rate: %llu, dsi_clk: %d, pclk_div: %d\n",
+	DSI_PLL_DBG(pll, "pclk rate: %llu, dsiclk_sel: %d, pclk_div: %d\n",
-			pll->pclk_rate, dsi_clk, pclk_div);
+			pll->pclk_rate, dsiclk_sel, pclk_div);
 
 	if (commit) {
-		dsi_pll_set_dsi_clk(pll, dsi_clk);
 		dsi_pll_set_pclk_div(pll, pclk_div);
 	}
 

msm/dsi/dsi_pll_5nm.c

@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <linux/kernel.h>
@@ -128,24 +128,24 @@ static inline int dsi_pll_get_phy_post_div(struct dsi_pll_resource *pll)
 }
 
 
-static inline void dsi_pll_set_dsi_clk(struct dsi_pll_resource *pll, u32
+static inline void dsi_pll_set_dsiclk_sel(struct dsi_pll_resource *pll, u32
-		dsi_clk)
+		dsiclk_sel)
 {
 	u32 reg_val = 0;
 
 	reg_val = DSI_PLL_REG_R(pll->phy_base, PHY_CMN_CLK_CFG1);
 	reg_val &= ~0x3;
-	reg_val |= dsi_clk;
+	reg_val |= dsiclk_sel;
 	DSI_PLL_REG_W(pll->phy_base, PHY_CMN_CLK_CFG1, reg_val);
 	if (pll->slave) {
 		reg_val = DSI_PLL_REG_R(pll->slave->phy_base, PHY_CMN_CLK_CFG1);
 		reg_val &= ~0x3;
-		reg_val |= dsi_clk;
+		reg_val |= dsiclk_sel;
 		DSI_PLL_REG_W(pll->slave->phy_base, PHY_CMN_CLK_CFG1, reg_val);
 	}
 }
 
-static inline int dsi_pll_get_dsi_clk(struct dsi_pll_resource *pll)
+static inline int dsi_pll_get_dsiclk_sel(struct dsi_pll_resource *pll)
 {
 	u32 reg_val;
 
@@ -1151,7 +1151,7 @@ static int dsi_pll_calc_cphy_pclk_div(struct dsi_pll_resource *pll)
 static int dsi_pll_5nm_set_pclk_div(struct dsi_pll_resource *pll, bool commit)
 {
 
-	int dsi_clk = 0, pclk_div = 0;
+	int dsiclk_sel = 0, pclk_div = 0;
 	u64 pclk_src_rate;
 	u32 pll_post_div;
 	u32 phy_post_div;
@@ -1159,13 +1159,13 @@ static int dsi_pll_5nm_set_pclk_div(struct dsi_pll_resource *pll, bool commit)
 	pll_post_div = dsi_pll_get_pll_post_div(pll);
 	pclk_src_rate = div_u64(pll->vco_rate, pll_post_div);
 	if (pll->type == DSI_PHY_TYPE_DPHY) {
-		dsi_clk = 0x1;
+		dsiclk_sel = 0x1;
 		phy_post_div = dsi_pll_get_phy_post_div(pll);
 		pclk_src_rate = div_u64(pclk_src_rate, phy_post_div);
 		pclk_src_rate = div_u64(pclk_src_rate, 2);
 		pclk_div = dsi_pll_calc_dphy_pclk_div(pll);
 	} else {
-		dsi_clk = 0x3;
+		dsiclk_sel = 0x3;
 		pclk_src_rate *= 2;
 		pclk_src_rate = div_u64(pclk_src_rate, 7);
 		pclk_div = dsi_pll_calc_cphy_pclk_div(pll);
@@ -1173,16 +1173,12 @@ static int dsi_pll_5nm_set_pclk_div(struct dsi_pll_resource *pll, bool commit)
 
 	pll->pclk_rate = div_u64(pclk_src_rate, pclk_div);
 
-	DSI_PLL_DBG(pll, "pclk rate: %llu, dsi_clk: %d, pclk_div: %d\n",
+	DSI_PLL_DBG(pll, "pclk rate: %llu, dsiclk_sel: %d, pclk_div: %d\n",
-			pll->pclk_rate, dsi_clk, pclk_div);
+			pll->pclk_rate, dsiclk_sel, pclk_div);
-
 	if (commit) {
-		dsi_pll_set_dsi_clk(pll, dsi_clk);
 		dsi_pll_set_pclk_div(pll, pclk_div);
 	}
-
 	return 0;
-
 }
 
 static int dsi_pll_5nm_vco_set_rate(struct dsi_pll_resource *pll_res)

msm/msm_atomic.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  * Copyright (C) 2014 Red Hat
  * Author: Rob Clark <robdclark@gmail.com>
@@ -114,11 +114,23 @@ static inline bool _msm_seamless_for_conn(struct drm_connector *connector,
 	if (!old_conn_state || !old_conn_state->crtc)
 		return false;
 
+	if (!priv || !priv->kms || !priv->kms->funcs->get_msm_mode)
+		return false;
+
+	msm_mode = priv->kms->funcs->get_msm_mode(
+			_msm_get_conn_state(old_conn_state->crtc->state));
+	if (!msm_mode)
+		return false;
+
 	if (!old_conn_state->crtc->state->mode_changed &&
 			!old_conn_state->crtc->state->active_changed &&
 			old_conn_state->crtc->state->connectors_changed) {
-		if (old_conn_state->crtc == connector->state->crtc)
+		if (old_conn_state->crtc == connector->state->crtc) {
+			if (enable && msm_is_private_mode_changed(
+				_msm_get_conn_state(old_conn_state->crtc->state)))
+				return false;
 			return true;
+		}
 	}
 
 	if (enable)
@@ -128,14 +140,6 @@ static inline bool _msm_seamless_for_conn(struct drm_connector *connector,
 		old_conn_state->crtc->state->connectors_changed)
 		return false;
 
-	if (!priv || !priv->kms || !priv->kms->funcs->get_msm_mode)
-		return false;
-
-	msm_mode = priv->kms->funcs->get_msm_mode(
-			_msm_get_conn_state(old_conn_state->crtc->state));
-	if (!msm_mode)
-		return false;
-
 	if (msm_is_mode_seamless(msm_mode) ||
 		msm_is_mode_seamless_vrr(msm_mode) ||
 		msm_is_mode_seamless_dyn_clk(msm_mode) ||
@@ -326,7 +330,7 @@ msm_crtc_set_mode(struct drm_device *dev, struct drm_atomic_state *old_state)
 		if (!new_crtc_state->mode_changed &&
 				new_crtc_state->connectors_changed) {
 			if (_msm_seamless_for_conn(connector,
-					old_conn_state, false))
+					old_conn_state, true))
 				continue;
 		} else if (!new_crtc_state->mode_changed) {
 			if (!msm_is_private_mode_changed(

msm/msm_drv.h

@@ -270,8 +270,11 @@ enum msm_display_wd_jitter_type {
 	MSM_DISPLAY_WD_LTJ_JITTER = BIT(2),
 };
 
-#define MSM_DISPLAY_COMPRESSION_RATIO_NONE 1
+/**
-#define MSM_DISPLAY_COMPRESSION_RATIO_MAX 5
+ * Scale macros so that compression ratio is a factor of 100 everywhere
+ */
+#define MSM_DISPLAY_COMPRESSION_RATIO_NONE 100
+#define MSM_DISPLAY_COMPRESSION_RATIO_MAX 500
 
 /**
  * enum msm_display_spr_pack_type - sub pixel rendering pack patterns supported
@@ -703,11 +706,17 @@ struct msm_display_vdc_info {
  */
 #define DSC_BPP(config) ((config).bits_per_pixel >> 4)
 
+/**
+ * Bits/component
+ * returns the integer bpc value from the drm_dsc_config struct
+ */
+#define DSC_BPC(config) ((config).bits_per_component)
+
 /**
  * struct msm_compression_info - defined panel compression
  * @enabled:          enabled/disabled
  * @comp_type:        type of compression supported
- * @comp_ratio:       compression ratio
+ * @comp_ratio:       compression ratio multiplied by 100
  * @src_bpp:          bits per pixel before compression
  * @tgt_bpp:          bits per pixel after compression
  * @dsc_info:         dsc configuration if the compression

msm/sde/sde_color_processing.c

@@ -2003,6 +2003,7 @@ int sde_cp_crtc_check_properties(struct drm_crtc *crtc,
 {
 	struct sde_crtc *sde_crtc = NULL;
 	struct sde_crtc_state *sde_crtc_state = NULL;
+	struct drm_display_mode *old_mode, *new_mode;
 	int i, ret = 0;
 
 	if (!crtc || !crtc->dev || !state) {
@@ -2023,8 +2024,11 @@ int sde_cp_crtc_check_properties(struct drm_crtc *crtc,
 		return -EINVAL;
 	}
 
-	/* force revalidation of some properties when there is a mode switch */
+	/* force revalidation of some properties when there is a resolution switch */
-	if (state->mode_changed)
+	old_mode = &crtc->state->adjusted_mode;
+	new_mode = &state->adjusted_mode;
+	if ((old_mode->hdisplay != new_mode->hdisplay) ||
+		(old_mode->vdisplay != new_mode->vdisplay))
 		sde_cp_crtc_res_change(crtc);
 
 	mutex_lock(&sde_crtc->crtc_cp_lock);

msm/sde/sde_encoder.c

@@ -750,6 +750,7 @@ void sde_encoder_destroy(struct drm_encoder *drm_enc)
 			phys->ops.destroy(phys);
 			--sde_enc->num_phys_encs;
 			sde_enc->phys_vid_encs[i] = NULL;
+			sde_enc->phys_encs[i] = NULL;
 		}
 
 		phys = sde_enc->phys_cmd_encs[i];
@@ -757,6 +758,7 @@ void sde_encoder_destroy(struct drm_encoder *drm_enc)
 			phys->ops.destroy(phys);
 			--sde_enc->num_phys_encs;
 			sde_enc->phys_cmd_encs[i] = NULL;
+			sde_enc->phys_encs[i] = NULL;
 		}
 
 		phys = sde_enc->phys_encs[i];

msm/sde/sde_encoder_dce.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  */
 
@@ -418,6 +418,7 @@ static int _dce_dsc_setup_helper(struct sde_encoder_virt *sde_enc,
 	int dsc_pic_width;
 	int dsc_common_mode = 0;
 	int i, rc = 0;
+	bool widebus_en;
 
 	sde_kms = sde_encoder_get_kms(&sde_enc->base);
 
@@ -486,7 +487,9 @@ static int _dce_dsc_setup_helper(struct sde_encoder_virt *sde_enc,
 	else if ((dsc_common_mode & DSC_MODE_MULTIPLEX) || (dsc->half_panel_pu))
 		dsc->num_active_ss_per_enc = dsc->config.slice_count >> 1;
 
-	sde_dsc_populate_dsc_private_params(dsc, intf_ip_w);
+	widebus_en = sde_encoder_is_widebus_enabled(enc_master->parent);
+
+	sde_dsc_populate_dsc_private_params(dsc, intf_ip_w, widebus_en);
 
 	_dce_dsc_initial_line_calc(dsc, enc_ip_w, dsc_common_mode);
 

msm/sde/sde_encoder_phys.h

@@ -287,7 +287,7 @@ struct sde_encoder_irq {
  * @intf_cfg_v1:        Interface hardware configuration to be used if control
  *                      path supports SDE_CTL_ACTIVE_CFG
  * @comp_type:      Type of compression supported
- * @comp_ratio:		Compression ratio
+ * @comp_ratio:		Compression ratio multiplied by 100
  * @dsc_extra_pclk_cycle_cnt: Extra pclk cycle count for DSC over DP
  * @dsc_extra_disp_width: Additional display width for DSC over DP
  * @poms_align_vsync:   poms with vsync aligned

msm/sde/sde_encoder_phys_vid.c

@@ -11,6 +11,7 @@
 #include "sde_formats.h"
 #include "dsi_display.h"
 #include "sde_trace.h"
+#include <drm/drm_fixed.h>
 
 #define SDE_DEBUG_VIDENC(e, fmt, ...) SDE_DEBUG("enc%d intf%d " fmt, \
 		(e) && (e)->base.parent ? \
@@ -48,6 +49,7 @@ static void drm_mode_to_intf_timing_params(
 		struct intf_timing_params *timing)
 {
 	const struct sde_encoder_phys *phys_enc = &vid_enc->base;
+	s64 comp_ratio, width;
 
 	memset(timing, 0, sizeof(*timing));
 
@@ -124,7 +126,7 @@ static void drm_mode_to_intf_timing_params(
 	 */
 	if (phys_enc->hw_intf->cap->type == INTF_DP &&
 			(timing->wide_bus_en ||
-			(vid_enc->base.comp_ratio > 1))) {
+			(vid_enc->base.comp_ratio > MSM_DISPLAY_COMPRESSION_RATIO_NONE))) {
 		timing->width = timing->width >> 1;
 		timing->xres = timing->xres >> 1;
 		timing->h_back_porch = timing->h_back_porch >> 1;
@@ -132,7 +134,7 @@ static void drm_mode_to_intf_timing_params(
 		timing->hsync_pulse_width = timing->hsync_pulse_width >> 1;
 
 		if (vid_enc->base.comp_type == MSM_DISPLAY_COMPRESSION_DSC &&
-				(vid_enc->base.comp_ratio > 1)) {
+				(vid_enc->base.comp_ratio > MSM_DISPLAY_COMPRESSION_RATIO_NONE)) {
 			timing->extra_dto_cycles =
 				vid_enc->base.dsc_extra_pclk_cycle_cnt;
 			timing->width += vid_enc->base.dsc_extra_disp_width;
@@ -151,10 +153,11 @@ static void drm_mode_to_intf_timing_params(
 			(vid_enc->base.comp_type ==
 			MSM_DISPLAY_COMPRESSION_VDC))) {
 		// adjust active dimensions
-		timing->width = DIV_ROUND_UP(timing->width,
+		width = drm_fixp_from_fraction(timing->width, 1);
-			vid_enc->base.comp_ratio);
+		comp_ratio = drm_fixp_from_fraction(vid_enc->base.comp_ratio, 100);
-		timing->xres = DIV_ROUND_UP(timing->xres,
+		width = drm_fixp_div(width, comp_ratio);
-			vid_enc->base.comp_ratio);
+		timing->width = drm_fixp2int_ceil(width);
+		timing->xres = timing->width;
 	}
 
 	/*

msm/sde/sde_hw_reg_dma_v1_color_proc.c

@@ -32,7 +32,7 @@
  * When disabling INIT property, we don't want to reset those bits since
  * they are needed for both LTM histogram and VLUT.
  */
-#define REG_DMA_LTM_INIT_ENABLE_OP_MASK 0xFFFF8CAB
+#define REG_DMA_LTM_INIT_ENABLE_OP_MASK 0x1100153
 #define REG_DMA_LTM_INIT_DISABLE_OP_MASK 0xFFFF8CAF
 #define REG_DMA_LTM_ROI_OP_MASK 0xFEFFFFFF
 /**
@@ -3794,22 +3794,16 @@ void reg_dmav1_setup_ltm_initv1(struct sde_hw_dspp *ctx, void *cfg)
 		}
 
 		if (init_param->init_param_01) {
-			if (ltm_vlut_ops_mask[dspp_idx[i]] & ltm_vlut)
-				opmode |= BIT(6);
 			ltm_vlut_ops_mask[dspp_idx[i]] |= ltm_dither;
 			opmode |= ((init_param->init_param_02 & 0x7) << 12);
 		} else {
-			opmode &= ~BIT(6);
 			ltm_vlut_ops_mask[dspp_idx[i]] &= ~ltm_dither;
 		}
 
 		if (init_param->init_param_03) {
-			if (ltm_vlut_ops_mask[dspp_idx[i]] & ltm_vlut)
-				opmode |= BIT(4);
 			ltm_vlut_ops_mask[dspp_idx[i]] |= ltm_unsharp;
 			opmode |= ((init_param->init_param_04 & 0x3) << 8);
 		} else {
-			opmode &= ~BIT(4);
 			ltm_vlut_ops_mask[dspp_idx[i]] &= ~ltm_unsharp;
 		}
 
@@ -3988,8 +3982,6 @@ void reg_dmav1_setup_ltm_roiv1(struct sde_hw_dspp *ctx, void *cfg)
 			return;
 		}
 
-		if (ltm_vlut_ops_mask[dspp_idx[i]] & ltm_vlut)
-			opmode |= BIT(24);
 		ltm_vlut_ops_mask[dspp_idx[i]] |= ltm_roi;
 
 		REG_DMA_SETUP_OPS(dma_write_cfg, 0x04, &opmode, sizeof(opmode),

msm/sde_dsc_helper.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  * Copyright (c) 2012-2021 The Linux Foundation. All rights reserved.
  */
 
@@ -372,12 +372,13 @@ int sde_dsc_populate_dsc_config(struct drm_dsc_config *dsc, int scr_ver) {
 }
 
 int sde_dsc_populate_dsc_private_params(struct msm_display_dsc_info *dsc_info,
-		int intf_width)
+		int intf_width, bool widebus_en)
 {
 	int  mod_offset;
 	int slice_per_pkt, slice_per_intf;
 	int bytes_in_slice, total_bytes_per_intf;
 	u16 bpp;
+	u16 bpc;
 	u32 bytes_in_dsc_pair;
 	u32 total_bytes_in_dsc_pair;
 
@@ -421,12 +422,26 @@ int sde_dsc_populate_dsc_private_params(struct msm_display_dsc_info *dsc_info,
 		slice_per_pkt = 1;
 
 	bpp = DSC_BPP(dsc_info->config);
+	bpc = DSC_BPC(dsc_info->config);
 	bytes_in_slice = DIV_ROUND_UP(dsc_info->config.slice_width *
 			bpp, 8);
 	total_bytes_per_intf = bytes_in_slice * slice_per_intf;
 
 	dsc_info->eol_byte_num = total_bytes_per_intf % 3;
-	dsc_info->pclk_per_line =  DIV_ROUND_UP(total_bytes_per_intf, 3);
+
+	/*
+	 * In DATABUS-WIDEN mode, MDP always sends out 48-bit compressed data per pclk
+	 * and on average, DSI consumes an amount of compressed data equivalent to the
+	 * uncompressed pixel depth per pclk.
+	 *
+	 * In NON-DATABUS-WIDEN mode, MDP always sends out 24-bit compressed data per
+	 * pclk and DSI always consumes 24-bit compressed data per pclk.
+	 */
+	if (widebus_en)
+		dsc_info->pclk_per_line = DIV_ROUND_UP(total_bytes_per_intf * 8,
+				msm_get_src_bpc(dsc_info->chroma_format, bpc));
+	else
+		dsc_info->pclk_per_line = DIV_ROUND_UP(total_bytes_per_intf * 8, 24);
 	dsc_info->bytes_in_slice = bytes_in_slice;
 	dsc_info->bytes_per_pkt = bytes_in_slice * slice_per_pkt;
 	dsc_info->pkt_per_line = slice_per_intf / slice_per_pkt;
@@ -571,4 +586,3 @@ int sde_dsc_create_pps_buf_cmd(struct msm_display_dsc_info *dsc_info,
 
 	return 0;
 }
-

msm/sde_dsc_helper.h

@@ -1,5 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
  * Copyright (c) 2020 The Linux Foundation. All rights reserved.
  */
 
@@ -13,10 +14,9 @@
 int sde_dsc_populate_dsc_config(struct drm_dsc_config *dsc, int scr_ver);
 
 int sde_dsc_populate_dsc_private_params(struct msm_display_dsc_info *dsc_info,
-		int intf_width);
+		int intf_width, bool widebus_en);
 
 int sde_dsc_create_pps_buf_cmd(struct msm_display_dsc_info *dsc_info,
 		char *buf, int pps_id, u32 len);
 
 #endif /* __SDE_DSC_HELPER_H__ */
-