From 3c5c21b0fb89ed906eb226a003289133bc8745c8 Mon Sep 17 00:00:00 2001 From: Mahadevan Date: Mon, 31 Jul 2023 10:03:22 +0530 Subject: [PATCH] disp: msm: sde: reset bw_control state during non-seamless commit During a seamless transition commit, the driver takes the values of bandwidth (BW) and clock that were set during the set_property phase of the commit, after the transition is completed. However, during a non-seamless transition commit, the BW and clock properties set by userspace cause the bw_control to be set to true. When crtc is disabled, this bw_control is set to false. If there are no updates to BW/clock for subsequent commits, the driver will set the maximum value, which will affect the power consumed by the display hardware. This change prevents bw_control from being set to false if it is not a power-off commit. Change-Id: I3348aacfb9ce338fe4625978364d14c11c2c26bc Signed-off-by: Mahadevan --- msm/sde/sde_crtc.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/msm/sde/sde_crtc.c b/msm/sde/sde_crtc.c index 16a80f4c..b7fbb016 100644 --- a/msm/sde/sde_crtc.c +++ b/msm/sde/sde_crtc.c @@ -5126,8 +5126,10 @@ static void _sde_crtc_reset(struct drm_crtc *crtc) sde_crtc->mixers_swapped = false; /* disable clk & bw control until clk & bw properties are set */ - cstate->bw_control = false; - cstate->bw_split_vote = false; + if (!crtc->state->active) { + cstate->bw_control = false; + cstate->bw_split_vote = false; + } cstate->hwfence_in_fences_set = false; sde_crtc_static_img_control(crtc, CACHE_STATE_DISABLED, false);