disp: msm: dsi: clear pll unlock error bit before unmasking
Since PLL UNLOCK status bit is a sticky bit, ensure this bit is cleared before unmasking PLL UNLOCK error. Otherwise unnecessarily DSI controller will trigger error interrupts for the stale status, the moment error is unmasked. Change-Id: I7b7aa63b5e508dde446a4469d9a6625a071dae00 Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
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@@ -1760,10 +1760,11 @@ int dsi_ctrl_hw_cmn_ctrl_reset(struct dsi_ctrl_hw *ctrl,
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void dsi_ctrl_hw_cmn_mask_error_intr(struct dsi_ctrl_hw *ctrl, u32 idx, bool en)
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void dsi_ctrl_hw_cmn_mask_error_intr(struct dsi_ctrl_hw *ctrl, u32 idx, bool en)
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{
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{
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u32 reg = 0;
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u32 reg = 0;
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u32 fifo_status = 0, timeout_status = 0;
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u32 fifo_status = 0, timeout_status = 0, pll_unlock_status = 0;
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u32 overflow_clear = BIT(10) | BIT(18) | BIT(22) | BIT(26) | BIT(30);
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u32 overflow_clear = BIT(10) | BIT(18) | BIT(22) | BIT(26) | BIT(30);
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u32 underflow_clear = BIT(19) | BIT(23) | BIT(27) | BIT(31);
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u32 underflow_clear = BIT(19) | BIT(23) | BIT(27) | BIT(31);
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u32 lp_rx_clear = BIT(4);
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u32 lp_rx_clear = BIT(4);
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u32 pll_unlock_clear = BIT(16);
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reg = DSI_R32(ctrl, DSI_ERR_INT_MASK0);
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reg = DSI_R32(ctrl, DSI_ERR_INT_MASK0);
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@@ -1808,8 +1809,11 @@ void dsi_ctrl_hw_cmn_mask_error_intr(struct dsi_ctrl_hw *ctrl, u32 idx, bool en)
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if (idx & BIT(DSI_PLL_UNLOCK_ERR)) {
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if (idx & BIT(DSI_PLL_UNLOCK_ERR)) {
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if (en)
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if (en)
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reg |= BIT(28);
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reg |= BIT(28);
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else
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else {
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reg &= ~BIT(28);
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reg &= ~BIT(28);
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pll_unlock_status = DSI_R32(ctrl, DSI_CLK_STATUS);
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DSI_W32(ctrl, DSI_CLK_STATUS, pll_unlock_status | pll_unlock_clear);
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}
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}
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}
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DSI_W32(ctrl, DSI_ERR_INT_MASK0, reg);
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DSI_W32(ctrl, DSI_ERR_INT_MASK0, reg);
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