Merge 59417d5d89 on remote branch

Change-Id: I803a082cacbec0ce6e0b37cdbefc8fd66ca5203f

msm/dsi/dsi_pll_4nm.c

@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <linux/kernel.h>
@@ -192,7 +192,7 @@ static void dsi_pll_config_slave(struct dsi_pll_resource *rsc)
 	rsc->slave = NULL;
 
 	if (!orsc) {
-		DSI_PLL_WARN(rsc, "slave PLL unavilable, assuming standalone config\n");
+		DSI_PLL_DBG(rsc, "slave PLL unavailable, assuming standalone config\n");
 		return;
 	}
 

msm/dsi/dsi_pll_5nm.c

@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <linux/kernel.h>
@@ -199,8 +199,8 @@ static void dsi_pll_config_slave(struct dsi_pll_resource *rsc)
 	rsc->slave = NULL;
 
 	if (!orsc) {
-		DSI_PLL_WARN(rsc,
+		DSI_PLL_DBG(rsc,
-			"slave PLL unavilable, assuming standalone config\n");
+			"slave PLL unavailable, assuming standalone config\n");
 		return;
 	}
 

msm/sde/sde_encoder.c

@@ -3715,7 +3715,12 @@ static void sde_encoder_vblank_callback(struct drm_encoder *drm_enc,
 
 	spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
 	phy_enc->last_vsync_timestamp = ts;
+
+	if (phy_enc->ops.is_master && phy_enc->ops.is_master(phy_enc))
+		atomic_inc(&sde_enc->vsync_cnt);
+	/* update count for debugfs */
 	atomic_inc(&phy_enc->vsync_cnt);
+
 	if (sde_enc->crtc_vblank_cb)
 		sde_enc->crtc_vblank_cb(sde_enc->crtc_vblank_cb_data, ts);
 	spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
@@ -3726,7 +3731,7 @@ static void sde_encoder_vblank_callback(struct drm_encoder *drm_enc,
 	if (phy_enc->sde_kms->debugfs_hw_fence)
 		sde_encoder_hw_fence_status(phy_enc->sde_kms, sde_enc->crtc, phy_enc->hw_ctl);
 
-	SDE_EVT32(DRMID(drm_enc), ktime_to_us(ts), atomic_read(&phy_enc->vsync_cnt));
+	SDE_EVT32(DRMID(drm_enc), ktime_to_us(ts), atomic_read(&sde_enc->vsync_cnt));
 	SDE_ATRACE_END("encoder_vblank_callback");
 }
 
@@ -5508,6 +5513,7 @@ static int sde_encoder_setup_display(struct sde_encoder_virt *sde_enc,
 	phys_params.parent_ops = parent_ops;
 	phys_params.enc_spinlock = &sde_enc->enc_spinlock;
 	phys_params.vblank_ctl_lock = &sde_enc->vblank_ctl_lock;
+	atomic_set(&sde_enc->vsync_cnt, 0);
 
 	SDE_DEBUG("\n");
 
@@ -5855,7 +5861,7 @@ u32 sde_encoder_get_frame_count(struct drm_encoder *encoder)
 
 	phys = sde_enc->cur_master;
 
-	return phys ? atomic_read(&phys->vsync_cnt) : 0;
+	return phys ? atomic_read(&sde_enc->vsync_cnt) : 0;
 }
 
 bool sde_encoder_get_vblank_timestamp(struct drm_encoder *encoder,

msm/sde/sde_encoder.h

@@ -147,6 +147,7 @@ enum sde_enc_rc_states {
  * @rsc_state_init:		boolean to indicate rsc config init
  * @disp_info:			local copy of msm_display_info struct
  * @misr_enable:		misr enable/disable status
+ * @vsync_cnt:			Vsync count for the physical encoder
  * @misr_reconfigure:		boolean entry indicates misr reconfigure status
  * @misr_frame_count:		misr frame count before start capturing the data
  * @idle_pc_enabled:		indicate if idle power collapse is enabled
@@ -224,6 +225,7 @@ struct sde_encoder_virt {
 	bool rsc_state_init;
 	struct msm_display_info disp_info;
 	atomic_t misr_enable;
+	atomic_t vsync_cnt;
 	bool misr_reconfigure;
 	u32 misr_frame_count;
 

msm/sde/sde_hw_catalog.c

@@ -217,6 +217,7 @@ enum sde_prop {
 	MACROTILE_MODE,
 	UBWC_BW_CALC_VERSION,
 	PIPE_ORDER_VERSION,
+	DDR_TYPE,
 	SEC_SID_MASK,
 	BASE_LAYER,
 	TRUSTED_VM_ENV,
@@ -617,6 +618,7 @@ static struct sde_prop_type sde_prop[] = {
 			PROP_TYPE_U32},
 	{PIPE_ORDER_VERSION, "qcom,sde-pipe-order-version", false,
 			PROP_TYPE_U32},
+	{DDR_TYPE, "qcom,sde-ddr-type", false, PROP_TYPE_U32_ARRAY},
 	{SEC_SID_MASK, "qcom,sde-secure-sid-mask", false, PROP_TYPE_U32_ARRAY},
 	{BASE_LAYER, "qcom,sde-mixer-stage-base-layer", false, PROP_TYPE_BOOL},
 	{TRUSTED_VM_ENV, "qcom,sde-trusted-vm-env", false, PROP_TYPE_BOOL},
@@ -3644,29 +3646,29 @@ static int _sde_vbif_populate_qos_parsing(struct sde_mdss_cfg *sde_cfg,
 {
 	int i, j, prop_index = VBIF_QOS_RT_REMAP;
 	u32 entries;
+	u32 ddr_list_index;
 
 	for (i = VBIF_RT_CLIENT; ((i < VBIF_MAX_CLIENT) && (prop_index < VBIF_PROP_MAX));
 						i++, prop_index++) {
-		vbif->qos_tbl[i].count = prop_count[prop_index];
-		SDE_DEBUG("qos_tbl[%d].count=%u\n", i, vbif->qos_tbl[i].count);
-
 		entries = 2 * sde_cfg->vbif_qos_nlvl;
-		if (vbif->qos_tbl[i].count == entries) {
+		vbif->qos_tbl[i].count = prop_count[prop_index];
-			vbif->qos_tbl[i].priority_lvl = kcalloc(entries, sizeof(u32), GFP_KERNEL);
+
-			if (!vbif->qos_tbl[i].priority_lvl) {
+		ddr_list_index = (vbif->qos_tbl[i].count == entries) ?
-				vbif->qos_tbl[i].count = 0;
+					0 : sde_cfg->ddr_list_index;
-				return -ENOMEM;
+
-			}
+		SDE_DEBUG("qos_tbl[%d].count=%u, ddr_list_index=%u\n",
-		} else if (vbif->qos_tbl[i].count) {
+				i, vbif->qos_tbl[i].count, ddr_list_index);
+
+		vbif->qos_tbl[i].priority_lvl = kcalloc(entries, sizeof(u32), GFP_KERNEL);
+		if (!vbif->qos_tbl[i].priority_lvl) {
 			vbif->qos_tbl[i].count = 0;
-			vbif->qos_tbl[i].priority_lvl = NULL;
+			return -ENOMEM;
-			SDE_ERROR("invalid qos table for client:%d, prop:%d\n", i, prop_index);
-			continue;
 		}
 
-		for (j = 0; j < vbif->qos_tbl[i].count; j++) {
+		for (j = 0; j < entries; j++) {
 			vbif->qos_tbl[i].priority_lvl[j] =
-					PROP_VALUE_ACCESS(prop_value, prop_index, j);
+					PROP_VALUE_ACCESS(prop_value, prop_index,
+					entries * ddr_list_index + j);
 			SDE_DEBUG("client:%d, prop:%d, lvl[%d]=%u\n", i, prop_index, j,
 					vbif->qos_tbl[i].priority_lvl[j]);
 		}
@@ -4021,6 +4023,16 @@ static void _sde_top_parse_dt_helper(struct sde_mdss_cfg *cfg,
 	if (!cfg->ipcc_protocol_id || !cfg->ipcc_client_phys_id)
 		cfg->hw_fence_rev = 0; /* disable hw fences*/
 
+	if (props->exists[DDR_TYPE]) {
+		for (i = 0; i < props->counts[DDR_TYPE]; i++) {
+			ddr_type = PROP_VALUE_ACCESS(props->values, DDR_TYPE, i);
+			if (ddr_type == of_fdt_get_ddrtype()) {
+				cfg->ddr_list_index = i;
+				break;
+			}
+		}
+	}
+
 	if (props->exists[SEC_SID_MASK]) {
 		cfg->sec_sid_mask_count = props->counts[SEC_SID_MASK];
 		for (i = 0; i < cfg->sec_sid_mask_count; i++)

msm/sde/sde_hw_catalog.h

@@ -1836,6 +1836,7 @@ struct sde_perf_cfg {
  * @max_mixer_width     max layer mixer line width
  * @max_mixer_blendstages       max layer mixer blend stages (z orders)
  * @max_cwb             max number of cwb supported
+ * @ddr_list_index      index of supported ddr type
  * @vbif_qos_nlvl       number of vbif QoS priority levels
  * @qos_target_time_ns  normalized qos target time for line-based qos
  * @macrotile_mode      UBWC parameter for macro tile channel distribution
@@ -1979,6 +1980,7 @@ struct sde_mdss_cfg {
 
 	u32 ipcc_protocol_id;
 	u32 ipcc_client_phys_id;
+	u32 ddr_list_index;
 };
 
 struct sde_mdss_hw_cfg_handler {