From d3516bd83f62967990815ec2c2ed51bb34274a7a Mon Sep 17 00:00:00 2001 From: Amine Najahi Date: Wed, 31 Aug 2022 16:14:25 -0400 Subject: [PATCH] disp: msm: update RSC bandwidth during solver mode transition Currently when disconnecting a secondary monitor, RSC will transition to solver mode. If the bandwidth remains the same for primary display, SW will not update BW indication register causing stale TCS wait values. This change forces a register update when RSC mode is changed to solver mode. Change-Id: I99d2332621bad75a7b6abdb64d6aedd35c30ca63 Signed-off-by: Amine Najahi Signed-off-by: V S Ganga VaraPrasad (VARA) Adabala --- msm/sde_rsc_hw_v3.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/msm/sde_rsc_hw_v3.c b/msm/sde_rsc_hw_v3.c index ef6066de..12229f22 100644 --- a/msm/sde_rsc_hw_v3.c +++ b/msm/sde_rsc_hw_v3.c @@ -429,6 +429,11 @@ static int sde_rsc_state_update_v3(struct sde_rsc_priv *rsc, reg, rsc->debug_mode); wmb(); /* make sure that solver is enabled */ + if (rsc->hw_ops.bwi_status) { + rsc->bwi_update = BW_NO_CHANGE; + rsc->hw_ops.bwi_status(rsc); + } + break; case SDE_RSC_VID_STATE: