From d66ea6fc296e16eabf8af746b2f305caec5feac9 Mon Sep 17 00:00:00 2001 From: Steve Cohen Date: Fri, 21 Aug 2020 16:23:24 -0400 Subject: [PATCH] disp: msm: sde: use the correct get_status op for all INTFs A new status register was added in DPU 5.x to INTFs to allow for confirmation when the timing engine is disabled. This functionality was controlled via an overloaded feature flag which is used to enable INTF tear-check ops (also added in DPU 5.x). External displays support INTF_STATUS but have no use for any tear-check functions. Separate these features so they can be enabled individually on the interfaces which support them. Change-Id: Ib8548619cb58bf19b7c02211ead7f33f52ffeae4 Signed-off-by: Steve Cohen --- msm/sde/sde_hw_catalog.c | 4 ++++ msm/sde/sde_hw_catalog.h | 2 ++ msm/sde/sde_hw_intf.c | 7 +++++-- 3 files changed, 11 insertions(+), 2 deletions(-) diff --git a/msm/sde/sde_hw_catalog.c b/msm/sde/sde_hw_catalog.c index 8d358775..4a941c9b 100644 --- a/msm/sde/sde_hw_catalog.c +++ b/msm/sde/sde_hw_catalog.c @@ -2238,6 +2238,10 @@ static int sde_intf_parse_dt(struct device_node *np, set_bit(SDE_INTF_TE, &intf->features); } + if (SDE_HW_MAJOR(sde_cfg->hwversion) >= + SDE_HW_MAJOR(SDE_HW_VER_500)) + set_bit(SDE_INTF_STATUS, &intf->features); + if (SDE_HW_MAJOR(sde_cfg->hwversion) >= SDE_HW_MAJOR(SDE_HW_VER_700)) set_bit(SDE_INTF_TE_ALIGN_VSYNC, &intf->features); diff --git a/msm/sde/sde_hw_catalog.h b/msm/sde/sde_hw_catalog.h index d674635e..77827c82 100644 --- a/msm/sde/sde_hw_catalog.h +++ b/msm/sde/sde_hw_catalog.h @@ -468,12 +468,14 @@ enum { * pixel data arrives to this INTF * @SDE_INTF_TE INTF block has TE configuration support * @SDE_INTF_TE_ALIGN_VSYNC INTF block has POMS Align vsync support + * @SDE_INTF_STATUS INTF block has INTF_STATUS register * @SDE_INTF_MAX */ enum { SDE_INTF_INPUT_CTRL = 0x1, SDE_INTF_TE, SDE_INTF_TE_ALIGN_VSYNC, + SDE_INTF_STATUS, SDE_INTF_MAX }; diff --git a/msm/sde/sde_hw_intf.c b/msm/sde/sde_hw_intf.c index 7dc8401f..5c4bc917 100644 --- a/msm/sde/sde_hw_intf.c +++ b/msm/sde/sde_hw_intf.c @@ -785,7 +785,6 @@ static void _setup_intf_ops(struct sde_hw_intf_ops *ops, { ops->setup_timing_gen = sde_hw_intf_setup_timing_engine; ops->setup_prg_fetch = sde_hw_intf_setup_prg_fetch; - ops->get_status = sde_hw_intf_get_status; ops->enable_timing = sde_hw_intf_enable_timing_engine; ops->setup_misr = sde_hw_intf_setup_misr; ops->collect_misr = sde_hw_intf_collect_misr; @@ -798,6 +797,11 @@ static void _setup_intf_ops(struct sde_hw_intf_ops *ops, ops->enable_compressed_input = sde_hw_intf_enable_compressed_input; ops->enable_wide_bus = sde_hw_intf_enable_wide_bus; + if (cap & BIT(SDE_INTF_STATUS)) + ops->get_status = sde_hw_intf_v1_get_status; + else + ops->get_status = sde_hw_intf_get_status; + if (cap & BIT(SDE_INTF_INPUT_CTRL)) ops->bind_pingpong_blk = sde_hw_intf_bind_pingpong_blk; @@ -811,7 +815,6 @@ static void _setup_intf_ops(struct sde_hw_intf_ops *ops, ops->get_autorefresh = sde_hw_intf_get_autorefresh_config; ops->poll_timeout_wr_ptr = sde_hw_intf_poll_timeout_wr_ptr; ops->vsync_sel = sde_hw_intf_vsync_sel; - ops->get_status = sde_hw_intf_v1_get_status; ops->check_and_reset_tearcheck = sde_hw_intf_v1_check_and_reset_tearcheck; }