diff --git a/msm/sde/sde_hw_ctl.c b/msm/sde/sde_hw_ctl.c
index 87975be1..3fcc7b1c 100644
--- a/msm/sde/sde_hw_ctl.c
+++ b/msm/sde/sde_hw_ctl.c
@@ -818,6 +818,9 @@ static inline int sde_hw_ctl_trigger_flush_v1(struct sde_hw_ctl *ctx)
 
 	SDE_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->flush.pending_flush_mask);
 
+	/* ensure all register writes are written without re-ordering*/
+	wmb();
+
 	return 0;
 }
 
diff --git a/msm/sde/sde_hw_reg_dma_v1.c b/msm/sde/sde_hw_reg_dma_v1.c
index d3de506a..c8fa8784 100644
--- a/msm/sde/sde_hw_reg_dma_v1.c
+++ b/msm/sde/sde_hw_reg_dma_v1.c
@@ -709,6 +709,13 @@ static int write_kick_off_v1(struct sde_reg_dma_kickoff_cfg *cfg)
 		SDE_EVT32(val);
 	}
 
+	if (cfg->last_command) {
+		/* ensure all packets are queued in packet queue before
+		 * queuing last command descriptor (last command)
+		 */
+		wmb();
+	}
+
 	if (cfg->dma_type == REG_DMA_TYPE_DB) {
 		SDE_REG_WRITE(&hw, reg_dma_ctl_queue_off[cfg->ctl->idx],
 				cfg->dma_buf->iova);
@@ -722,6 +729,9 @@ static int write_kick_off_v1(struct sde_reg_dma_kickoff_cfg *cfg)
 	}
 
 	if (cfg->last_command) {
+		/* ensure last command is queued before lut dma trigger */
+		wmb();
+
 		mask = ctl_trigger_done_mask[cfg->ctl->idx][cfg->queue_select];
 		SDE_REG_WRITE(&hw, reg_dma_intr_clear_offset, mask);
 		/* DB LUTDMA use SW trigger while SB LUTDMA uses DSPP_SB