From dd632ed2f78234554d6560220cf696913b0561d0 Mon Sep 17 00:00:00 2001 From: Anjaneya Prasad Musunuri Date: Sun, 6 Nov 2022 16:41:37 +0530 Subject: [PATCH] disp: msm: sde: add memory barrier to avoid out of order writes add memory barrier before and after last command to avoid out of order packet queuing to lut dma packet queue. add memory barrier after ctrl flush to ensure lut dma trigger, dspp flush and ctrl flush all are written to dpu before control start. Change-Id: I7e1613034af8407d55529cf3f95c70994334af82 Signed-off-by: Anjaneya Prasad Musunuri --- msm/sde/sde_hw_ctl.c | 3 +++ msm/sde/sde_hw_reg_dma_v1.c | 10 ++++++++++ 2 files changed, 13 insertions(+) diff --git a/msm/sde/sde_hw_ctl.c b/msm/sde/sde_hw_ctl.c index 87975be1..3fcc7b1c 100644 --- a/msm/sde/sde_hw_ctl.c +++ b/msm/sde/sde_hw_ctl.c @@ -818,6 +818,9 @@ static inline int sde_hw_ctl_trigger_flush_v1(struct sde_hw_ctl *ctx) SDE_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->flush.pending_flush_mask); + /* ensure all register writes are written without re-ordering*/ + wmb(); + return 0; } diff --git a/msm/sde/sde_hw_reg_dma_v1.c b/msm/sde/sde_hw_reg_dma_v1.c index d3de506a..c8fa8784 100644 --- a/msm/sde/sde_hw_reg_dma_v1.c +++ b/msm/sde/sde_hw_reg_dma_v1.c @@ -709,6 +709,13 @@ static int write_kick_off_v1(struct sde_reg_dma_kickoff_cfg *cfg) SDE_EVT32(val); } + if (cfg->last_command) { + /* ensure all packets are queued in packet queue before + * queuing last command descriptor (last command) + */ + wmb(); + } + if (cfg->dma_type == REG_DMA_TYPE_DB) { SDE_REG_WRITE(&hw, reg_dma_ctl_queue_off[cfg->ctl->idx], cfg->dma_buf->iova); @@ -722,6 +729,9 @@ static int write_kick_off_v1(struct sde_reg_dma_kickoff_cfg *cfg) } if (cfg->last_command) { + /* ensure last command is queued before lut dma trigger */ + wmb(); + mask = ctl_trigger_done_mask[cfg->ctl->idx][cfg->queue_select]; SDE_REG_WRITE(&hw, reg_dma_intr_clear_offset, mask); /* DB LUTDMA use SW trigger while SB LUTDMA uses DSPP_SB