From 0e2b3d56a29bd2fa358f01a68247344fc16278dc Mon Sep 17 00:00:00 2001 From: Mahadevan Date: Fri, 31 Mar 2023 01:40:49 +0530 Subject: [PATCH] disp: msm: sde: signal cwb retire fence on cwb overflow In the current SW, cwb overflow interrupt is not enabled for mid and low tier targets due to which CWB retire fence is not signaled, causing HWCBufferSyncHandler SyncWait timeouts on fence. This change enables the cwb overflow interrupt always to detect the overflow and signal the retire fence in such cases. Change-Id: I4841814d91bcd7b31f00554da6b2369078ce4693 Signed-off-by: Jayaprakash Madisetty Signed-off-by: Mahadevan --- msm/sde/sde_encoder_phys_wb.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/msm/sde/sde_encoder_phys_wb.c b/msm/sde/sde_encoder_phys_wb.c index d3897f52..d4fb117b 100644 --- a/msm/sde/sde_encoder_phys_wb.c +++ b/msm/sde/sde_encoder_phys_wb.c @@ -35,10 +35,6 @@ static const u32 cwb_irq_tbl[PINGPONG_MAX] = {SDE_NONE, INTR_IDX_PP1_OVFL, INTR_IDX_PP2_OVFL, INTR_IDX_PP3_OVFL, INTR_IDX_PP4_OVFL, INTR_IDX_PP5_OVFL, SDE_NONE, SDE_NONE}; -static const u32 dcwb_irq_tbl[PINGPONG_MAX] = {SDE_NONE, SDE_NONE, - SDE_NONE, SDE_NONE, SDE_NONE, SDE_NONE, - INTR_IDX_PP_CWB_OVFL, SDE_NONE}; - /** * sde_rgb2yuv_601l - rgb to yuv color space conversion matrix * @@ -1717,6 +1713,7 @@ static void sde_encoder_phys_wb_irq_ctrl(struct sde_encoder_phys *phys, bool ena int index = 0, pp = 0; u32 max_num_of_irqs = 0; const u32 *irq_table = NULL; + enum sde_intr_idx intr_idx; if (!wb_enc) return; @@ -1735,7 +1732,6 @@ static void sde_encoder_phys_wb_irq_ctrl(struct sde_encoder_phys *phys, bool ena wb_cfg = wb_enc->hw_wb->caps; if (wb_cfg->features & BIT(SDE_WB_HAS_DCWB)) { max_num_of_irqs = 1; - irq_table = dcwb_irq_tbl; } else { max_num_of_irqs = CRTC_DUAL_MIXERS_ONLY; irq_table = cwb_irq_tbl; @@ -1748,9 +1744,11 @@ static void sde_encoder_phys_wb_irq_ctrl(struct sde_encoder_phys *phys, bool ena if (test_bit(SDE_WB_PROG_LINE, &wb_cfg->features)) sde_encoder_helper_register_irq(phys, INTR_IDX_WB_LINEPTR); - for (index = 0; index < max_num_of_irqs; index++) - if (irq_table[index + pp] != SDE_NONE) - sde_encoder_helper_register_irq(phys, irq_table[index + pp]); + for (index = 0; index < max_num_of_irqs; index++) { + intr_idx = irq_table ? irq_table[index + pp] : INTR_IDX_PP_CWB_OVFL; + if (intr_idx != SDE_NONE) + sde_encoder_helper_register_irq(phys, intr_idx); + } } else if (!enable && atomic_dec_return(&phys->wbirq_refcount) == 0) { sde_encoder_helper_unregister_irq(phys, INTR_IDX_WB_DONE); sde_encoder_helper_unregister_irq(phys, INTR_IDX_CTL_START); @@ -1758,9 +1756,11 @@ static void sde_encoder_phys_wb_irq_ctrl(struct sde_encoder_phys *phys, bool ena if (test_bit(SDE_WB_PROG_LINE, &wb_cfg->features)) sde_encoder_helper_unregister_irq(phys, INTR_IDX_WB_LINEPTR); - for (index = 0; index < max_num_of_irqs; index++) - if (irq_table[index + pp] != SDE_NONE) - sde_encoder_helper_unregister_irq(phys, irq_table[index + pp]); + for (index = 0; index < max_num_of_irqs; index++) { + intr_idx = irq_table ? irq_table[index + pp] : INTR_IDX_PP_CWB_OVFL; + if (intr_idx != SDE_NONE) + sde_encoder_helper_unregister_irq(phys, intr_idx); + } } }