From e55c68138b04770d51067c158f92de526e0c926e Mon Sep 17 00:00:00 2001 From: Veera Sundaram Sankaran Date: Fri, 25 Feb 2022 16:31:31 -0800 Subject: [PATCH] disp: msm: sde: fix the wd-timer-ctrl config for WD TE Avoid read/update for WD_TIMER_0_CTL2 register as the default value changed from MDSS 9.x.x to disable clock granularity and this leads to issues with VSYNC generation. Instead program the necessary configs directly. Change-Id: Id545ad772480f94cf432bff8e8bfeb2b679f8aa9 Signed-off-by: Veera Sundaram Sankaran --- msm/sde/sde_hw_intf.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/msm/sde/sde_hw_intf.c b/msm/sde/sde_hw_intf.c index 2c2f7481..786478e0 100644 --- a/msm/sde/sde_hw_intf.c +++ b/msm/sde/sde_hw_intf.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. */ @@ -459,7 +459,7 @@ static void sde_hw_intf_setup_vsync_source(struct sde_hw_intf *intf, u32 frame_rate) { struct sde_hw_blk_reg_map *c; - u32 reg; + u32 reg = 0; if (!intf) return; @@ -469,9 +469,9 @@ static void sde_hw_intf_setup_vsync_source(struct sde_hw_intf *intf, SDE_REG_WRITE(c, INTF_WD_TIMER_0_LOAD_VALUE, CALCULATE_WD_LOAD_VALUE(frame_rate)); SDE_REG_WRITE(c, INTF_WD_TIMER_0_CTL, BIT(0)); /* clear timer */ - reg = SDE_REG_READ(c, INTF_WD_TIMER_0_CTL2); reg |= BIT(8); /* enable heartbeat timer */ reg |= BIT(0); /* enable WD timer */ + reg |= BIT(1); /* select default 16 clock ticks */ SDE_REG_WRITE(c, INTF_WD_TIMER_0_CTL2, reg); /* make sure that timers are enabled/disabled for vsync state */