From a4cae5882274b3048bff6d92ab0e656eb8fd1054 Mon Sep 17 00:00:00 2001 From: Yahui Wang Date: Tue, 4 Jan 2022 13:49:19 +0800 Subject: [PATCH 1/3] disp: msm: sde: move sde power event call into kms post init The sde power event function needs to get actual sde kms irq number to handle irq update call, but it is not able to know the irq number before irq installation, so move sde power event call into kms post init to avoid unbalanced irq issues. Change-Id: Id262b86f98299fbb9a51c9ccb8e68c7bde7f57ed Signed-off-by: Yahui Wang --- msm/sde/sde_kms.c | 52 ++++++++++++++++++++++++++--------------------- 1 file changed, 29 insertions(+), 23 deletions(-) diff --git a/msm/sde/sde_kms.c b/msm/sde/sde_kms.c index 660e1014..b6cf67f1 100644 --- a/msm/sde/sde_kms.c +++ b/msm/sde/sde_kms.c @@ -118,6 +118,8 @@ static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms); static int _sde_kms_mmu_init(struct sde_kms *sde_kms); static int _sde_kms_register_events(struct msm_kms *kms, struct drm_mode_object *obj, u32 event, bool en); +static void sde_kms_handle_power_event(u32 event_type, void *usr); + bool sde_is_custom_client(void) { return sdecustom; @@ -2218,14 +2220,38 @@ static int sde_kms_postinit(struct msm_kms *kms) struct sde_kms *sde_kms = to_sde_kms(kms); struct drm_device *dev; struct drm_crtc *crtc; - int rc; + struct msm_drm_private *priv; + int i, rc; - if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) { + if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev || + !sde_kms->dev->dev_private) { SDE_ERROR("invalid sde_kms\n"); return -EINVAL; } dev = sde_kms->dev; + priv = sde_kms->dev->dev_private; + + /* + * Handle (re)initializations during power enable, the sde power + * event call has to be after drm_irq_install to handle irq update. + */ + sde_kms_handle_power_event(SDE_POWER_EVENT_POST_ENABLE, sde_kms); + sde_kms->power_event = sde_power_handle_register_event(&priv->phandle, + SDE_POWER_EVENT_POST_ENABLE | + SDE_POWER_EVENT_PRE_DISABLE, + sde_kms_handle_power_event, sde_kms, "kms"); + + if (sde_kms->splash_data.num_splash_displays) { + SDE_DEBUG("Skipping MDP Resources disable\n"); + } else { + for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++) + sde_power_data_bus_set_quota(&priv->phandle, i, + SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA, + SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA); + + pm_runtime_put_sync(sde_kms->dev->dev); + } rc = _sde_debugfs_init(sde_kms); if (rc) @@ -4890,7 +4916,7 @@ static int sde_kms_hw_init(struct msm_kms *kms) struct drm_device *dev; struct msm_drm_private *priv; struct platform_device *platformdev; - int i, irq_num, rc = -EINVAL; + int irq_num, rc = -EINVAL; if (!kms) { SDE_ERROR("invalid kms\n"); @@ -4939,26 +4965,6 @@ static int sde_kms_hw_init(struct msm_kms *kms) */ dev->mode_config.allow_fb_modifiers = true; - /* - * Handle (re)initializations during power enable - */ - sde_kms_handle_power_event(SDE_POWER_EVENT_POST_ENABLE, sde_kms); - sde_kms->power_event = sde_power_handle_register_event(&priv->phandle, - SDE_POWER_EVENT_POST_ENABLE | - SDE_POWER_EVENT_PRE_DISABLE, - sde_kms_handle_power_event, sde_kms, "kms"); - - if (sde_kms->splash_data.num_splash_displays) { - SDE_DEBUG("Skipping MDP Resources disable\n"); - } else { - for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++) - sde_power_data_bus_set_quota(&priv->phandle, i, - SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA, - SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA); - - pm_runtime_put_sync(sde_kms->dev->dev); - } - sde_kms->affinity_notify.notify = sde_kms_irq_affinity_notify; sde_kms->affinity_notify.release = sde_kms_irq_affinity_release; From 5c291599a573924e5e1dc1b5417436703d9c68f2 Mon Sep 17 00:00:00 2001 From: Yahui Wang Date: Mon, 17 Jan 2022 16:53:25 +0800 Subject: [PATCH 2/3] disp: msm: sde: set NOAUTOEN for sde irq to match with power event If display cont-splash is enabled, then sde irq will be enabled after registration, but sde power event assumes irq to be disabled by default and will still try to enable irq with first power event call, then could cause unbalanced irq enable warning on boot up. Change-Id: Ic5482dd06501721664994f77cd5764140afb7a62 Signed-off-by: Yahui Wang --- msm/sde/sde_irq.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/msm/sde/sde_irq.c b/msm/sde/sde_irq.c index e8574156..5e970082 100644 --- a/msm/sde/sde_irq.c +++ b/msm/sde/sde_irq.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. */ @@ -101,7 +102,7 @@ void sde_irq_preinstall(struct msm_kms *kms) } /* disable irq until power event enables it */ - if (!sde_kms->splash_data.num_splash_displays && !sde_kms->irq_enabled) + if (!sde_kms->irq_enabled) irq_set_status_flags(sde_kms->irq_num, IRQ_NOAUTOEN); } From e55c68138b04770d51067c158f92de526e0c926e Mon Sep 17 00:00:00 2001 From: Veera Sundaram Sankaran Date: Fri, 25 Feb 2022 16:31:31 -0800 Subject: [PATCH 3/3] disp: msm: sde: fix the wd-timer-ctrl config for WD TE Avoid read/update for WD_TIMER_0_CTL2 register as the default value changed from MDSS 9.x.x to disable clock granularity and this leads to issues with VSYNC generation. Instead program the necessary configs directly. Change-Id: Id545ad772480f94cf432bff8e8bfeb2b679f8aa9 Signed-off-by: Veera Sundaram Sankaran --- msm/sde/sde_hw_intf.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/msm/sde/sde_hw_intf.c b/msm/sde/sde_hw_intf.c index 2c2f7481..786478e0 100644 --- a/msm/sde/sde_hw_intf.c +++ b/msm/sde/sde_hw_intf.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. */ @@ -459,7 +459,7 @@ static void sde_hw_intf_setup_vsync_source(struct sde_hw_intf *intf, u32 frame_rate) { struct sde_hw_blk_reg_map *c; - u32 reg; + u32 reg = 0; if (!intf) return; @@ -469,9 +469,9 @@ static void sde_hw_intf_setup_vsync_source(struct sde_hw_intf *intf, SDE_REG_WRITE(c, INTF_WD_TIMER_0_LOAD_VALUE, CALCULATE_WD_LOAD_VALUE(frame_rate)); SDE_REG_WRITE(c, INTF_WD_TIMER_0_CTL, BIT(0)); /* clear timer */ - reg = SDE_REG_READ(c, INTF_WD_TIMER_0_CTL2); reg |= BIT(8); /* enable heartbeat timer */ reg |= BIT(0); /* enable WD timer */ + reg |= BIT(1); /* select default 16 clock ticks */ SDE_REG_WRITE(c, INTF_WD_TIMER_0_CTL2, reg); /* make sure that timers are enabled/disabled for vsync state */