142 lines
4.2 KiB
C
Executable File
142 lines
4.2 KiB
C
Executable File
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
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*/
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#ifndef SDE_ROTATOR_R1_HWIO_H
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#define SDE_ROTATOR_R1_HWIO_H
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#include <linux/bitops.h>
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#define SDE_MDP_FETCH_CONFIG_RESET_VALUE 0x00000087
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#define SDE_MDP_REG_HW_VERSION 0x0
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#define SDE_MDP_REG_INTR_EN 0x00010
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#define SDE_MDP_REG_INTR_STATUS 0x00014
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#define SDE_MDP_REG_INTR_CLEAR 0x00018
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#define SDE_MDP_INTR_WB_0_DONE BIT(0)
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#define SDE_MDP_INTR_WB_1_DONE BIT(1)
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enum mdss_mdp_intr_type {
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SDE_MDP_IRQ_WB_ROT_COMP = 0,
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SDE_MDP_IRQ_WB_WFD = 4,
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SDE_MDP_IRQ_PING_PONG_COMP = 8,
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SDE_MDP_IRQ_PING_PONG_RD_PTR = 12,
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SDE_MDP_IRQ_PING_PONG_WR_PTR = 16,
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SDE_MDP_IRQ_PING_PONG_AUTO_REF = 20,
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SDE_MDP_IRQ_INTF_UNDER_RUN = 24,
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SDE_MDP_IRQ_INTF_VSYNC = 25,
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};
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enum mdss_mdp_ctl_index {
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SDE_MDP_CTL0,
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SDE_MDP_CTL1,
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SDE_MDP_CTL2,
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SDE_MDP_CTL3,
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SDE_MDP_CTL4,
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SDE_MDP_CTL5,
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SDE_MDP_MAX_CTL
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};
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#define SDE_MDP_REG_CTL_LAYER(lm) \
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((lm == 5) ? (0x024) : ((lm) * 0x004))
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#define SDE_MDP_REG_CTL_TOP 0x014
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#define SDE_MDP_REG_CTL_FLUSH 0x018
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#define SDE_MDP_REG_CTL_START 0x01C
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#define SDE_MDP_CTL_OP_ROT0_MODE 0x1
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#define SDE_MDP_CTL_OP_ROT1_MODE 0x2
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enum sde_mdp_sspp_index {
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SDE_MDP_SSPP_VIG0,
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SDE_MDP_SSPP_VIG1,
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SDE_MDP_SSPP_VIG2,
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SDE_MDP_SSPP_RGB0,
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SDE_MDP_SSPP_RGB1,
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SDE_MDP_SSPP_RGB2,
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SDE_MDP_SSPP_DMA0,
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SDE_MDP_SSPP_DMA1,
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SDE_MDP_SSPP_VIG3,
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SDE_MDP_SSPP_RGB3,
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SDE_MDP_SSPP_CURSOR0,
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SDE_MDP_SSPP_CURSOR1,
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SDE_MDP_MAX_SSPP
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};
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#define SDE_MDP_REG_SSPP_SRC_SIZE 0x000
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#define SDE_MDP_REG_SSPP_SRC_IMG_SIZE 0x004
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#define SDE_MDP_REG_SSPP_SRC_XY 0x008
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#define SDE_MDP_REG_SSPP_OUT_SIZE 0x00C
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#define SDE_MDP_REG_SSPP_OUT_XY 0x010
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#define SDE_MDP_REG_SSPP_SRC0_ADDR 0x014
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#define SDE_MDP_REG_SSPP_SRC1_ADDR 0x018
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#define SDE_MDP_REG_SSPP_SRC2_ADDR 0x01C
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#define SDE_MDP_REG_SSPP_SRC3_ADDR 0x020
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#define SDE_MDP_REG_SSPP_SRC_YSTRIDE0 0x024
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#define SDE_MDP_REG_SSPP_SRC_YSTRIDE1 0x028
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#define SDE_MDP_REG_SSPP_STILE_FRAME_SIZE 0x02C
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#define SDE_MDP_REG_SSPP_SRC_FORMAT 0x030
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#define SDE_MDP_REG_SSPP_SRC_UNPACK_PATTERN 0x034
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#define SDE_MDP_REG_SSPP_SRC_CONSTANT_COLOR 0x03C
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#define SDE_MDP_REG_SSPP_REQPRIO_FIFO_WM_0 0x050
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#define SDE_MDP_REG_SSPP_REQPRIO_FIFO_WM_1 0x054
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#define SDE_MDP_REG_SSPP_REQPRIO_FIFO_WM_2 0x058
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#define SDE_MDP_REG_SSPP_DANGER_LUT 0x060
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#define SDE_MDP_REG_SSPP_SAFE_LUT 0x064
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#define SDE_MDP_REG_SSPP_CREQ_LUT 0x068
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#define SDE_MDP_REG_SSPP_QOS_CTRL 0x06C
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#define SDE_MDP_REG_SSPP_CDP_CTRL 0x134
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#define SDE_MDP_REG_SSPP_UBWC_ERROR_STATUS 0x138
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#define SDE_MDP_REG_SSPP_SRC_OP_MODE 0x038
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#define SDE_MDP_OP_FLIP_UD BIT(14)
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#define SDE_MDP_OP_FLIP_LR BIT(13)
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#define SDE_MDP_OP_BWC_EN BIT(0)
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#define SDE_MDP_OP_BWC_LOSSLESS (0 << 1)
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#define SDE_MDP_OP_BWC_Q_HIGH (1 << 1)
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#define SDE_MDP_OP_BWC_Q_MED (2 << 1)
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#define SDE_MDP_REG_SSPP_SRC_CONSTANT_COLOR 0x03C
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#define SDE_MDP_REG_SSPP_FETCH_CONFIG 0x048
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#define SDE_MDP_REG_SSPP_VC1_RANGE 0x04C
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#define SDE_MDP_REG_SSPP_SRC_ADDR_SW_STATUS 0x070
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#define SDE_MDP_REG_SSPP_CURRENT_SRC0_ADDR 0x0A4
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#define SDE_MDP_REG_SSPP_CURRENT_SRC1_ADDR 0x0A8
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#define SDE_MDP_REG_SSPP_CURRENT_SRC2_ADDR 0x0AC
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#define SDE_MDP_REG_SSPP_CURRENT_SRC3_ADDR 0x0B0
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#define SDE_MDP_REG_SSPP_DECIMATION_CONFIG 0x0B4
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enum sde_mdp_mixer_wb_index {
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SDE_MDP_WB_LAYERMIXER0,
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SDE_MDP_WB_LAYERMIXER1,
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SDE_MDP_WB_MAX_LAYERMIXER,
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};
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enum mdss_mdp_writeback_index {
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SDE_MDP_WRITEBACK0,
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SDE_MDP_WRITEBACK1,
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SDE_MDP_WRITEBACK2,
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SDE_MDP_WRITEBACK3,
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SDE_MDP_WRITEBACK4,
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SDE_MDP_MAX_WRITEBACK
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};
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#define SDE_MDP_REG_WB_DST_FORMAT 0x000
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#define SDE_MDP_REG_WB_DST_OP_MODE 0x004
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#define SDE_MDP_REG_WB_DST_PACK_PATTERN 0x008
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#define SDE_MDP_REG_WB_DST0_ADDR 0x00C
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#define SDE_MDP_REG_WB_DST1_ADDR 0x010
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#define SDE_MDP_REG_WB_DST2_ADDR 0x014
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#define SDE_MDP_REG_WB_DST3_ADDR 0x018
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#define SDE_MDP_REG_WB_DST_YSTRIDE0 0x01C
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#define SDE_MDP_REG_WB_DST_YSTRIDE1 0x020
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#define SDE_MDP_REG_WB_DST_WRITE_CONFIG 0x048
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#define SDE_MDP_REG_WB_ROTATION_DNSCALER 0x050
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#define SDE_MDP_REG_WB_ROTATOR_PIPE_DOWNSCALER 0x054
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#define SDE_MDP_REG_WB_OUT_SIZE 0x074
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#define SDE_MDP_REG_WB_ALPHA_X_VALUE 0x078
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#define SDE_MDP_REG_WB_DST_ADDR_SW_STATUS 0x2B0
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#endif
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