From 6931fe14326929168f1edde5ef3b3dc33bb660c7 Mon Sep 17 00:00:00 2001 From: Anaadi Mishra Date: Wed, 1 Nov 2023 20:54:51 +0530 Subject: [PATCH] clk: qcom: gpucc: Add support for FREQUENCY LIMITER reset for CROW Add support for the consumer to be able to set/reset the GPU_CC_FREQUENCY_LIMITER_IRQ_CLEAR register as an when required. Change-Id: I631404203558751bda442cd59684e382bb8e3120 Signed-off-by: Anaadi Mishra --- drivers/clk/qcom/gpucc-crow.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/qcom/gpucc-crow.c b/drivers/clk/qcom/gpucc-crow.c index b40a3efbe2fe..9df63f9770c0 100644 --- a/drivers/clk/qcom/gpucc-crow.c +++ b/drivers/clk/qcom/gpucc-crow.c @@ -567,6 +567,7 @@ static const struct qcom_reset_map gpu_cc_crow_resets[] = { [GPUCC_GPU_CC_GX_BCR] = { 0x9058 }, [GPUCC_GPU_CC_RBCPR_BCR] = { 0x91e0 }, [GPUCC_GPU_CC_XO_BCR] = { 0x9000 }, + [GPUCC_GPU_CC_FREQUENCY_LIMITER_IRQ_CLEAR] = { 0x9538 }, }; static const struct regmap_config gpu_cc_crow_regmap_config = { @@ -605,6 +606,9 @@ static int gpu_cc_crow_probe(struct platform_device *pdev) clk_lucid_ole_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); clk_lucid_ole_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); + /* Enable frequency limiter irq */ + regmap_write(regmap, 0x9534, 0x0); + /* * Keep clocks always enabled: * gpu_cc_cxo_aon_clk