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Change-Id: Iae3c91f87a61bf09804ad893a3564bded87f6a18
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Android Build Coastguard Worker
2021-09-15 00:00:21 +00:00
parent 5f052f1180 a05466ceab
commit 3115a2d7df
3657 changed files with 230031 additions and 105656 deletions
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10
Documentation/ABI/testing/configfs-usb-gadget-uac1
View File

@@ -8,9 +8,19 @@ Description:
c_chmask capture channel mask
c_srate capture sampling rate
c_ssize capture sample size (bytes)
c_mute_present capture mute control enable
c_volume_present capture volume control enable
c_volume_min capture volume control min value (in 1/256 dB)
c_volume_max capture volume control max value (in 1/256 dB)
c_volume_res capture volume control resolution (in 1/256 dB)
p_chmask playback channel mask
p_srate playback sampling rate
p_ssize playback sample size (bytes)
p_mute_present playback mute control enable
p_volume_present playback volume control enable
p_volume_min playback volume control min value (in 1/256 dB)
p_volume_max playback volume control max value (in 1/256 dB)
p_volume_res playback volume control resolution (in 1/256 dB)
req_number the number of pre-allocated request
for both capture and playback
========== ===================================

10
Documentation/ABI/testing/configfs-usb-gadget-uac2
View File

@@ -9,8 +9,18 @@ Description:
c_srate capture sampling rate
c_ssize capture sample size (bytes)
c_sync capture synchronization type (async/adaptive)
c_mute_present capture mute control enable
c_volume_present capture volume control enable
c_volume_min capture volume control min value (in 1/256 dB)
c_volume_max capture volume control max value (in 1/256 dB)
c_volume_res capture volume control resolution (in 1/256 dB)
fb_max maximum extra bandwidth in async mode
p_chmask playback channel mask
p_srate playback sampling rate
p_ssize playback sample size (bytes)
p_mute_present playback mute control enable
p_volume_present playback volume control enable
p_volume_min playback volume control min value (in 1/256 dB)
p_volume_max playback volume control max value (in 1/256 dB)
p_volume_res playback volume control resolution (in 1/256 dB)
========= ============================

31
Documentation/ABI/testing/sysfs-bus-iio-chemical-sgp40 Normal file
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@@ -0,0 +1,31 @@
What: /sys/bus/iio/devices/iio:deviceX/out_temp_raw
Date: August 2021
KernelVersion: 5.15
Contact: Andreas Klinger <ak@it-klinger.de>
Description:
Set the temperature. This value is sent to the sensor for
temperature compensation.
Default value: 25000 (25 °C)
What: /sys/bus/iio/devices/iio:deviceX/out_humidityrelative_raw
Date: August 2021
KernelVersion: 5.15
Contact: Andreas Klinger <ak@it-klinger.de>
Description:
Set the relative humidity. This value is sent to the sensor for
humidity compensation.
Default value: 50000 (50 % relative humidity)
What: /sys/bus/iio/devices/iio:deviceX/in_resistance_calibbias
Date: August 2021
KernelVersion: 5.15
Contact: Andreas Klinger <ak@it-klinger.de>
Description:
Set the bias value for the resistance which is used for
calculation of in_concentration_input as follows:
x = (in_resistance_raw - in_resistance_calibbias) * 0.65
in_concentration_input = 500 / (1 + e^x)
Default value: 30000

26
Documentation/ABI/testing/sysfs-devices-system-cpu
View File

@@ -494,6 +494,15 @@ Description: AArch64 CPU registers
'identification' directory exposes the CPU ID registers for
identifying model and revision of the CPU.
What: /sys/devices/system/cpu/aarch32_el0
Date: May 2021
Contact: Linux ARM Kernel Mailing list <linux-arm-kernel@lists.infradead.org>
Description: Identifies the subset of CPUs in the system that can execute
AArch32 (32-bit ARM) applications. If present, the same format as
/sys/devices/system/cpu/{offline,online,possible,present} is used.
If absent, then all or none of the CPUs can execute AArch32
applications and execve() will behave accordingly.
What: /sys/devices/system/cpu/cpu#/cpu_capacity
Date: December 2016
Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
@@ -640,3 +649,20 @@ Description: SPURR ticks for cpuX when it was idle.
This sysfs interface exposes the number of SPURR ticks
for cpuX when it was idle.
What: /sys/devices/system/cpu/cpuX/mte_tcf_preferred
Date: July 2021
Contact: Linux ARM Kernel Mailing list <linux-arm-kernel@lists.infradead.org>
Description: Preferred MTE tag checking mode
When a user program specifies more than one MTE tag checking
mode, this sysfs node is used to specify which mode should
be preferred when scheduling a task on that CPU. Possible
values:
================ ==============================================
"sync" Prefer synchronous mode
"async" Prefer asynchronous mode
================ ==============================================
See also: Documentation/arm64/memory-tagging-extension.rst

24
Documentation/ABI/testing/sysfs-kernel-dmabuf-buffers Normal file
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@@ -0,0 +1,24 @@
What: /sys/kernel/dmabuf/buffers
Date: May 2021
KernelVersion: v5.13
Contact: Hridya Valsaraju <hridya@google.com>
Description: The /sys/kernel/dmabuf/buffers directory contains a
snapshot of the internal state of every DMA-BUF.
/sys/kernel/dmabuf/buffers/<inode_number> will contain the
statistics for the DMA-BUF with the unique inode number
<inode_number>
Users: kernel memory tuning/debugging tools
What: /sys/kernel/dmabuf/buffers/<inode_number>/exporter_name
Date: May 2021
KernelVersion: v5.13
Contact: Hridya Valsaraju <hridya@google.com>
Description: This file is read-only and contains the name of the exporter of
the DMA-BUF.
What: /sys/kernel/dmabuf/buffers/<inode_number>/size
Date: May 2021
KernelVersion: v5.13
Contact: Hridya Valsaraju <hridya@google.com>
Description: This file is read-only and specifies the size of the DMA-BUF in
bytes.

10
Documentation/admin-guide/cputopology.rst
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@@ -58,9 +58,9 @@ source for the output is in brackets ("[]").
[NR_CPUS-1]
offline: CPUs that are not online because they have been
HOTPLUGGED off (see cpu-hotplug.txt) or exceed the limit
of CPUs allowed by the kernel configuration (kernel_max
above). [~cpu_online_mask + cpus >= NR_CPUS]
HOTPLUGGED off or exceed the limit of CPUs allowed by the
kernel configuration (kernel_max above).
[~cpu_online_mask + cpus >= NR_CPUS]
online: CPUs that are online and being scheduled [cpu_online_mask]
@@ -96,5 +96,5 @@ online.)::
possible: 0-127
present: 0-3
See cpu-hotplug.txt for the possible_cpus=NUM kernel start parameter
as well as more information on the various cpumasks.
See Documentation/core-api/cpu_hotplug.rst for the possible_cpus=NUM
kernel start parameter as well as more information on the various cpumasks.

10
Documentation/admin-guide/hw-vuln/core-scheduling.rst
View File

@@ -181,10 +181,12 @@ Open cross-HT issues that core scheduling does not solve
--------------------------------------------------------
1. For MDS
~~~~~~~~~~
Core scheduling cannot protect against MDS attacks between an HT running in
user mode and another running in kernel mode. Even though both HTs run tasks
which trust each other, kernel memory is still considered untrusted. Such
attacks are possible for any combination of sibling CPU modes (host or guest mode).
Core scheduling cannot protect against MDS attacks between the siblings
running in user mode and the others running in kernel mode. Even though all
siblings run tasks which trust each other, when the kernel is executing
code on behalf of a task, it cannot trust the code running in the
sibling. Such attacks are possible for any combination of sibling CPU modes
(host or guest mode).
2. For L1TF
~~~~~~~~~~~

23
Documentation/admin-guide/kernel-parameters.txt
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@@ -287,6 +287,17 @@
do not want to use tracing_snapshot_alloc() as it needs
to be done where GFP_KERNEL allocations are allowed.
allow_mismatched_32bit_el0 [ARM64]
Allow execve() of 32-bit applications and setting of the
PER_LINUX32 personality on systems where only a strict
subset of the CPUs support 32-bit EL0. When this
parameter is present, the set of CPUs supporting 32-bit
EL0 is indicated by /sys/devices/system/cpu/aarch32_el0
and hot-unplug operations may be restricted.
See Documentation/arm64/asymmetric-32bit.rst for more
information.
amd_iommu= [HW,X86-64]
Pass parameters to the AMD IOMMU driver in the system.
Possible values are:
@@ -380,6 +391,9 @@
arm64.nopauth [ARM64] Unconditionally disable Pointer Authentication
support
arm64.nomte [ARM64] Unconditionally disable Memory Tagging Extension
support
ataflop= [HW,M68k]
atarimouse= [HW,MOUSE] Atari Mouse
@@ -4188,6 +4202,15 @@
Format: <bool> (1/Y/y=enable, 0/N/n=disable)
default: disabled
printk.console_no_auto_verbose=
Disable console loglevel raise on oops, panic
or lockdep-detected issues (only if lock debug is on).
With an exception to setups with low baudrate on
serial console, keeping this 0 is a good choice
in order to provide more debug information.
Format: <bool>
default: 0 (auto_verbose is enabled)
printk.devkmsg={on,off,ratelimit}
Control writing to /dev/kmsg.
on - unlimited logging to /dev/kmsg from userspace

16
Documentation/admin-guide/sysctl/vm.rst
View File

@@ -37,7 +37,6 @@ Currently, these files are in /proc/sys/vm:
- dirty_writeback_centisecs
- drop_caches
- extfrag_threshold
- extra_free_kbytes
- highmem_is_dirtyable
- hugetlb_shm_group
- laptop_mode
@@ -300,21 +299,6 @@ only use the low memory and they can fill it up with dirty data without
any throttling.
extra_free_kbytes
This parameter tells the VM to keep extra free memory between the threshold
where background reclaim (kswapd) kicks in, and the threshold where direct
reclaim (by allocating processes) kicks in.
This is useful for workloads that require low latency memory allocations
and have a bounded burstiness in memory allocations, for example a
realtime application that receives and transmits network traffic
(causing in-kernel memory allocations) with a maximum total message burst
size of 200MB may need 200MB of extra free memory to avoid direct reclaim
related latencies.
==============================================================
hugetlb_shm_group
=================

12
Documentation/admin-guide/sysrq.rst
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@@ -72,7 +72,7 @@ On PowerPC
On other
If you know of the key combos for other architectures, please
let me know so I can add them to this section.
submit a patch to be included in this section.
On all
Write a character to /proc/sysrq-trigger. e.g.::
@@ -205,10 +205,12 @@ frozen (probably root) filesystem via the FIFREEZE ioctl.
Sometimes SysRq seems to get 'stuck' after using it, what can I do?
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
That happens to me, also. I've found that tapping shift, alt, and control
on both sides of the keyboard, and hitting an invalid sysrq sequence again
will fix the problem. (i.e., something like :kbd:`alt-sysrq-z`). Switching to
another virtual console (:kbd:`ALT+Fn`) and then back again should also help.
When this happens, try tapping shift, alt and control on both sides of the
keyboard, and hitting an invalid sysrq sequence again. (i.e., something like
:kbd:`alt-sysrq-z`).
Switching to another virtual console (:kbd:`ALT+Fn`) and then back again
should also help.
I hit SysRq, but nothing seems to happen, what's wrong?
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

18
Documentation/arm/marvell.rst
View File

@@ -58,11 +58,19 @@ Kirkwood family
- Product Brief : https://web.archive.org/web/20120616201621/http://www.marvell.com/embedded-processors/kirkwood/assets/88F6180-003_ver1.pdf
- Hardware Spec : https://web.archive.org/web/20130730091654/http://www.marvell.com/embedded-processors/kirkwood/assets/HW_88F6180_OpenSource.pdf
- Functional Spec: https://web.archive.org/web/20130730091033/http://www.marvell.com/embedded-processors/kirkwood/assets/FS_88F6180_9x_6281_OpenSource.pdf
- 88F6280
- Product Brief : https://web.archive.org/web/20130730091058/http://www.marvell.com/embedded-processors/kirkwood/assets/88F6280_SoC_PB-001.pdf
- 88F6281
- Product Brief : https://web.archive.org/web/20120131133709/http://www.marvell.com/embedded-processors/kirkwood/assets/88F6281-004_ver1.pdf
- Hardware Spec : https://web.archive.org/web/20120620073511/http://www.marvell.com/embedded-processors/kirkwood/assets/HW_88F6281_OpenSource.pdf
- Functional Spec: https://web.archive.org/web/20130730091033/http://www.marvell.com/embedded-processors/kirkwood/assets/FS_88F6180_9x_6281_OpenSource.pdf
- 88F6321
- 88F6322
- 88F6323
- Product Brief : https://web.archive.org/web/20120616201639/http://www.marvell.com/embedded-processors/kirkwood/assets/88f632x_pb.pdf
Homepage:
https://web.archive.org/web/20160513194943/http://www.marvell.com/embedded-processors/kirkwood/
Core:
@@ -89,6 +97,10 @@ Discovery family
- MV76100
- Product Brief : https://web.archive.org/web/20140722064429/http://www.marvell.com/embedded-processors/discovery-innovation/assets/MV76100-002_WEB.pdf
- Hardware Spec : https://web.archive.org/web/20140722064425/http://www.marvell.com/embedded-processors/discovery-innovation/assets/HW_MV76100_OpenSource.pdf
- Functional Spec: https://web.archive.org/web/20111110081125/http://www.marvell.com/embedded-processors/discovery-innovation/assets/FS_MV76100_78100_78200_OpenSource.pdf
Not supported by the Linux kernel.
Core:
@@ -124,17 +136,23 @@ EBU Armada family
Armada 38x Flavors:
- 88F6810 Armada 380
- 88F6811 Armada 381
- 88F6821 Armada 382
- 88F6W21 Armada 383
- 88F6820 Armada 385
- 88F6828 Armada 388
- Product infos: https://web.archive.org/web/20181006144616/http://www.marvell.com/embedded-processors/armada-38x/
- Functional Spec: https://web.archive.org/web/20200420191927/https://www.marvell.com/content/dam/marvell/en/public-collateral/embedded-processors/marvell-embedded-processors-armada-38x-functional-specifications-2015-11.pdf
- Hardware Spec: https://web.archive.org/web/20180713105318/https://www.marvell.com/docs/embedded-processors/assets/marvell-embedded-processors-armada-38x-hardware-specifications-2017-03.pdf
- Design guide: https://web.archive.org/web/20180712231737/https://www.marvell.com/docs/embedded-processors/assets/marvell-embedded-processors-armada-38x-hardware-design-guide-2017-08.pdf
Core:
ARM Cortex-A9
Armada 39x Flavors:
- 88F6920 Armada 390
- 88F6925 Armada 395
- 88F6928 Armada 398
- Product infos: https://web.archive.org/web/20181020222559/http://www.marvell.com/embedded-processors/armada-39x/

155
Documentation/arm64/asymmetric-32bit.rst Normal file
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@@ -0,0 +1,155 @@
======================
Asymmetric 32-bit SoCs
======================
Author: Will Deacon <will@kernel.org>
This document describes the impact of asymmetric 32-bit SoCs on the
execution of 32-bit (``AArch32``) applications.
Date: 2021-05-17
Introduction
============
Some Armv9 SoCs suffer from a big.LITTLE misfeature where only a subset
of the CPUs are capable of executing 32-bit user applications. On such
a system, Linux by default treats the asymmetry as a "mismatch" and
disables support for both the ``PER_LINUX32`` personality and
``execve(2)`` of 32-bit ELF binaries, with the latter returning
``-ENOEXEC``. If the mismatch is detected during late onlining of a
64-bit-only CPU, then the onlining operation fails and the new CPU is
unavailable for scheduling.
Surprisingly, these SoCs have been produced with the intention of
running legacy 32-bit binaries. Unsurprisingly, that doesn't work very
well with the default behaviour of Linux.
It seems inevitable that future SoCs will drop 32-bit support
altogether, so if you're stuck in the unenviable position of needing to
run 32-bit code on one of these transitionary platforms then you would
be wise to consider alternatives such as recompilation, emulation or
retirement. If neither of those options are practical, then read on.
Enabling kernel support
=======================
Since the kernel support is not completely transparent to userspace,
allowing 32-bit tasks to run on an asymmetric 32-bit system requires an
explicit "opt-in" and can be enabled by passing the
``allow_mismatched_32bit_el0`` parameter on the kernel command-line.
For the remainder of this document we will refer to an *asymmetric
system* to mean an asymmetric 32-bit SoC running Linux with this kernel
command-line option enabled.
Userspace impact
================
32-bit tasks running on an asymmetric system behave in mostly the same
way as on a homogeneous system, with a few key differences relating to
CPU affinity.
sysfs
-----
The subset of CPUs capable of running 32-bit tasks is described in
``/sys/devices/system/cpu/aarch32_el0`` and is documented further in
``Documentation/ABI/testing/sysfs-devices-system-cpu``.
**Note:** CPUs are advertised by this file as they are detected and so
late-onlining of 32-bit-capable CPUs can result in the file contents
being modified by the kernel at runtime. Once advertised, CPUs are never
removed from the file.
``execve(2)``
-------------
On a homogeneous system, the CPU affinity of a task is preserved across
``execve(2)``. This is not always possible on an asymmetric system,
specifically when the new program being executed is 32-bit yet the
affinity mask contains 64-bit-only CPUs. In this situation, the kernel
determines the new affinity mask as follows:
1. If the 32-bit-capable subset of the affinity mask is not empty,
then the affinity is restricted to that subset and the old affinity
mask is saved. This saved mask is inherited over ``fork(2)`` and
preserved across ``execve(2)`` of 32-bit programs.
**Note:** This step does not apply to ``SCHED_DEADLINE`` tasks.
See `SCHED_DEADLINE`_.
2. Otherwise, the cpuset hierarchy of the task is walked until an
ancestor is found containing at least one 32-bit-capable CPU. The
affinity of the task is then changed to match the 32-bit-capable
subset of the cpuset determined by the walk.
3. On failure (i.e. out of memory), the affinity is changed to the set
of all 32-bit-capable CPUs of which the kernel is aware.
A subsequent ``execve(2)`` of a 64-bit program by the 32-bit task will
invalidate the affinity mask saved in (1) and attempt to restore the CPU
affinity of the task using the saved mask if it was previously valid.
This restoration may fail due to intervening changes to the deadline
policy or cpuset hierarchy, in which case the ``execve(2)`` continues
with the affinity unchanged.
Calls to ``sched_setaffinity(2)`` for a 32-bit task will consider only
the 32-bit-capable CPUs of the requested affinity mask. On success, the
affinity for the task is updated and any saved mask from a prior
``execve(2)`` is invalidated.
``SCHED_DEADLINE``
------------------
Explicit admission of a 32-bit deadline task to the default root domain
(e.g. by calling ``sched_setattr(2)``) is rejected on an asymmetric
32-bit system unless admission control is disabled by writing -1 to
``/proc/sys/kernel/sched_rt_runtime_us``.
``execve(2)`` of a 32-bit program from a 64-bit deadline task will
return ``-ENOEXEC`` if the root domain for the task contains any
64-bit-only CPUs and admission control is enabled. Concurrent offlining
of 32-bit-capable CPUs may still necessitate the procedure described in
`execve(2)`_, in which case step (1) is skipped and a warning is
emitted on the console.
**Note:** It is recommended that a set of 32-bit-capable CPUs are placed
into a separate root domain if ``SCHED_DEADLINE`` is to be used with
32-bit tasks on an asymmetric system. Failure to do so is likely to
result in missed deadlines.
Cpusets
-------
The affinity of a 32-bit task on an asymmetric system may include CPUs
that are not explicitly allowed by the cpuset to which it is attached.
This can occur as a result of the following two situations:
- A 64-bit task attached to a cpuset which allows only 64-bit CPUs
executes a 32-bit program.
- All of the 32-bit-capable CPUs allowed by a cpuset containing a
32-bit task are offlined.
In both of these cases, the new affinity is calculated according to step
(2) of the process described in `execve(2)`_ and the cpuset hierarchy is
unchanged irrespective of the cgroup version.
CPU hotplug
-----------
On an asymmetric system, the first detected 32-bit-capable CPU is
prevented from being offlined by userspace and any such attempt will
return ``-EPERM``. Note that suspend is still permitted even if the
primary CPU (i.e. CPU 0) is 64-bit-only.
KVM
---
Although KVM will not advertise 32-bit EL0 support to any vCPUs on an
asymmetric system, a broken guest at EL1 could still attempt to execute
32-bit code at EL0. In this case, an exit from a vCPU thread in 32-bit
mode will return to host userspace with an ``exit_reason`` of
``KVM_EXIT_FAIL_ENTRY`` and will remain non-runnable until successfully
re-initialised by a subsequent ``KVM_ARM_VCPU_INIT`` operation.

37
Documentation/arm64/booting.rst
View File

@@ -207,10 +207,17 @@ Before jumping into the kernel, the following conditions must be met:
software at a higher exception level to prevent execution in an UNKNOWN
state.
- SCR_EL3.FIQ must have the same value across all CPUs the kernel is
executing on.
- The value of SCR_EL3.FIQ must be the same as the one present at boot
time whenever the kernel is executing.
For all systems:
- If EL3 is present:
- SCR_EL3.FIQ must have the same value across all CPUs the kernel is
executing on.
- The value of SCR_EL3.FIQ must be the same as the one present at boot
time whenever the kernel is executing.
- If EL3 is present and the kernel is entered at EL2:
- SCR_EL3.HCE (bit 8) must be initialised to 0b1.
For systems with a GICv3 interrupt controller to be used in v3 mode:
- If EL3 is present:
@@ -311,6 +318,28 @@ Before jumping into the kernel, the following conditions must be met:
- ZCR_EL2.LEN must be initialised to the same value for all CPUs the
kernel will execute on.
For CPUs with the Scalable Matrix Extension (FEAT_SME):
- If EL3 is present:
- CPTR_EL3.ESM (bit 12) must be initialised to 0b1.
- SCR_EL3.EnTP2 (bit 41) must be initialised to 0b1.
- SMCR_EL3.LEN must be initialised to the same value for all CPUs the
kernel will execute on.
- If the kernel is entered at EL1 and EL2 is present:
- CPTR_EL2.TSM (bit 12) must be initialised to 0b0.
- CPTR_EL2.SMEN (bits 25:24) must be initialised to 0b11.
- SCTLR_EL2.EnTP2 (bit 60) must be initialised to 0b1.
- SMCR_EL2.LEN must be initialised to the same value for all CPUs the
kernel will execute on.
The requirements described above for CPU mode, caches, MMUs, architected
timers, coherency and system registers apply to all CPUs. All CPUs must
enter the kernel in the same exception level. Where the values documented

1
Documentation/arm64/index.rst
View File

@@ -10,6 +10,7 @@ ARM64 Architecture
acpi_object_usage
amu
arm-acpi
asymmetric-32bit
booting
cpu-feature-registers
elf_hwcaps

48
Documentation/arm64/memory-tagging-extension.rst
View File

@@ -77,14 +77,20 @@ configurable behaviours:
address is unknown).
The user can select the above modes, per thread, using the
``prctl(PR_SET_TAGGED_ADDR_CTRL, flags, 0, 0, 0)`` system call where
``flags`` contain one of the following values in the ``PR_MTE_TCF_MASK``
``prctl(PR_SET_TAGGED_ADDR_CTRL, flags, 0, 0, 0)`` system call where ``flags``
contains any number of the following values in the ``PR_MTE_TCF_MASK``
bit-field:
- ``PR_MTE_TCF_NONE`` - *Ignore* tag check faults
- ``PR_MTE_TCF_NONE``  - *Ignore* tag check faults
(ignored if combined with other options)
- ``PR_MTE_TCF_SYNC`` - *Synchronous* tag check fault mode
- ``PR_MTE_TCF_ASYNC`` - *Asynchronous* tag check fault mode
If no modes are specified, tag check faults are ignored. If a single
mode is specified, the program will run in that mode. If multiple
modes are specified, the mode is selected as described in the "Per-CPU
preferred tag checking modes" section below.
The current tag check fault mode can be read using the
``prctl(PR_GET_TAGGED_ADDR_CTRL, 0, 0, 0, 0)`` system call.
@@ -120,13 +126,39 @@ in the ``PR_MTE_TAG_MASK`` bit-field.
interface provides an include mask. An include mask of ``0`` (exclusion
mask ``0xffff``) results in the CPU always generating tag ``0``.
Per-CPU preferred tag checking mode
-----------------------------------
On some CPUs the performance of MTE in stricter tag checking modes
is similar to that of less strict tag checking modes. This makes it
worthwhile to enable stricter checks on those CPUs when a less strict
checking mode is requested, in order to gain the error detection
benefits of the stricter checks without the performance downsides. To
support this scenario, a privileged user may configure a stricter
tag checking mode as the CPU's preferred tag checking mode.
The preferred tag checking mode for each CPU is controlled by
``/sys/devices/system/cpu/cpu<N>/mte_tcf_preferred``, to which a
privileged user may write the value ``async`` or ``sync``. The default
preferred mode for each CPU is ``async``.
To allow a program to potentially run in the CPU's preferred tag
checking mode, the user program may set multiple tag check fault mode
bits in the ``flags`` argument to the ``prctl(PR_SET_TAGGED_ADDR_CTRL,
flags, 0, 0, 0)`` system call. If the CPU's preferred tag checking
mode is in the task's set of provided tag checking modes (this will
always be the case at present because the kernel only supports two
tag checking modes, but future kernels may support more modes), that
mode will be selected. Otherwise, one of the modes in the task's mode
set will be selected in a currently unspecified manner.
Initial process state
---------------------
On ``execve()``, the new process has the following configuration:
- ``PR_TAGGED_ADDR_ENABLE`` set to 0 (disabled)
- Tag checking mode set to ``PR_MTE_TCF_NONE``
- No tag checking modes are selected (tag check faults ignored)
- ``PR_MTE_TAG_MASK`` set to 0 (all tags excluded)
- ``PSTATE.TCO`` set to 0
- ``PROT_MTE`` not set on any of the initial memory maps
@@ -251,11 +283,13 @@ Example of correct usage
return EXIT_FAILURE;
/*
* Enable the tagged address ABI, synchronous MTE tag check faults and
* allow all non-zero tags in the randomly generated set.
* Enable the tagged address ABI, synchronous or asynchronous MTE
* tag check faults (based on per-CPU preference) and allow all
* non-zero tags in the randomly generated set.
*/
if (prctl(PR_SET_TAGGED_ADDR_CTRL,
PR_TAGGED_ADDR_ENABLE | PR_MTE_TCF_SYNC | (0xfffe << PR_MTE_TAG_SHIFT),
PR_TAGGED_ADDR_ENABLE | PR_MTE_TCF_SYNC | PR_MTE_TCF_ASYNC |
(0xfffe << PR_MTE_TAG_SHIFT),
0, 0, 0)) {
perror("prctl() failed");
return EXIT_FAILURE;

121
Documentation/conf.py
View File

@@ -16,8 +16,6 @@ import sys
import os
import sphinx
from subprocess import check_output
# Get Sphinx version
major, minor, patch = sphinx.version_info[:3]
@@ -343,6 +341,9 @@ latex_elements = {
verbatimhintsturnover=false,
''',
# For CJK One-half spacing, need to be in front of hyperref
'extrapackages': r'\usepackage{setspace}',
# Additional stuff for the LaTeX preamble.
'preamble': '''
% Prevent column squeezing of tabulary.
@@ -355,29 +356,117 @@ latex_elements = {
''',
}
# At least one book (translations) may have Asian characters
# with are only displayed if xeCJK is used
# Translations have Asian (CJK) characters which are only displayed if
# xeCJK is used
cjk_cmd = check_output(['fc-list', '--format="%{family[0]}\n"']).decode('utf-8', 'ignore')
if cjk_cmd.find("Noto Sans CJK SC") >= 0:
latex_elements['preamble'] += '''
latex_elements['preamble'] += '''
\\IfFontExistsTF{Noto Sans CJK SC}{
% This is needed for translations
\\usepackage{xeCJK}
\\setCJKmainfont{Noto Sans CJK SC}
\\usepackage{xeCJK}
\\IfFontExistsTF{Noto Serif CJK SC}{
\\setCJKmainfont{Noto Serif CJK SC}[AutoFakeSlant]
}{
\\setCJKmainfont{Noto Sans CJK SC}[AutoFakeSlant]
}
\\setCJKsansfont{Noto Sans CJK SC}[AutoFakeSlant]
\\setCJKmonofont{Noto Sans Mono CJK SC}[AutoFakeSlant]
% CJK Language-specific font choices
\\IfFontExistsTF{Noto Serif CJK SC}{
\\newCJKfontfamily[SCmain]\\scmain{Noto Serif CJK SC}[AutoFakeSlant]
\\newCJKfontfamily[SCserif]\\scserif{Noto Serif CJK SC}[AutoFakeSlant]
}{
\\newCJKfontfamily[SCmain]\\scmain{Noto Sans CJK SC}[AutoFakeSlant]
\\newCJKfontfamily[SCserif]\\scserif{Noto Sans CJK SC}[AutoFakeSlant]
}
\\newCJKfontfamily[SCsans]\\scsans{Noto Sans CJK SC}[AutoFakeSlant]
\\newCJKfontfamily[SCmono]\\scmono{Noto Sans Mono CJK SC}[AutoFakeSlant]
\\IfFontExistsTF{Noto Serif CJK TC}{
\\newCJKfontfamily[TCmain]\\tcmain{Noto Serif CJK TC}[AutoFakeSlant]
\\newCJKfontfamily[TCserif]\\tcserif{Noto Serif CJK TC}[AutoFakeSlant]
}{
\\newCJKfontfamily[TCmain]\\tcmain{Noto Sans CJK TC}[AutoFakeSlant]
\\newCJKfontfamily[TCserif]\\tcserif{Noto Sans CJK TC}[AutoFakeSlant]
}
\\newCJKfontfamily[TCsans]\\tcsans{Noto Sans CJK TC}[AutoFakeSlant]
\\newCJKfontfamily[TCmono]\\tcmono{Noto Sans Mono CJK TC}[AutoFakeSlant]
\\IfFontExistsTF{Noto Serif CJK KR}{
\\newCJKfontfamily[KRmain]\\krmain{Noto Serif CJK KR}[AutoFakeSlant]
\\newCJKfontfamily[KRserif]\\krserif{Noto Serif CJK KR}[AutoFakeSlant]
}{
\\newCJKfontfamily[KRmain]\\krmain{Noto Sans CJK KR}[AutoFakeSlant]
\\newCJKfontfamily[KRserif]\\krserif{Noto Sans CJK KR}[AutoFakeSlant]
}
\\newCJKfontfamily[KRsans]\\krsans{Noto Sans CJK KR}[AutoFakeSlant]
\\newCJKfontfamily[KRmono]\\krmono{Noto Sans Mono CJK KR}[AutoFakeSlant]
\\IfFontExistsTF{Noto Serif CJK JP}{
\\newCJKfontfamily[JPmain]\\jpmain{Noto Serif CJK JP}[AutoFakeSlant]
\\newCJKfontfamily[JPserif]\\jpserif{Noto Serif CJK JP}[AutoFakeSlant]
}{
\\newCJKfontfamily[JPmain]\\jpmain{Noto Sans CJK JP}[AutoFakeSlant]
\\newCJKfontfamily[JPserif]\\jpserif{Noto Sans CJK JP}[AutoFakeSlant]
}
\\newCJKfontfamily[JPsans]\\jpsans{Noto Sans CJK JP}[AutoFakeSlant]
\\newCJKfontfamily[JPmono]\\jpmono{Noto Sans Mono CJK JP}[AutoFakeSlant]
% Dummy commands for Sphinx < 2.3 (no 'extrapackages' support)
\\providecommand{\\onehalfspacing}{}
\\providecommand{\\singlespacing}{}
% Define custom macros to on/off CJK
\\newcommand{\\kerneldocCJKon}{\\makexeCJKactive}
\\newcommand{\\kerneldocCJKoff}{\\makexeCJKinactive}
% To customize \sphinxtableofcontents
\\newcommand{\\kerneldocCJKon}{\\makexeCJKactive\\onehalfspacing}
\\newcommand{\\kerneldocCJKoff}{\\makexeCJKinactive\\singlespacing}
\\newcommand{\\kerneldocBeginSC}{%
\\begingroup%
\\scmain%
}
\\newcommand{\\kerneldocEndSC}{\\endgroup}
\\newcommand{\\kerneldocBeginTC}{%
\\begingroup%
\\tcmain%
\\renewcommand{\\CJKrmdefault}{TCserif}%
\\renewcommand{\\CJKsfdefault}{TCsans}%
\\renewcommand{\\CJKttdefault}{TCmono}%
}
\\newcommand{\\kerneldocEndTC}{\\endgroup}
\\newcommand{\\kerneldocBeginKR}{%
\\begingroup%
\\xeCJKDeclareCharClass{HalfLeft}{`“,`‘}%
\\xeCJKDeclareCharClass{HalfRight}{`”,`’}%
\\krmain%
\\renewcommand{\\CJKrmdefault}{KRserif}%
\\renewcommand{\\CJKsfdefault}{KRsans}%
\\renewcommand{\\CJKttdefault}{KRmono}%
\\xeCJKsetup{CJKspace = true} % For inter-phrase space
}
\\newcommand{\\kerneldocEndKR}{\\endgroup}
\\newcommand{\\kerneldocBeginJP}{%
\\begingroup%
\\xeCJKDeclareCharClass{HalfLeft}{`“,`‘}%
\\xeCJKDeclareCharClass{HalfRight}{`”,`’}%
\\jpmain%
\\renewcommand{\\CJKrmdefault}{JPserif}%
\\renewcommand{\\CJKsfdefault}{JPsans}%
\\renewcommand{\\CJKttdefault}{JPmono}%
}
\\newcommand{\\kerneldocEndJP}{\\endgroup}
% Single spacing in literal blocks
\\fvset{baselinestretch=1}
% To customize \\sphinxtableofcontents
\\usepackage{etoolbox}
% Inactivate CJK after tableofcontents
\\apptocmd{\\sphinxtableofcontents}{\\kerneldocCJKoff}{}{}
'''
else:
latex_elements['preamble'] += '''
}{ % No CJK font found
% Custom macros to on/off CJK (Dummy)
\\newcommand{\\kerneldocCJKon}{}
\\newcommand{\\kerneldocCJKoff}{}
'''
\\newcommand{\\kerneldocBeginSC}{}
\\newcommand{\\kerneldocEndSC}{}
\\newcommand{\\kerneldocBeginTC}{}
\\newcommand{\\kerneldocEndTC}{}
\\newcommand{\\kerneldocBeginKR}{}
\\newcommand{\\kerneldocEndKR}{}
\\newcommand{\\kerneldocBeginSC}{}
\\newcommand{\\kerneldocEndKR}{}
}
'''
# Fix reference escape troubles with Sphinx 1.4.x
if major == 1:

38
Documentation/core-api/cpu_hotplug.rst
View File

@@ -91,9 +91,10 @@ Never use anything other than ``cpumask_t`` to represent bitmap of CPUs.
Using CPU hotplug
=================
The kernel option *CONFIG_HOTPLUG_CPU* needs to be enabled. It is currently
available on multiple architectures including ARM, MIPS, PowerPC and X86. The
configuration is done via the sysfs interface: ::
configuration is done via the sysfs interface::
$ ls -lh /sys/devices/system/cpu
total 0
@@ -113,14 +114,14 @@ configuration is done via the sysfs interface: ::
The files *offline*, *online*, *possible*, *present* represent the CPU masks.
Each CPU folder contains an *online* file which controls the logical on (1) and
off (0) state. To logically shutdown CPU4: ::
off (0) state. To logically shutdown CPU4::
$ echo 0 > /sys/devices/system/cpu/cpu4/online
smpboot: CPU 4 is now offline
Once the CPU is shutdown, it will be removed from */proc/interrupts*,
*/proc/cpuinfo* and should also not be shown visible by the *top* command. To
bring CPU4 back online: ::
bring CPU4 back online::
$ echo 1 > /sys/devices/system/cpu/cpu4/online
smpboot: Booting Node 0 Processor 4 APIC 0x1
@@ -142,6 +143,7 @@ The CPU hotplug coordination
The offline case
----------------
Once a CPU has been logically shutdown the teardown callbacks of registered
hotplug states will be invoked, starting with ``CPUHP_ONLINE`` and terminating
at state ``CPUHP_OFFLINE``. This includes:
@@ -158,9 +160,10 @@ at state ``CPUHP_OFFLINE``. This includes:
Using the hotplug API
---------------------
It is possible to receive notifications once a CPU is offline or onlined. This
might be important to certain drivers which need to perform some kind of setup
or clean up functions based on the number of available CPUs: ::
or clean up functions based on the number of available CPUs::
#include <linux/cpuhotplug.h>
@@ -186,9 +189,10 @@ During the removal of a hotplug state the teardown callback will be invoked.
Multiple instances
~~~~~~~~~~~~~~~~~~
If a driver has multiple instances and each instance needs to perform the
callback independently then it is likely that a ''multi-state'' should be used.
First a multi-state state needs to be registered: ::
First a multi-state state needs to be registered::
ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, "X/Y:online,
Y_online, Y_prepare_down);
@@ -197,7 +201,7 @@ First a multi-state state needs to be registered: ::
The ``cpuhp_setup_state_multi()`` behaves similar to ``cpuhp_setup_state()``
except it prepares the callbacks for a multi state and does not invoke
the callbacks. This is a one time setup.
Once a new instance is allocated, you need to register this new instance: ::
Once a new instance is allocated, you need to register this new instance::
ret = cpuhp_state_add_instance(Y_hp_online, &d->node);
@@ -206,7 +210,8 @@ This function will add this instance to your previously allocated
(*Y_online*) on all online CPUs. The *node* element is a ``struct
hlist_node`` member of your per-instance data structure.
On removal of the instance: ::
On removal of the instance::
cpuhp_state_remove_instance(Y_hp_online, &d->node)
should be invoked which will invoke the teardown callback on all online
@@ -214,6 +219,7 @@ CPUs.
Manual setup
~~~~~~~~~~~~
Usually it is handy to invoke setup and teardown callbacks on registration or
removal of a state because usually the operation needs to performed once a CPU
goes online (offline) and during initial setup (shutdown) of the driver. However
@@ -226,6 +232,7 @@ hotplug operations.
The ordering of the events
--------------------------
The hotplug states are defined in ``include/linux/cpuhotplug.h``:
* The states *CPUHP_OFFLINE* … *CPUHP_AP_OFFLINE* are invoked before the
@@ -248,13 +255,14 @@ another hotplug event.
Testing of hotplug states
=========================
One way to verify whether a custom state is working as expected or not is to
shutdown a CPU and then put it online again. It is also possible to put the CPU
to certain state (for instance *CPUHP_AP_ONLINE*) and then go back to
*CPUHP_ONLINE*. This would simulate an error one state after *CPUHP_AP_ONLINE*
which would lead to rollback to the online state.
All registered states are enumerated in ``/sys/devices/system/cpu/hotplug/states``: ::
All registered states are enumerated in ``/sys/devices/system/cpu/hotplug/states`` ::
$ tail /sys/devices/system/cpu/hotplug/states
138: mm/vmscan:online
@@ -268,7 +276,7 @@ All registered states are enumerated in ``/sys/devices/system/cpu/hotplug/states
168: sched:active
169: online
To rollback CPU4 to ``lib/percpu_cnt:online`` and back online just issue: ::
To rollback CPU4 to ``lib/percpu_cnt:online`` and back online just issue::
$ cat /sys/devices/system/cpu/cpu4/hotplug/state
169
@@ -276,14 +284,14 @@ To rollback CPU4 to ``lib/percpu_cnt:online`` and back online just issue: ::
$ cat /sys/devices/system/cpu/cpu4/hotplug/state
140
It is important to note that the teardown callbac of state 140 have been
invoked. And now get back online: ::
It is important to note that the teardown callback of state 140 have been
invoked. And now get back online::
$ echo 169 > /sys/devices/system/cpu/cpu4/hotplug/target
$ cat /sys/devices/system/cpu/cpu4/hotplug/state
169
With trace events enabled, the individual steps are visible, too: ::
With trace events enabled, the individual steps are visible, too::
# TASK-PID CPU# TIMESTAMP FUNCTION
# | | | | |
@@ -318,6 +326,7 @@ trace.
Architecture's requirements
===========================
The following functions and configurations are required:
``CONFIG_HOTPLUG_CPU``
@@ -339,11 +348,12 @@ The following functions and configurations are required:
User Space Notification
=======================
After CPU successfully onlined or offline udev events are sent. A udev rule like: ::
After CPU successfully onlined or offline udev events are sent. A udev rule like::
SUBSYSTEM=="cpu", DRIVERS=="processor", DEVPATH=="/devices/system/cpu/*", RUN+="the_hotplug_receiver.sh"
will receive all events. A script like: ::
will receive all events. A script like::
#!/bin/sh

5
Documentation/core-api/printk-basics.rst
View File

@@ -107,9 +107,6 @@ also ``CONFIG_DYNAMIC_DEBUG`` in the case of pr_debug()) is defined.
Function reference
==================
.. kernel-doc:: kernel/printk/printk.c
:functions: printk
.. kernel-doc:: include/linux/printk.h
:functions: pr_emerg pr_alert pr_crit pr_err pr_warn pr_notice pr_info
:functions: printk pr_emerg pr_alert pr_crit pr_err pr_warn pr_notice pr_info
pr_fmt pr_debug pr_devel pr_cont

1
Documentation/core-api/printk-formats.rst
View File

@@ -130,6 +130,7 @@ printed after the symbol name with an extra ``b`` appended to the end of the
specifier.
::
%pS versatile_init+0x0/0x110 [module_name]
%pSb versatile_init+0x0/0x110 [module_name ed5019fdf5e53be37cb1ba7899292d7e143b259e]
%pSRb versatile_init+0x9/0x110 [module_name ed5019fdf5e53be37cb1ba7899292d7e143b259e]

2
Documentation/devicetree/bindings/Makefile
View File

@@ -28,7 +28,7 @@ find_cmd = find $(srctree)/$(src) \( -name '*.yaml' ! \
quiet_cmd_yamllint = LINT $(src)
cmd_yamllint = ($(find_cmd) | \
xargs $(DT_SCHEMA_LINT) -f parsable -c $(srctree)/$(src)/.yamllint) || true
xargs $(DT_SCHEMA_LINT) -f parsable -c $(srctree)/$(src)/.yamllint >&2) || true
quiet_cmd_chk_bindings = CHKDT $@
cmd_chk_bindings = ($(find_cmd) | \

5
Documentation/devicetree/bindings/arm/atmel-at91.yaml
View File

@@ -145,6 +145,11 @@ properties:
- const: atmel,sama5d4
- const: atmel,sama5
- items:
- const: microchip,sama7g5ek # SAMA7G5 Evaluation Kit
- const: microchip,sama7g5
- const: microchip,sama7
- items:
- enum:
- atmel,sams70j19

14
Documentation/devicetree/bindings/arm/atmel-sysregs.txt
View File

@@ -45,7 +45,8 @@ RAMC SDRAM/DDR Controller required properties:
"atmel,at91sam9260-sdramc",
"atmel,at91sam9g45-ddramc",
"atmel,sama5d3-ddramc",
"microchip,sam9x60-ddramc"
"microchip,sam9x60-ddramc",
"microchip,sama7g5-uddrc"
- reg: Should contain registers location and length
Examples:
@@ -55,6 +56,17 @@ Examples:
reg = <0xffffe800 0x200>;
};
RAMC PHY Controller required properties:
- compatible: Should be "microchip,sama7g5-ddr3phy", "syscon"
- reg: Should contain registers location and length
Example:
ddr3phy: ddr3phy@e3804000 {
compatible = "microchip,sama7g5-ddr3phy", "syscon";
reg = <0xe3804000 0x1000>;
};
SHDWC Shutdown Controller
required properties:

29
Documentation/devicetree/bindings/arm/fsl.yaml
View File

@@ -221,9 +221,13 @@ properties:
- prt,prti6q # Protonic PRTI6Q board
- prt,prtwd2 # Protonic WD2 board
- rex,imx6q-rex-pro # Rex Pro i.MX6 Quad Board
- skov,imx6q-skov-revc-lt2 # SKOV IMX6 CPU QuadCore lt2
- skov,imx6q-skov-revc-lt6 # SKOV IMX6 CPU QuadCore lt6
- skov,imx6q-skov-reve-mi1010ait-1cp1 # SKOV IMX6 CPU QuadCore mi1010ait-1cp1
- solidrun,cubox-i/q # SolidRun Cubox-i Dual/Quad
- solidrun,hummingboard/q
- solidrun,hummingboard2/q
- solidrun,solidsense/q # SolidRun SolidSense Dual/Quad
- tbs,imx6q-tbs2910 # TBS2910 Matrix ARM mini PC
- technexion,imx6q-pico-dwarf # TechNexion i.MX6Q Pico-Dwarf
- technexion,imx6q-pico-hobbit # TechNexion i.MX6Q Pico-Hobbit
@@ -377,9 +381,12 @@ properties:
- prt,prtvt7 # Protonic VT7 board
- rex,imx6dl-rex-basic # Rex Basic i.MX6 Dual Lite Board
- riot,imx6s-riotboard # RIoTboard i.MX6S
- skov,imx6dl-skov-revc-lt2 # SKOV IMX6 CPU SoloCore lt2
- skov,imx6dl-skov-revc-lt6 # SKOV IMX6 CPU SoloCore lt6
- solidrun,cubox-i/dl # SolidRun Cubox-i Solo/DualLite
- solidrun,hummingboard/dl
- solidrun,hummingboard2/dl # SolidRun HummingBoard2 Solo/DualLite
- solidrun,solidsense/dl # SolidRun SolidSense Solo/DualLite
- technexion,imx6dl-pico-dwarf # TechNexion i.MX6DL Pico-Dwarf
- technexion,imx6dl-pico-hobbit # TechNexion i.MX6DL Pico-Hobbit
- technexion,imx6dl-pico-nymph # TechNexion i.MX6DL Pico-Nymph
@@ -418,6 +425,12 @@ properties:
- const: dfi,fs700e-m60
- const: fsl,imx6dl
- description: i.MX6DL DHCOM PicoITX Board
items:
- const: dh,imx6dl-dhcom-picoitx
- const: dh,imx6dl-dhcom-som
- const: fsl,imx6dl
- description: i.MX6DL Gateworks Ventana Boards
items:
- enum:
@@ -469,6 +482,12 @@ properties:
- const: toradex,colibri_imx6dl # Colibri iMX6 Module
- const: fsl,imx6dl
- description: i.MX6S DHCOM DRC02 Board
items:
- const: dh,imx6s-dhcom-drc02
- const: dh,imx6s-dhcom-som
- const: fsl,imx6dl
- description: i.MX6SL based Boards
items:
- enum:
@@ -698,6 +717,7 @@ properties:
- gw,imx8mm-gw72xx-0x # i.MX8MM Gateworks Development Kit
- gw,imx8mm-gw73xx-0x # i.MX8MM Gateworks Development Kit
- gw,imx8mm-gw7901 # i.MX8MM Gateworks Board
- gw,imx8mm-gw7902 # i.MX8MM Gateworks Board
- kontron,imx8mm-n801x-som # i.MX8MM Kontron SL (N801X) SOM
- variscite,var-som-mx8mm # i.MX8MM Variscite VAR-SOM-MX8MM module
- const: fsl,imx8mm
@@ -728,6 +748,7 @@ properties:
- beacon,imx8mn-beacon-kit # i.MX8MN Beacon Development Kit
- fsl,imx8mn-ddr4-evk # i.MX8MN DDR4 EVK Board
- fsl,imx8mn-evk # i.MX8MN LPDDR4 EVK Board
- gw,imx8mn-gw7902 # i.MX8MM Gateworks Board
- const: fsl,imx8mn
- description: Variscite VAR-SOM-MX8MN based boards
@@ -752,10 +773,12 @@ properties:
items:
- enum:
- boundary,imx8mq-nitrogen8m # i.MX8MQ NITROGEN Board
- boundary,imx8mq-nitrogen8m-som # i.MX8MQ NITROGEN SoM
- einfochips,imx8mq-thor96 # i.MX8MQ Thor96 Board
- fsl,imx8mq-evk # i.MX8MQ EVK Board
- google,imx8mq-phanbell # Google Coral Edge TPU
- kontron,pitx-imx8m # Kontron pITX-imx8m Board
- mntre,reform2 # MNT Reform2 Laptop
- purism,librem5-devkit # Purism Librem5 devkit
- solidrun,hummingboard-pulse # SolidRun Hummingboard Pulse
- technexion,pico-pi-imx8m # TechNexion PICO-PI-8M evk
@@ -973,6 +996,12 @@ properties:
- fsl,s32v234-evb # S32V234-EVB2 Customer Evaluation Board
- const: fsl,s32v234
- description: Traverse LS1088A based Boards
items:
- enum:
- traverse,ten64 # Ten64 Networking Appliance / Board
- const: fsl,ls1088a
additionalProperties: true
...

108
Documentation/devicetree/bindings/arm/gemini.txt
View File

@@ -1,108 +0,0 @@
Cortina systems Gemini platforms
The Gemini SoC is the project name for an ARMv4 FA525-based SoC originally
produced by Storlink Semiconductor around 2005. The company was renamed
later renamed Storm Semiconductor. The chip product name is Storlink SL3516.
It was derived from earlier products from Storm named SL3316 (Centroid) and
SL3512 (Bulverde).
Storm Semiconductor was acquired by Cortina Systems in 2008 and the SoC was
produced and used for NAS and similar usecases. In 2014 Cortina Systems was
in turn acquired by Inphi, who seem to have discontinued this product family.
Many of the IP blocks used in the SoC comes from Faraday Technology.
Required properties (in root node):
compatible = "cortina,gemini";
Required nodes:
- soc: the SoC should be represented by a simple bus encompassing all the
onchip devices, this is referred to as the soc bus node.
- syscon: the soc bus node must have a system controller node pointing to the
global control registers, with the compatible string
"cortina,gemini-syscon", "syscon";
Required properties on the syscon:
- reg: syscon register location and size.
- #clock-cells: should be set to <1> - the system controller is also a
clock provider.
- #reset-cells: should be set to <1> - the system controller is also a
reset line provider.
The clock sources have shorthand defines in the include file:
<dt-bindings/clock/cortina,gemini-clock.h>
The reset lines have shorthand defines in the include file:
<dt-bindings/reset/cortina,gemini-reset.h>
- timer: the soc bus node must have a timer node pointing to the SoC timer
block, with the compatible string "cortina,gemini-timer"
See: clocksource/cortina,gemini-timer.txt
- interrupt-controller: the sob bus node must have an interrupt controller
node pointing to the SoC interrupt controller block, with the compatible
string "cortina,gemini-interrupt-controller"
See interrupt-controller/cortina,gemini-interrupt-controller.txt
Example:
/ {
model = "Foo Gemini Machine";
compatible = "cortina,gemini";
#address-cells = <1>;
#size-cells = <1>;
memory {
device_type = "memory";
reg = <0x00000000 0x8000000>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "simple-bus";
interrupt-parent = <&intcon>;
syscon: syscon@40000000 {
compatible = "cortina,gemini-syscon", "syscon";
reg = <0x40000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
uart0: serial@42000000 {
compatible = "ns16550a";
reg = <0x42000000 0x100>;
resets = <&syscon GEMINI_RESET_UART>;
clocks = <&syscon GEMINI_CLK_UART>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
};
timer@43000000 {
compatible = "cortina,gemini-timer";
reg = <0x43000000 0x1000>;
interrupt-parent = <&intcon>;
interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */
<15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */
<16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */
resets = <&syscon GEMINI_RESET_TIMER>;
/* APB clock or RTC clock */
clocks = <&syscon GEMINI_CLK_APB>,
<&syscon GEMINI_CLK_RTC>;
clock-names = "PCLK", "EXTCLK";
syscon = <&syscon>;
};
intcon: interrupt-controller@48000000 {
compatible = "cortina,gemini-interrupt-controller";
reg = <0x48000000 0x1000>;
resets = <&syscon GEMINI_RESET_INTCON0>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};

95
Documentation/devicetree/bindings/arm/gemini.yaml Normal file
View File

@@ -0,0 +1,95 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/gemini.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cortina systems Gemini platforms
description: |
The Gemini SoC is the project name for an ARMv4 FA525-based SoC originally
produced by Storlink Semiconductor around 2005. The company was renamed
later renamed Storm Semiconductor. The chip product name is Storlink SL3516.
It was derived from earlier products from Storm named SL3316 (Centroid) and
SL3512 (Bulverde).
Storm Semiconductor was acquired by Cortina Systems in 2008 and the SoC was
produced and used for NAS and similar usecases. In 2014 Cortina Systems was
in turn acquired by Inphi, who seem to have discontinued this product family.
Many of the IP blocks used in the SoC comes from Faraday Technology.
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: Storlink Semiconductor Gemini324 EV-Board also known
as Storm Semiconductor SL93512R_BRD
items:
- const: storlink,gemini324
- const: storm,sl93512r
- const: cortina,gemini
- description: D-Link DIR-685 Xtreme N Storage Router
items:
- const: dlink,dir-685
- const: cortina,gemini
- description: D-Link DNS-313 1-Bay Network Storage Enclosure
items:
- const: dlink,dns-313
- const: cortina,gemini
- description: Edimax NS-2502
items:
- const: edimax,ns-2502
- const: cortina,gemini
- description: ITian Square One SQ201
items:
- const: itian,sq201
- const: cortina,gemini
- description: Raidsonic NAS IB-4220-B
items:
- const: raidsonic,ib-4220-b
- const: cortina,gemini
- description: SSI 1328
items:
- const: ssi,1328
- const: cortina,gemini
- description: Teltonika RUT1xx Mobile Router
items:
- const: teltonika,rut1xx
- const: cortina,gemini
- description: Wiligear Wiliboard WBD-111
items:
- const: wiligear,wiliboard-wbd111
- const: cortina,gemini
- description: Wiligear Wiliboard WBD-222
items:
- const: wiligear,wiliboard-wbd222
- const: cortina,gemini
- description: Wiligear Wiliboard WBD-111 - old incorrect binding
items:
- const: wiliboard,wbd111
- const: cortina,gemini
deprecated: true
- description: Wiligear Wiliboard WBD-222 - old incorrect binding
items:
- const: wiliboard,wbd222
- const: cortina,gemini
deprecated: true
additionalProperties: true

31
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
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@@ -1,31 +0,0 @@
Mediatek mmsys controller
============================
The Mediatek mmsys system controller provides clock control, routing control,
and miscellaneous control in mmsys partition.
Required Properties:
- compatible: Should be one of:
- "mediatek,mt2701-mmsys", "syscon"
- "mediatek,mt2712-mmsys", "syscon"
- "mediatek,mt6765-mmsys", "syscon"
- "mediatek,mt6779-mmsys", "syscon"
- "mediatek,mt6797-mmsys", "syscon"
- "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon"
- "mediatek,mt8167-mmsys", "syscon"
- "mediatek,mt8173-mmsys", "syscon"
- "mediatek,mt8183-mmsys", "syscon"
- #clock-cells: Must be 1
For the clock control, the mmsys controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
Example:
mmsys: syscon@14000000 {
compatible = "mediatek,mt8173-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
#clock-cells = <1>;
};

58
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml Normal file
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@@ -0,0 +1,58 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mmsys.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: MediaTek mmsys controller
maintainers:
- Matthias Brugger <matthias.bgg@gmail.com>
description:
The MediaTek mmsys system controller provides clock control, routing control,
and miscellaneous control in mmsys partition.
properties:
$nodename:
pattern: "^syscon@[0-9a-f]+$"
compatible:
oneOf:
- items:
- enum:
- mediatek,mt2701-mmsys
- mediatek,mt2712-mmsys
- mediatek,mt6765-mmsys
- mediatek,mt6779-mmsys
- mediatek,mt6797-mmsys
- mediatek,mt8167-mmsys
- mediatek,mt8173-mmsys
- mediatek,mt8183-mmsys
- mediatek,mt8365-mmsys
- const: syscon
- items:
- const: mediatek,mt7623-mmsys
- const: mediatek,mt2701-mmsys
- const: syscon
reg:
maxItems: 1
"#clock-cells":
const: 1
required:
- compatible
- reg
- "#clock-cells"
additionalProperties: false
examples:
- |
mmsys: syscon@14000000 {
compatible = "mediatek,mt8173-mmsys", "syscon";
reg = <0x14000000 0x1000>;
#clock-cells = <1>;
};

10
Documentation/devicetree/bindings/arm/qcom.yaml
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@@ -31,6 +31,7 @@ description: |
ipq6018
ipq8074
mdm9615
msm8226
msm8916
msm8974
msm8992
@@ -114,6 +115,11 @@ properties:
- qcom,apq8084-sbc
- const: qcom,apq8084
- items:
- enum:
- samsung,s3ve3g
- const: qcom,msm8226
- items:
- enum:
- qcom,msm8960-cdp
@@ -129,6 +135,8 @@ properties:
- const: qcom,msm8974
- items:
- enum:
- alcatel,idol347
- const: qcom,msm8916-mtp/1
- const: qcom,msm8916-mtp
- const: qcom,msm8916
@@ -181,6 +189,8 @@ properties:
- items:
- enum:
- qcom,sc7280-idp
- qcom,sc7280-idp2
- google,piglin
- google,senor
- const: qcom,sc7280

50
Documentation/devicetree/bindings/arm/renesas.yaml
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@@ -238,17 +238,29 @@ properties:
- const: renesas,r8a77961
- description: Kingfisher (SBEV-RCAR-KF-M03)
items:
- const: shimafuji,kingfisher
- enum:
- renesas,h3ulcb
- renesas,m3ulcb
- renesas,m3nulcb
- enum:
- renesas,r8a7795
- renesas,r8a7796
- renesas,r8a77961
- renesas,r8a77965
oneOf:
- items:
- const: shimafuji,kingfisher
- enum:
- renesas,h3ulcb
- renesas,m3ulcb
- renesas,m3nulcb
- enum:
- renesas,r8a7795
- renesas,r8a7796
- renesas,r8a77961
- renesas,r8a77965
- items:
- const: shimafuji,kingfisher
- enum:
- renesas,h3ulcb
- renesas,m3ulcb
- enum:
- renesas,r8a779m1
- renesas,r8a779m3
- enum:
- renesas,r8a7795
- renesas,r8a77961
- description: R-Car M3-N (R8A77965)
items:
@@ -296,6 +308,22 @@ properties:
- const: renesas,falcon-cpu
- const: renesas,r8a779a0
- description: R-Car H3e-2G (R8A779M1)
items:
- enum:
- renesas,h3ulcb # H3ULCB (R-Car Starter Kit Premier)
- renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version)
- const: renesas,r8a779m1
- const: renesas,r8a7795
- description: R-Car M3e-2G (R8A779M3)
items:
- enum:
- renesas,m3ulcb # M3ULCB (R-Car Starter Kit Pro)
- renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version)
- const: renesas,r8a779m3
- const: renesas,r8a77961
- description: RZ/N1D (R9A06G032)
items:
- enum:

1
Documentation/devicetree/bindings/arm/tegra.yaml
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@@ -111,6 +111,7 @@ properties:
- items:
- enum:
- nvidia,p2771-0000
- nvidia,p3509-0000+p3636-0001
- const: nvidia,tegra186
- items:
- enum:

30
Documentation/devicetree/bindings/ata/exynos-sata.txt
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@@ -1,30 +0,0 @@
* Samsung AHCI SATA Controller
SATA nodes are defined to describe on-chip Serial ATA controllers.
Each SATA controller should have its own node.
Required properties:
- compatible : compatible list, contains "samsung,exynos5-sata"
- interrupts : <interrupt mapping for SATA IRQ>
- reg : <registers mapping>
- samsung,sata-freq : <frequency in MHz>
- phys : Must contain exactly one entry as specified
in phy-bindings.txt
- phy-names : Must be "sata-phy"
Optional properties:
- clocks : Must contain an entry for each entry in clock-names.
- clock-names : Shall be "sata" for the external SATA bus clock,
and "sclk_sata" for the internal controller clock.
Example:
sata@122f0000 {
compatible = "snps,dwc-ahci";
samsung,sata-freq = <66>;
reg = <0x122f0000 0x1ff>;
interrupts = <0 115 0>;
clocks = <&clock 277>, <&clock 143>;
clock-names = "sata", "sclk_sata";
phys = <&sata_phy>;
phy-names = "sata-phy";
};

61
Documentation/devicetree/bindings/ata/intel,ixp4xx-compact-flash.yaml Normal file
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@@ -0,0 +1,61 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/intel,ixp4xx-compact-flash.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intel IXP4xx CompactFlash Card Controller
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
description: |
The IXP4xx network processors have a CompactFlash interface that presents
a CompactFlash card to the system as a true IDE (parallel ATA) device. The
device is always connected to the expansion bus of the IXP4xx SoCs using one
or two chip select areas and address translating logic on the board. The
node must be placed inside a chip select node on the IXP4xx expansion bus.
properties:
compatible:
const: intel,ixp4xx-compact-flash
reg:
items:
- description: Command interface registers
- description: Control interface registers
interrupts:
maxItems: 1
required:
- compatible
- reg
- interrupts
allOf:
- $ref: pata-common.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
bus@c4000000 {
compatible = "intel,ixp43x-expansion-bus-controller", "syscon";
reg = <0xc4000000 0x1000>;
native-endian;
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0x0 0x50000000 0x01000000>, <1 0x0 0x51000000 0x01000000>;
dma-ranges = <0 0x0 0x50000000 0x01000000>, <1 0x0 0x51000000 0x01000000>;
ide@1,0 {
compatible = "intel,ixp4xx-compact-flash";
reg = <1 0x00000000 0x1000>, <1 0x00040000 0x1000>;
interrupt-parent = <&gpio0>;
interrupts = <12 IRQ_TYPE_EDGE_RISING>;
};
};
...

44
Documentation/devicetree/bindings/auxdisplay/arm,versatile-lcd.yaml Normal file
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@@ -0,0 +1,44 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/auxdisplay/arm,versatile-lcd.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Versatile Character LCD
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
- Rob Herring <robh@kernel.org>
description:
This binding defines the character LCD interface found on ARM Versatile AB
and PB reference platforms.
properties:
compatible:
const: arm,versatile-lcd
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
maxItems: 1
interrupts:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
lcd@10008000 {
compatible = "arm,versatile-lcd";
reg = <0x10008000 0x1000>;
};

18
Documentation/devicetree/bindings/auxdisplay/arm-charlcd.txt
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@@ -1,18 +0,0 @@
ARM Versatile Character LCD
-----------------------------------------------------
This binding defines the character LCD interface found on ARM Versatile AB
and PB reference platforms.
Required properties:
- compatible : "arm,versatile-clcd"
- reg : Location and size of character LCD registers
Optional properties:
- interrupts - single interrupt for character LCD. The character LCD can
operate in polled mode without an interrupt.
Example:
lcd@10008000 {
compatible = "arm,versatile-lcd";
reg = <0x10008000 0x1000>;
};

55
Documentation/devicetree/bindings/auxdisplay/img,ascii-lcd.yaml Normal file
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@@ -0,0 +1,55 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/auxdisplay/img,ascii-lcd.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ASCII LCD displays on Imagination Technologies boards
maintainers:
- Paul Burton <paulburton@kernel.org>
properties:
compatible:
enum:
- img,boston-lcd
- mti,malta-lcd
- mti,sead3-lcd
reg:
maxItems: 1
offset:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Offset in bytes to the LCD registers within the system controller
required:
- compatible
oneOf:
- required:
- reg
- required:
- offset
if:
properties:
compatible:
contains:
const: img,boston-lcd
then:
required:
- reg
else:
required:
- offset
additionalProperties: false
examples:
- |
lcd: lcd@17fff000 {
compatible = "img,boston-lcd";
reg = <0x17fff000 0x8>;
};

17
Documentation/devicetree/bindings/auxdisplay/img-ascii-lcd.txt
View File

@@ -1,17 +0,0 @@
Binding for ASCII LCD displays on Imagination Technologies boards
Required properties:
- compatible : should be one of:
"img,boston-lcd"
"mti,malta-lcd"
"mti,sead3-lcd"
Required properties for "img,boston-lcd":
- reg : memory region locating the device registers
Required properties for "mti,malta-lcd" or "mti,sead3-lcd":
- regmap: phandle of the system controller containing the LCD registers
- offset: offset in bytes to the LCD registers within the system controller
The layout of the registers & properties of the display are determined
from the compatible string, making this binding somewhat trivial.

168
Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml Normal file
View File

@@ -0,0 +1,168 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/bus/intel,ixp4xx-expansion-bus-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intel IXP4xx Expansion Bus Controller
description: |
The IXP4xx expansion bus controller handles access to devices on the
memory-mapped expansion bus on the Intel IXP4xx family of system on chips,
including IXP42x, IXP43x, IXP45x and IXP46x.
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
properties:
$nodename:
pattern: '^bus@[0-9a-f]+$'
compatible:
items:
- enum:
- intel,ixp42x-expansion-bus-controller
- intel,ixp43x-expansion-bus-controller
- intel,ixp45x-expansion-bus-controller
- intel,ixp46x-expansion-bus-controller
- const: syscon
reg:
description: Control registers for the expansion bus, these are not
inside the memory range handled by the expansion bus.
maxItems: 1
native-endian:
$ref: /schemas/types.yaml#/definitions/flag
description: The IXP4xx has a peculiar MMIO access scheme, as it changes
the access pattern for words (swizzling) on the bus depending on whether
the SoC is running in big-endian or little-endian mode. Thus the
registers must always be accessed using native endianness.
"#address-cells":
description: |
The first cell is the chip select number.
The second cell is the address offset within the bank.
const: 2
"#size-cells":
const: 1
ranges: true
dma-ranges: true
patternProperties:
"^.*@[0-7],[0-9a-f]+$":
description: Devices attached to chip selects are represented as
subnodes.
type: object
properties:
intel,ixp4xx-eb-t1:
description: Address timing, extend address phase with n cycles.
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 3
intel,ixp4xx-eb-t2:
description: Setup chip select timing, extend setup phase with n cycles.
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 3
intel,ixp4xx-eb-t3:
description: Strobe timing, extend strobe phase with n cycles.
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
intel,ixp4xx-eb-t4:
description: Hold timing, extend hold phase with n cycles.
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 3
intel,ixp4xx-eb-t5:
description: Recovery timing, extend recovery phase with n cycles.
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
intel,ixp4xx-eb-cycle-type:
description: The type of cycles to use on the expansion bus for this
chip select. 0 = Intel cycles, 1 = Motorola cycles, 2 = HPI cycles.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2]
intel,ixp4xx-eb-byte-access-on-halfword:
description: Allow byte read access on half word devices.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
intel,ixp4xx-eb-hpi-hrdy-pol-high:
description: Set HPI HRDY polarity to active high when using HPI.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
intel,ixp4xx-eb-mux-address-and-data:
description: Multiplex address and data on the data bus.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
intel,ixp4xx-eb-ahb-split-transfers:
description: Enable AHB split transfers.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
intel,ixp4xx-eb-write-enable:
description: Enable write cycles.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
intel,ixp4xx-eb-byte-access:
description: Expansion bus uses only 8 bits. The default is to use
16 bits.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
required:
- compatible
- reg
- native-endian
- "#address-cells"
- "#size-cells"
- ranges
- dma-ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
bus@50000000 {
compatible = "intel,ixp42x-expansion-bus-controller", "syscon";
reg = <0xc4000000 0x28>;
native-endian;
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0x0 0x50000000 0x01000000>,
<1 0x0 0x51000000 0x01000000>;
dma-ranges = <0 0x0 0x50000000 0x01000000>,
<1 0x0 0x51000000 0x01000000>;
flash@0,0 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
reg = <0 0x00000000 0x1000000>;
intel,ixp4xx-eb-t3 = <3>;
intel,ixp4xx-eb-cycle-type = <0>;
intel,ixp4xx-eb-byte-access-on-halfword = <1>;
intel,ixp4xx-eb-write-enable = <1>;
intel,ixp4xx-eb-byte-access = <0>;
};
serial@1,0 {
compatible = "exar,xr16l2551", "ns8250";
reg = <1 0x00000000 0x10>;
interrupt-parent = <&gpio0>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
clock-frequency = <1843200>;
intel,ixp4xx-eb-t3 = <3>;
intel,ixp4xx-eb-cycle-type = <1>;
intel,ixp4xx-eb-write-enable = <1>;
intel,ixp4xx-eb-byte-access = <1>;
};
};

12
Documentation/devicetree/bindings/chosen.txt
View File

@@ -79,9 +79,9 @@ a different secondary CPU release mechanism)
linux,usable-memory-range
-------------------------
This property (arm64 only) holds a base address and size, describing a
limited region in which memory may be considered available for use by
the kernel. Memory outside of this range is not available for use.
This property holds a base address and size, describing a limited region in
which memory may be considered available for use by the kernel. Memory outside
of this range is not available for use.
This property describes a limitation: memory within this range is only
valid when also described through another mechanism that the kernel
@@ -106,9 +106,9 @@ respectively, of the root node.
linux,elfcorehdr
----------------
This property (currently used only on arm64) holds the memory range,
the address and the size, of the elf core header which mainly describes
the panicked kernel's memory layout as PT_LOAD segments of elf format.
This property holds the memory range, the address and the size, of the elf
core header which mainly describes the panicked kernel's memory layout as
PT_LOAD segments of elf format.
e.g.
/ {

4
Documentation/devicetree/bindings/connector/usb-connector.yaml
View File

@@ -111,6 +111,10 @@ properties:
- 1.5A
- 3.0A
pd-disable:
description: Set this property if the Type-C connector has no power delivery support.
type: boolean
# The following are optional properties for "usb-c-connector" with power
# delivery support.
source-pdos:

26
Documentation/devicetree/bindings/devfreq/event/exynos-nocp.txt
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@@ -1,26 +0,0 @@
* Samsung Exynos NoC (Network on Chip) Probe device
The Samsung Exynos542x SoC has NoC (Network on Chip) Probe for NoC bus.
NoC provides the primitive values to get the performance data. The packets
that the Network on Chip (NoC) probes detects are transported over
the network infrastructure to observer units. You can configure probes to
capture packets with header or data on the data request response network,
or as traffic debug or statistic collectors. Exynos542x bus has multiple
NoC probes to provide bandwidth information about behavior of the SoC
that you can use while analyzing system performance.
Required properties:
- compatible: Should be "samsung,exynos5420-nocp"
- reg: physical base address of each NoC Probe and length of memory mapped region.
Optional properties:
- clock-names : the name of clock used by the NoC Probe, "nocp"
- clocks : phandles for clock specified in "clock-names" property
Example : NoC Probe nodes in Device Tree are listed below.
nocp_mem0_0: nocp@10ca1000 {
compatible = "samsung,exynos5420-nocp";
reg = <0x10CA1000 0x200>;
};

169
Documentation/devicetree/bindings/devfreq/event/exynos-ppmu.txt
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@@ -1,169 +0,0 @@
* Samsung Exynos PPMU (Platform Performance Monitoring Unit) device
The Samsung Exynos SoC has PPMU (Platform Performance Monitoring Unit) for
each IP. PPMU provides the primitive values to get performance data. These
PPMU events provide information of the SoC's behaviors so that you may
use to analyze system performance, to make behaviors visible and to count
usages of each IP (DMC, CPU, RIGHTBUS, LEFTBUS, CAM interface, LCD, G3D, MFC).
The Exynos PPMU driver uses the devfreq-event class to provide event data
to various devfreq devices. The devfreq devices would use the event data when
derterming the current state of each IP.
Required properties for PPMU device:
- compatible: Should be "samsung,exynos-ppmu" or "samsung,exynos-ppmu-v2.
- reg: physical base address of each PPMU and length of memory mapped region.
Optional properties for PPMU device:
- clock-names : the name of clock used by the PPMU, "ppmu"
- clocks : phandles for clock specified in "clock-names" property
Required properties for 'events' child node of PPMU device:
- event-name : the unique event name among PPMU device
Optional properties for 'events' child node of PPMU device:
- event-data-type : Define the type of data which shell be counted
by the counter. You can check include/dt-bindings/pmu/exynos_ppmu.h for
all possible type, i.e. count read requests, count write data in bytes,
etc. This field is optional and when it is missing, the driver code
will use default data type.
Example1 : PPMUv1 nodes in exynos3250.dtsi are listed below.
ppmu_dmc0: ppmu_dmc0@106a0000 {
compatible = "samsung,exynos-ppmu";
reg = <0x106a0000 0x2000>;
status = "disabled";
};
ppmu_dmc1: ppmu_dmc1@106b0000 {
compatible = "samsung,exynos-ppmu";
reg = <0x106b0000 0x2000>;
status = "disabled";
};
ppmu_cpu: ppmu_cpu@106c0000 {
compatible = "samsung,exynos-ppmu";
reg = <0x106c0000 0x2000>;
status = "disabled";
};
ppmu_rightbus: ppmu_rightbus@112a0000 {
compatible = "samsung,exynos-ppmu";
reg = <0x112a0000 0x2000>;
clocks = <&cmu CLK_PPMURIGHT>;
clock-names = "ppmu";
status = "disabled";
};
ppmu_leftbus: ppmu_leftbus0@116a0000 {
compatible = "samsung,exynos-ppmu";
reg = <0x116a0000 0x2000>;
clocks = <&cmu CLK_PPMULEFT>;
clock-names = "ppmu";
status = "disabled";
};
Example2 : Events of each PPMU node in exynos3250-rinato.dts are listed below.
&ppmu_dmc0 {
status = "okay";
events {
ppmu_dmc0_3: ppmu-event3-dmc0 {
event-name = "ppmu-event3-dmc0";
};
ppmu_dmc0_2: ppmu-event2-dmc0 {
event-name = "ppmu-event2-dmc0";
};
ppmu_dmc0_1: ppmu-event1-dmc0 {
event-name = "ppmu-event1-dmc0";
};
ppmu_dmc0_0: ppmu-event0-dmc0 {
event-name = "ppmu-event0-dmc0";
};
};
};
&ppmu_dmc1 {
status = "okay";
events {
ppmu_dmc1_3: ppmu-event3-dmc1 {
event-name = "ppmu-event3-dmc1";
};
};
};
&ppmu_leftbus {
status = "okay";
events {
ppmu_leftbus_3: ppmu-event3-leftbus {
event-name = "ppmu-event3-leftbus";
};
};
};
&ppmu_rightbus {
status = "okay";
events {
ppmu_rightbus_3: ppmu-event3-rightbus {
event-name = "ppmu-event3-rightbus";
};
};
};
Example3 : PPMUv2 nodes in exynos5433.dtsi are listed below.
ppmu_d0_cpu: ppmu_d0_cpu@10480000 {
compatible = "samsung,exynos-ppmu-v2";
reg = <0x10480000 0x2000>;
status = "disabled";
};
ppmu_d0_general: ppmu_d0_general@10490000 {
compatible = "samsung,exynos-ppmu-v2";
reg = <0x10490000 0x2000>;
status = "disabled";
};
ppmu_d0_rt: ppmu_d0_rt@104a0000 {
compatible = "samsung,exynos-ppmu-v2";
reg = <0x104a0000 0x2000>;
status = "disabled";
};
ppmu_d1_cpu: ppmu_d1_cpu@104b0000 {
compatible = "samsung,exynos-ppmu-v2";
reg = <0x104b0000 0x2000>;
status = "disabled";
};
ppmu_d1_general: ppmu_d1_general@104c0000 {
compatible = "samsung,exynos-ppmu-v2";
reg = <0x104c0000 0x2000>;
status = "disabled";
};
ppmu_d1_rt: ppmu_d1_rt@104d0000 {
compatible = "samsung,exynos-ppmu-v2";
reg = <0x104d0000 0x2000>;
status = "disabled";
};
Example4 : 'event-data-type' in exynos4412-ppmu-common.dtsi are listed below.
&ppmu_dmc0 {
status = "okay";
events {
ppmu_dmc0_3: ppmu-event3-dmc0 {
event-name = "ppmu-event3-dmc0";
event-data-type = <(PPMU_RO_DATA_CNT |
PPMU_WO_DATA_CNT)>;
};
};
};

48
Documentation/devicetree/bindings/devfreq/event/samsung,exynos-nocp.yaml Normal file
View File

@@ -0,0 +1,48 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/devfreq/event/samsung,exynos-nocp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos NoC (Network on Chip) Probe
maintainers:
- Chanwoo Choi <cw00.choi@samsung.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
description: |
The Samsung Exynos542x SoC has a NoC (Network on Chip) Probe for NoC bus.
NoC provides the primitive values to get the performance data. The packets
that the Network on Chip (NoC) probes detects are transported over the
network infrastructure to observer units. You can configure probes to capture
packets with header or data on the data request response network, or as
traffic debug or statistic collectors. Exynos542x bus has multiple NoC probes
to provide bandwidth information about behavior of the SoC that you can use
while analyzing system performance.
properties:
compatible:
const: samsung,exynos5420-nocp
clock-names:
items:
- const: nocp
clocks:
maxItems: 1
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
nocp_mem0_0: nocp@10ca1000 {
compatible = "samsung,exynos5420-nocp";
reg = <0x10ca1000 0x200>;
};

169
Documentation/devicetree/bindings/devfreq/event/samsung,exynos-ppmu.yaml Normal file
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@@ -0,0 +1,169 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/devfreq/event/samsung,exynos-ppmu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos SoC PPMU (Platform Performance Monitoring Unit)
maintainers:
- Chanwoo Choi <cw00.choi@samsung.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
description: |
The Samsung Exynos SoC has PPMU (Platform Performance Monitoring Unit) for
each IP. PPMU provides the primitive values to get performance data. These
PPMU events provide information of the SoC's behaviors so that you may use to
analyze system performance, to make behaviors visible and to count usages of
each IP (DMC, CPU, RIGHTBUS, LEFTBUS, CAM interface, LCD, G3D, MFC). The
Exynos PPMU driver uses the devfreq-event class to provide event data to
various devfreq devices. The devfreq devices would use the event data when
derterming the current state of each IP.
properties:
compatible:
enum:
- samsung,exynos-ppmu
- samsung,exynos-ppmu-v2
clock-names:
items:
- const: ppmu
clocks:
maxItems: 1
reg:
maxItems: 1
events:
type: object
patternProperties:
'^ppmu-event[0-9]+(-[a-z0-9]+){,2}$':
type: object
properties:
event-name:
description: |
The unique event name among PPMU device
$ref: /schemas/types.yaml#/definitions/string
event-data-type:
description: |
Define the type of data which shell be counted by the counter.
You can check include/dt-bindings/pmu/exynos_ppmu.h for all
possible type, i.e. count read requests, count write data in
bytes, etc. This field is optional and when it is missing, the
driver code will use default data type.
$ref: /schemas/types.yaml#/definitions/uint32
required:
- event-name
additionalProperties: false
additionalProperties: false
required:
- compatible
- reg
additionalProperties: false
examples:
- |
// PPMUv1 nodes for Exynos3250 (although the board DTS defines events)
#include <dt-bindings/clock/exynos3250.h>
ppmu_dmc0: ppmu@106a0000 {
compatible = "samsung,exynos-ppmu";
reg = <0x106a0000 0x2000>;
events {
ppmu_dmc0_3: ppmu-event3-dmc0 {
event-name = "ppmu-event3-dmc0";
};
ppmu_dmc0_2: ppmu-event2-dmc0 {
event-name = "ppmu-event2-dmc0";
};
ppmu_dmc0_1: ppmu-event1-dmc0 {
event-name = "ppmu-event1-dmc0";
};
ppmu_dmc0_0: ppmu-event0-dmc0 {
event-name = "ppmu-event0-dmc0";
};
};
};
ppmu_rightbus: ppmu@112a0000 {
compatible = "samsung,exynos-ppmu";
reg = <0x112a0000 0x2000>;
clocks = <&cmu CLK_PPMURIGHT>;
clock-names = "ppmu";
events {
ppmu_rightbus_3: ppmu-event3-rightbus {
event-name = "ppmu-event3-rightbus";
};
};
};
- |
// PPMUv2 nodes in Exynos5433
ppmu_d0_cpu: ppmu@10480000 {
compatible = "samsung,exynos-ppmu-v2";
reg = <0x10480000 0x2000>;
};
ppmu_d0_general: ppmu@10490000 {
compatible = "samsung,exynos-ppmu-v2";
reg = <0x10490000 0x2000>;
events {
ppmu_event0_d0_general: ppmu-event0-d0-general {
event-name = "ppmu-event0-d0-general";
};
};
};
ppmu_d0_rt: ppmu@104a0000 {
compatible = "samsung,exynos-ppmu-v2";
reg = <0x104a0000 0x2000>;
};
ppmu_d1_cpu: ppmu@104b0000 {
compatible = "samsung,exynos-ppmu-v2";
reg = <0x104b0000 0x2000>;
};
ppmu_d1_general: ppmu@104c0000 {
compatible = "samsung,exynos-ppmu-v2";
reg = <0x104c0000 0x2000>;
};
ppmu_d1_rt: ppmu@104d0000 {
compatible = "samsung,exynos-ppmu-v2";
reg = <0x104d0000 0x2000>;
};
- |
// PPMUv1 nodes with event-data-type for Exynos4412
#include <dt-bindings/pmu/exynos_ppmu.h>
ppmu@106a0000 {
compatible = "samsung,exynos-ppmu";
reg = <0x106a0000 0x2000>;
clocks = <&clock 400>;
clock-names = "ppmu";
events {
ppmu-event3-dmc0 {
event-name = "ppmu-event3-dmc0";
event-data-type = <(PPMU_RO_DATA_CNT |
PPMU_WO_DATA_CNT)>;
};
};
};

2
Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml
View File

@@ -174,7 +174,6 @@ examples:
phy-names = "phy";
pinctrl-names = "default";
pinctrl-0 = <&hdmi_pins>;
status = "disabled";
ports {
#address-cells = <1>;
@@ -233,7 +232,6 @@ examples:
phy-names = "phy";
pinctrl-names = "default";
pinctrl-0 = <&hdmi_pins>;
status = "disabled";
ports {
#address-cells = <1>;

3
Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml
View File

@@ -22,6 +22,9 @@ properties:
- ti,ths8134a
- ti,ths8134b
- const: ti,ths8134
- items:
- const: corpro,gm7123
- const: adi,adv7123
- enum:
- adi,adv7123
- dumb-vga-dac

6
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi83.yaml
View File

@@ -37,7 +37,8 @@ properties:
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: Video port for MIPI DSI Channel-A input
properties:
@@ -57,7 +58,8 @@ properties:
- const: 4
port@1:
$ref: /schemas/graph.yaml#/properties/port
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: Video port for MIPI DSI Channel-B input
properties:

21
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml
View File

@@ -70,6 +70,9 @@ properties:
const: 1
description: See ../../pwm/pwm.yaml for description of the cell formats.
aux-bus:
$ref: /schemas/display/dp-aux-bus.yaml#
ports:
$ref: /schemas/graph.yaml#/properties/ports
@@ -150,7 +153,6 @@ properties:
required:
- compatible
- reg
- enable-gpios
- vccio-supply
- vpll-supply
- vcca-supply
@@ -201,11 +203,26 @@ examples:
port@1 {
reg = <1>;
endpoint {
sn65dsi86_out: endpoint {
remote-endpoint = <&panel_in_edp>;
};
};
};
aux-bus {
panel {
compatible = "boe,nv133fhm-n62";
power-supply = <&pp3300_dx_edp>;
backlight = <&backlight>;
hpd-gpios = <&sn65dsi86_bridge 2 GPIO_ACTIVE_HIGH>;
port {
panel_in_edp: endpoint {
remote-endpoint = <&sn65dsi86_out>;
};
};
};
};
};
};
- |

37
Documentation/devicetree/bindings/display/dp-aux-bus.yaml Normal file
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@@ -0,0 +1,37 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/dp-aux-bus.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: DisplayPort AUX bus
maintainers:
- Douglas Anderson <dianders@chromium.org>
description:
DisplayPort controllers provide a control channel to the sinks that
are hooked up to them. This is the DP AUX bus. Over the DP AUX bus
we can query properties about a sink and also configure it. In
particular, DP sinks support DDC over DP AUX which allows tunneling
a standard I2C DDC connection over the AUX channel.
To model this relationship, DP sinks should be placed as children
of the DP controller under the "aux-bus" node.
At the moment, this binding only handles the eDP case. It is
possible it will be extended in the future to handle the DP case.
For DP, presumably a connector would be listed under the DP AUX
bus instead of a panel.
properties:
$nodename:
const: "aux-bus"
panel:
$ref: panel/panel-common.yaml#
additionalProperties: false
required:
- panel

1
Documentation/devicetree/bindings/display/fsl,lcdif.yaml
View File

@@ -27,6 +27,7 @@ properties:
- fsl,imx6ul-lcdif
- fsl,imx7d-lcdif
- fsl,imx8mm-lcdif
- fsl,imx8mn-lcdif
- fsl,imx8mq-lcdif
- const: fsl,imx6sx-lcdif

2
Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
View File

@@ -7,7 +7,7 @@ channel output.
Required properties:
- compatible: "mediatek,<chip>-dsi"
- the supported chips are mt2701, mt7623, mt8173 and mt8183.
- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers
- interrupts: The interrupt signal from the function block.
- clocks: device clocks

23
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
View File

@@ -64,6 +64,18 @@ properties:
Indicates if the DSI controller is driving a panel which needs
2 DSI links.
assigned-clocks:
minItems: 2
maxItems: 2
description: |
Parents of "byte" and "pixel" for the given platform.
assigned-clock-parents:
minItems: 2
maxItems: 2
description: |
The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block.
power-domains:
maxItems: 1
@@ -77,7 +89,8 @@ properties:
properties:
port@0:
$ref: "/schemas/graph.yaml#/properties/port"
$ref: "/schemas/graph.yaml#/$defs/port-base"
unevaluatedProperties: false
description: |
Input endpoints of the controller.
properties:
@@ -92,7 +105,8 @@ properties:
enum: [ 0, 1, 2, 3 ]
port@1:
$ref: "/schemas/graph.yaml#/properties/port"
$ref: "/schemas/graph.yaml#/$defs/port-base"
unevaluatedProperties: false
description: |
Output endpoints of the controller.
properties:
@@ -119,6 +133,8 @@ required:
- clock-names
- phys
- phy-names
- assigned-clocks
- assigned-clock-parents
- power-domains
- operating-points-v2
- ports
@@ -159,6 +175,9 @@ examples:
phys = <&dsi0_phy>;
phy-names = "dsi";
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
power-domains = <&rpmhpd SC7180_CX>;
operating-points-v2 = <&dsi_opp_table>;

6
Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml
View File

@@ -14,9 +14,9 @@ allOf:
properties:
compatible:
oneOf:
- const: qcom,dsi-phy-10nm
- const: qcom,dsi-phy-10nm-8998
enum:
- qcom,dsi-phy-10nm
- qcom,dsi-phy-10nm-8998
reg:
items:

6
Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
View File

@@ -14,9 +14,9 @@ allOf:
properties:
compatible:
oneOf:
- const: qcom,dsi-phy-14nm
- const: qcom,dsi-phy-14nm-660
enum:
- qcom,dsi-phy-14nm
- qcom,dsi-phy-14nm-660
reg:
items:

3
Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml
View File

@@ -14,8 +14,7 @@ allOf:
properties:
compatible:
oneOf:
- const: qcom,dsi-phy-20nm
const: qcom,dsi-phy-20nm
reg:
items:

8
Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml
View File

@@ -14,10 +14,10 @@ allOf:
properties:
compatible:
oneOf:
- const: qcom,dsi-phy-28nm-hpm
- const: qcom,dsi-phy-28nm-lp
- const: qcom,dsi-phy-28nm-8960
enum:
- qcom,dsi-phy-28nm-hpm
- qcom,dsi-phy-28nm-lp
- qcom,dsi-phy-28nm-8960
reg:
items:

72
Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml Normal file
View File

@@ -0,0 +1,72 @@
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/dsi-phy-7nm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display DSI 7nm PHY
maintainers:
- Jonathan Marek <jonathan@marek.ca>
allOf:
- $ref: dsi-phy-common.yaml#
properties:
compatible:
oneOf:
- const: qcom,dsi-phy-7nm
- const: qcom,dsi-phy-7nm-8150
- const: qcom,sc7280-dsi-phy-7nm
reg:
items:
- description: dsi phy register set
- description: dsi phy lane register set
- description: dsi pll register set
reg-names:
items:
- const: dsi_phy
- const: dsi_phy_lane
- const: dsi_pll
vdds-supply:
description: |
Connected to VDD_A_DSI_PLL_0P9 pin (or VDDA_DSI{0,1}_PLL_0P9 for sm8150)
phy-type:
description: D-PHY (default) or C-PHY mode
enum: [ 10, 11 ]
default: 10
required:
- compatible
- reg
- reg-names
- vdds-supply
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,dispcc-sm8250.h>
#include <dt-bindings/clock/qcom,rpmh.h>
dsi-phy@ae94400 {
compatible = "qcom,dsi-phy-7nm";
reg = <0x0ae94400 0x200>,
<0x0ae94600 0x280>,
<0x0ae94900 0x260>;
reg-names = "dsi_phy",
"dsi_phy_lane",
"dsi_pll";
#clock-cells = <1>;
#phy-cells = <0>;
vdds-supply = <&vreg_l5a_0p88>;
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface", "ref";
};

1
Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.yaml
View File

@@ -70,7 +70,6 @@ examples:
avee-supply = <&ppvarp_lcd>;
pp1800-supply = <&pp1800_lcd>;
backlight = <&backlight_lcd0>;
status = "okay";
port {
panel_in: endpoint {
remote-endpoint = <&dsi_out>;

78
Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml Normal file
View File

@@ -0,0 +1,78 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/ilitek,ili9341.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ilitek-9341 Display Panel
maintainers:
- Dillon Min <dillon.minfei@gmail.com>
description: |
Ilitek ILI9341 TFT panel driver with SPI control bus
This is a driver for 320x240 TFT panels, accepting a rgb input
streams with 16 bits or 18 bits.
allOf:
- $ref: panel-common.yaml#
properties:
compatible:
items:
- enum:
# ili9341 240*320 Color on stm32f429-disco board
- st,sf-tc240t-9370-t
- const: ilitek,ili9341
reg: true
dc-gpios:
maxItems: 1
description: Display data/command selection (D/CX) of this DBI panel
spi-3wire: true
spi-max-frequency:
const: 10000000
port: true
vci-supply:
description: Analog voltage supply (2.5 .. 3.3V)
vddi-supply:
description: Voltage supply for interface logic (1.65 .. 3.3 V)
vddi-led-supply:
description: Voltage supply for the LED driver (1.65 .. 3.3 V)
additionalProperties: false
required:
- compatible
- reg
- dc-gpios
- port
examples:
- |+
spi {
#address-cells = <1>;
#size-cells = <0>;
panel: display@0 {
compatible = "st,sf-tc240t-9370-t",
"ilitek,ili9341";
reg = <0>;
spi-3wire;
spi-max-frequency = <10000000>;
dc-gpios = <&gpiod 13 0>;
port {
panel_in: endpoint {
remote-endpoint = <&display_out>;
};
};
};
};
...

62
Documentation/devicetree/bindings/display/panel/innolux,ej030na.yaml Normal file
View File

@@ -0,0 +1,62 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/innolux,ej030na.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Innolux EJ030NA 3.0" (320x480 pixels) 24-bit TFT LCD panel
description: |
The panel must obey the rules for a SPI slave device as specified in
spi/spi-controller.yaml
maintainers:
- Paul Cercueil <paul@crapouillou.net>
allOf:
- $ref: panel-common.yaml#
properties:
compatible:
const: innolux,ej030na
backlight: true
port: true
power-supply: true
reg: true
reset-gpios: true
required:
- compatible
- reg
- power-supply
- reset-gpios
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
spi {
#address-cells = <1>;
#size-cells = <0>;
panel@0 {
compatible = "innolux,ej030na";
reg = <0>;
spi-max-frequency = <10000000>;
reset-gpios = <&gpe 4 GPIO_ACTIVE_LOW>;
power-supply = <&lcd_power>;
backlight = <&backlight>;
port {
panel_input: endpoint {
remote-endpoint = <&panel_output>;
};
};
};
};

24
Documentation/devicetree/bindings/display/panel/panel-simple.yaml
View File

@@ -46,9 +46,13 @@ properties:
# AU Optronics Corporation 11.6" HD (1366x768) color TFT-LCD panel
- auo,b116xw03
# AU Optronics Corporation 13.3" FHD (1920x1080) color TFT-LCD panel
- auo,b133han05
# AU Optronics Corporation 13.3" FHD (1920x1080) color TFT-LCD panel
- auo,b133htn01
# AU Optronics Corporation 13.3" WXGA (1366x768) TFT LCD panel
- auo,b133xtn01
# AU Optronics Corporation 14.0" FHD (1920x1080) color TFT-LCD panel
- auo,b140han06
# AU Optronics Corporation 7.0" FHD (800 x 480) TFT LCD panel
- auo,g070vvn01
# AU Optronics Corporation 10.1" (1280x800) color TFT LCD panel
@@ -110,6 +114,9 @@ properties:
# Emerging Display Technology Corp. 5.7" VGA TFT LCD panel
- edt,et057090dhu
- edt,et070080dh6
# Emerging Display Technology Corp. 3.5" WVGA TFT LCD panel with
# capacitive multitouch
- edt,etm0350g0dh6
# Emerging Display Technology Corp. 480x272 TFT Display with capacitive touch
- edt,etm043080dh6gp
# Emerging Display Technology Corp. 480x272 TFT Display
@@ -128,6 +135,11 @@ properties:
# Emerging Display Technology Corp. WVGA TFT Display with capacitive touch
- edt,etm0700g0dh6
- edt,etm0700g0edh6
# Emerging Display Technology Corp. 5.7" VGA TFT LCD panel with
# capacitive touch
- edt,etmv570g2dhu
# E Ink VB3300-KCA
- eink,vb3300-kca
# Evervision Electronics Co. Ltd. VGG804821 5.0" WVGA TFT LCD Panel
- evervision,vgg804821
# Foxlink Group 5" WVGA TFT LCD panel
@@ -202,8 +214,14 @@ properties:
- logictechno,lt161010-2nhr
# Logic Technologies LT170410-2WHC 10.1" 1280x800 IPS TFT Cap Touch Mod.
- logictechno,lt170410-2whc
# Logic Technologies LTTD800x480 L2RT 7" 800x480 TFT Resistive Touch Module
- logictechno,lttd800480070-l2rt
# Logic Technologies LTTD800480070-L6WH-RT 7” 800x480 TFT Resistive Touch Module
- logictechno,lttd800480070-l6wh-rt
# Mitsubishi "AA070MC01 7.0" WVGA TFT LCD panel
- mitsubishi,aa070mc01-ca1
# Multi-Inno Technology Co.,Ltd MI1010AIT-1CP 10.1" 1280x800 LVDS IPS Cap Touch Mod.
- multi-inno,mi1010ait-1cp
# NEC LCD Technologies, Ltd. 12.1" WXGA (1280x800) LVDS TFT LCD panel
- nec,nl12880bc20-05
# NEC LCD Technologies,Ltd. WQVGA TFT LCD panel
@@ -238,10 +256,14 @@ properties:
- powertip,ph800480t013-idf02
# QiaoDian XianShi Corporation 4"3 TFT LCD panel
- qiaodian,qd43003c0-40
# Shenzhen QiShenglong Industrialist Co., Ltd. Gopher 2b 4.3" 480(RGB)x272 TFT LCD panel
- qishenglong,gopher2b-lcd
# Rocktech Displays Ltd. RK101II01D-CT 10.1" TFT 1280x800
- rocktech,rk101ii01d-ct
# Rocktech Display Ltd. RK070ER9427 800(RGB)x480 TFT LCD panel
- rocktech,rk070er9427
# Samsung 13.3" FHD (1920x1080 pixels) eDP AMOLED panel
- samsung,atna33xc20
# Samsung 12.2" (2560x1600 pixels) TFT LCD panel
- samsung,lsn122dl01-c01
# Samsung Electronics 10.1" WSVGA TFT LCD panel
@@ -298,6 +320,8 @@ properties:
enable-gpios: true
port: true
power-supply: true
no-hpd: true
hpd-gpios: true
additionalProperties: false

99
Documentation/devicetree/bindings/display/panel/samsung,lms380kf01.yaml Normal file
View File

@@ -0,0 +1,99 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/samsung,lms380kf01.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung LMS380KF01 display panel
description: The LMS380KF01 is a 480x800 DPI display panel from Samsung Mobile
Displays (SMD) utilizing the WideChips WS2401 display controller. It can be
used with internal or external backlight control.
The panel must obey the rules for a SPI slave device as specified in
spi/spi-controller.yaml
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
allOf:
- $ref: panel-common.yaml#
properties:
compatible:
const: samsung,lms380kf01
reg: true
interrupts:
description: provides an optional ESD (electrostatic discharge)
interrupt that signals abnormalities in the display hardware.
This can also be raised for other reasons like erroneous
configuration.
maxItems: 1
reset-gpios: true
vci-supply:
description: regulator that supplies the VCI analog voltage
usually around 3.0 V
vccio-supply:
description: regulator that supplies the VCCIO voltage usually
around 1.8 V
backlight: true
spi-cpha: true
spi-cpol: true
spi-max-frequency:
maximum: 1200000
port: true
required:
- compatible
- reg
- spi-cpha
- spi-cpol
- port
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
spi {
compatible = "spi-gpio";
sck-gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
miso-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
mosi-gpios = <&gpio 2 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio 3 GPIO_ACTIVE_HIGH>;
num-chipselects = <1>;
#address-cells = <1>;
#size-cells = <0>;
panel@0 {
compatible = "samsung,lms380kf01";
spi-max-frequency = <1200000>;
spi-cpha;
spi-cpol;
reg = <0>;
vci-supply = <&lcd_3v0_reg>;
vccio-supply = <&lcd_1v8_reg>;
reset-gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio>;
interrupts = <5 IRQ_TYPE_EDGE_RISING>;
port {
panel_in: endpoint {
remote-endpoint = <&display_out>;
};
};
};
};
...

18
Documentation/devicetree/bindings/display/panel/samsung,lms397kf04.yaml
View File

@@ -33,8 +33,11 @@ properties:
backlight: true
spi-cpha: true
spi-cpol: true
spi-max-frequency:
$ref: /schemas/types.yaml#/definitions/uint32
description: inherited as a SPI client node, the datasheet specifies
maximum 300 ns minimum cycle which gives around 3 MHz max frequency
maximum: 3000000
@@ -44,6 +47,9 @@ properties:
required:
- compatible
- reg
- spi-cpha
- spi-cpol
- port
additionalProperties: false
@@ -52,15 +58,23 @@ examples:
#include <dt-bindings/gpio/gpio.h>
spi {
compatible = "spi-gpio";
sck-gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
miso-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
mosi-gpios = <&gpio 2 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio 3 GPIO_ACTIVE_HIGH>;
num-chipselects = <1>;
#address-cells = <1>;
#size-cells = <0>;
panel@0 {
compatible = "samsung,lms397kf04";
spi-max-frequency = <3000000>;
spi-cpha;
spi-cpol;
reg = <0>;
vci-supply = <&lcd_3v0_reg>;
vccio-supply = <&lcd_1v8_reg>;
reset-gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
reset-gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
backlight = <&ktd259>;
port {

1
Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
View File

@@ -23,6 +23,7 @@ Required properties:
Optional properties:
- phys: from general PHY binding: the phandle for the PHY device.
- phy-names: Should be "dphy" if phys references an external phy.
- #phy-cells: Defined when used as ISP phy, should be 0.
- power-domains: a phandle to mipi dsi power domain node.
- resets: list of phandle + reset specifier pairs, as described in [3].
- reset-names: string reset name, must be "apb".

208
Documentation/devicetree/bindings/display/solomon,ssd1307fb.yaml Normal file
View File

@@ -0,0 +1,208 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/solomon,ssd1307fb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Solomon SSD1307 OLED Controller Framebuffer
maintainers:
- Maxime Ripard <mripard@kernel.org>
properties:
compatible:
enum:
- solomon,ssd1305fb-i2c
- solomon,ssd1306fb-i2c
- solomon,ssd1307fb-i2c
- solomon,ssd1309fb-i2c
reg:
maxItems: 1
pwms:
maxItems: 1
reset-gpios:
maxItems: 1
vbat-supply:
description: The supply for VBAT
solomon,height:
$ref: /schemas/types.yaml#/definitions/uint32
default: 16
description:
Height in pixel of the screen driven by the controller
solomon,width:
$ref: /schemas/types.yaml#/definitions/uint32
default: 96
description:
Width in pixel of the screen driven by the controller
solomon,page-offset:
$ref: /schemas/types.yaml#/definitions/uint32
default: 1
description:
Offset of pages (band of 8 pixels) that the screen is mapped to
solomon,segment-no-remap:
type: boolean
description:
Display needs normal (non-inverted) data column to segment mapping
solomon,col-offset:
$ref: /schemas/types.yaml#/definitions/uint32
default: 0
description:
Offset of columns (COL/SEG) that the screen is mapped to
solomon,com-seq:
type: boolean
description:
Display uses sequential COM pin configuration
solomon,com-lrremap:
type: boolean
description:
Display uses left-right COM pin remap
solomon,com-invdir:
type: boolean
description:
Display uses inverted COM pin scan direction
solomon,com-offset:
$ref: /schemas/types.yaml#/definitions/uint32
default: 0
description:
Number of the COM pin wired to the first display line
solomon,prechargep1:
$ref: /schemas/types.yaml#/definitions/uint32
default: 2
description:
Length of deselect period (phase 1) in clock cycles
solomon,prechargep2:
$ref: /schemas/types.yaml#/definitions/uint32
default: 2
description:
Length of precharge period (phase 2) in clock cycles. This needs to be
the higher, the higher the capacitance of the OLED's pixels is.
solomon,dclk-div:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 1
maximum: 16
description:
Clock divisor. The default value is controller-dependent.
solomon,dclk-frq:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 15
description:
Clock frequency, higher value means higher frequency.
The default value is controller-dependent.
solomon,lookup-table:
$ref: /schemas/types.yaml#/definitions/uint8-array
maxItems: 4
description:
8 bit value array of current drive pulse widths for BANK0, and colors A,
B, and C. Each value in range of 31 to 63 for pulse widths of 32 to 64.
Color D is always width 64.
solomon,area-color-enable:
type: boolean
description:
Display uses color mode
solomon,low-power:
type: boolean
description:
Display runs in low power mode
required:
- compatible
- reg
allOf:
- if:
properties:
compatible:
contains:
const: solomon,ssd1305fb-i2c
then:
properties:
solomon,dclk-div:
default: 1
solomon,dclk-frq:
default: 7
- if:
properties:
compatible:
contains:
const: solomon,ssd1306fb-i2c
then:
properties:
solomon,dclk-div:
default: 1
solomon,dclk-frq:
default: 8
- if:
properties:
compatible:
contains:
const: solomon,ssd1307fb-i2c
then:
properties:
solomon,dclk-div:
default: 2
solomon,dclk-frq:
default: 12
required:
- pwms
- if:
properties:
compatible:
contains:
const: solomon,ssd1309fb-i2c
then:
properties:
solomon,dclk-div:
default: 1
solomon,dclk-frq:
default: 10
additionalProperties: false
examples:
- |
i2c1 {
#address-cells = <1>;
#size-cells = <0>;
ssd1307: oled@3c {
compatible = "solomon,ssd1307fb-i2c";
reg = <0x3c>;
pwms = <&pwm 4 3000>;
reset-gpios = <&gpio2 7>;
};
ssd1306: oled@3d {
compatible = "solomon,ssd1306fb-i2c";
reg = <0x3c>;
pwms = <&pwm 4 3000>;
reset-gpios = <&gpio2 7>;
solomon,com-lrremap;
solomon,com-invdir;
solomon,com-offset = <32>;
solomon,lookup-table = /bits/ 8 <0x3f 0x3f 0x3f 0x3f>;
};
};

60
Documentation/devicetree/bindings/display/ssd1307fb.txt
View File

@@ -1,60 +0,0 @@
* Solomon SSD1307 Framebuffer Driver
Required properties:
- compatible: Should be "solomon,<chip>fb-<bus>". The only supported bus for
now is i2c, and the supported chips are ssd1305, ssd1306, ssd1307 and
ssd1309.
- reg: Should contain address of the controller on the I2C bus. Most likely
0x3c or 0x3d
- pwm: Should contain the pwm to use according to the OF device tree PWM
specification [0]. Only required for the ssd1307.
- solomon,height: Height in pixel of the screen driven by the controller
- solomon,width: Width in pixel of the screen driven by the controller
- solomon,page-offset: Offset of pages (band of 8 pixels) that the screen is
mapped to.
Optional properties:
- reset-gpios: The GPIO used to reset the OLED display, if available. See
Documentation/devicetree/bindings/gpio/gpio.txt for details.
- vbat-supply: The supply for VBAT
- solomon,segment-no-remap: Display needs normal (non-inverted) data column
to segment mapping
- solomon,col-offset: Offset of columns (COL/SEG) that the screen is mapped to.
- solomon,com-seq: Display uses sequential COM pin configuration
- solomon,com-lrremap: Display uses left-right COM pin remap
- solomon,com-invdir: Display uses inverted COM pin scan direction
- solomon,com-offset: Number of the COM pin wired to the first display line
- solomon,prechargep1: Length of deselect period (phase 1) in clock cycles.
- solomon,prechargep2: Length of precharge period (phase 2) in clock cycles.
This needs to be the higher, the higher the capacitance
of the OLED's pixels is
- solomon,dclk-div: Clock divisor 1 to 16
- solomon,dclk-frq: Clock frequency 0 to 15, higher value means higher
frequency
- solomon,lookup-table: 8 bit value array of current drive pulse widths for
BANK0, and colors A, B, and C. Each value in range
of 31 to 63 for pulse widths of 32 to 64. Color D
is always width 64.
- solomon,area-color-enable: Display uses color mode
- solomon,low-power. Display runs in low power mode
[0]: Documentation/devicetree/bindings/pwm/pwm.txt
Examples:
ssd1307: oled@3c {
compatible = "solomon,ssd1307fb-i2c";
reg = <0x3c>;
pwms = <&pwm 4 3000>;
reset-gpios = <&gpio2 7>;
};
ssd1306: oled@3c {
compatible = "solomon,ssd1306fb-i2c";
reg = <0x3c>;
pwms = <&pwm 4 3000>;
reset-gpios = <&gpio2 7>;
solomon,com-lrremap;
solomon,com-invdir;
solomon,com-offset = <32>;
solomon,lookup-table = /bits/ 8 <0x3f 0x3f 0x3f 0x3f>;
};

120
Documentation/devicetree/bindings/display/zte,vou.txt
View File

@@ -1,120 +0,0 @@
ZTE VOU Display Controller
This is a display controller found on ZTE ZX296718 SoC. It includes multiple
Graphic Layer (GL) and Video Layer (VL), two Mixers/Channels, and a few blocks
handling scaling, color space conversion etc. VOU also integrates the support
for typical output devices, like HDMI, TV Encoder, VGA, and RGB LCD.
* Master VOU node
It must be the parent node of all the sub-device nodes.
Required properties:
- compatible: should be "zte,zx296718-vou"
- #address-cells: should be <1>
- #size-cells: should be <1>
- ranges: list of address translations between VOU and sub-devices
* VOU DPC device
Required properties:
- compatible: should be "zte,zx296718-dpc"
- reg: Physical base address and length of DPC register regions, one for each
entry in 'reg-names'
- reg-names: The names of register regions. The following regions are required:
"osd"
"timing_ctrl"
"dtrc"
"vou_ctrl"
"otfppu"
- interrupts: VOU DPC interrupt number to CPU
- clocks: A list of phandle + clock-specifier pairs, one for each entry
in 'clock-names'
- clock-names: A list of clock names. The following clocks are required:
"aclk"
"ppu_wclk"
"main_wclk"
"aux_wclk"
* HDMI output device
Required properties:
- compatible: should be "zte,zx296718-hdmi"
- reg: Physical base address and length of the HDMI device IO region
- interrupts : HDMI interrupt number to CPU
- clocks: A list of phandle + clock-specifier pairs, one for each entry
in 'clock-names'
- clock-names: A list of clock names. The following clocks are required:
"osc_cec"
"osc_clk"
"xclk"
* TV Encoder output device
Required properties:
- compatible: should be "zte,zx296718-tvenc"
- reg: Physical base address and length of the TVENC device IO region
- zte,tvenc-power-control: the phandle to SYSCTRL block followed by two
integer cells. The first cell is the offset of SYSCTRL register used
to control TV Encoder DAC power, and the second cell is the bit mask.
* VGA output device
Required properties:
- compatible: should be "zte,zx296718-vga"
- reg: Physical base address and length of the VGA device IO region
- interrupts : VGA interrupt number to CPU
- clocks: Phandle with clock-specifier pointing to VGA I2C clock.
- clock-names: Must be "i2c_wclk".
- zte,vga-power-control: the phandle to SYSCTRL block followed by two
integer cells. The first cell is the offset of SYSCTRL register used
to control VGA DAC power, and the second cell is the bit mask.
Example:
vou: vou@1440000 {
compatible = "zte,zx296718-vou";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1440000 0x10000>;
dpc: dpc@0 {
compatible = "zte,zx296718-dpc";
reg = <0x0000 0x1000>, <0x1000 0x1000>,
<0x5000 0x1000>, <0x6000 0x1000>,
<0xa000 0x1000>;
reg-names = "osd", "timing_ctrl",
"dtrc", "vou_ctrl",
"otfppu";
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topcrm VOU_ACLK>, <&topcrm VOU_PPU_WCLK>,
<&topcrm VOU_MAIN_WCLK>, <&topcrm VOU_AUX_WCLK>;
clock-names = "aclk", "ppu_wclk",
"main_wclk", "aux_wclk";
};
vga: vga@8000 {
compatible = "zte,zx296718-vga";
reg = <0x8000 0x1000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topcrm VGA_I2C_WCLK>;
clock-names = "i2c_wclk";
zte,vga-power-control = <&sysctrl 0x170 0xe0>;
};
hdmi: hdmi@c000 {
compatible = "zte,zx296718-hdmi";
reg = <0xc000 0x4000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
clocks = <&topcrm HDMI_OSC_CEC>,
<&topcrm HDMI_OSC_CLK>,
<&topcrm HDMI_XCLK>;
clock-names = "osc_cec", "osc_clk", "xclk";
};
tvenc: tvenc@2000 {
compatible = "zte,zx296718-tvenc";
reg = <0x2000 0x1000>;
zte,tvenc-power-control = <&sysctrl 0x170 0x10>;
};
};

12
Documentation/devicetree/bindings/dma/allwinner,sun6i-a31-dma.yaml
View File

@@ -19,12 +19,12 @@ properties:
description: The cell is the request line number.
compatible:
oneOf:
- const: allwinner,sun6i-a31-dma
- const: allwinner,sun8i-a23-dma
- const: allwinner,sun8i-a83t-dma
- const: allwinner,sun8i-h3-dma
- const: allwinner,sun8i-v3s-dma
enum:
- allwinner,sun6i-a31-dma
- allwinner,sun8i-a23-dma
- allwinner,sun8i-a83t-dma
- allwinner,sun8i-h3-dma
- allwinner,sun8i-v3s-dma
reg:
maxItems: 1

1
Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
View File

@@ -9,6 +9,7 @@ Required properties:
"fsl,imx53-sdma"
"fsl,imx6q-sdma"
"fsl,imx7d-sdma"
"fsl,imx6ul-sdma"
"fsl,imx8mq-sdma"
"fsl,imx8mm-sdma"
"fsl,imx8mn-sdma"

8
Documentation/devicetree/bindings/firmware/arm,scmi.yaml
View File

@@ -34,6 +34,10 @@ properties:
- description: SCMI compliant firmware with ARM SMC/HVC transport
items:
- const: arm,scmi-smc
- description: SCMI compliant firmware with SCMI Virtio transport.
The virtio transport only supports a single device.
items:
- const: arm,scmi-virtio
interrupts:
description:
@@ -172,6 +176,7 @@ patternProperties:
Each sub-node represents a protocol supported. If the platform
supports a dedicated communication channel for a particular protocol,
then the corresponding transport properties must be present.
The virtio transport does not support a dedicated communication channel.
properties:
reg:
@@ -195,7 +200,6 @@ patternProperties:
required:
- compatible
- shmem
if:
properties:
@@ -209,6 +213,7 @@ then:
required:
- mboxes
- shmem
else:
if:
@@ -219,6 +224,7 @@ else:
then:
required:
- arm,smc-id
- shmem
examples:
- |

6
Documentation/devicetree/bindings/firmware/arm,scpi.yaml
View File

@@ -131,9 +131,9 @@ properties:
properties:
compatible:
oneOf:
- const: arm,scpi-dvfs-clocks
- const: arm,scpi-variable-clocks
enum:
- arm,scpi-dvfs-clocks
- arm,scpi-variable-clocks
'#clock-cells':
const: 1

25
Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
View File

@@ -1,25 +0,0 @@
Devicetree bindings for Zynq Ultrascale MPSoC FPGA Manager.
The ZynqMP SoC uses the PCAP (Processor configuration Port) to configure the
Programmable Logic (PL). The configuration uses the firmware interface.
Required properties:
- compatible: should contain "xlnx,zynqmp-pcap-fpga"
Example for full FPGA configuration:
fpga-region0 {
compatible = "fpga-region";
fpga-mgr = <&zynqmp_pcap>;
#address-cells = <0x1>;
#size-cells = <0x1>;
};
firmware {
zynqmp_firmware: zynqmp-firmware {
compatible = "xlnx,zynqmp-firmware";
method = "smc";
zynqmp_pcap: pcap {
compatible = "xlnx,zynqmp-pcap-fpga";
};
};
};

36
Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.yaml Normal file
View File

@@ -0,0 +1,36 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/fpga/xlnx,zynqmp-pcap-fpga.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Zynq Ultrascale MPSoC FPGA Manager Device Tree Bindings
maintainers:
- Nava kishore Manne <navam@xilinx.com>
description: |
Device Tree Bindings for Zynq Ultrascale MPSoC FPGA Manager.
The ZynqMP SoC uses the PCAP (Processor Configuration Port) to
configure the Programmable Logic (PL). The configuration uses the
firmware interface.
properties:
compatible:
const: xlnx,zynqmp-pcap-fpga
required:
- compatible
additionalProperties: false
examples:
- |
firmware {
zynqmp_firmware: zynqmp-firmware {
zynqmp_pcap: pcap {
compatible = "xlnx,zynqmp-pcap-fpga";
};
};
};
...

77
Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml Normal file
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@@ -0,0 +1,77 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/aspeed,sgpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Aspeed SGPIO controller
maintainers:
- Andrew Jeffery <andrew@aj.id.au>
description:
This SGPIO controller is for ASPEED AST2400, AST2500 and AST2600 SoC,
AST2600 have two sgpio master one with 128 pins another one with 80 pins,
AST2500/AST2400 have one sgpio master with 80 pins. Each of the Serial
GPIO pins can be programmed to support the following options
- Support interrupt option for each input port and various interrupt
sensitivity option (level-high, level-low, edge-high, edge-low)
- Support reset tolerance option for each output port
- Directly connected to APB bus and its shift clock is from APB bus clock
divided by a programmable value.
- Co-work with external signal-chained TTL components (74LV165/74LV595)
properties:
compatible:
enum:
- aspeed,ast2400-sgpio
- aspeed,ast2500-sgpio
- aspeed,ast2600-sgpiom
reg:
maxItems: 1
gpio-controller: true
'#gpio-cells':
const: 2
interrupts:
maxItems: 1
interrupt-controller: true
clocks:
maxItems: 1
ngpios: true
bus-frequency: true
required:
- compatible
- reg
- gpio-controller
- '#gpio-cells'
- interrupts
- interrupt-controller
- ngpios
- clocks
- bus-frequency
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/aspeed-clock.h>
sgpio: sgpio@1e780200 {
#gpio-cells = <2>;
compatible = "aspeed,ast2500-sgpio";
gpio-controller;
interrupts = <40>;
reg = <0x1e780200 0x0100>;
clocks = <&syscon ASPEED_CLK_APB>;
interrupt-controller;
ngpios = <80>;
bus-frequency = <12000000>;
};

46
Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt
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@@ -1,46 +0,0 @@
Aspeed SGPIO controller Device Tree Bindings
--------------------------------------------
This SGPIO controller is for ASPEED AST2500 SoC, it supports up to 80 full
featured Serial GPIOs. Each of the Serial GPIO pins can be programmed to
support the following options:
- Support interrupt option for each input port and various interrupt
sensitivity option (level-high, level-low, edge-high, edge-low)
- Support reset tolerance option for each output port
- Directly connected to APB bus and its shift clock is from APB bus clock
divided by a programmable value.
- Co-work with external signal-chained TTL components (74LV165/74LV595)
Required properties:
- compatible : Should be one of
"aspeed,ast2400-sgpio", "aspeed,ast2500-sgpio"
- #gpio-cells : Should be 2, see gpio.txt
- reg : Address and length of the register set for the device
- gpio-controller : Marks the device node as a GPIO controller
- interrupts : Interrupt specifier, see interrupt-controller/interrupts.txt
- interrupt-controller : Mark the GPIO controller as an interrupt-controller
- ngpios : number of *hardware* GPIO lines, see gpio.txt. This will expose
2 software GPIOs per hardware GPIO: one for hardware input, one for hardware
output. Up to 80 pins, must be a multiple of 8.
- clocks : A phandle to the APB clock for SGPM clock division
- bus-frequency : SGPM CLK frequency
The sgpio and interrupt properties are further described in their respective
bindings documentation:
- Documentation/devicetree/bindings/gpio/gpio.txt
- Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
Example:
sgpio: sgpio@1e780200 {
#gpio-cells = <2>;
compatible = "aspeed,ast2500-sgpio";
gpio-controller;
interrupts = <40>;
reg = <0x1e780200 0x0100>;
clocks = <&syscon ASPEED_CLK_APB>;
interrupt-controller;
ngpios = <8>;
bus-frequency = <12000000>;
};

1
Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
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@@ -20,6 +20,7 @@ properties:
- mediatek,mt8183-mali
- realtek,rtd1619-mali
- rockchip,px30-mali
- rockchip,rk3568-mali
- const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable
reg:

12
Documentation/devicetree/bindings/hwmon/max1619.txt
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@@ -1,12 +0,0 @@
Bindings for MAX1619 Temperature Sensor
Required properties:
- compatible : "maxim,max1619"
- reg : I2C address, one of 0x18, 0x19, 0x1a, 0x29, 0x2a, 0x2b, 0x4c, or
0x4d, 0x4e
Example:
temp@4c {
compatible = "maxim,max1619";
reg = <0x4c>;
};

46
Documentation/devicetree/bindings/i2c/brcm,iproc-i2c.txt
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@@ -1,46 +0,0 @@
Broadcom iProc I2C controller
Required properties:
- compatible:
Must be "brcm,iproc-i2c" or "brcm,iproc-nic-i2c"
- reg:
Define the base and range of the I/O address space that contain the iProc
I2C controller registers
- clock-frequency:
This is the I2C bus clock. Need to be either 100000 or 400000
- #address-cells:
Always 1 (for I2C addresses)
- #size-cells:
Always 0
Optional properties:
- interrupts:
Should contain the I2C interrupt. For certain revisions of the I2C
controller, I2C interrupt is unwired to the interrupt controller. In such
case, this property should be left unspecified, and driver will fall back
to polling mode
- brcm,ape-hsls-addr-mask:
Required for "brcm,iproc-nic-i2c". Host view of address mask into the
'APE' co-processor. Value must be unsigned, 32-bit
Example:
i2c0: i2c@18008000 {
compatible = "brcm,iproc-i2c";
reg = <0x18008000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
clock-frequency = <100000>;
codec: wm8750@1a {
compatible = "wlf,wm8750";
reg = <0x1a>;
};
};

71
Documentation/devicetree/bindings/i2c/brcm,iproc-i2c.yaml Normal file
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@@ -0,0 +1,71 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/brcm,iproc-i2c.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom iProc I2C controller
maintainers:
- Rafał Miłecki <rafal@milecki.pl>
properties:
compatible:
enum:
- brcm,iproc-i2c
- brcm,iproc-nic-i2c
reg:
maxItems: 1
clock-frequency:
enum: [ 100000, 400000 ]
interrupts:
description: |
Should contain the I2C interrupt. For certain revisions of the I2C
controller, I2C interrupt is unwired to the interrupt controller. In such
case, this property should be left unspecified, and driver will fall back
to polling mode
maxItems: 1
brcm,ape-hsls-addr-mask:
$ref: /schemas/types.yaml#/definitions/uint32
description: Host view of address mask into the 'APE' co-processor
allOf:
- $ref: /schemas/i2c/i2c-controller.yaml#
- if:
properties:
compatible:
contains:
const: brcm,iproc-nic-i2c
then:
required:
- brcm,ape-hsls-addr-mask
unevaluatedProperties: false
required:
- reg
- clock-frequency
- '#address-cells'
- '#size-cells'
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
i2c@18008000 {
compatible = "brcm,iproc-i2c";
reg = <0x18008000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
clock-frequency = <100000>;
wm8750@1a {
compatible = "wlf,wm8750";
reg = <0x1a>;
};
};

30
Documentation/devicetree/bindings/i2c/renesas,riic.yaml
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@@ -27,14 +27,25 @@ properties:
interrupts:
items:
- description: Transmit End Interrupt (TEI)
- description: Receive Data Full Interrupt (RI)
- description: Transmit Data Empty Interrupt (TI)
- description: Stop Condition Detection Interrupt (SPI)
- description: Start Condition Detection Interrupt (STI)
- description: NACK Reception Interrupt (NAKI)
- description: Arbitration-Lost Interrupt (ALI)
- description: Timeout Interrupt (TMOI)
- description: Transmit End Interrupt
- description: Receive Data Full Interrupt
- description: Transmit Data Empty Interrupt
- description: Stop Condition Detection Interrupt
- description: Start Condition Detection Interrupt
- description: NACK Reception Interrupt
- description: Arbitration-Lost Interrupt
- description: Timeout Interrupt
interrupt-names:
items:
- const: tei
- const: ri
- const: ti
- const: spi
- const: sti
- const: naki
- const: ali
- const: tmoi
clock-frequency:
description:
@@ -51,6 +62,7 @@ required:
- compatible
- reg
- interrupts
- interrupt-names
- clocks
- clock-frequency
- power-domains
@@ -85,6 +97,8 @@ examples:
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tei", "ri", "ti", "spi", "sti", "naki", "ali",
"tmoi";
clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
clock-frequency = <100000>;
power-domains = <&cpg_clocks>;

10
Documentation/devicetree/bindings/i2c/ti,omap4-i2c.yaml
View File

@@ -72,11 +72,11 @@ additionalProperties: false
if:
properties:
compatible:
oneOf:
- const: ti,omap2420-i2c
- const: ti,omap2430-i2c
- const: ti,omap3-i2c
- const: ti,omap4-i2c
enum:
- ti,omap2420-i2c
- ti,omap2430-i2c
- ti,omap3-i2c
- ti,omap4-i2c
then:
properties:

61
Documentation/devicetree/bindings/iio/accel/bosch,bma180.yaml
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@@ -1,61 +0,0 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/accel/bosch,bma180.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Bosch BMA023 / BMA150/ BMA180 / BMA250 / SMB380 triaxial accelerometers
maintainers:
- Jonathan Cameron <jic23@kernel.org>
description: |
https://media.digikey.com/pdf/Data%20Sheets/Bosch/BMA150.pdf
http://omapworld.com/BMA180_111_1002839.pdf
http://ae-bst.resource.bosch.com/media/products/dokumente/bma250/bst-bma250-ds002-05.pdf
properties:
compatible:
enum:
- bosch,bma023
- bosch,bma150
- bosch,bma180
- bosch,bma250
- bosch,smb380
reg:
maxItems: 1
vdd-supply: true
vddio-supply: true
interrupts:
minItems: 1
maxItems: 2
description: |
Type should be either IRQ_TYPE_LEVEL_HIGH or IRQ_TYPE_EDGE_RISING.
For the bma250 the first interrupt listed must be the one
connected to the INT1 pin, the second (optional) interrupt
listed must be the one connected to the INT2 pin.
required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
accel@40 {
compatible = "bosch,bma180";
reg = <0x40>;
interrupt-parent = <&gpio6>;
interrupts = <18 (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING)>;
};
};
...

55
Documentation/devicetree/bindings/iio/accel/bosch,bma255.yaml
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@@ -8,6 +8,7 @@ title: Bosch BMA255 and Similar Accelerometers
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
- Stephan Gerhold <stephan@gerhold.net>
description:
3 axis accelerometers with varying range and I2C or SPI
@@ -16,15 +17,24 @@ description:
properties:
compatible:
enum:
- bosch,bmc150_accel
- bosch,bmi055_accel
# bmc150-accel driver in Linux
- bosch,bma222
- bosch,bma222e
- bosch,bma250e
- bosch,bma253
- bosch,bma254
- bosch,bma255
- bosch,bma250e
- bosch,bma222
- bosch,bma222e
- bosch,bma280
- bosch,bmc150_accel
- bosch,bmc156_accel
- bosch,bmi055_accel
# bma180 driver in Linux
- bosch,bma023
- bosch,bma150
- bosch,bma180
- bosch,bma250
- bosch,smb380
reg:
maxItems: 1
@@ -36,9 +46,21 @@ properties:
minItems: 1
maxItems: 2
description: |
The first interrupt listed must be the one connected to the INT1 pin,
the second (optional) interrupt listed must be the one connected to the
INT2 pin (if available).
Without interrupt-names, the first interrupt listed must be the one
connected to the INT1 pin, the second (optional) interrupt listed must be
the one connected to the INT2 pin (if available). The type should be
IRQ_TYPE_EDGE_RISING.
BMC156 does not have an INT1 pin, therefore the first interrupt pin is
always treated as INT2.
interrupt-names:
minItems: 1
maxItems: 2
items:
enum:
- INT1
- INT2
mount-matrix:
description: an optional 3x3 mounting rotation matrix.
@@ -63,7 +85,22 @@ examples:
reg = <0x08>;
vddio-supply = <&vddio>;
vdd-supply = <&vdd>;
interrupts = <57 IRQ_TYPE_EDGE_FALLING>;
interrupts = <57 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "INT1";
};
};
- |
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
accelerometer@10 {
compatible = "bosch,bmc156_accel";
reg = <0x10>;
vddio-supply = <&vddio>;
vdd-supply = <&vdd>;
interrupts = <116 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "INT2";
};
};
- |

19
Documentation/devicetree/bindings/iio/adc/ingenic,adc.yaml
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@@ -23,6 +23,8 @@ properties:
enum:
- ingenic,jz4725b-adc
- ingenic,jz4740-adc
- ingenic,jz4760-adc
- ingenic,jz4760b-adc
- ingenic,jz4770-adc
'#io-channel-cells':
@@ -43,6 +45,23 @@ properties:
interrupts:
maxItems: 1
ingenic,use-internal-divider:
description:
If present, battery voltage is read from the VBAT_IR pin, which has an
internal 1/4 divider. If absent, it is read through the VBAT_ER pin,
which does not have such a divider.
type: boolean
if:
not:
properties:
compatible:
contains:
const: ingenic,jz4760b-adc
then:
properties:
ingenic,use-internal-divider: false
required:
- compatible
- '#io-channel-cells'

134
Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml Normal file
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@@ -0,0 +1,134 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/adc/renesas,rzg2l-adc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas RZ/G2L ADC
maintainers:
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
description: |
A/D Converter block is a successive approximation analog-to-digital converter
with a 12-bit accuracy. Up to eight analog input channels can be selected.
Conversions can be performed in single or repeat mode. Result of the ADC is
stored in a 32-bit data register corresponding to each channel.
properties:
compatible:
items:
- enum:
- renesas,r9a07g044-adc # RZ/G2{L,LC}
- const: renesas,rzg2l-adc
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: converter clock
- description: peripheral clock
clock-names:
items:
- const: adclk
- const: pclk
power-domains:
maxItems: 1
resets:
maxItems: 2
reset-names:
items:
- const: presetn
- const: adrst-n
'#address-cells':
const: 1
'#size-cells':
const: 0
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- power-domains
- resets
- reset-names
patternProperties:
"^channel@[0-7]$":
$ref: "adc.yaml"
type: object
description: |
Represents the external channels which are connected to the ADC.
properties:
reg:
description: |
The channel number. It can have up to 8 channels numbered from 0 to 7.
items:
- minimum: 0
maximum: 7
required:
- reg
additionalProperties: false
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/r9a07g044-cpg.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
adc: adc@10059000 {
compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc";
reg = <0x10059000 0x400>;
interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>,
<&cpg CPG_MOD R9A07G044_ADC_PCLK>;
clock-names = "adclk", "pclk";
power-domains = <&cpg>;
resets = <&cpg R9A07G044_ADC_PRESETN>,
<&cpg R9A07G044_ADC_ADRST_N>;
reset-names = "presetn", "adrst-n";
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
reg = <0>;
};
channel@1 {
reg = <1>;
};
channel@2 {
reg = <2>;
};
channel@3 {
reg = <3>;
};
channel@4 {
reg = <4>;
};
channel@5 {
reg = <5>;
};
channel@6 {
reg = <6>;
};
channel@7 {
reg = <7>;
};
};

1
Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml
View File

@@ -20,6 +20,7 @@ properties:
- rockchip,px30-saradc
- rockchip,rk3308-saradc
- rockchip,rk3328-saradc
- rockchip,rk3568-saradc
- rockchip,rv1108-saradc
- const: rockchip,rk3399-saradc

268
Documentation/devicetree/bindings/iio/dac/adi,ad5064.yaml Normal file
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@@ -0,0 +1,268 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/dac/adi,ad5064.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analog Devices AD5064 and similar DACs
maintainers:
- Lars-Peter Clausen <lars@metafoo.de>
- Jonathan Cameron <jic23@kernel.org>
description: |
A range of similar DAC devices with between 1 and 12 channels. Some parts
have internal references, others require a single shared external reference
and the remainder have a separate reference pin for each DAC.
properties:
compatible:
oneOf:
- description: I2C devics
enum:
- adi,ad5024
- adi,ad5025
- adi,ad5044
- adi,ad5045
- adi,ad5064
- adi,ad5064-1
- adi,ad5065
- adi,ad5628-1
- adi,ad5628-2
- adi,ad5648-1
- adi,ad5648-2
- adi,ad5666-1
- adi,ad5666-2
- adi,ad5668-1
- adi,ad5668-2
- adi,ad5668-3
- description: SPI devices
enum:
- adi,ad5625
- adi,ad5625r-1v25
- adi,ad5625r-2v5
- adi,ad5627
- adi,ad5627r-1v25
- adi,ad5627r-2v5
- adi,ad5629-1
- adi,ad5629-2
- adi,ad5629-3
- adi,ad5645r-1v25
- adi,ad5645r-2v5
- adi,ad5665
- adi,ad5665r-1v25
- adi,ad5665r-2v5
- adi,ad5667
- adi,ad5667r-1v25
- adi,ad5667r-2v5
- adi,ad5669-1
- adi,ad5669-2
- adi,ad5669-3
- lltc,ltc2606
- lltc,ltc2607
- lltc,ltc2609
- lltc,ltc2616
- lltc,ltc2617
- lltc,ltc2619
- lltc,ltc2626
- lltc,ltc2627
- lltc,ltc2629
- lltc,ltc2631-l12
- lltc,ltc2631-h12
- lltc,ltc2631-l10
- lltc,ltc2631-h10
- lltc,ltc2631-l8
- lltc,ltc2631-h8
- lltc,ltc2633-l12
- lltc,ltc2633-h12
- lltc,ltc2633-l10
- lltc,ltc2633-h10
- lltc,ltc2633-l8
- lltc,ltc2633-h8
- lltc,ltc2635-l12
- lltc,ltc2635-h12
- lltc,ltc2635-l10
- lltc,ltc2635-h10
- lltc,ltc2635-l8
- lltc,ltc2635-h8
reg:
maxItems: 1
vrefA-supply: true
vrefB-supply: true
vrefC-supply: true
vrefD-supply: true
vref-supply: true
spi-max-frequency: true
additionalProperties: false
required:
- compatible
- reg
allOf:
- # Shared external vref, no internal reference
if:
properties:
compatible:
contains:
enum:
- adi,ad5064-1
- adi,ad5625
- adi,ad5627
- adi,ad5665
- adi,ad5667
- lltc,ltc2606
- lltc,ltc2607
- lltc,ltc2616
- lltc,ltc2617
- lltc,ltc2626
- lltc,ltc2627
then:
properties:
vref-supply: true
vrefA-supply: false
vrefB-supply: false
vrefC-supply: false
vrefD-supply: false
required:
- vref-supply
- # Shared external vref, internal reference available
if:
properties:
compatible:
contains:
enum:
- adi,ad5625r-1v25
- adi,ad5625r-2v5
- adi,ad5627r-1v25
- adi,ad5627r-2v5
- adi,ad5628-1
- adi,ad5628-2
- adi,ad5629-1
- adi,ad5629-2
- adi,ad5629-3
- adi,ad5645r-1v25
- adi,ad5645r-2v5
- adi,ad5647r-1v25
- adi,ad5647r-2v5
- adi,ad5648-1
- adi,ad5648-2
- adi,ad5665r-1v25
- adi,ad5665r-2v5
- adi,ad5666-1
- adi,ad5666-2
- adi,ad5667r-1v25
- adi,ad5667r-2v5
- adi,ad5668-1
- adi,ad5668-2
- adi,ad5668-3
- adi,ad5669-1
- adi,ad5669-2
- adi,ad5669-3
- lltc,ltc2631-l12
- lltc,ltc2631-h12
- lltc,ltc2631-l10
- lltc,ltc2631-h10
- lltc,ltc2631-l8
- lltc,ltc2631-h8
- lltc,ltc2633-l12
- lltc,ltc2633-h12
- lltc,ltc2633-l10
- lltc,ltc2633-h10
- lltc,ltc2633-l8
- lltc,ltc2633-h8
- lltc,ltc2635-l12
- lltc,ltc2635-h12
- lltc,ltc2635-l10
- lltc,ltc2635-h10
- lltc,ltc2635-l8
- lltc,ltc2635-h8
then:
properties:
vref-supply: true
vrefA-supply: false
vrefB-supply: false
vrefC-supply: false
vrefD-supply: false
- # 4 input devices, separate vrefs, no internal reference
if:
properties:
compatible:
contains:
enum:
- adi,ad5024
- adi,ad5044
- adi,ad5064
- lltc,ltc2609
- lltc,ltc2619
- lltc,ltc2629
then:
properties:
vrefA-supply: true
vrefB-supply: true
vrefC-supply: true
vrefD-supply: true
vref-supply: false
required:
- vrefA-supply
- vrefB-supply
- vrefC-supply
- vrefD-supply
- # 2 input devices, separate vrefs, no internal reference
if:
properties:
compatible:
contains:
enum:
- adi,ad5025
- adi,ad5045
- adi,ad5065
then:
properties:
vrefA-supply: true
vrefB-supply: true
vrefC-supply: false
vrefD-supply: false
vref-supply: false
required:
- vrefA-supply
- vrefB-supply
examples:
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
dac@0 {
reg = <0>;
compatible = "adi,ad5625";
vref-supply = <&dac_vref>;
};
};
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
dac@0 {
reg = <0>;
compatible = "adi,ad5625r-1v25";
};
};
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
dac@42 {
reg = <0x42>;
compatible = "adi,ad5024";
vrefA-supply = <&dac_vref>;
vrefB-supply = <&dac_vref>;
vrefC-supply = <&dac_vref2>;
vrefD-supply = <&dac_vref2>;
};
};
...

79
Documentation/devicetree/bindings/iio/dac/adi,ad5360.yaml Normal file
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@@ -0,0 +1,79 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/dac/adi,ad5360.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analog Devices AD5360 and similar DACs
maintainers:
- Lars-Peter Clausen <lars@metafoo.de>
- Jonathan Cameron <jic23@kernel.org>
properties:
compatible:
enum:
- adi,ad5360
- adi,ad5361
- adi,ad5363
- adi,ad5370
- adi,ad5371
- adi,ad5372
- adi,ad5373
reg:
maxItems: 1
vref0-supply: true
vref1-supply: true
vref2-supply: true
spi-max-frequency: true
additionalProperties: false
required:
- compatible
- reg
- vref0-supply
- vref1-supply
allOf:
- if:
properties:
compatible:
contains:
enum:
- adi,ad5360
- adi,ad5361
- adi,ad5363
- adi,ad5370
- adi,ad5372
- adi,ad5373
then:
properties:
vref2-supply: false
- if:
properties:
compatible:
contains:
enum:
- adi,ad5371
then:
required:
- vref2-supply
examples:
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
dac@0 {
reg = <0>;
compatible = "adi,ad5371";
vref0-supply = <&dac_vref0>;
vref1-supply = <&dac_vref1>;
vref2-supply = <&dac_vref2>;
};
};
...

70
Documentation/devicetree/bindings/iio/dac/adi,ad5380.yaml Normal file
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@@ -0,0 +1,70 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/dac/adi,ad5380.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analog Devices AD5380 and similar DACs
maintainers:
- Lars-Peter Clausen <lars@metafoo.de>
- Jonathan Cameron <jic23@kernel.org>
description: |
DAC devices supporting both SPI and I2C interfaces.
properties:
compatible:
enum:
- adi,ad5380-3
- adi,ad5380-5
- adi,ad5381-3
- adi,ad5381-5
- adi,ad5382-3
- adi,ad5382-5
- adi,ad5383-3
- adi,ad5383-5
- adi,ad5384-3
- adi,ad5384-5
- adi,ad5390-3
- adi,ad5390-5
- adi,ad5391-3
- adi,ad5391-5
- adi,ad5392-3
- adi,ad5392-5
reg:
maxItems: 1
vref-supply:
description:
If not supplied devices will use internal regulators.
spi-max-frequency: true
additionalProperties: false
required:
- compatible
- reg
examples:
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
dac@0 {
reg = <0>;
compatible = "adi,ad5390-5";
vref-supply = <&dacvref>;
};
};
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
dac@42 {
reg = <0x42>;
compatible = "adi,ad5380-3";
};
};
...

51
Documentation/devicetree/bindings/iio/dac/adi,ad5421.yaml Normal file
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@@ -0,0 +1,51 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/dac/adi,ad5421.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analog Devices AD5421 DAC
maintainers:
- Lars-Peter Clausen <lars@metafoo.de>
- Jonathan Cameron <jic23@kernel.org>
description: |
AD5421 is designed for us in loop-powered, 4 mA to 20 mA smart transmitter
applications. It provides a 16-bit DAC, current amplifier, voltage regulator
to drive the loop and a voltage reference.
properties:
compatible:
const: adi,ad5421
reg:
maxItems: 1
interrupts:
maxItems: 1
description: Fault signal.
spi-max-frequency: true
required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
spi {
#address-cells = <1>;
#size-cells = <0>;
dac@0 {
compatible = "adi,ad5421";
reg = <0>;
spi-max-frequency = <30000000>;
interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
};
};
...

97
Documentation/devicetree/bindings/iio/dac/adi,ad5449.yaml Normal file
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@@ -0,0 +1,97 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/dac/adi,ad5449.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analog Devices AD5449 and similar DACs
maintainers:
- Lars-Peter Clausen <lars@metafoo.de>
- Jonathan Cameron <jic23@kernel.org>
description:
Family of multiplying DACs from Analog Devices
properties:
compatible:
enum:
- adi,ad5415
- adi,ad5426
- adi,ad5429
- adi,ad5432
- adi,ad5439
- adi,ad5443
- adi,ad5449
reg:
maxItems: 1
spi-max-frequency: true
VREF-supply: true
VREFA-supply: true
VREFB-supply: true
additionalProperties: false
required:
- compatible
- reg
allOf:
- if:
properties:
compatible:
contains:
enum:
- adi,ad5415
- adi,ad5426
- adi,ad5432
then:
properties:
VREF-supply: true
VREFA-supply: false
VREFB-supply: false
required:
- VREF-supply
- if:
properties:
compatible:
contains:
enum:
- adi,ad5429
- adi,ad5439
- adi,ad5449
then:
properties:
VREF-supply: false
VREFA-supply: true
VREFB-supply: true
required:
- VREFA-supply
- VREFB-supply
examples:
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
dac@0 {
reg = <0>;
compatible = "adi,ad5415";
VREF-supply = <&dac_ref>;
};
};
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
dac@0 {
reg = <0>;
compatible = "adi,ad5429";
VREFA-supply = <&dac_refA>;
VREFB-supply = <&dac_refB>;
};
};
...

50
Documentation/devicetree/bindings/iio/dac/adi,ad5504.yaml Normal file
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@@ -0,0 +1,50 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/dac/adi,ad5504.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analog Devices AD5501 and AD5504 DACs
maintainers:
- Lars-Peter Clausen <lars@metafoo.de>
- Jonathan Cameron <jic23@kernel.org>
description:
High voltage (up to 60V) DACs with temperature sensor alarm function
properties:
compatible:
enum:
- adi,ad5501
- adi,ad5504
reg:
maxItems: 1
interrupts:
description: Used for temperature alarm.
maxItems: 1
vcc-supply: true
additionalProperties: false
required:
- compatible
- reg
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
spi {
#address-cells = <1>;
#size-cells = <0>;
dac@0 {
reg = <0>;
compatible = "adi,ad5504";
vcc-supply = <&dac_vcc>;
interrupts = <55 IRQ_TYPE_EDGE_FALLING>;
};
};
...

47
Documentation/devicetree/bindings/iio/dac/adi,ad5624r.yaml Normal file
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@@ -0,0 +1,47 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/dac/adi,ad5624r.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analog Devices AD5624r and similar DACs
maintainers:
- Jonathan Cameron <jic23@kernel.org>
properties:
compatible:
enum:
- adi,ad5624r3
- adi,ad5644r3
- adi,ad5664r3
- adi,ad5624r5
- adi,ad5644r5
- adi,ad5664r5
reg:
maxItems: 1
spi-max-frequency: true
vref-supply:
description: If not present, internal reference will be used.
additionalProperties: false
required:
- compatible
- reg
examples:
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
dac@0 {
reg = <0>;
compatible = "adi,ad5624r3";
vref-supply = <&vref>;
};
};
...

75
Documentation/devicetree/bindings/iio/dac/adi,ad5686.yaml Normal file
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@@ -0,0 +1,75 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/dac/adi,ad5686.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analog Devices AD5360 and similar DACs
maintainers:
- Michael Hennerich <michael.hennerich@analog.com>
- Jonathan Cameron <jic23@kernel.org>
properties:
compatible:
oneOf:
- description: SPI devices
enum:
- adi,ad5310r
- adi,ad5672r
- adi,ad5674r
- adi,ad5676
- adi,ad5676r
- adi,ad5679r
- adi,ad5681r
- adi,ad5682r
- adi,ad5683
- adi,ad5683r
- adi,ad5684
- adi,ad5684r
- adi,ad5685r
- adi,ad5686
- adi,ad5686r
- description: I2C devices
enum:
- adi,ad5311r
- adi,ad5338r
- adi,ad5671r
- adi,ad5675r
- adi,ad5691r
- adi,ad5692r
- adi,ad5693
- adi,ad5693r
- adi,ad5694
- adi,ad5694r
- adi,ad5695r
- adi,ad5696
- adi,ad5696r
reg:
maxItems: 1
vcc-supply:
description: If not supplied the internal reference is used.
spi-max-frequency: true
additionalProperties: false
required:
- compatible
- reg
examples:
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
dac@0 {
reg = <0>;
compatible = "adi,ad5310r";
vcc-supply = <&dac_vref0>;
};
};
...

60
Documentation/devicetree/bindings/iio/dac/adi,ad5761.yaml Normal file
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@@ -0,0 +1,60 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/dac/adi,ad5761.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analog Devices AD5761 and similar DACs
maintainers:
- Ricardo Ribalda <ribalda@kernel.org>
- Jonathan Cameron <jic23@kernel.org>
properties:
compatible:
enum:
- adi,ad5721
- adi,ad5721r
- adi,ad5761
- adi,ad5761r
reg:
maxItems: 1
spi-max-frequency: true
vref-supply:
description: If not supplied, internal reference will be used.
additionalProperties: false
required:
- compatible
- reg
allOf:
- if:
properties:
compatible:
contains:
enum:
- adi,ad5721
- adi,ad5761
then:
required:
- vref-supply
examples:
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
dac@0 {
compatible = "adi,ad5721";
reg = <0>;
vref-supply = <&dac_vref>;
};
};
...

62
Documentation/devicetree/bindings/iio/dac/adi,ad5764.yaml Normal file
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@@ -0,0 +1,62 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/dac/adi,ad5764.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analog Devices AD5744 and AD5764 DAC families
maintainers:
- Lars-Peter Clausen <lars@metafoo.de>
- Jonathan Cameron <jic23@kernel.org>
properties:
compatible:
enum:
- adi,ad5744
- adi,ad5744r
- adi,ad5764
- adi,ad5764r
reg:
maxItems: 1
spi-max-frequency: true
vrefAB-supply: true
vrefCD-supply: true
additionalProperties: false
required:
- compatible
- reg
allOf:
- if:
properties:
compatible:
contains:
enum:
- adi,ad5744
- adi,ad5764
then:
required:
- vrefAB-supply
- vrefCD-supply
examples:
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
dac@0 {
compatible = "adi,ad5744";
reg = <0>;
vrefAB-supply = <&dac_vref>;
vrefCD-supply = <&dac_vref>;
};
};
...

52
Documentation/devicetree/bindings/iio/dac/adi,ad5791.yaml Normal file
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@@ -0,0 +1,52 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/dac/adi,ad5791.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analog Devices AD5791 and similar DACs
maintainers:
- Michael Hennerich <michael.hennerich@analog.com>
- Jonathan Cameron <jic23@kernel.org>
properties:
compatible:
enum:
- adi,ad5760
- adi,ad5780
- adi,ad5781
- adi,ad5790
- adi,ad5791
reg:
maxItems: 1
spi-max-frequency: true
vdd-supply: true
vss-supply: true
additionalProperties: false
required:
- compatible
- reg
- vdd-supply
- vss-supply
examples:
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
dac@0 {
compatible = "adi,ad5791";
reg = <0>;
vss-supply = <&dac_vss>;
vdd-supply = <&dac_vdd>;
};
};
...

60
Documentation/devicetree/bindings/iio/dac/adi,ad8801.yaml Normal file
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@@ -0,0 +1,60 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/dac/adi,ad8801.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analog Devices AD8801 and AD8803 DACs
maintainers:
- Jonathan Cameron <jic23@kernel.org>
properties:
compatible:
enum:
- adi,ad8801
- adi,ad8803
reg:
maxItems: 1
spi-max-frequency: true
vrefh-supply: true
vrefl-supply: true
additionalProperties: false
required:
- compatible
- reg
- vrefh-supply
allOf:
- if:
properties:
compatible:
contains:
const: adi,ad8803
then:
required:
- vrefl-supply
else:
properties:
vrefl-supply: false
examples:
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
dac@0 {
compatible = "adi,ad8803";
reg = <0>;
vrefl-supply = <&dac_vrefl>;
vrefh-supply = <&dac_vrefh>;
};
};
...

46
Documentation/devicetree/bindings/iio/dac/microchip,mcp4922.yaml Normal file
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@@ -0,0 +1,46 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/dac/microchip,mcp4922.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip MCP4902, MCP4912 and MPC4922 dual output SPI DACs
maintainers:
- Jonathan Cameron <jic23@kernel.org>
- Michael Welling <mwelling@ieee.org>
properties:
compatible:
enum:
- microchip,mcp4902
- microchip,mcp4912
- microchip,mcp4922
reg:
maxItems: 1
spi-max-frequency: true
vref-supply: true
additionalProperties: false
required:
- compatible
- reg
- vref-supply
examples:
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
dac@0 {
compatible = "microchip,mcp4912";
reg = <0>;
vref-supply = <&dac_vref>;
};
};
...

8
Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml
View File

@@ -19,10 +19,10 @@ allOf:
properties:
compatible:
oneOf:
- const: loongson,liointc-1.0
- const: loongson,liointc-1.0a
- const: loongson,liointc-2.0
enum:
- loongson,liointc-1.0
- loongson,liointc-1.0a
- loongson,liointc-2.0
reg:
minItems: 1

50
Documentation/devicetree/bindings/interrupt-controller/samsung,exynos4210-combiner.txt
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@@ -1,50 +0,0 @@
* Samsung Exynos Interrupt Combiner Controller
Samsung's Exynos4 architecture includes a interrupt combiner controller which
can combine interrupt sources as a group and provide a single interrupt request
for the group. The interrupt request from each group are connected to a parent
interrupt controller, such as GIC in case of Exynos4210.
The interrupt combiner controller consists of multiple combiners. Up to eight
interrupt sources can be connected to a combiner. The combiner outputs one
combined interrupt for its eight interrupt sources. The combined interrupt
is usually connected to a parent interrupt controller.
A single node in the device tree is used to describe the interrupt combiner
controller module (which includes multiple combiners). A combiner in the
interrupt controller module shares config/control registers with other
combiners. For example, a 32-bit interrupt enable/disable config register
can accommodate up to 4 interrupt combiners (with each combiner supporting
up to 8 interrupt sources).
Required properties:
- compatible: should be "samsung,exynos4210-combiner".
- interrupt-controller: Identifies the node as an interrupt controller.
- #interrupt-cells: should be <2>. The meaning of the cells are
* First Cell: Combiner Group Number.
* Second Cell: Interrupt number within the group.
- reg: Base address and size of interrupt combiner registers.
- interrupts: The list of interrupts generated by the combiners which are then
connected to a parent interrupt controller. The format of the interrupt
specifier depends in the interrupt parent controller.
Optional properties:
- samsung,combiner-nr: The number of interrupt combiners supported. If this
property is not specified, the default number of combiners is assumed
to be 16.
Example:
The following is a an example from the Exynos4210 SoC dtsi file.
combiner:interrupt-controller@10440000 {
compatible = "samsung,exynos4210-combiner";
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x10440000 0x1000>;
interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
};

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