ANDROID: irqchip: irq-gic: Add vendor hook for gic-v2 resume

This change adds vendor hook for gic-v2 resume to allow vendor GIC
enhancement. This is inline with hook present today in irq-gic-v3.c
with one difference that vendor hooks in v2 driver do not pass entire
gic_chip_data struct to vendor module. Instead it passes the required
fields which are irq_domain and the gic dist base to know the wakeup
IRQ reason.

The newly added vendor hook can get invoked by two ways.
  1. By registering with syscore ops, .resume method can invoke vendor
     hook. This is applicable for cases like suspend-to-ram which
     invokes syscore ops.
  2. By exporting the gic_v2_resume(), the newly added vendor hook will
     get invoked during the first CPU waking up from suspend-to-idle
     case.

While at this move android_vh_gic_resume() to gic_v3.h as its specific
to v3 driver.

Bug: 234108369
Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
Change-Id: I4c857b40f25ad58a6daca491e89adb90e8f6ca93

drivers/android/vendor_hooks.c

@@ -392,3 +392,4 @@ EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_binder_thread_release);
 EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_binder_has_work_ilocked);
 EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_binder_read_done);
 EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_binder_preset);
+EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_gic_v2_resume);

drivers/irqchip/irq-gic.c

@@ -35,6 +35,7 @@
 #include <linux/interrupt.h>
 #include <linux/percpu.h>
 #include <linux/slab.h>
+#include <linux/syscore_ops.h>
 #include <linux/irqchip.h>
 #include <linux/irqchip/chained_irq.h>
 #include <linux/irqchip/arm-gic.h>
@@ -398,6 +399,27 @@ static void gic_handle_cascade_irq(struct irq_desc *desc)
 	chained_irq_exit(chip, desc);
 }
 
+#ifdef CONFIG_PM
+void gic_v2_resume(void)
+{
+	trace_android_vh_gic_v2_resume(gic_data_dist_base(&gic_data[0]), &gic_data[0].domain);
+}
+EXPORT_SYMBOL_GPL(gic_v2_resume);
+
+static struct syscore_ops gic_v2_syscore_ops = {
+	.resume = gic_v2_resume,
+};
+
+static void gic_v2_syscore_init(void)
+{
+	register_syscore_ops(&gic_v2_syscore_ops);
+}
+
+#else
+static inline void gic_syscore_init(void) { }
+void gic_v2_resume(void) { }
+#endif
+
 static const struct irq_chip gic_chip = {
 	.irq_mask		= gic_mask_irq,
 	.irq_unmask		= gic_unmask_irq,
@@ -1241,6 +1263,8 @@ static int gic_init_bases(struct gic_chip_data *gic,
 	if (ret)
 		goto error;
 
+	gic_v2_syscore_init();
+
 	return 0;
 
 error:

include/linux/irqchip/arm-gic-v3.h

@@ -599,7 +599,9 @@
 #define ICC_SGI1R_AFFINITY_3_SHIFT	48
 #define ICC_SGI1R_AFFINITY_3_MASK	(0xffULL << ICC_SGI1R_AFFINITY_3_SHIFT)
 
+#if defined(CONFIG_ARM64) || defined(CONFIG_ARM)
 #include <asm/arch_gicv3.h>
+#endif
 
 #ifndef __ASSEMBLY__
 
@@ -651,6 +653,7 @@ struct gic_chip_data {
 	struct partition_desc	**ppi_descs;
 };
 
+#if defined(CONFIG_ARM64) || defined(CONFIG_ARM)
 static inline bool gic_enable_sre(void)
 {
 	u32 val;
@@ -665,6 +668,12 @@ static inline bool gic_enable_sre(void)
 
 	return !!(val & ICC_SRE_EL1_SRE);
 }
+#else
+static inline bool gic_enable_sre(void)
+{
+	return false;
+}
+#endif
 
 void gic_resume(void);
 

include/linux/irqchip/arm-gic.h

@@ -161,6 +161,7 @@ void gic_send_sgi(unsigned int cpu_id, unsigned int irq);
 int gic_get_cpu_id(unsigned int cpu);
 void gic_migrate_target(unsigned int new_cpu_id);
 unsigned long gic_get_sgir_physaddr(void);
+void gic_v2_resume(void);
 
 #endif /* __ASSEMBLY */
 #endif

include/trace/hooks/gic.h

@@ -8,13 +8,17 @@
 #define _TRACE_HOOK_GIC_H
 
 #include <trace/hooks/vendor_hooks.h>
+
+/* struct cpumask */
+#include <linux/cpumask.h>
 /* struct irq_data */
 #include <linux/irq.h>
-struct gic_chip_data;
+/* struct irq_domain */
+#include <linux/irqdomain.h>
 
-DECLARE_HOOK(android_vh_gic_resume,
-       TP_PROTO(struct gic_chip_data *gd),
-       TP_ARGS(gd));
+DECLARE_HOOK(android_vh_gic_v2_resume,
+	TP_PROTO(struct irq_domain *domain, void __iomem *dist_base),
+	TP_ARGS(domain, dist_base));
 
 DECLARE_HOOK(android_vh_gic_set_affinity,
 	TP_PROTO(struct irq_data *d, const struct cpumask *mask_val,

include/trace/hooks/gic_v3.h

@@ -13,6 +13,9 @@
 #include <linux/cpumask.h>
 /* struct irq_data */
 #include <linux/irq.h>
+/* struct gic_chip_data */
+#include <linux/irqchip/arm-gic-v3.h>
+
 DECLARE_HOOK(android_vh_gic_v3_affinity_init,
 	TP_PROTO(int irq, u32 offset, u64 *affinity),
 	TP_ARGS(irq, offset, affinity));
@@ -22,6 +25,9 @@ DECLARE_RESTRICTED_HOOK(android_rvh_gic_v3_set_affinity,
 		 void __iomem *rbase, u64 redist_stride),
 	TP_ARGS(d, mask_val, affinity, force, base, rbase, redist_stride),
 	1);
+DECLARE_HOOK(android_vh_gic_resume,
+	TP_PROTO(struct gic_chip_data *gd),
+	TP_ARGS(gd));
 
 #endif /* _TRACE_HOOK_GIC_V3_H */
 /* This part must be outside protection */