Revert "PCI: loongson: Prevent LS7A MRRS increases"
This reverts commit baec889a81 which is
commit 8b3517f88ff2983f52698893519227c10aac90b2 upstream.
It breaks the Android kernel abi in the struct pci_host_bridge
structure, and is not needed in any Android devices, so revert it. If
it is needed in the future it can come back in an abi-safe way.
Bug: 161946584
Change-Id: Ief974ca2a06bc5174efddc03d2938dabee7065d7
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
This commit is contained in:
@@ -60,23 +60,37 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
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DEV_LS7A_LPC, system_bus_quirk);
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static void loongson_mrrs_quirk(struct pci_dev *pdev)
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static void loongson_mrrs_quirk(struct pci_dev *dev)
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{
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/*
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* Some Loongson PCIe ports have h/w limitations of maximum read
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* request size. They can't handle anything larger than this. So
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* force this limit on any devices attached under these ports.
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*/
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struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
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struct pci_bus *bus = dev->bus;
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struct pci_dev *bridge;
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static const struct pci_device_id bridge_devids[] = {
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{ PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_0) },
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{ PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_1) },
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{ PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_2) },
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{ 0, },
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};
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bridge->no_inc_mrrs = 1;
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/* look for the matching bridge */
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while (!pci_is_root_bus(bus)) {
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bridge = bus->self;
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bus = bus->parent;
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/*
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* Some Loongson PCIe ports have a h/w limitation of
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* 256 bytes maximum read request size. They can't handle
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* anything larger than this. So force this limit on
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* any devices attached under these ports.
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*/
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if (pci_match_id(bridge_devids, bridge)) {
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if (pcie_get_readrq(dev) > 256) {
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pci_info(dev, "limiting MRRS to 256\n");
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pcie_set_readrq(dev, 256);
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}
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break;
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}
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}
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}
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
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DEV_PCIE_PORT_0, loongson_mrrs_quirk);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
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DEV_PCIE_PORT_1, loongson_mrrs_quirk);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
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DEV_PCIE_PORT_2, loongson_mrrs_quirk);
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DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, loongson_mrrs_quirk);
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static void __iomem *cfg1_map(struct loongson_pci *priv, int bus,
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unsigned int devfn, int where)
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@@ -5970,7 +5970,6 @@ int pcie_set_readrq(struct pci_dev *dev, int rq)
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{
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u16 v;
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int ret;
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struct pci_host_bridge *bridge = pci_find_host_bridge(dev->bus);
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if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
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return -EINVAL;
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@@ -5989,15 +5988,6 @@ int pcie_set_readrq(struct pci_dev *dev, int rq)
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v = (ffs(rq) - 8) << 12;
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if (bridge->no_inc_mrrs) {
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int max_mrrs = pcie_get_readrq(dev);
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if (rq > max_mrrs) {
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pci_info(dev, "can't set Max_Read_Request_Size to %d; max is %d\n", rq, max_mrrs);
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return -EINVAL;
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}
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}
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ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
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PCI_EXP_DEVCTL_READRQ, v);
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@@ -563,7 +563,6 @@ struct pci_host_bridge {
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void *release_data;
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unsigned int ignore_reset_delay:1; /* For entire hierarchy */
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unsigned int no_ext_tags:1; /* No Extended Tags */
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unsigned int no_inc_mrrs:1; /* No Increase MRRS */
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unsigned int native_aer:1; /* OS may use PCIe AER */
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unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
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unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
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