UPSTREAM: arm64: Add macro version of the BTI instruction
BTI is only available from v8.5 so we need to encode it using HINT in generic code and for older toolchains. Add an assembler macro based on one written by Mark Rutland which lets us use the mnemonic and update the existing users. Suggested-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Acked-by: Will Deacon <will@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20211214152714.2380849-2-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Bug: 233652475 Link: https://lore.kernel.org/all/20211214152714.2380849-1-broonie@kernel.org/ (cherry picked from commit 9be34be87cc8d1afe3c3bc2e645b4dee512d9eda) Signed-off-by: Nathan Huckleberry <nhuck@google.com> Change-Id: I961472f606d6eb34f49832b96f69e2156419da79
This commit is contained in:
committed by
Alistair Delva
parent
1fd5d6489a
commit
96c87ab88b
@@ -363,15 +363,15 @@ ST5( mov v4.16b, vctr.16b )
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adr x16, 1f
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sub x16, x16, x12, lsl #3
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br x16
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hint 34 // bti c
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bti c
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mov v0.d[0], vctr.d[0]
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hint 34 // bti c
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bti c
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mov v1.d[0], vctr.d[0]
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hint 34 // bti c
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bti c
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mov v2.d[0], vctr.d[0]
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hint 34 // bti c
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bti c
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mov v3.d[0], vctr.d[0]
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ST5( hint 34 )
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ST5( bti c )
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ST5( mov v4.d[0], vctr.d[0] )
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1: b 2f
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.previous
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@@ -787,6 +787,16 @@ alternative_endif
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.Lnoyield_\@:
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.endm
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/*
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* Branch Target Identifier (BTI)
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*/
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.macro bti, targets
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.equ .L__bti_targets_c, 34
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.equ .L__bti_targets_j, 36
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.equ .L__bti_targets_jc,38
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hint #.L__bti_targets_\targets
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.endm
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/*
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* This macro emits a program property note section identifying
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* architecture features which require special handling, mainly for
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@@ -6,12 +6,7 @@
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#if defined(CONFIG_ARM64_BTI_KERNEL) && defined(__aarch64__)
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/*
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* Since current versions of gas reject the BTI instruction unless we
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* set the architecture version to v8.5 we use the hint instruction
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* instead.
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*/
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#define BTI_C hint 34 ;
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#define BTI_C bti c ;
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/*
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* When using in-kernel BTI we need to ensure that PCS-conformant assembly
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