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BACKPORT: FROMLIST: PCI: dwc: Add support for 64-bit MSI target address

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Since not all devices require a 32-bit MSI address, add support to the
PCIe host driver to allow setting the DMA mask to 64-bits. This allows
kernels to disable ZONE_DMA32 and bounce buffering (swiotlb) without
risking not being able to get a 32-bit address during DMA allocation.
Basically, in the slim chance that there are no 32-bit allocations
available, the current PCIe host driver will fail to allocate the
msi_msg page due to a DMA address overflow (seen in [1]). With this
patch, the PCIe device can advertise 64-bit support via its MSI
capabilities to hint to the PCIe host driver to set the DMA mask to
64-bits.

[1] https://lore.kernel.org/all/Yo0soniFborDl7+C@google.com/

Link: https://lore.kernel.org/all/20220812000327.3154251-3-willmcvicker@google.com/
Bug: 241473543
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Will McVicker <willmcvicker@google.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Jingoo Han <jingoohan1@gmail.com>
Change-Id: I23276717dd6fdf8b3e5adb2d6a706a8378f9c6bb
This commit is contained in:
Will McVicker
2022-08-12 00:03:26 +00:00
committed by Treehugger Robot
parent 6c9828727f
commit b38034b5d5
3 changed files with 22 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
drivers/pci/controller/dwc/pcie-designware-host.c
View File

@@ -289,6 +289,8 @@ int dw_pcie_host_init(struct pcie_port *pp)
struct resource *cfg_res;
u64 *msi_vaddr;
int ret;
bool msi_64bit = false;
u16 msi_capabilities;
raw_spin_lock_init(&pci->pp.lock);
@@ -366,9 +368,18 @@ int dw_pcie_host_init(struct pcie_port *pp)
dw_chained_msi_isr,
pp);
ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
msi_capabilities = dw_pcie_msi_capabilities(pci);
if (msi_capabilities & PCI_MSI_FLAGS_ENABLE)
msi_64bit = msi_capabilities & PCI_MSI_FLAGS_64BIT;
dev_dbg(dev, "Setting MSI DMA mask to %s-bit.\n",
msi_64bit ? "64" : "32");
ret = dma_set_mask_and_coherent(dev, msi_64bit ?
DMA_BIT_MASK(64) : DMA_BIT_MASK(32));
if (ret)
dev_warn(pci->dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n");
dev_warn(dev, "Failed to set DMA mask to %s-bit.\n",
msi_64bit ? "64" : "32");
msi_vaddr = dmam_alloc_coherent(dev, sizeof(u64), &pp->msi_data,
GFP_KERNEL);

8
drivers/pci/controller/dwc/pcie-designware.c
View File

@@ -55,6 +55,14 @@ u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap)
}
EXPORT_SYMBOL_GPL(dw_pcie_find_capability);
u16 dw_pcie_msi_capabilities(struct dw_pcie *pci)
{
u8 offset;
offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI);
return dw_pcie_readw_dbi(pci, offset + PCI_MSI_FLAGS);
}
static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start,
u8 cap)
{

1
drivers/pci/controller/dwc/pcie-designware.h
View File

@@ -285,6 +285,7 @@ struct dw_pcie {
u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap);
u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap);
u16 dw_pcie_msi_capabilities(struct dw_pcie *pci);
int dw_pcie_read(void __iomem *addr, int size, u32 *val);
int dw_pcie_write(void __iomem *addr, int size, u32 val);